From: Anup Patel <anup@brainfault.org> To: Wei Fu <wefu@redhat.com> Cc: "Anup Patel" <anup.patel@wdc.com>, "Atish Patra" <atish.patra@wdc.com>, "Palmer Dabbelt" <palmerdabbelt@google.com>, "Guo Ren" <guoren@kernel.org>, "Christoph Müllner" <christoph.muellner@vrull.eu>, "Philipp Tomsich" <philipp.tomsich@vrull.eu>, "Christoph Hellwig" <hch@lst.de>, liush <liush@allwinnertech.com>, "Wei Wu (吴伟)" <lazyparser@gmail.com>, "Drew Fustini" <drew@beagleboard.org>, linux-riscv <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, taiten.peng@canonical.com, "Aniket Ponkshe" <aniket.ponkshe@canonical.com>, "Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>, "Gordan Markus" <gordan.markus@canonical.com>, "Guo Ren" <guoren@linux.alibaba.com>, "Arnd Bergmann" <arnd@arndb.de>, "Chen-Yu Tsai" <wens@csie.org>, "Maxime Ripard" <maxime@cerno.tech>, "Daniel Lustig" <dlustig@nvidia.com>, "Greg Favor" <gfavor@ventanamicro.com>, "Andrea Mondelli" <andrea.mondelli@huawei.com>, "Jonathan Behrens" <behrensj@mit.edu>, Xinhaoqu <xinhaoqu@huawei.com>, "Bill Huffman" <huffman@cadence.com>, "Nick Kossifidis" <mick@ics.forth.gr>, "Allen Baum" <allen.baum@esperantotech.com>, "Josh Scheid" <jscheid@ventanamicro.com>, "Richard Trauben" <rtrauben@gmail.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Rob Herring" <robh+dt@kernel.org> Subject: Re: [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt Date: Mon, 25 Oct 2021 09:47:34 +0530 [thread overview] Message-ID: <CAAhSdy1N-UQFnbFc7PSwf62y=gbvX7pK=vwUaG8m_KzdWx3AgQ@mail.gmail.com> (raw) In-Reply-To: <20211025040607.92786-2-wefu@redhat.com> On Mon, Oct 25, 2021 at 9:36 AM <wefu@redhat.com> wrote: > > From: Wei Fu <wefu@redhat.com> > > Previous patch has added svpbmt in arch/riscv and changed the > DT mmu-type. Update dt-bindings related property here. > > Signed-off-by: Wei Fu <wefu@redhat.com> > Co-developed-by: Guo Ren <guoren@kernel.org> > Signed-off-by: Guo Ren <guoren@kernel.org> > Cc: Anup Patel <anup@brainfault.org> > Cc: Palmer Dabbelt <palmer@dabbelt.com> > Cc: Rob Herring <robh+dt@kernel.org> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index e534f6a7cfa1..76f324d85e12 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -59,6 +59,11 @@ properties: > - riscv,sv48 > - riscv,none > > + mmu-supports-svpbmt: > + description: > + Describes the CPU's mmu-supports-svpbmt support > + $ref: '/schemas/types.yaml#/definitions/phandle' There were various proposals from different folks in the previous email threads. I think most of us were converging on: 1) Don't modify "mmu-type" DT property for backward compatibility 2) Add boolean DT property "riscv,svpmbt" under "mmu" child DT node of each CPU DT node. Same will apply to boolean DT property "riscv,svnapot" as well. We also have bitmanip and vector broken down into smaller extensions so grouping related extensions as separate DT node under each CPU node will be more readable and easy to parse. Regards, Anup > + > riscv,isa: > description: > Identifies the specific RISC-V instruction set architecture > -- > 2.25.4 >
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Wei Fu <wefu@redhat.com> Cc: "Anup Patel" <anup.patel@wdc.com>, "Atish Patra" <atish.patra@wdc.com>, "Palmer Dabbelt" <palmerdabbelt@google.com>, "Guo Ren" <guoren@kernel.org>, "Christoph Müllner" <christoph.muellner@vrull.eu>, "Philipp Tomsich" <philipp.tomsich@vrull.eu>, "Christoph Hellwig" <hch@lst.de>, liush <liush@allwinnertech.com>, "Wei Wu (吴伟)" <lazyparser@gmail.com>, "Drew Fustini" <drew@beagleboard.org>, linux-riscv <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, taiten.peng@canonical.com, "Aniket Ponkshe" <aniket.ponkshe@canonical.com>, "Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>, "Gordan Markus" <gordan.markus@canonical.com>, "Guo Ren" <guoren@linux.alibaba.com>, "Arnd Bergmann" <arnd@arndb.de>, "Chen-Yu Tsai" <wens@csie.org>, "Maxime Ripard" <maxime@cerno.tech>, "Daniel Lustig" <dlustig@nvidia.com>, "Greg Favor" <gfavor@ventanamicro.com>, "Andrea Mondelli" <andrea.mondelli@huawei.com>, "Jonathan Behrens" <behrensj@mit.edu>, Xinhaoqu <xinhaoqu@huawei.com>, "Bill Huffman" <huffman@cadence.com>, "Nick Kossifidis" <mick@ics.forth.gr>, "Allen Baum" <allen.baum@esperantotech.com>, "Josh Scheid" <jscheid@ventanamicro.com>, "Richard Trauben" <rtrauben@gmail.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Rob Herring" <robh+dt@kernel.org> Subject: Re: [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt Date: Mon, 25 Oct 2021 09:47:34 +0530 [thread overview] Message-ID: <CAAhSdy1N-UQFnbFc7PSwf62y=gbvX7pK=vwUaG8m_KzdWx3AgQ@mail.gmail.com> (raw) In-Reply-To: <20211025040607.92786-2-wefu@redhat.com> On Mon, Oct 25, 2021 at 9:36 AM <wefu@redhat.com> wrote: > > From: Wei Fu <wefu@redhat.com> > > Previous patch has added svpbmt in arch/riscv and changed the > DT mmu-type. Update dt-bindings related property here. > > Signed-off-by: Wei Fu <wefu@redhat.com> > Co-developed-by: Guo Ren <guoren@kernel.org> > Signed-off-by: Guo Ren <guoren@kernel.org> > Cc: Anup Patel <anup@brainfault.org> > Cc: Palmer Dabbelt <palmer@dabbelt.com> > Cc: Rob Herring <robh+dt@kernel.org> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index e534f6a7cfa1..76f324d85e12 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -59,6 +59,11 @@ properties: > - riscv,sv48 > - riscv,none > > + mmu-supports-svpbmt: > + description: > + Describes the CPU's mmu-supports-svpbmt support > + $ref: '/schemas/types.yaml#/definitions/phandle' There were various proposals from different folks in the previous email threads. I think most of us were converging on: 1) Don't modify "mmu-type" DT property for backward compatibility 2) Add boolean DT property "riscv,svpmbt" under "mmu" child DT node of each CPU DT node. Same will apply to boolean DT property "riscv,svnapot" as well. We also have bitmanip and vector broken down into smaller extensions so grouping related extensions as separate DT node under each CPU node will be more readable and easy to parse. Regards, Anup > + > riscv,isa: > description: > Identifies the specific RISC-V instruction set architecture > -- > 2.25.4 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-10-25 4:17 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-25 4:06 [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports wefu 2021-10-25 4:06 ` wefu 2021-10-25 4:06 ` [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt wefu 2021-10-25 4:06 ` wefu 2021-10-25 4:17 ` Anup Patel [this message] 2021-10-25 4:17 ` Anup Patel 2021-10-25 6:00 ` Guo Ren 2021-10-25 6:00 ` Guo Ren 2021-10-25 6:08 ` Anup Patel 2021-10-25 6:08 ` Anup Patel 2021-10-25 13:21 ` Philipp Tomsich 2021-10-25 13:21 ` Philipp Tomsich 2021-10-25 6:09 ` Guo Ren 2021-10-25 6:09 ` Guo Ren 2021-10-25 4:06 ` [RESEND PATCH V3 2/2] riscv: add RISC-V Svpbmt extension supports wefu 2021-10-25 4:06 ` wefu 2021-10-25 6:55 ` Christoph Hellwig 2021-10-25 6:55 ` Christoph Hellwig 2021-10-25 10:55 ` Wei Fu 2021-10-25 10:55 ` Wei Fu 2021-11-02 6:07 ` Christoph Hellwig 2021-11-02 6:07 ` Christoph Hellwig 2021-11-07 7:23 ` Wei Fu 2021-11-07 7:23 ` Wei Fu 2021-10-25 14:49 ` Wei Fu 2021-10-25 14:49 ` Wei Fu 2021-11-02 6:04 ` Christoph Hellwig 2021-11-02 6:04 ` Christoph Hellwig 2021-11-07 6:54 ` Wei Fu 2021-11-07 6:54 ` Wei Fu 2021-10-27 0:12 ` [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Palmer Dabbelt 2021-10-27 0:12 ` Palmer Dabbelt 2021-10-27 7:54 ` Heinrich Schuchardt 2021-10-27 7:54 ` Heinrich Schuchardt 2021-11-02 2:07 ` Guo Ren 2021-11-02 2:07 ` Guo Ren 2021-11-02 5:58 ` Christoph Hellwig 2021-11-02 5:58 ` Christoph Hellwig 2021-11-02 8:51 ` Guo Ren 2021-11-02 8:51 ` Guo Ren 2021-11-07 7:12 ` Wei Fu 2021-11-07 7:12 ` Wei Fu 2021-11-08 7:52 ` Christoph Hellwig 2021-11-08 7:52 ` Christoph Hellwig 2021-11-26 16:23 ` Wei Fu 2021-11-26 16:23 ` Wei Fu
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