[PATCH v3 00/20] Support UXL filed in xstatus

* [PATCH v3 00/20] Support UXL filed in xstatus
@ 2021-11-11  5:57 ` LIU Zhiwei
  0 siblings, 0 replies; 72+ messages in thread
From: LIU Zhiwei @ 2021-11-11  5:57 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: palmer, richard.henderson, bin.meng, Alistair.Francis, LIU Zhiwei

In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.

The patch set v3 mainly address Richard comments on v2.
Patch 1,2,3,5,6,16,17 have been reviewed.

v3:
  Merge gen_pm_adjust_address into a canonical address function
  Adjust address for RVA with XLEN
  Split pm_enabled into pm_mask_enabled and pm_base_enabled
  Replace array of pm tcg globals with one scalar tcg global
  Split and change patch sequence

v2:
  Split out vill from vtype
  Remove context switch when xlen changes at exception
  Use XL instead of OL in many places
  Use pointer masking and XLEN for vector address
  Define an common fuction to calculate address for ldst

LIU Zhiwei (20):
  target/riscv: Don't save pc when exception return
  target/riscv: Sign extend pc for different XLEN
  target/riscv: Ignore the pc bits above XLEN
  target/riscv: Extend pc for runtime pc write
  target/riscv: Use gdb xml according to max mxlen
  target/riscv: Relax debug check for pm write
  target/riscv: Adjust csr write mask with XLEN
  target/riscv: Create current pm fields in env
  target/riscv: Alloc tcg global for cur_pm[mask|base]
  target/riscv: Calculate address according to XLEN
  target/riscv: Split pm_enabled into mask and base
  target/riscv: Split out the vill from vtype
  target/riscv: Fix RESERVED field length in VTYPE
  target/riscv: Adjust vsetvl according to XLEN
  target/riscv: Remove VILL field in VTYPE
  target/riscv: Ajdust vector atomic check with XLEN
  target/riscv: Fix check range for first fault only
  target/riscv: Adjust vector address with mask
  target/riscv: Adjust scalar reg in vector with XLEN
  target/riscv: Enable uxl field write

 target/riscv/cpu.c                            | 23 +++++-
 target/riscv/cpu.h                            | 13 +++-
 target/riscv/cpu_helper.c                     | 66 ++++++++++++----
 target/riscv/csr.c                            | 40 +++++++++-
 target/riscv/gdbstub.c                        | 71 ++++++++++++-----
 target/riscv/helper.h                         |  6 +-
 .../riscv/insn_trans/trans_privileged.c.inc   |  7 +-
 target/riscv/insn_trans/trans_rva.c.inc       |  9 +--
 target/riscv/insn_trans/trans_rvd.c.inc       | 19 +----
 target/riscv/insn_trans/trans_rvf.c.inc       | 19 +----
 target/riscv/insn_trans/trans_rvi.c.inc       | 22 +-----
 target/riscv/insn_trans/trans_rvv.c.inc       | 51 ++++++++----
 target/riscv/machine.c                        | 11 +++
 target/riscv/op_helper.c                      |  7 +-
 target/riscv/translate.c                      | 77 +++++++++----------
 target/riscv/vector_helper.c                  | 38 +++++----
 16 files changed, 293 insertions(+), 186 deletions(-)

-- 
2.25.1

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