[PATCH v5 0/3] Add octal DTR support for Macronix flash

[PATCH v5 0/3] Add octal DTR support for Macronix flash

[JaimeLiao]

This series add support for Macronix octal DTR flash, add flag for
Softreset with "INVERT" command extension type on boot and follow
linux kernel to enable 4byte opcode when possible.

v5:
  Replace SPI_FLASH_MACRONIX_OCTAL with SPI_FLASH_MACRONIX.
  Remove patch of set_4byte opcode.

v4:
  Add flag SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT to seperate command extension
  types.
  Replace ifdef with CONFIG_IS_ENABLED and modify uncorrect descriptions.

v3:
  Add flag  SPI_NOR_CMD_EXT_INVERT to seperate command extension types.
  replace CONFIG_SPI_FLASH_MACRONIX with SPI_FLASH_MACRONIX_OCTAL for
  spi_nor_macronix_octal_dtr_enable function.
v2:
  add ret checking for write enable in spi_nor_macronix_octal_dtr_enable
  function.

JaimeLiao (3):
  mtd: spi-nor: macronix: add support for Macronix Octal
  mtd: spi-nor-core: Adding different type of command extension in Soft
    Reset
  mtd: spi-nor-core: Add support for Macronix Octal flash

 drivers/mtd/spi/Kconfig        |  7 +++
 drivers/mtd/spi/spi-nor-core.c | 90 +++++++++++++++++++++++++++++++++-
 drivers/mtd/spi/spi-nor-ids.c  | 22 ++++++++-
 include/linux/mtd/spi-nor.h    | 12 ++++-
 4 files changed, 127 insertions(+), 4 deletions(-)

-- 
2.17.1

[PATCH v5 1/3] mtd: spi-nor: macronix: add support for Macronix Octal

[JaimeLiao]

Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
Macronix flash in Octal DTR mode.

Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency.
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
 include/linux/mtd/spi-nor.h    | 12 ++++-
 2 files changed, 93 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index d5d905fa5a..0a6550984b 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
 };
 #endif /* CONFIG_SPI_FLASH_MT35XU */
 
+#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
+/**
+ * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
+ * @nor:	pointer to a 'struct spi_nor'
+ *
+ * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
+ * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
+{
+	struct spi_mem_op op;
+	int ret;
+	u8 buf;
+
+	ret = write_enable(nor);
+	if (ret)
+		return ret;
+
+	buf = SPINOR_REG_MXIC_DC_20;
+	op = (struct spi_mem_op)
+		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
+			   SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
+			   SPI_MEM_OP_NO_DUMMY,
+			   SPI_MEM_OP_DATA_OUT(1, &buf, 1));
+
+	ret = spi_mem_exec_op(nor->spi, &op);
+	if (ret)
+		return ret;
+
+	ret = spi_nor_wait_till_ready(nor);
+	if (ret)
+		return ret;
+
+	nor->read_dummy = MXIC_MAX_DC;
+	ret = write_enable(nor);
+	if (ret)
+		return ret;
+
+	buf = SPINOR_REG_MXIC_OPI_DTR_EN;
+	op = (struct spi_mem_op)
+		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
+			   SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
+			   SPI_MEM_OP_NO_DUMMY,
+			   SPI_MEM_OP_DATA_OUT(1, &buf, 1));
+
+	ret = spi_mem_exec_op(nor->spi, &op);
+	if (ret) {
+		dev_err(nor->dev, "Failed to enable octal DTR mode\n");
+		return ret;
+	}
+	nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
+
+	return 0;
+}
+
+static void macronix_octal_default_init(struct spi_nor *nor)
+{
+	nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
+}
+
+static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
+					 struct spi_nor_flash_parameter *params)
+{
+	/*
+	 * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
+	 * SPI_NOR_OCTAL_DTR_READ flag exists.
+	 */
+	if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
+		params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+}
+
+static struct spi_nor_fixups macronix_octal_fixups = {
+	.default_init = macronix_octal_default_init,
+	.post_sfdp = macronix_octal_post_sfdp_fixup,
+};
+#endif /* CONFIG_SPI_FLASH_MACRONIX */
+
 /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
  * @nor:                 pointer to a 'struct spi_nor'
  *
@@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
 	if (!strcmp(nor->info->name, "mt35xu512aba"))
 		nor->fixups = &mt35xu512aba_fixups;
 #endif
+
+#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
+	nor->fixups = &macronix_octal_fixups;
+#endif /* SPI_FLASH_MACRONIX */
 }
 
 int spi_nor_scan(struct spi_nor *nor)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 7ddc4ba2bf..8682368f2f 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -116,8 +116,16 @@
 #define XSR_RDY			BIT(7)	/* Ready */
 
 /* Used for Macronix and Winbond flashes. */
-#define SPINOR_OP_EN4B		0xb7	/* Enter 4-byte mode */
-#define SPINOR_OP_EX4B		0xe9	/* Exit 4-byte mode */
+#define SPINOR_OP_EN4B			0xb7		/* Enter 4-byte mode */
+#define SPINOR_OP_EX4B			0xe9		/* Exit 4-byte mode */
+#define SPINOR_OP_RD_CR2		0x71		/* Read configuration register 2 */
+#define SPINOR_OP_WR_CR2		0x72		/* Write configuration register 2 */
+#define SPINOR_OP_MXIC_DTR_RD		0xee		/* Fast Read opcode in DTR mode */
+#define SPINOR_REG_MXIC_CR2_MODE	0x00000000	/* For setting octal DTR mode */
+#define SPINOR_REG_MXIC_OPI_DTR_EN	0x2		/* Enable Octal DTR */
+#define SPINOR_REG_MXIC_CR2_DC		0x00000300	/* For setting dummy cycles */
+#define SPINOR_REG_MXIC_DC_20		0x0		/* Setting dummy cycles to 20 */
+#define MXIC_MAX_DC			20		/* Maximum value of dummy cycles */
 
 /* Used for Spansion flashes only. */
 #define SPINOR_OP_BRWR		0x17	/* Bank register write */
-- 
2.17.1

[PATCH v5 2/3] mtd: spi-nor-core: Adding different type of command extension in Soft Reset

[JaimeLiao]

Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
in the begging of probe.

Command extension type is not standardized across flash vendors in DTR mode.

For suiting different vendor flash devices, adding a flag to seperate types for
soft reset on boot.

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/Kconfig        | 7 +++++++
 drivers/mtd/spi/spi-nor-core.c | 7 ++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 1b2ef37e92..9b7d195770 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -97,6 +97,13 @@ config SPI_FLASH_SMART_HWCAPS
 	 can support a type of operation in a much more refined way compared
 	 to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc.
 
+config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT
+	bool "Command extension type is INVERT for Software Reset on boot"
+	default n
+	help
+	 Because of SFDP information can not be get before boot.
+	 So define command extension type is INVERT when Software Reset on boot only.
+
 config SPI_FLASH_SOFT_RESET
 	bool "Software Reset support for SPI NOR flashes"
 	default n
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 0a6550984b..2b6947cefc 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -3661,7 +3661,12 @@ static int spi_nor_soft_reset(struct spi_nor *nor)
 	enum spi_nor_cmd_ext ext;
 
 	ext = nor->cmd_ext_type;
-	nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+	if (nor->cmd_ext_type == SPI_NOR_EXT_NONE) {
+		nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+#if CONFIG_IS_ENABLED(SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT)
+		nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
+#endif /* SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT */
+	}
 
 	op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
 			SPI_MEM_OP_NO_DUMMY,
-- 
2.17.1

[PATCH v5 3/3] mtd: spi-nor-core: Add support for Macronix Octal flash

[JaimeLiao]

Adding Macronix Octal flash for Octal DTR support.

The octaflash series can be divided into the following types:

MX25 series : Serial NOR Flash.
MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
LW/UW series : Support simultaneous Read-while-Write operation in multiple
               bank architecture. Read-while-write feature which means read
               data one bank while another bank is programing or erasing.

MX25LM : 3.0V Octal I/O
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf

MX25UM : 1.8V Octal I/O
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf

MX66LM : 3.0V Octal I/O with stacked die
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf

MX66UM : 1.8V Octal I/O with stacked die
 -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf

MX25LW : 3.0V Octal I/O with Read-while-Write
MX25UW : 1.8V Octal I/O with Read-while-Write
MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
MX66UW : 1.8V Octal I/O with Read-while-Write and stack die

About LW/UW series, please contact us freely if you have any
questions. For adding Octal NOR Flash IDs, we have validated
each Flash on plateform zynq-picozed.

Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
---
 drivers/mtd/spi/spi-nor-ids.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index cb3a08872d..5c13ea3a78 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -169,7 +169,27 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
 	{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
-	{ INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66lm1g45g",    0xc2853b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25lm51245g",   0xc2853a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25lw51245g",   0xc2863a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25lm25645g",   0xc28539, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66um2g45g",    0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66uw2g345g",   0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66um1g45g",    0xc2803b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx66uw1g45g",    0xc2813b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25um51245g",   0xc2803a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw51245g",   0xc2813a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw51345g",   0xc2843a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25um25645g",   0xc28039, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw25645g",   0xc28139, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25um25345g",   0xc28339, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw25345g",   0xc28439, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw12845g",   0xc28138, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw12a45g",   0xc28938, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw12345g",   0xc28438, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw6445g",    0xc28137, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+	{ INFO("mx25uw6345g",    0xc28437, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
 #endif
 
 #ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
-- 
2.17.1

Re: [PATCH v5 1/3] mtd: spi-nor: macronix: add support for Macronix Octal

[Tudor.Ambarus]

On 11/18/21 12:13 PM, JaimeLiao wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 

Hi, Jaime,

> Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
> Macronix flash in Octal DTR mode.
> 
> Enable Octal DTR mode with 20 dummy cycles to allow running at the
> maximum supported frequency.
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> 

I have submitted a similar patch at
https://lore.kernel.org/all/20211103162454.179191-2-tudor.ambarus@microchip.com/T/#me9b6e48c33fd545a9c0b5a5136778651ea64171a

but I think yours has precedence, you're already at v5.

> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> ---
>  drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
>  include/linux/mtd/spi-nor.h    | 12 ++++-
>  2 files changed, 93 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index d5d905fa5a..0a6550984b 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
>  };
>  #endif /* CONFIG_SPI_FLASH_MT35XU */
> 
> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> +/**
> + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
> + * @nor:       pointer to a 'struct spi_nor'
> + *
> + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
> + * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
> + *
> + * Return: 0 on success, -errno otherwise.
> + */
> +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
> +{
> +       struct spi_mem_op op;
> +       int ret;
> +       u8 buf;
> +
> +       ret = write_enable(nor);
> +       if (ret)
> +               return ret;
> +
> +       buf = SPINOR_REG_MXIC_DC_20;
> +       op = (struct spi_mem_op)
> +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
> +                          SPI_MEM_OP_NO_DUMMY,
> +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> +
> +       ret = spi_mem_exec_op(nor->spi, &op);
> +       if (ret)
> +               return ret;
> +
> +       ret = spi_nor_wait_till_ready(nor);
> +       if (ret)
> +               return ret;
> +
> +       nor->read_dummy = MXIC_MAX_DC;
> +       ret = write_enable(nor);
> +       if (ret)
> +               return ret;
> +
> +       buf = SPINOR_REG_MXIC_OPI_DTR_EN;
> +       op = (struct spi_mem_op)
> +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
> +                          SPI_MEM_OP_NO_DUMMY,
> +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> +
> +       ret = spi_mem_exec_op(nor->spi, &op);
> +       if (ret) {
> +               dev_err(nor->dev, "Failed to enable octal DTR mode\n");
> +               return ret;
> +       }
> +       nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
> +
> +       return 0;
> +}
> +
> +static void macronix_octal_default_init(struct spi_nor *nor)
> +{
> +       nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
> +}

Can't we determine the octal dtr method by parsing SFDP?

Cheers,
ta

> +
> +static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
> +                                        struct spi_nor_flash_parameter *params)
> +{
> +       /*
> +        * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
> +        * SPI_NOR_OCTAL_DTR_READ flag exists.
> +        */
> +       if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
> +               params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
> +}
> +
> +static struct spi_nor_fixups macronix_octal_fixups = {
> +       .default_init = macronix_octal_default_init,
> +       .post_sfdp = macronix_octal_post_sfdp_fixup,
> +};
> +#endif /* CONFIG_SPI_FLASH_MACRONIX */
> +
>  /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
>   * @nor:                 pointer to a 'struct spi_nor'
>   *
> @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
>         if (!strcmp(nor->info->name, "mt35xu512aba"))
>                 nor->fixups = &mt35xu512aba_fixups;
>  #endif
> +
> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> +       nor->fixups = &macronix_octal_fixups;
> +#endif /* SPI_FLASH_MACRONIX */
>  }
> 
>  int spi_nor_scan(struct spi_nor *nor)
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index 7ddc4ba2bf..8682368f2f 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -116,8 +116,16 @@
>  #define XSR_RDY                        BIT(7)  /* Ready */
> 
>  /* Used for Macronix and Winbond flashes. */
> -#define SPINOR_OP_EN4B         0xb7    /* Enter 4-byte mode */
> -#define SPINOR_OP_EX4B         0xe9    /* Exit 4-byte mode */
> +#define SPINOR_OP_EN4B                 0xb7            /* Enter 4-byte mode */
> +#define SPINOR_OP_EX4B                 0xe9            /* Exit 4-byte mode */
> +#define SPINOR_OP_RD_CR2               0x71            /* Read configuration register 2 */
> +#define SPINOR_OP_WR_CR2               0x72            /* Write configuration register 2 */
> +#define SPINOR_OP_MXIC_DTR_RD          0xee            /* Fast Read opcode in DTR mode */
> +#define SPINOR_REG_MXIC_CR2_MODE       0x00000000      /* For setting octal DTR mode */
> +#define SPINOR_REG_MXIC_OPI_DTR_EN     0x2             /* Enable Octal DTR */
> +#define SPINOR_REG_MXIC_CR2_DC         0x00000300      /* For setting dummy cycles */
> +#define SPINOR_REG_MXIC_DC_20          0x0             /* Setting dummy cycles to 20 */
> +#define MXIC_MAX_DC                    20              /* Maximum value of dummy cycles */
> 
>  /* Used for Spansion flashes only. */
>  #define SPINOR_OP_BRWR         0x17    /* Bank register write */
> --
> 2.17.1
> 

Re: [PATCH v5 2/3] mtd: spi-nor-core: Adding different type of command extension in Soft Reset

[Tudor.Ambarus]

On 11/18/21 12:13 PM, JaimeLiao wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
> in the begging of probe.
> 
> Command extension type is not standardized across flash vendors in DTR mode.
> 
> For suiting different vendor flash devices, adding a flag to seperate types for
> soft reset on boot.
> 
> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> ---
>  drivers/mtd/spi/Kconfig        | 7 +++++++
>  drivers/mtd/spi/spi-nor-core.c | 7 ++++++-
>  2 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
> index 1b2ef37e92..9b7d195770 100644
> --- a/drivers/mtd/spi/Kconfig
> +++ b/drivers/mtd/spi/Kconfig
> @@ -97,6 +97,13 @@ config SPI_FLASH_SMART_HWCAPS
>          can support a type of operation in a much more refined way compared
>          to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc.
> 
> +config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT

There will be many combinations of reset types and cmd_ext types, better to introduce
a way to select the reset type and then to select the cmd_ext type so that we avoid
introducing so many configs/dt props.

I think Pratyush is working to fix this, would you sync with him?
Check the discussion at
https://lore.kernel.org/all/20211103234950.202289-4-tudor.ambarus@microchip.com/

Cheers,
ta

> +       bool "Command extension type is INVERT for Software Reset on boot"
> +       default n
> +       help
> +        Because of SFDP information can not be get before boot.
> +        So define command extension type is INVERT when Software Reset on boot only.
> +
>  config SPI_FLASH_SOFT_RESET
>         bool "Software Reset support for SPI NOR flashes"
>         default n
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index 0a6550984b..2b6947cefc 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -3661,7 +3661,12 @@ static int spi_nor_soft_reset(struct spi_nor *nor)
>         enum spi_nor_cmd_ext ext;
> 
>         ext = nor->cmd_ext_type;
> -       nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
> +       if (nor->cmd_ext_type == SPI_NOR_EXT_NONE) {
> +               nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
> +#if CONFIG_IS_ENABLED(SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT)
> +               nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
> +#endif /* SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT */
> +       }
> 
>         op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
>                         SPI_MEM_OP_NO_DUMMY,
> --
> 2.17.1
> 

Re: [PATCH v5 3/3] mtd: spi-nor-core: Add support for Macronix Octal flash

[Tudor.Ambarus]

On 11/18/21 12:13 PM, JaimeLiao wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Adding Macronix Octal flash for Octal DTR support.
> 
> The octaflash series can be divided into the following types:
> 
> MX25 series : Serial NOR Flash.
> MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> LW/UW series : Support simultaneous Read-while-Write operation in multiple
>                bank architecture. Read-while-write feature which means read
>                data one bank while another bank is programing or erasing.
> 
> MX25LM : 3.0V Octal I/O
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> 
> MX25UM : 1.8V Octal I/O
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf
> 
> MX66LM : 3.0V Octal I/O with stacked die
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
> 
> MX66UM : 1.8V Octal I/O with stacked die
>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf
> 
> MX25LW : 3.0V Octal I/O with Read-while-Write
> MX25UW : 1.8V Octal I/O with Read-while-Write
> MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
> MX66UW : 1.8V Octal I/O with Read-while-Write and stack die
> 
> About LW/UW series, please contact us freely if you have any
> questions. For adding Octal NOR Flash IDs, we have validated
> each Flash on plateform zynq-picozed.
> 
> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> ---
>  drivers/mtd/spi/spi-nor-ids.c | 22 +++++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index cb3a08872d..5c13ea3a78 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -169,7 +169,27 @@ const struct flash_info spi_nor_ids[] = {
>         { INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
>         { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
> -       { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66lm1g45g",    0xc2853b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },

which one of all these flashes (including the ones from below) support
SFDP and which not? Which can discover the octal dtr method by parsing
SFDP and which not? Depending on these those flash_info flags may change.
Why do you need SPI_NOR_4B_OPCODES, can't this support be discovered
when parsing SFDP? How about SECT_4K?

I know for sure there are variants of mx66lm1g45g that do not support
SFDP, and flavors that do support SFDP. How you'll differentiate between
the two flavors of the same flash?

I chose to SKIP SFDP parsing for mx66lm1g45g as there's no infrastructure
to handle its case, neither in linux, nor u-boot.
Here's what I proposed for now:
https://lore.kernel.org/all/20211103234950.202289-3-tudor.ambarus@microchip.com/


Cheers,
ta

> +       { INFO("mx25lm51245g",   0xc2853a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25lw51245g",   0xc2863a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25lm25645g",   0xc28539, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66um2g45g",    0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66uw2g345g",   0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66um1g45g",    0xc2803b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx66uw1g45g",    0xc2813b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25um51245g",   0xc2803a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw51245g",   0xc2813a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw51345g",   0xc2843a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25um25645g",   0xc28039, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw25645g",   0xc28139, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25um25345g",   0xc28339, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw25345g",   0xc28439, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw12845g",   0xc28138, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw12a45g",   0xc28938, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw12345g",   0xc28438, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw6445g",    0xc28137, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> +       { INFO("mx25uw6345g",    0xc28437, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
>  #endif
> 
>  #ifdef CONFIG_SPI_FLASH_STMICRO                /* STMICRO */
> --
> 2.17.1
> 

Re: [PATCH v5 1/3] mtd: spi-nor: macronix: add support for Macronix Octal

[liao jaime]

Hi Tudor

>
> On 11/18/21 12:13 PM, JaimeLiao wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
>
> Hi, Jaime,
>
> > Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
> > Macronix flash in Octal DTR mode.
> >
> > Enable Octal DTR mode with 20 dummy cycles to allow running at the
> > maximum supported frequency.
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> >
>
> I have submitted a similar patch at
> https://lore.kernel.org/all/20211103162454.179191-2-tudor.ambarus@microchip.com/T/#me9b6e48c33fd545a9c0b5a5136778651ea64171a
>
> but I think yours has precedence, you're already at v5.
>
> > Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> > ---
> >  drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
> >  include/linux/mtd/spi-nor.h    | 12 ++++-
> >  2 files changed, 93 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> > index d5d905fa5a..0a6550984b 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
> >  };
> >  #endif /* CONFIG_SPI_FLASH_MT35XU */
> >
> > +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > +/**
> > + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
> > + * @nor:       pointer to a 'struct spi_nor'
> > + *
> > + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
> > + * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
> > + *
> > + * Return: 0 on success, -errno otherwise.
> > + */
> > +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
> > +{
> > +       struct spi_mem_op op;
> > +       int ret;
> > +       u8 buf;
> > +
> > +       ret = write_enable(nor);
> > +       if (ret)
> > +               return ret;
> > +
> > +       buf = SPINOR_REG_MXIC_DC_20;
> > +       op = (struct spi_mem_op)
> > +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> > +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
> > +                          SPI_MEM_OP_NO_DUMMY,
> > +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> > +
> > +       ret = spi_mem_exec_op(nor->spi, &op);
> > +       if (ret)
> > +               return ret;
> > +
> > +       ret = spi_nor_wait_till_ready(nor);
> > +       if (ret)
> > +               return ret;
> > +
> > +       nor->read_dummy = MXIC_MAX_DC;
> > +       ret = write_enable(nor);
> > +       if (ret)
> > +               return ret;
> > +
> > +       buf = SPINOR_REG_MXIC_OPI_DTR_EN;
> > +       op = (struct spi_mem_op)
> > +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> > +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
> > +                          SPI_MEM_OP_NO_DUMMY,
> > +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> > +
> > +       ret = spi_mem_exec_op(nor->spi, &op);
> > +       if (ret) {
> > +               dev_err(nor->dev, "Failed to enable octal DTR mode\n");
> > +               return ret;
> > +       }
> > +       nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
> > +
> > +       return 0;
> > +}
> > +
> > +static void macronix_octal_default_init(struct spi_nor *nor)
> > +{
> > +       nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
> > +}
>
> Can't we determine the octal dtr method by parsing SFDP?
>
It is a good idea for getting flash parameters by checking SFDP.
Your patchwork is on-going to solve the ID collision issues in Linux kernel.
I think U-boot should follow the method after ID collision patchwork
finish in Linux kenel.
So that octal dtr method follow the configuration for now.

Thanks
Jaime
> Cheers,
> ta
>
> > +
> > +static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
> > +                                        struct spi_nor_flash_parameter *params)
> > +{
> > +       /*
> > +        * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
> > +        * SPI_NOR_OCTAL_DTR_READ flag exists.
> > +        */
> > +       if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
> > +               params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
> > +}
> > +
> > +static struct spi_nor_fixups macronix_octal_fixups = {
> > +       .default_init = macronix_octal_default_init,
> > +       .post_sfdp = macronix_octal_post_sfdp_fixup,
> > +};
> > +#endif /* CONFIG_SPI_FLASH_MACRONIX */
> > +
> >  /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
> >   * @nor:                 pointer to a 'struct spi_nor'
> >   *
> > @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
> >         if (!strcmp(nor->info->name, "mt35xu512aba"))
> >                 nor->fixups = &mt35xu512aba_fixups;
> >  #endif
> > +
> > +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> > +       nor->fixups = &macronix_octal_fixups;
> > +#endif /* SPI_FLASH_MACRONIX */
> >  }
> >
> >  int spi_nor_scan(struct spi_nor *nor)
> > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> > index 7ddc4ba2bf..8682368f2f 100644
> > --- a/include/linux/mtd/spi-nor.h
> > +++ b/include/linux/mtd/spi-nor.h
> > @@ -116,8 +116,16 @@
> >  #define XSR_RDY                        BIT(7)  /* Ready */
> >
> >  /* Used for Macronix and Winbond flashes. */
> > -#define SPINOR_OP_EN4B         0xb7    /* Enter 4-byte mode */
> > -#define SPINOR_OP_EX4B         0xe9    /* Exit 4-byte mode */
> > +#define SPINOR_OP_EN4B                 0xb7            /* Enter 4-byte mode */
> > +#define SPINOR_OP_EX4B                 0xe9            /* Exit 4-byte mode */
> > +#define SPINOR_OP_RD_CR2               0x71            /* Read configuration register 2 */
> > +#define SPINOR_OP_WR_CR2               0x72            /* Write configuration register 2 */
> > +#define SPINOR_OP_MXIC_DTR_RD          0xee            /* Fast Read opcode in DTR mode */
> > +#define SPINOR_REG_MXIC_CR2_MODE       0x00000000      /* For setting octal DTR mode */
> > +#define SPINOR_REG_MXIC_OPI_DTR_EN     0x2             /* Enable Octal DTR */
> > +#define SPINOR_REG_MXIC_CR2_DC         0x00000300      /* For setting dummy cycles */
> > +#define SPINOR_REG_MXIC_DC_20          0x0             /* Setting dummy cycles to 20 */
> > +#define MXIC_MAX_DC                    20              /* Maximum value of dummy cycles */
> >
> >  /* Used for Spansion flashes only. */
> >  #define SPINOR_OP_BRWR         0x17    /* Bank register write */
> > --
> > 2.17.1
> >
>

Re: [PATCH v5 2/3] mtd: spi-nor-core: Adding different type of command extension in Soft Reset

[liao jaime]

Hi Tudor

>
> On 11/18/21 12:13 PM, JaimeLiao wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
> > in the begging of probe.
> >
> > Command extension type is not standardized across flash vendors in DTR mode.
> >
> > For suiting different vendor flash devices, adding a flag to seperate types for
> > soft reset on boot.
> >
> > Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> > ---
> >  drivers/mtd/spi/Kconfig        | 7 +++++++
> >  drivers/mtd/spi/spi-nor-core.c | 7 ++++++-
> >  2 files changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
> > index 1b2ef37e92..9b7d195770 100644
> > --- a/drivers/mtd/spi/Kconfig
> > +++ b/drivers/mtd/spi/Kconfig
> > @@ -97,6 +97,13 @@ config SPI_FLASH_SMART_HWCAPS
> >          can support a type of operation in a much more refined way compared
> >          to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc.
> >
> > +config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT
>
> There will be many combinations of reset types and cmd_ext types, better to introduce
> a way to select the reset type and then to select the cmd_ext type so that we avoid
> introducing so many configs/dt props.
>
> I think Pratyush is working to fix this, would you sync with him?
Sure, this configuration is according Pratyush suggestion.

> Check the discussion at
> https://lore.kernel.org/all/20211103234950.202289-4-tudor.ambarus@microchip.com/
>
> Cheers,
> ta
>
> > +       bool "Command extension type is INVERT for Software Reset on boot"
> > +       default n
> > +       help
> > +        Because of SFDP information can not be get before boot.
> > +        So define command extension type is INVERT when Software Reset on boot only.
> > +
> >  config SPI_FLASH_SOFT_RESET
> >         bool "Software Reset support for SPI NOR flashes"
> >         default n
> > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> > index 0a6550984b..2b6947cefc 100644
> > --- a/drivers/mtd/spi/spi-nor-core.c
> > +++ b/drivers/mtd/spi/spi-nor-core.c
> > @@ -3661,7 +3661,12 @@ static int spi_nor_soft_reset(struct spi_nor *nor)
> >         enum spi_nor_cmd_ext ext;
> >
> >         ext = nor->cmd_ext_type;
> > -       nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
> > +       if (nor->cmd_ext_type == SPI_NOR_EXT_NONE) {
> > +               nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
> > +#if CONFIG_IS_ENABLED(SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT)
> > +               nor->cmd_ext_type = SPI_NOR_EXT_INVERT;
> > +#endif /* SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT */
> > +       }
> >
> >         op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0),
> >                         SPI_MEM_OP_NO_DUMMY,
> > --
> > 2.17.1
> >
>

Re: [PATCH v5 1/3] mtd: spi-nor: macronix: add support for Macronix Octal

[Tudor.Ambarus]

On 11/26/21 7:28 AM, liao jaime wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi Tudor

Hi,

> 
>>
>> On 11/18/21 12:13 PM, JaimeLiao wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>
>> Hi, Jaime,
>>
>>> Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
>>> Macronix flash in Octal DTR mode.
>>>
>>> Enable Octal DTR mode with 20 dummy cycles to allow running at the
>>> maximum supported frequency.
>>>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
>>>
>>
>> I have submitted a similar patch at
>> https://lore.kernel.org/all/20211103162454.179191-2-tudor.ambarus@microchip.com/T/#me9b6e48c33fd545a9c0b5a5136778651ea64171a
>>
>> but I think yours has precedence, you're already at v5.
>>
>>> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
>>> ---
>>>  drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
>>>  include/linux/mtd/spi-nor.h    | 12 ++++-
>>>  2 files changed, 93 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
>>> index d5d905fa5a..0a6550984b 100644
>>> --- a/drivers/mtd/spi/spi-nor-core.c
>>> +++ b/drivers/mtd/spi/spi-nor-core.c
>>> @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
>>>  };
>>>  #endif /* CONFIG_SPI_FLASH_MT35XU */
>>>
>>> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
>>> +/**
>>> + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
>>> + * @nor:       pointer to a 'struct spi_nor'
>>> + *
>>> + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
>>> + * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
>>> + *
>>> + * Return: 0 on success, -errno otherwise.
>>> + */
>>> +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
>>> +{
>>> +       struct spi_mem_op op;
>>> +       int ret;
>>> +       u8 buf;
>>> +
>>> +       ret = write_enable(nor);
>>> +       if (ret)
>>> +               return ret;
>>> +
>>> +       buf = SPINOR_REG_MXIC_DC_20;
>>> +       op = (struct spi_mem_op)
>>> +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
>>> +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
>>> +                          SPI_MEM_OP_NO_DUMMY,
>>> +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
>>> +
>>> +       ret = spi_mem_exec_op(nor->spi, &op);
>>> +       if (ret)
>>> +               return ret;
>>> +
>>> +       ret = spi_nor_wait_till_ready(nor);
>>> +       if (ret)
>>> +               return ret;
>>> +
>>> +       nor->read_dummy = MXIC_MAX_DC;
>>> +       ret = write_enable(nor);
>>> +       if (ret)
>>> +               return ret;
>>> +
>>> +       buf = SPINOR_REG_MXIC_OPI_DTR_EN;
>>> +       op = (struct spi_mem_op)
>>> +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
>>> +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
>>> +                          SPI_MEM_OP_NO_DUMMY,
>>> +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
>>> +
>>> +       ret = spi_mem_exec_op(nor->spi, &op);
>>> +       if (ret) {
>>> +               dev_err(nor->dev, "Failed to enable octal DTR mode\n");
>>> +               return ret;
>>> +       }
>>> +       nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
>>> +
>>> +       return 0;
>>> +}
>>> +
>>> +static void macronix_octal_default_init(struct spi_nor *nor)
>>> +{
>>> +       nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
>>> +}
>>
>> Can't we determine the octal dtr method by parsing SFDP?
>>
> It is a good idea for getting flash parameters by checking SFDP.
> Your patchwork is on-going to solve the ID collision issues in Linux kernel.
> I think U-boot should follow the method after ID collision patchwork
> finish in Linux kenel.
> So that octal dtr method follow the configuration for now.
> 

What I meant was that if we can determine the octal dtr method from SFDP,
we should use that. If we can't determine the octal dtr method from SFDP,
or SFDP is skipped intentionally, then we can define explicit methods,
as you did. But we'll need to differentiate between the two methods,
otherwise maintaining the flash entries will become a burden.

Cheers,
ta
> Thanks
> Jaime
>> Cheers,
>> ta
>>
>>> +
>>> +static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
>>> +                                        struct spi_nor_flash_parameter *params)
>>> +{
>>> +       /*
>>> +        * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
>>> +        * SPI_NOR_OCTAL_DTR_READ flag exists.
>>> +        */
>>> +       if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
>>> +               params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
>>> +}
>>> +
>>> +static struct spi_nor_fixups macronix_octal_fixups = {
>>> +       .default_init = macronix_octal_default_init,
>>> +       .post_sfdp = macronix_octal_post_sfdp_fixup,
>>> +};
>>> +#endif /* CONFIG_SPI_FLASH_MACRONIX */
>>> +
>>>  /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
>>>   * @nor:                 pointer to a 'struct spi_nor'
>>>   *
>>> @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
>>>         if (!strcmp(nor->info->name, "mt35xu512aba"))
>>>                 nor->fixups = &mt35xu512aba_fixups;
>>>  #endif
>>> +
>>> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
>>> +       nor->fixups = &macronix_octal_fixups;
>>> +#endif /* SPI_FLASH_MACRONIX */
>>>  }
>>>
>>>  int spi_nor_scan(struct spi_nor *nor)
>>> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
>>> index 7ddc4ba2bf..8682368f2f 100644
>>> --- a/include/linux/mtd/spi-nor.h
>>> +++ b/include/linux/mtd/spi-nor.h
>>> @@ -116,8 +116,16 @@
>>>  #define XSR_RDY                        BIT(7)  /* Ready */
>>>
>>>  /* Used for Macronix and Winbond flashes. */
>>> -#define SPINOR_OP_EN4B         0xb7    /* Enter 4-byte mode */
>>> -#define SPINOR_OP_EX4B         0xe9    /* Exit 4-byte mode */
>>> +#define SPINOR_OP_EN4B                 0xb7            /* Enter 4-byte mode */
>>> +#define SPINOR_OP_EX4B                 0xe9            /* Exit 4-byte mode */
>>> +#define SPINOR_OP_RD_CR2               0x71            /* Read configuration register 2 */
>>> +#define SPINOR_OP_WR_CR2               0x72            /* Write configuration register 2 */
>>> +#define SPINOR_OP_MXIC_DTR_RD          0xee            /* Fast Read opcode in DTR mode */
>>> +#define SPINOR_REG_MXIC_CR2_MODE       0x00000000      /* For setting octal DTR mode */
>>> +#define SPINOR_REG_MXIC_OPI_DTR_EN     0x2             /* Enable Octal DTR */
>>> +#define SPINOR_REG_MXIC_CR2_DC         0x00000300      /* For setting dummy cycles */
>>> +#define SPINOR_REG_MXIC_DC_20          0x0             /* Setting dummy cycles to 20 */
>>> +#define MXIC_MAX_DC                    20              /* Maximum value of dummy cycles */
>>>
>>>  /* Used for Spansion flashes only. */
>>>  #define SPINOR_OP_BRWR         0x17    /* Bank register write */
>>> --
>>> 2.17.1
>>>
>>

Re: [PATCH v5 1/3] mtd: spi-nor: macronix: add support for Macronix Octal

[liao jaime]

Hi Tudor

>
> On 11/26/21 7:28 AM, liao jaime wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Hi Tudor
>
> Hi,
>
> >
> >>
> >> On 11/18/21 12:13 PM, JaimeLiao wrote:
> >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>
> >>
> >> Hi, Jaime,
> >>
> >>> Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
> >>> Macronix flash in Octal DTR mode.
> >>>
> >>> Enable Octal DTR mode with 20 dummy cycles to allow running at the
> >>> maximum supported frequency.
> >>>  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> >>>
> >>
> >> I have submitted a similar patch at
> >> https://lore.kernel.org/all/20211103162454.179191-2-tudor.ambarus@microchip.com/T/#me9b6e48c33fd545a9c0b5a5136778651ea64171a
> >>
> >> but I think yours has precedence, you're already at v5.
> >>
> >>> Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> >>> ---
> >>>  drivers/mtd/spi/spi-nor-core.c | 83 ++++++++++++++++++++++++++++++++++
> >>>  include/linux/mtd/spi-nor.h    | 12 ++++-
> >>>  2 files changed, 93 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> >>> index d5d905fa5a..0a6550984b 100644
> >>> --- a/drivers/mtd/spi/spi-nor-core.c
> >>> +++ b/drivers/mtd/spi/spi-nor-core.c
> >>> @@ -3489,6 +3489,85 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
> >>>  };
> >>>  #endif /* CONFIG_SPI_FLASH_MT35XU */
> >>>
> >>> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> >>> +/**
> >>> + * spi_nor_macronix_octal_dtr_enable() - set DTR OPI Enable bit in Configuration Register 2.
> >>> + * @nor:       pointer to a 'struct spi_nor'
> >>> + *
> >>> + * Set the DTR OPI Enable (DOPI) bit in Configuration Register 2.
> >>> + * Bit 2 of  Configuration Register 2 is the DOPI bit for Macronix like OPI memories.
> >>> + *
> >>> + * Return: 0 on success, -errno otherwise.
> >>> + */
> >>> +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)
> >>> +{
> >>> +       struct spi_mem_op op;
> >>> +       int ret;
> >>> +       u8 buf;
> >>> +
> >>> +       ret = write_enable(nor);
> >>> +       if (ret)
> >>> +               return ret;
> >>> +
> >>> +       buf = SPINOR_REG_MXIC_DC_20;
> >>> +       op = (struct spi_mem_op)
> >>> +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> >>> +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
> >>> +                          SPI_MEM_OP_NO_DUMMY,
> >>> +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> >>> +
> >>> +       ret = spi_mem_exec_op(nor->spi, &op);
> >>> +       if (ret)
> >>> +               return ret;
> >>> +
> >>> +       ret = spi_nor_wait_till_ready(nor);
> >>> +       if (ret)
> >>> +               return ret;
> >>> +
> >>> +       nor->read_dummy = MXIC_MAX_DC;
> >>> +       ret = write_enable(nor);
> >>> +       if (ret)
> >>> +               return ret;
> >>> +
> >>> +       buf = SPINOR_REG_MXIC_OPI_DTR_EN;
> >>> +       op = (struct spi_mem_op)
> >>> +               SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> >>> +                          SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1),
> >>> +                          SPI_MEM_OP_NO_DUMMY,
> >>> +                          SPI_MEM_OP_DATA_OUT(1, &buf, 1));
> >>> +
> >>> +       ret = spi_mem_exec_op(nor->spi, &op);
> >>> +       if (ret) {
> >>> +               dev_err(nor->dev, "Failed to enable octal DTR mode\n");
> >>> +               return ret;
> >>> +       }
> >>> +       nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
> >>> +
> >>> +       return 0;
> >>> +}
> >>> +
> >>> +static void macronix_octal_default_init(struct spi_nor *nor)
> >>> +{
> >>> +       nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable;
> >>> +}
> >>
> >> Can't we determine the octal dtr method by parsing SFDP?
> >>
> > It is a good idea for getting flash parameters by checking SFDP.
> > Your patchwork is on-going to solve the ID collision issues in Linux kernel.
> > I think U-boot should follow the method after ID collision patchwork
> > finish in Linux kenel.
> > So that octal dtr method follow the configuration for now.
> >
>
> What I meant was that if we can determine the octal dtr method from SFDP,
> we should use that. If we can't determine the octal dtr method from SFDP,
> or SFDP is skipped intentionally, then we can define explicit methods,
> as you did. But we'll need to differentiate between the two methods,
> otherwise maintaining the flash entries will become a burden.
>
Sure, I prefer to parsing information from SFDP but not got according
to configuration
and differentiate methods via configuration "SPI_NOR_SKIP_SFDP".
Hook corresponding function on .post_sfdp and .post_bfdp if
configuration SPI_NOR_SKIP_SFDP existing.
I need add the changes for v6 patch if you have any other idea.
But I hope that we can seperate octal dtr support by two patches.

> Cheers,
> ta
> > Thanks
> > Jaime
> >> Cheers,
> >> ta
> >>
> >>> +
> >>> +static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor,
> >>> +                                        struct spi_nor_flash_parameter *params)
> >>> +{
> >>> +       /*
> >>> +        * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when
> >>> +        * SPI_NOR_OCTAL_DTR_READ flag exists.
> >>> +        */
> >>> +       if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR)
> >>> +               params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
> >>> +}
> >>> +
> >>> +static struct spi_nor_fixups macronix_octal_fixups = {
> >>> +       .default_init = macronix_octal_default_init,
> >>> +       .post_sfdp = macronix_octal_post_sfdp_fixup,
> >>> +};
> >>> +#endif /* CONFIG_SPI_FLASH_MACRONIX */
> >>> +
> >>>  /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
> >>>   * @nor:                 pointer to a 'struct spi_nor'
> >>>   *
> >>> @@ -3655,6 +3734,10 @@ void spi_nor_set_fixups(struct spi_nor *nor)
> >>>         if (!strcmp(nor->info->name, "mt35xu512aba"))
> >>>                 nor->fixups = &mt35xu512aba_fixups;
> >>>  #endif
> >>> +
> >>> +#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX)
> >>> +       nor->fixups = &macronix_octal_fixups;
> >>> +#endif /* SPI_FLASH_MACRONIX */
> >>>  }
> >>>
> >>>  int spi_nor_scan(struct spi_nor *nor)
> >>> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> >>> index 7ddc4ba2bf..8682368f2f 100644
> >>> --- a/include/linux/mtd/spi-nor.h
> >>> +++ b/include/linux/mtd/spi-nor.h
> >>> @@ -116,8 +116,16 @@
> >>>  #define XSR_RDY                        BIT(7)  /* Ready */
> >>>
> >>>  /* Used for Macronix and Winbond flashes. */
> >>> -#define SPINOR_OP_EN4B         0xb7    /* Enter 4-byte mode */
> >>> -#define SPINOR_OP_EX4B         0xe9    /* Exit 4-byte mode */
> >>> +#define SPINOR_OP_EN4B                 0xb7            /* Enter 4-byte mode */
> >>> +#define SPINOR_OP_EX4B                 0xe9            /* Exit 4-byte mode */
> >>> +#define SPINOR_OP_RD_CR2               0x71            /* Read configuration register 2 */
> >>> +#define SPINOR_OP_WR_CR2               0x72            /* Write configuration register 2 */
> >>> +#define SPINOR_OP_MXIC_DTR_RD          0xee            /* Fast Read opcode in DTR mode */
> >>> +#define SPINOR_REG_MXIC_CR2_MODE       0x00000000      /* For setting octal DTR mode */
> >>> +#define SPINOR_REG_MXIC_OPI_DTR_EN     0x2             /* Enable Octal DTR */
> >>> +#define SPINOR_REG_MXIC_CR2_DC         0x00000300      /* For setting dummy cycles */
> >>> +#define SPINOR_REG_MXIC_DC_20          0x0             /* Setting dummy cycles to 20 */
> >>> +#define MXIC_MAX_DC                    20              /* Maximum value of dummy cycles */
> >>>
> >>>  /* Used for Spansion flashes only. */
> >>>  #define SPINOR_OP_BRWR         0x17    /* Bank register write */
> >>> --
> >>> 2.17.1
> >>>
> >>
>

Re: [PATCH v5 3/3] mtd: spi-nor-core: Add support for Macronix Octal flash

[liao jaime]

Hi Tudor

>
> On 11/18/21 12:13 PM, JaimeLiao wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Adding Macronix Octal flash for Octal DTR support.
> >
> > The octaflash series can be divided into the following types:
> >
> > MX25 series : Serial NOR Flash.
> > MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
> > LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
> > LW/UW series : Support simultaneous Read-while-Write operation in multiple
> >                bank architecture. Read-while-write feature which means read
> >                data one bank while another bank is programing or erasing.
> >
> > MX25LM : 3.0V Octal I/O
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
> >
> > MX25UM : 1.8V Octal I/O
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf
> >
> > MX66LM : 3.0V Octal I/O with stacked die
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
> >
> > MX66UM : 1.8V Octal I/O with stacked die
> >  -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf
> >
> > MX25LW : 3.0V Octal I/O with Read-while-Write
> > MX25UW : 1.8V Octal I/O with Read-while-Write
> > MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
> > MX66UW : 1.8V Octal I/O with Read-while-Write and stack die
> >
> > About LW/UW series, please contact us freely if you have any
> > questions. For adding Octal NOR Flash IDs, we have validated
> > each Flash on plateform zynq-picozed.
> >
> > Signed-off-by: JaimeLiao <jaimeliao.tw@gmail.com>
> > ---
> >  drivers/mtd/spi/spi-nor-ids.c | 22 +++++++++++++++++++++-
> >  1 file changed, 21 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> > index cb3a08872d..5c13ea3a78 100644
> > --- a/drivers/mtd/spi/spi-nor-ids.c
> > +++ b/drivers/mtd/spi/spi-nor-ids.c
> > @@ -169,7 +169,27 @@ const struct flash_info spi_nor_ids[] = {
> >         { INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> >         { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
> >         { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
> > -       { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66lm1g45g",    0xc2853b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
>
> which one of all these flashes (including the ones from below) support
> SFDP and which not? Which can discover the octal dtr method by parsing
> SFDP and which not? Depending on these those flash_info flags may change.

I agree that we need a method for octal dtr support on flash which
didn't include SFDP
but the patch of method is separate with Octal DTR patch.


> Why do you need SPI_NOR_4B_OPCODES, can't this support be discovered
> when parsing SFDP? How about SECT_4K?
>
> I know for sure there are variants of mx66lm1g45g that do not support
> SFDP, and flavors that do support SFDP. How you'll differentiate between
> the two flavors of the same flash?
>
> I chose to SKIP SFDP parsing for mx66lm1g45g as there's no infrastructure
> to handle its case, neither in linux, nor u-boot.
> Here's what I proposed for now:
> https://lore.kernel.org/all/20211103234950.202289-3-tudor.ambarus@microchip.com/
>
>
> Cheers,
> ta
>
> > +       { INFO("mx25lm51245g",   0xc2853a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25lw51245g",   0xc2863a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25lm25645g",   0xc28539, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66um2g45g",    0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66uw2g345g",   0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66um1g45g",    0xc2803b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx66uw1g45g",    0xc2813b, 0, 32 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25um51245g",   0xc2803a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw51245g",   0xc2813a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw51345g",   0xc2843a, 0, 16 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25um25645g",   0xc28039, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw25645g",   0xc28139, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25um25345g",   0xc28339, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw25345g",   0xc28439, 0, 8 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw12845g",   0xc28138, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw12a45g",   0xc28938, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw12345g",   0xc28438, 0, 4 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw6445g",    0xc28137, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> > +       { INFO("mx25uw6345g",    0xc28437, 0, 2 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
> >  #endif
> >
> >  #ifdef CONFIG_SPI_FLASH_STMICRO                /* STMICRO */
> > --
> > 2.17.1
> >
>