* [PATCH 0/4] Add ARTPEC-8 support to DWMMC controller
@ 2021-12-01 15:38 ` Mårten Lindahl
0 siblings, 0 replies; 18+ messages in thread
From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung
Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel,
linux-samsung-soc, Mårten Lindahl
Hi!
The ARTPEC-8 SoC has a DWMMC controller that is compatible with the
Exynos 7 version v2.70a. The main differences from Exynos 7 is that it
does not support HS400 and has an extended data read timeout. To run
this controller we need to add compatibility for ARTPEC-8, because we
need a quirk to separate the configuration of the TMOUT register from
the non ARTPEC-8 versions.
This patchset is dependent on 2 changes that has been added to the mmc
git next branch, but has not yet been merged to mainline:
Patch 2 of this patchset depends on commit 0e6f2c4c2072b ("mmc: dw_mmc:
add common capabilities to replace caps").
Patch 3 of this patchset depends on commit d5bc33487eab3 ("mmc: dw_mmc:
Allow lower TMOUT value than maximum").
Kind regards
Mårten Lindahl
Mårten Lindahl (4):
dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8
mmc: dw_mmc-exynos: Add support for ARTPEC-8
mmc: dw_mmc: Add quirk for extended data read timeout
mmc: dw_mmc: Do not wait for DTO in case of error
.../bindings/mmc/exynos-dw-mshc.txt | 2 +
drivers/mmc/host/dw_mmc-exynos.c | 52 +++++++++++++++----
drivers/mmc/host/dw_mmc.c | 41 +++++++++++++--
drivers/mmc/host/dw_mmc.h | 7 +++
4 files changed, 87 insertions(+), 15 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 0/4] Add ARTPEC-8 support to DWMMC controller @ 2021-12-01 15:38 ` Mårten Lindahl 0 siblings, 0 replies; 18+ messages in thread From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc, Mårten Lindahl Hi! The ARTPEC-8 SoC has a DWMMC controller that is compatible with the Exynos 7 version v2.70a. The main differences from Exynos 7 is that it does not support HS400 and has an extended data read timeout. To run this controller we need to add compatibility for ARTPEC-8, because we need a quirk to separate the configuration of the TMOUT register from the non ARTPEC-8 versions. This patchset is dependent on 2 changes that has been added to the mmc git next branch, but has not yet been merged to mainline: Patch 2 of this patchset depends on commit 0e6f2c4c2072b ("mmc: dw_mmc: add common capabilities to replace caps"). Patch 3 of this patchset depends on commit d5bc33487eab3 ("mmc: dw_mmc: Allow lower TMOUT value than maximum"). Kind regards Mårten Lindahl Mårten Lindahl (4): dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 mmc: dw_mmc-exynos: Add support for ARTPEC-8 mmc: dw_mmc: Add quirk for extended data read timeout mmc: dw_mmc: Do not wait for DTO in case of error .../bindings/mmc/exynos-dw-mshc.txt | 2 + drivers/mmc/host/dw_mmc-exynos.c | 52 +++++++++++++++---- drivers/mmc/host/dw_mmc.c | 41 +++++++++++++-- drivers/mmc/host/dw_mmc.h | 7 +++ 4 files changed, 87 insertions(+), 15 deletions(-) -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 2021-12-01 15:38 ` Mårten Lindahl @ 2021-12-01 15:38 ` Mårten Lindahl -1 siblings, 0 replies; 18+ messages in thread From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc, Mårten Lindahl The ARTPEC-8 SoC has a DWMMC controller that is compatible with the Exynos 7 version v2.70a. The main differences from Exynos 7 is that it does not support HS400 and has extended data read timeout. Add compatibility string "samsung,artpec8-dw-mshc" for ARTPEC-8. Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> --- Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 0419a63f73a0..161be451a1f0 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -22,6 +22,8 @@ Required Properties: specific extensions. - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 specific extensions having an SMU. + - "samsung,artpec8-dw-mshc": for controllers with ARTPEC-8 specific + extensions. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and -- 2.20.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 @ 2021-12-01 15:38 ` Mårten Lindahl 0 siblings, 0 replies; 18+ messages in thread From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc, Mårten Lindahl The ARTPEC-8 SoC has a DWMMC controller that is compatible with the Exynos 7 version v2.70a. The main differences from Exynos 7 is that it does not support HS400 and has extended data read timeout. Add compatibility string "samsung,artpec8-dw-mshc" for ARTPEC-8. Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> --- Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 0419a63f73a0..161be451a1f0 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -22,6 +22,8 @@ Required Properties: specific extensions. - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 specific extensions having an SMU. + - "samsung,artpec8-dw-mshc": for controllers with ARTPEC-8 specific + extensions. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 2021-12-01 15:38 ` Mårten Lindahl @ 2021-12-02 8:41 ` Krzysztof Kozlowski -1 siblings, 0 replies; 18+ messages in thread From: Krzysztof Kozlowski @ 2021-12-02 8:41 UTC (permalink / raw) To: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc On 01/12/2021 16:38, Mårten Lindahl wrote: > The ARTPEC-8 SoC has a DWMMC controller that is compatible with the > Exynos 7 version v2.70a. The main differences from Exynos 7 is that it > does not support HS400 and has extended data read timeout. > > Add compatibility string "samsung,artpec8-dw-mshc" for ARTPEC-8. > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > --- > Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > index 0419a63f73a0..161be451a1f0 100644 > --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > @@ -22,6 +22,8 @@ Required Properties: > specific extensions. > - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 > specific extensions having an SMU. > + - "samsung,artpec8-dw-mshc": for controllers with ARTPEC-8 specific > + extensions. Artpec8 does not look like Samsung, so vendor prefix does not match. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 @ 2021-12-02 8:41 ` Krzysztof Kozlowski 0 siblings, 0 replies; 18+ messages in thread From: Krzysztof Kozlowski @ 2021-12-02 8:41 UTC (permalink / raw) To: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc On 01/12/2021 16:38, Mårten Lindahl wrote: > The ARTPEC-8 SoC has a DWMMC controller that is compatible with the > Exynos 7 version v2.70a. The main differences from Exynos 7 is that it > does not support HS400 and has extended data read timeout. > > Add compatibility string "samsung,artpec8-dw-mshc" for ARTPEC-8. > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > --- > Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > index 0419a63f73a0..161be451a1f0 100644 > --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > @@ -22,6 +22,8 @@ Required Properties: > specific extensions. > - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 > specific extensions having an SMU. > + - "samsung,artpec8-dw-mshc": for controllers with ARTPEC-8 specific > + extensions. Artpec8 does not look like Samsung, so vendor prefix does not match. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 2021-12-02 8:41 ` Krzysztof Kozlowski @ 2021-12-03 12:00 ` Marten Lindahl -1 siblings, 0 replies; 18+ messages in thread From: Marten Lindahl @ 2021-12-03 12:00 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung, Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc On Thu, Dec 02, 2021 at 09:41:05AM +0100, Krzysztof Kozlowski wrote: Hi Krzysztof! Thanks for looking at this! > On 01/12/2021 16:38, Mårten Lindahl wrote: > > The ARTPEC-8 SoC has a DWMMC controller that is compatible with the > > Exynos 7 version v2.70a. The main differences from Exynos 7 is that it > > does not support HS400 and has extended data read timeout. > > > > Add compatibility string "samsung,artpec8-dw-mshc" for ARTPEC-8. > > > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > > --- > > Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > > index 0419a63f73a0..161be451a1f0 100644 > > --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > > +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > > @@ -22,6 +22,8 @@ Required Properties: > > specific extensions. > > - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 > > specific extensions having an SMU. > > + - "samsung,artpec8-dw-mshc": for controllers with ARTPEC-8 specific > > + extensions. > > Artpec8 does not look like Samsung, so vendor prefix does not match. Since the IP is very similar, I just copied the vendor prefix from the others, but ok, I will change it to 'axis'. Kind regards Mårten > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 @ 2021-12-03 12:00 ` Marten Lindahl 0 siblings, 0 replies; 18+ messages in thread From: Marten Lindahl @ 2021-12-03 12:00 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung, Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc On Thu, Dec 02, 2021 at 09:41:05AM +0100, Krzysztof Kozlowski wrote: Hi Krzysztof! Thanks for looking at this! > On 01/12/2021 16:38, Mårten Lindahl wrote: > > The ARTPEC-8 SoC has a DWMMC controller that is compatible with the > > Exynos 7 version v2.70a. The main differences from Exynos 7 is that it > > does not support HS400 and has extended data read timeout. > > > > Add compatibility string "samsung,artpec8-dw-mshc" for ARTPEC-8. > > > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > > --- > > Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > > index 0419a63f73a0..161be451a1f0 100644 > > --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > > +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt > > @@ -22,6 +22,8 @@ Required Properties: > > specific extensions. > > - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 > > specific extensions having an SMU. > > + - "samsung,artpec8-dw-mshc": for controllers with ARTPEC-8 specific > > + extensions. > > Artpec8 does not look like Samsung, so vendor prefix does not match. Since the IP is very similar, I just copied the vendor prefix from the others, but ok, I will change it to 'axis'. Kind regards Mårten > > Best regards, > Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/4] mmc: dw_mmc-exynos: Add support for ARTPEC-8 2021-12-01 15:38 ` Mårten Lindahl @ 2021-12-01 15:38 ` Mårten Lindahl -1 siblings, 0 replies; 18+ messages in thread From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc, Mårten Lindahl The ARTPEC-8 SoC has a DWMMC controller that is compatible with the Exynos 7 version v2.70a. The main differences from Exynos 7 is that it does not support HS400 and has extended data read timeout. This patch adds compatibility string "samsung,artpec8-dw-mshc" for ARTPEC-8, and DW_MCI_TYPE_ARTPEC8 is added to the dw_mci_exynos_type. Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> --- drivers/mmc/host/dw_mmc-exynos.c | 47 ++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 11 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index f76eeeb0cc53..cae7c94b5d6e 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -28,6 +28,7 @@ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS5420_SMU, DW_MCI_TYPE_EXYNOS7, DW_MCI_TYPE_EXYNOS7_SMU, + DW_MCI_TYPE_ARTPEC8, }; /* Exynos implementation specific driver private data */ @@ -69,6 +70,9 @@ static struct dw_mci_exynos_compatible { }, { .compatible = "samsung,exynos7-dw-mshc-smu", .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, + }, { + .compatible = "samsung,artpec8-dw-mshc", + .ctrl_type = DW_MCI_TYPE_ARTPEC8, }, }; @@ -81,7 +85,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) return EXYNOS4210_FIXED_CIU_CLK_DIV; else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; else return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; @@ -133,7 +138,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) u32 clksel; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else clksel = mci_readl(host, CLKSEL); @@ -141,7 +147,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else mci_writel(host, CLKSEL, clksel); @@ -210,14 +217,16 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) return ret; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else clksel = mci_readl(host, CLKSEL); if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else mci_writel(host, CLKSEL, clksel); @@ -238,7 +247,8 @@ static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) * Not supported to configure register * related to HS400 */ - if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) { + if ((priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) || + (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)) { if (timing == MMC_TIMING_MMC_HS400) dev_warn(host->dev, "cannot configure HS400, unsupported chipset\n"); @@ -394,7 +404,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) struct dw_mci_exynos_priv_data *priv = host->priv; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); else return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL)); @@ -406,13 +417,15 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) struct dw_mci_exynos_priv_data *priv = host->priv; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else clksel = mci_readl(host, CLKSEL); clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else mci_writel(host, CLKSEL, clksel); @@ -425,7 +438,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) u8 sample; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else clksel = mci_readl(host, CLKSEL); @@ -434,7 +448,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else mci_writel(host, CLKSEL, clksel); @@ -543,6 +558,14 @@ static const struct dw_mci_drv_data exynos_drv_data = { .prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning, }; +static const struct dw_mci_drv_data artpec_drv_data = { + .common_caps = MMC_CAP_CMD23, + .init = dw_mci_exynos_priv_init, + .set_ios = dw_mci_exynos_set_ios, + .parse_dt = dw_mci_exynos_parse_dt, + .execute_tuning = dw_mci_exynos_execute_tuning, +}; + static const struct of_device_id dw_mci_exynos_match[] = { { .compatible = "samsung,exynos4412-dw-mshc", .data = &exynos_drv_data, }, @@ -556,6 +579,8 @@ static const struct of_device_id dw_mci_exynos_match[] = { .data = &exynos_drv_data, }, { .compatible = "samsung,exynos7-dw-mshc-smu", .data = &exynos_drv_data, }, + { .compatible = "samsung,artpec8-dw-mshc", + .data = &artpec_drv_data, }, {}, }; MODULE_DEVICE_TABLE(of, dw_mci_exynos_match); -- 2.20.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/4] mmc: dw_mmc-exynos: Add support for ARTPEC-8 @ 2021-12-01 15:38 ` Mårten Lindahl 0 siblings, 0 replies; 18+ messages in thread From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc, Mårten Lindahl The ARTPEC-8 SoC has a DWMMC controller that is compatible with the Exynos 7 version v2.70a. The main differences from Exynos 7 is that it does not support HS400 and has extended data read timeout. This patch adds compatibility string "samsung,artpec8-dw-mshc" for ARTPEC-8, and DW_MCI_TYPE_ARTPEC8 is added to the dw_mci_exynos_type. Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> --- drivers/mmc/host/dw_mmc-exynos.c | 47 ++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 11 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index f76eeeb0cc53..cae7c94b5d6e 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -28,6 +28,7 @@ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS5420_SMU, DW_MCI_TYPE_EXYNOS7, DW_MCI_TYPE_EXYNOS7_SMU, + DW_MCI_TYPE_ARTPEC8, }; /* Exynos implementation specific driver private data */ @@ -69,6 +70,9 @@ static struct dw_mci_exynos_compatible { }, { .compatible = "samsung,exynos7-dw-mshc-smu", .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU, + }, { + .compatible = "samsung,artpec8-dw-mshc", + .ctrl_type = DW_MCI_TYPE_ARTPEC8, }, }; @@ -81,7 +85,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) return EXYNOS4210_FIXED_CIU_CLK_DIV; else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1; else return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; @@ -133,7 +138,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) u32 clksel; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else clksel = mci_readl(host, CLKSEL); @@ -141,7 +147,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else mci_writel(host, CLKSEL, clksel); @@ -210,14 +217,16 @@ static int dw_mci_exynos_resume_noirq(struct device *dev) return ret; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else clksel = mci_readl(host, CLKSEL); if (clksel & SDMMC_CLKSEL_WAKEUP_INT) { if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else mci_writel(host, CLKSEL, clksel); @@ -238,7 +247,8 @@ static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing) * Not supported to configure register * related to HS400 */ - if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) { + if ((priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) || + (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)) { if (timing == MMC_TIMING_MMC_HS400) dev_warn(host->dev, "cannot configure HS400, unsupported chipset\n"); @@ -394,7 +404,8 @@ static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host) struct dw_mci_exynos_priv_data *priv = host->priv; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64)); else return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL)); @@ -406,13 +417,15 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) struct dw_mci_exynos_priv_data *priv = host->priv; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else clksel = mci_readl(host, CLKSEL); clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else mci_writel(host, CLKSEL, clksel); @@ -425,7 +438,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) u8 sample; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) clksel = mci_readl(host, CLKSEL64); else clksel = mci_readl(host, CLKSEL); @@ -434,7 +448,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU || + priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) mci_writel(host, CLKSEL64, clksel); else mci_writel(host, CLKSEL, clksel); @@ -543,6 +558,14 @@ static const struct dw_mci_drv_data exynos_drv_data = { .prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning, }; +static const struct dw_mci_drv_data artpec_drv_data = { + .common_caps = MMC_CAP_CMD23, + .init = dw_mci_exynos_priv_init, + .set_ios = dw_mci_exynos_set_ios, + .parse_dt = dw_mci_exynos_parse_dt, + .execute_tuning = dw_mci_exynos_execute_tuning, +}; + static const struct of_device_id dw_mci_exynos_match[] = { { .compatible = "samsung,exynos4412-dw-mshc", .data = &exynos_drv_data, }, @@ -556,6 +579,8 @@ static const struct of_device_id dw_mci_exynos_match[] = { .data = &exynos_drv_data, }, { .compatible = "samsung,exynos7-dw-mshc-smu", .data = &exynos_drv_data, }, + { .compatible = "samsung,artpec8-dw-mshc", + .data = &artpec_drv_data, }, {}, }; MODULE_DEVICE_TABLE(of, dw_mci_exynos_match); -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout 2021-12-01 15:38 ` Mårten Lindahl @ 2021-12-01 15:38 ` Mårten Lindahl -1 siblings, 0 replies; 18+ messages in thread From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc, Mårten Lindahl Current dw_mci driver supports a TMOUT register which consists of a 24 bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: 0xFFFFFF / 200000000 => ~84 ms However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an extended DATA_TIMEOUT field, which supports longer timers for the DRTO. In this version the DATA_TIMEOUT field is split into two, which with the same 200MHz clock as above will allow a maximum timeout of: ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms Add a quirk to support this. The quirk is enabled for ARTPEC-8 SoCs. Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> --- drivers/mmc/host/dw_mmc-exynos.c | 5 +++++ drivers/mmc/host/dw_mmc.c | 33 ++++++++++++++++++++++++++++---- drivers/mmc/host/dw_mmc.h | 7 +++++++ 3 files changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index cae7c94b5d6e..6ae9c0ec1282 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -127,6 +127,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); } + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { + /* Quirk needed for ARTPEC-8 SoCs */ + host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; + } + host->bus_hz /= (priv->ciu_div + 1); return 0; diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index f2a14a434bef..45ea9fd97a6a 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -1289,6 +1289,7 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, { u32 clk_div, tmout; u64 tmp; + unsigned int tmp2; clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; if (clk_div == 0) @@ -1301,10 +1302,28 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, tmout = 0xFF; /* Set maximum */ /* TMOUT[31:8] (DATA_TIMEOUT) */ - if (!tmp || tmp > 0xFFFFFF) - tmout |= (0xFFFFFF << 8); - else - tmout |= (tmp & 0xFFFFFF) << 8; + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) { + /* + * Extended HW timer (max = 0x6FFFFF2): + * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) + */ + if (!tmp || tmp > 0x6FFFFF2) + tmout |= (0xFFFFFF << 8); + else { + /* TMOUT[10:8] */ + tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7; + tmout |= tmp2 << 8; + + /* TMOUT[31:11] */ + tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); + tmout |= (tmp & 0xFFFFF8) << 8; + } + } else { + if (!tmp || tmp > 0xFFFFFF) + tmout |= (0xFFFFFF << 8); + else + tmout |= (tmp & 0xFFFFFF) << 8; + } mci_writel(host, TMOUT, tmout); dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: 0x%#08x", @@ -2005,9 +2024,15 @@ static void dw_mci_set_drto(struct dw_mci *host) if (drto_div == 0) drto_div = 1; + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) + drto_clks = (((drto_clks & 0x7) - 1) * 0xFFFFFF) + + ((drto_clks & 0xFFFFF8)); + drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, host->bus_hz); + dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); + /* add a bit spare time */ drto_ms += 10; diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 771d5afa3136..071f4479f166 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -118,6 +118,7 @@ struct dw_mci_dma_slave { * @part_buf: Simple buffer for partial fifo reads/writes. * @push_data: Pointer to FIFO push function. * @pull_data: Pointer to FIFO pull function. + * @quirks: Set of quirks that apply to specific versions of the IP. * @vqmmc_enabled: Status of vqmmc, should be true or false. * @irq_flags: The flags to be passed to request_irq. * @irq: The irq value to be passed to request_irq. @@ -223,6 +224,9 @@ struct dw_mci { void (*push_data)(struct dw_mci *host, void *buf, int cnt); void (*pull_data)(struct dw_mci *host, void *buf, int cnt); + /* Workaround flags */ + u32 quirks; + bool vqmmc_enabled; unsigned long irq_flags; /* IRQ flags */ int irq; @@ -274,6 +278,9 @@ struct dw_mci_board { struct dma_pdata *data; }; +/* Support for longer data read timeout */ +#define DW_MMC_QUIRK_EXTENDED_TMOUT (1<<0) + #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a -- 2.20.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout @ 2021-12-01 15:38 ` Mårten Lindahl 0 siblings, 0 replies; 18+ messages in thread From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc, Mårten Lindahl Current dw_mci driver supports a TMOUT register which consists of a 24 bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: 0xFFFFFF / 200000000 => ~84 ms However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an extended DATA_TIMEOUT field, which supports longer timers for the DRTO. In this version the DATA_TIMEOUT field is split into two, which with the same 200MHz clock as above will allow a maximum timeout of: ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms Add a quirk to support this. The quirk is enabled for ARTPEC-8 SoCs. Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> --- drivers/mmc/host/dw_mmc-exynos.c | 5 +++++ drivers/mmc/host/dw_mmc.c | 33 ++++++++++++++++++++++++++++---- drivers/mmc/host/dw_mmc.h | 7 +++++++ 3 files changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index cae7c94b5d6e..6ae9c0ec1282 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -127,6 +127,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); } + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { + /* Quirk needed for ARTPEC-8 SoCs */ + host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; + } + host->bus_hz /= (priv->ciu_div + 1); return 0; diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index f2a14a434bef..45ea9fd97a6a 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -1289,6 +1289,7 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, { u32 clk_div, tmout; u64 tmp; + unsigned int tmp2; clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; if (clk_div == 0) @@ -1301,10 +1302,28 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, tmout = 0xFF; /* Set maximum */ /* TMOUT[31:8] (DATA_TIMEOUT) */ - if (!tmp || tmp > 0xFFFFFF) - tmout |= (0xFFFFFF << 8); - else - tmout |= (tmp & 0xFFFFFF) << 8; + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) { + /* + * Extended HW timer (max = 0x6FFFFF2): + * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) + */ + if (!tmp || tmp > 0x6FFFFF2) + tmout |= (0xFFFFFF << 8); + else { + /* TMOUT[10:8] */ + tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7; + tmout |= tmp2 << 8; + + /* TMOUT[31:11] */ + tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); + tmout |= (tmp & 0xFFFFF8) << 8; + } + } else { + if (!tmp || tmp > 0xFFFFFF) + tmout |= (0xFFFFFF << 8); + else + tmout |= (tmp & 0xFFFFFF) << 8; + } mci_writel(host, TMOUT, tmout); dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: 0x%#08x", @@ -2005,9 +2024,15 @@ static void dw_mci_set_drto(struct dw_mci *host) if (drto_div == 0) drto_div = 1; + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) + drto_clks = (((drto_clks & 0x7) - 1) * 0xFFFFFF) + + ((drto_clks & 0xFFFFF8)); + drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, host->bus_hz); + dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); + /* add a bit spare time */ drto_ms += 10; diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 771d5afa3136..071f4479f166 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -118,6 +118,7 @@ struct dw_mci_dma_slave { * @part_buf: Simple buffer for partial fifo reads/writes. * @push_data: Pointer to FIFO push function. * @pull_data: Pointer to FIFO pull function. + * @quirks: Set of quirks that apply to specific versions of the IP. * @vqmmc_enabled: Status of vqmmc, should be true or false. * @irq_flags: The flags to be passed to request_irq. * @irq: The irq value to be passed to request_irq. @@ -223,6 +224,9 @@ struct dw_mci { void (*push_data)(struct dw_mci *host, void *buf, int cnt); void (*pull_data)(struct dw_mci *host, void *buf, int cnt); + /* Workaround flags */ + u32 quirks; + bool vqmmc_enabled; unsigned long irq_flags; /* IRQ flags */ int irq; @@ -274,6 +278,9 @@ struct dw_mci_board { struct dma_pdata *data; }; +/* Support for longer data read timeout */ +#define DW_MMC_QUIRK_EXTENDED_TMOUT (1<<0) + #define DW_MMC_240A 0x240a #define DW_MMC_280A 0x280a -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout 2021-12-01 15:38 ` Mårten Lindahl @ 2021-12-02 8:39 ` Krzysztof Kozlowski -1 siblings, 0 replies; 18+ messages in thread From: Krzysztof Kozlowski @ 2021-12-02 8:39 UTC (permalink / raw) To: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc On 01/12/2021 16:38, Mårten Lindahl wrote: > Current dw_mci driver supports a TMOUT register which consists of a 24 > bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this > field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: > > 0xFFFFFF / 200000000 => ~84 ms > > However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an > extended DATA_TIMEOUT field, which supports longer timers for the DRTO. > In this version the DATA_TIMEOUT field is split into two, which with the > same 200MHz clock as above will allow a maximum timeout of: > > ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms > > Add a quirk to support this. The quirk is enabled for ARTPEC-8 SoCs. > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > --- > drivers/mmc/host/dw_mmc-exynos.c | 5 +++++ > drivers/mmc/host/dw_mmc.c | 33 ++++++++++++++++++++++++++++---- > drivers/mmc/host/dw_mmc.h | 7 +++++++ > 3 files changed, 41 insertions(+), 4 deletions(-) > > diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c > index cae7c94b5d6e..6ae9c0ec1282 100644 > --- a/drivers/mmc/host/dw_mmc-exynos.c > +++ b/drivers/mmc/host/dw_mmc-exynos.c > @@ -127,6 +127,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) > DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); > } > > + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { > + /* Quirk needed for ARTPEC-8 SoCs */ > + host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; > + } > + > host->bus_hz /= (priv->ciu_div + 1); > > return 0; > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > index f2a14a434bef..45ea9fd97a6a 100644 > --- a/drivers/mmc/host/dw_mmc.c > +++ b/drivers/mmc/host/dw_mmc.c > @@ -1289,6 +1289,7 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > { > u32 clk_div, tmout; > u64 tmp; > + unsigned int tmp2; > > clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; > if (clk_div == 0) > @@ -1301,10 +1302,28 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > tmout = 0xFF; /* Set maximum */ > > /* TMOUT[31:8] (DATA_TIMEOUT) */ > - if (!tmp || tmp > 0xFFFFFF) > - tmout |= (0xFFFFFF << 8); > - else > - tmout |= (tmp & 0xFFFFFF) << 8; > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) { > + /* > + * Extended HW timer (max = 0x6FFFFF2): > + * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) > + */ > + if (!tmp || tmp > 0x6FFFFF2) > + tmout |= (0xFFFFFF << 8); > + else { > + /* TMOUT[10:8] */ > + tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7; > + tmout |= tmp2 << 8; > + > + /* TMOUT[31:11] */ > + tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); > + tmout |= (tmp & 0xFFFFF8) << 8; > + } > + } else { > + if (!tmp || tmp > 0xFFFFFF) > + tmout |= (0xFFFFFF << 8); > + else > + tmout |= (tmp & 0xFFFFFF) << 8; > + } > > mci_writel(host, TMOUT, tmout); > dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: 0x%#08x", > @@ -2005,9 +2024,15 @@ static void dw_mci_set_drto(struct dw_mci *host) > if (drto_div == 0) > drto_div = 1; > > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) > + drto_clks = (((drto_clks & 0x7) - 1) * 0xFFFFFF) + > + ((drto_clks & 0xFFFFF8)); > + > drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, > host->bus_hz); > > + dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); > + > /* add a bit spare time */ > drto_ms += 10; > > diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h > index 771d5afa3136..071f4479f166 100644 > --- a/drivers/mmc/host/dw_mmc.h > +++ b/drivers/mmc/host/dw_mmc.h > @@ -118,6 +118,7 @@ struct dw_mci_dma_slave { > * @part_buf: Simple buffer for partial fifo reads/writes. > * @push_data: Pointer to FIFO push function. > * @pull_data: Pointer to FIFO pull function. > + * @quirks: Set of quirks that apply to specific versions of the IP. > * @vqmmc_enabled: Status of vqmmc, should be true or false. > * @irq_flags: The flags to be passed to request_irq. > * @irq: The irq value to be passed to request_irq. > @@ -223,6 +224,9 @@ struct dw_mci { > void (*push_data)(struct dw_mci *host, void *buf, int cnt); > void (*pull_data)(struct dw_mci *host, void *buf, int cnt); > > + /* Workaround flags */ No need for this comment - you already described the field in kerneldoc. > + u32 quirks; > + > bool vqmmc_enabled; > unsigned long irq_flags; /* IRQ flags */ > int irq; > @@ -274,6 +278,9 @@ struct dw_mci_board { > struct dma_pdata *data; > }; > > +/* Support for longer data read timeout */ > +#define DW_MMC_QUIRK_EXTENDED_TMOUT (1<<0) BIT() > + > #define DW_MMC_240A 0x240a > #define DW_MMC_280A 0x280a > > Best regards, Krzysztof ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout @ 2021-12-02 8:39 ` Krzysztof Kozlowski 0 siblings, 0 replies; 18+ messages in thread From: Krzysztof Kozlowski @ 2021-12-02 8:39 UTC (permalink / raw) To: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc On 01/12/2021 16:38, Mårten Lindahl wrote: > Current dw_mci driver supports a TMOUT register which consists of a 24 > bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this > field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: > > 0xFFFFFF / 200000000 => ~84 ms > > However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an > extended DATA_TIMEOUT field, which supports longer timers for the DRTO. > In this version the DATA_TIMEOUT field is split into two, which with the > same 200MHz clock as above will allow a maximum timeout of: > > ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms > > Add a quirk to support this. The quirk is enabled for ARTPEC-8 SoCs. > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > --- > drivers/mmc/host/dw_mmc-exynos.c | 5 +++++ > drivers/mmc/host/dw_mmc.c | 33 ++++++++++++++++++++++++++++---- > drivers/mmc/host/dw_mmc.h | 7 +++++++ > 3 files changed, 41 insertions(+), 4 deletions(-) > > diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c > index cae7c94b5d6e..6ae9c0ec1282 100644 > --- a/drivers/mmc/host/dw_mmc-exynos.c > +++ b/drivers/mmc/host/dw_mmc-exynos.c > @@ -127,6 +127,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) > DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); > } > > + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { > + /* Quirk needed for ARTPEC-8 SoCs */ > + host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; > + } > + > host->bus_hz /= (priv->ciu_div + 1); > > return 0; > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > index f2a14a434bef..45ea9fd97a6a 100644 > --- a/drivers/mmc/host/dw_mmc.c > +++ b/drivers/mmc/host/dw_mmc.c > @@ -1289,6 +1289,7 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > { > u32 clk_div, tmout; > u64 tmp; > + unsigned int tmp2; > > clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; > if (clk_div == 0) > @@ -1301,10 +1302,28 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > tmout = 0xFF; /* Set maximum */ > > /* TMOUT[31:8] (DATA_TIMEOUT) */ > - if (!tmp || tmp > 0xFFFFFF) > - tmout |= (0xFFFFFF << 8); > - else > - tmout |= (tmp & 0xFFFFFF) << 8; > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) { > + /* > + * Extended HW timer (max = 0x6FFFFF2): > + * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) > + */ > + if (!tmp || tmp > 0x6FFFFF2) > + tmout |= (0xFFFFFF << 8); > + else { > + /* TMOUT[10:8] */ > + tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7; > + tmout |= tmp2 << 8; > + > + /* TMOUT[31:11] */ > + tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); > + tmout |= (tmp & 0xFFFFF8) << 8; > + } > + } else { > + if (!tmp || tmp > 0xFFFFFF) > + tmout |= (0xFFFFFF << 8); > + else > + tmout |= (tmp & 0xFFFFFF) << 8; > + } > > mci_writel(host, TMOUT, tmout); > dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: 0x%#08x", > @@ -2005,9 +2024,15 @@ static void dw_mci_set_drto(struct dw_mci *host) > if (drto_div == 0) > drto_div = 1; > > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) > + drto_clks = (((drto_clks & 0x7) - 1) * 0xFFFFFF) + > + ((drto_clks & 0xFFFFF8)); > + > drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, > host->bus_hz); > > + dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); > + > /* add a bit spare time */ > drto_ms += 10; > > diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h > index 771d5afa3136..071f4479f166 100644 > --- a/drivers/mmc/host/dw_mmc.h > +++ b/drivers/mmc/host/dw_mmc.h > @@ -118,6 +118,7 @@ struct dw_mci_dma_slave { > * @part_buf: Simple buffer for partial fifo reads/writes. > * @push_data: Pointer to FIFO push function. > * @pull_data: Pointer to FIFO pull function. > + * @quirks: Set of quirks that apply to specific versions of the IP. > * @vqmmc_enabled: Status of vqmmc, should be true or false. > * @irq_flags: The flags to be passed to request_irq. > * @irq: The irq value to be passed to request_irq. > @@ -223,6 +224,9 @@ struct dw_mci { > void (*push_data)(struct dw_mci *host, void *buf, int cnt); > void (*pull_data)(struct dw_mci *host, void *buf, int cnt); > > + /* Workaround flags */ No need for this comment - you already described the field in kerneldoc. > + u32 quirks; > + > bool vqmmc_enabled; > unsigned long irq_flags; /* IRQ flags */ > int irq; > @@ -274,6 +278,9 @@ struct dw_mci_board { > struct dma_pdata *data; > }; > > +/* Support for longer data read timeout */ > +#define DW_MMC_QUIRK_EXTENDED_TMOUT (1<<0) BIT() > + > #define DW_MMC_240A 0x240a > #define DW_MMC_280A 0x280a > > Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout 2021-12-02 8:39 ` Krzysztof Kozlowski @ 2021-12-03 12:02 ` Marten Lindahl -1 siblings, 0 replies; 18+ messages in thread From: Marten Lindahl @ 2021-12-03 12:02 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung, Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc On Thu, Dec 02, 2021 at 09:39:30AM +0100, Krzysztof Kozlowski wrote: Hi Krzysztof! Thanks for looking at this! > On 01/12/2021 16:38, Mårten Lindahl wrote: > > Current dw_mci driver supports a TMOUT register which consists of a 24 > > bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this > > field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: > > > > 0xFFFFFF / 200000000 => ~84 ms > > > > However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an > > extended DATA_TIMEOUT field, which supports longer timers for the DRTO. > > In this version the DATA_TIMEOUT field is split into two, which with the > > same 200MHz clock as above will allow a maximum timeout of: > > > > ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms > > > > Add a quirk to support this. The quirk is enabled for ARTPEC-8 SoCs. > > > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > > --- > > drivers/mmc/host/dw_mmc-exynos.c | 5 +++++ > > drivers/mmc/host/dw_mmc.c | 33 ++++++++++++++++++++++++++++---- > > drivers/mmc/host/dw_mmc.h | 7 +++++++ > > 3 files changed, 41 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c > > index cae7c94b5d6e..6ae9c0ec1282 100644 > > --- a/drivers/mmc/host/dw_mmc-exynos.c > > +++ b/drivers/mmc/host/dw_mmc-exynos.c > > @@ -127,6 +127,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) > > DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); > > } > > > > + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { > > + /* Quirk needed for ARTPEC-8 SoCs */ > > + host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; > > + } > > + > > host->bus_hz /= (priv->ciu_div + 1); > > > > return 0; > > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > > index f2a14a434bef..45ea9fd97a6a 100644 > > --- a/drivers/mmc/host/dw_mmc.c > > +++ b/drivers/mmc/host/dw_mmc.c > > @@ -1289,6 +1289,7 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > > { > > u32 clk_div, tmout; > > u64 tmp; > > + unsigned int tmp2; > > > > clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; > > if (clk_div == 0) > > @@ -1301,10 +1302,28 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > > tmout = 0xFF; /* Set maximum */ > > > > /* TMOUT[31:8] (DATA_TIMEOUT) */ > > - if (!tmp || tmp > 0xFFFFFF) > > - tmout |= (0xFFFFFF << 8); > > - else > > - tmout |= (tmp & 0xFFFFFF) << 8; > > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) { > > + /* > > + * Extended HW timer (max = 0x6FFFFF2): > > + * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) > > + */ > > + if (!tmp || tmp > 0x6FFFFF2) > > + tmout |= (0xFFFFFF << 8); > > + else { > > + /* TMOUT[10:8] */ > > + tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7; > > + tmout |= tmp2 << 8; > > + > > + /* TMOUT[31:11] */ > > + tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); > > + tmout |= (tmp & 0xFFFFF8) << 8; > > + } > > + } else { > > + if (!tmp || tmp > 0xFFFFFF) > > + tmout |= (0xFFFFFF << 8); > > + else > > + tmout |= (tmp & 0xFFFFFF) << 8; > > + } > > > > mci_writel(host, TMOUT, tmout); > > dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: 0x%#08x", > > @@ -2005,9 +2024,15 @@ static void dw_mci_set_drto(struct dw_mci *host) > > if (drto_div == 0) > > drto_div = 1; > > > > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) > > + drto_clks = (((drto_clks & 0x7) - 1) * 0xFFFFFF) + > > + ((drto_clks & 0xFFFFF8)); > > + > > drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, > > host->bus_hz); > > > > + dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); > > + > > /* add a bit spare time */ > > drto_ms += 10; > > > > diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h > > index 771d5afa3136..071f4479f166 100644 > > --- a/drivers/mmc/host/dw_mmc.h > > +++ b/drivers/mmc/host/dw_mmc.h > > @@ -118,6 +118,7 @@ struct dw_mci_dma_slave { > > * @part_buf: Simple buffer for partial fifo reads/writes. > > * @push_data: Pointer to FIFO push function. > > * @pull_data: Pointer to FIFO pull function. > > + * @quirks: Set of quirks that apply to specific versions of the IP. > > * @vqmmc_enabled: Status of vqmmc, should be true or false. > > * @irq_flags: The flags to be passed to request_irq. > > * @irq: The irq value to be passed to request_irq. > > @@ -223,6 +224,9 @@ struct dw_mci { > > void (*push_data)(struct dw_mci *host, void *buf, int cnt); > > void (*pull_data)(struct dw_mci *host, void *buf, int cnt); > > > > + /* Workaround flags */ > > No need for this comment - you already described the field in kerneldoc. Ok, will remove it. > > > + u32 quirks; > > + > > bool vqmmc_enabled; > > unsigned long irq_flags; /* IRQ flags */ > > int irq; > > @@ -274,6 +278,9 @@ struct dw_mci_board { > > struct dma_pdata *data; > > }; > > > > +/* Support for longer data read timeout */ > > +#define DW_MMC_QUIRK_EXTENDED_TMOUT (1<<0) > > BIT() Will fix. > > > + > > #define DW_MMC_240A 0x240a > > #define DW_MMC_280A 0x280a > > > > > Kind regards Mårten > > Best regards, > Krzysztof ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout @ 2021-12-03 12:02 ` Marten Lindahl 0 siblings, 0 replies; 18+ messages in thread From: Marten Lindahl @ 2021-12-03 12:02 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Mårten Lindahl, Ulf Hansson, Rob Herring, Jaehoon Chung, Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc On Thu, Dec 02, 2021 at 09:39:30AM +0100, Krzysztof Kozlowski wrote: Hi Krzysztof! Thanks for looking at this! > On 01/12/2021 16:38, Mårten Lindahl wrote: > > Current dw_mci driver supports a TMOUT register which consists of a 24 > > bit field (TMOUT[31:8]) for the DATA_TIMEOUT. The maximum value of this > > field is 0xFFFFFF, which with a 200MHz clock will give a full DRTO of: > > > > 0xFFFFFF / 200000000 => ~84 ms > > > > However, the ARTPEC-8 SoC DWMMC IP version has a TMOUT register with an > > extended DATA_TIMEOUT field, which supports longer timers for the DRTO. > > In this version the DATA_TIMEOUT field is split into two, which with the > > same 200MHz clock as above will allow a maximum timeout of: > > > > ((TMOUT[10:8] -1) * 0xFFFFFF + TMOUT[31:11] * 8) / 200000000 => ~587 ms > > > > Add a quirk to support this. The quirk is enabled for ARTPEC-8 SoCs. > > > > Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> > > --- > > drivers/mmc/host/dw_mmc-exynos.c | 5 +++++ > > drivers/mmc/host/dw_mmc.c | 33 ++++++++++++++++++++++++++++---- > > drivers/mmc/host/dw_mmc.h | 7 +++++++ > > 3 files changed, 41 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c > > index cae7c94b5d6e..6ae9c0ec1282 100644 > > --- a/drivers/mmc/host/dw_mmc-exynos.c > > +++ b/drivers/mmc/host/dw_mmc-exynos.c > > @@ -127,6 +127,11 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) > > DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl); > > } > > > > + if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) { > > + /* Quirk needed for ARTPEC-8 SoCs */ > > + host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT; > > + } > > + > > host->bus_hz /= (priv->ciu_div + 1); > > > > return 0; > > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > > index f2a14a434bef..45ea9fd97a6a 100644 > > --- a/drivers/mmc/host/dw_mmc.c > > +++ b/drivers/mmc/host/dw_mmc.c > > @@ -1289,6 +1289,7 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > > { > > u32 clk_div, tmout; > > u64 tmp; > > + unsigned int tmp2; > > > > clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2; > > if (clk_div == 0) > > @@ -1301,10 +1302,28 @@ static void dw_mci_set_data_timeout(struct dw_mci *host, > > tmout = 0xFF; /* Set maximum */ > > > > /* TMOUT[31:8] (DATA_TIMEOUT) */ > > - if (!tmp || tmp > 0xFFFFFF) > > - tmout |= (0xFFFFFF << 8); > > - else > > - tmout |= (tmp & 0xFFFFFF) << 8; > > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) { > > + /* > > + * Extended HW timer (max = 0x6FFFFF2): > > + * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8) > > + */ > > + if (!tmp || tmp > 0x6FFFFF2) > > + tmout |= (0xFFFFFF << 8); > > + else { > > + /* TMOUT[10:8] */ > > + tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7; > > + tmout |= tmp2 << 8; > > + > > + /* TMOUT[31:11] */ > > + tmp = tmp - ((tmp2 - 1) * 0xFFFFFF); > > + tmout |= (tmp & 0xFFFFF8) << 8; > > + } > > + } else { > > + if (!tmp || tmp > 0xFFFFFF) > > + tmout |= (0xFFFFFF << 8); > > + else > > + tmout |= (tmp & 0xFFFFFF) << 8; > > + } > > > > mci_writel(host, TMOUT, tmout); > > dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: 0x%#08x", > > @@ -2005,9 +2024,15 @@ static void dw_mci_set_drto(struct dw_mci *host) > > if (drto_div == 0) > > drto_div = 1; > > > > + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) > > + drto_clks = (((drto_clks & 0x7) - 1) * 0xFFFFFF) + > > + ((drto_clks & 0xFFFFF8)); > > + > > drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, > > host->bus_hz); > > > > + dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); > > + > > /* add a bit spare time */ > > drto_ms += 10; > > > > diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h > > index 771d5afa3136..071f4479f166 100644 > > --- a/drivers/mmc/host/dw_mmc.h > > +++ b/drivers/mmc/host/dw_mmc.h > > @@ -118,6 +118,7 @@ struct dw_mci_dma_slave { > > * @part_buf: Simple buffer for partial fifo reads/writes. > > * @push_data: Pointer to FIFO push function. > > * @pull_data: Pointer to FIFO pull function. > > + * @quirks: Set of quirks that apply to specific versions of the IP. > > * @vqmmc_enabled: Status of vqmmc, should be true or false. > > * @irq_flags: The flags to be passed to request_irq. > > * @irq: The irq value to be passed to request_irq. > > @@ -223,6 +224,9 @@ struct dw_mci { > > void (*push_data)(struct dw_mci *host, void *buf, int cnt); > > void (*pull_data)(struct dw_mci *host, void *buf, int cnt); > > > > + /* Workaround flags */ > > No need for this comment - you already described the field in kerneldoc. Ok, will remove it. > > > + u32 quirks; > > + > > bool vqmmc_enabled; > > unsigned long irq_flags; /* IRQ flags */ > > int irq; > > @@ -274,6 +278,9 @@ struct dw_mci_board { > > struct dma_pdata *data; > > }; > > > > +/* Support for longer data read timeout */ > > +#define DW_MMC_QUIRK_EXTENDED_TMOUT (1<<0) > > BIT() Will fix. > > > + > > #define DW_MMC_240A 0x240a > > #define DW_MMC_280A 0x280a > > > > > Kind regards Mårten > > Best regards, > Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/4] mmc: dw_mmc: Do not wait for DTO in case of error 2021-12-01 15:38 ` Mårten Lindahl @ 2021-12-01 15:38 ` Mårten Lindahl -1 siblings, 0 replies; 18+ messages in thread From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc, Mårten Lindahl When running the ARTPEC-8 DWMMC IP version, and a data error interrupt comes during a data read transfer, there is no guarantee for the data transfer over interrupt (DTO) to come within the specified data timeout. This case is handled by the dto_timer handler which will complete the request with the comment: /* * If DTO interrupt does NOT come in sending data state, * we should notify the driver to terminate current transfer * and report a data timeout to the core. */ But since the ARTPEC-8 DWMMC IP version, supports an extended TMOUT register which allows longer timeouts than the non ARTPEC-8 version does, waiting for the dto_timer to complete the request in error cases may cause the request to take significantly longer time than necessary. This is specifically true for the failing steps during tuning of a device. Fix this by completing the request when the error interrupt comes. Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> --- drivers/mmc/host/dw_mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 45ea9fd97a6a..d6b76f47b1a2 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2777,11 +2777,19 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) if (pending & DW_MCI_DATA_ERROR_FLAGS) { spin_lock(&host->irq_lock); + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) + del_timer(&host->dto_timer); + /* if there is an error report DATA_ERROR */ mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); host->data_status = pending; smp_wmb(); /* drain writebuffer */ set_bit(EVENT_DATA_ERROR, &host->pending_events); + + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) + /* In case of error, we cannot expect a DTO */ + set_bit(EVENT_DATA_COMPLETE, &host->pending_events); + tasklet_schedule(&host->tasklet); spin_unlock(&host->irq_lock); -- 2.20.1 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/4] mmc: dw_mmc: Do not wait for DTO in case of error @ 2021-12-01 15:38 ` Mårten Lindahl 0 siblings, 0 replies; 18+ messages in thread From: Mårten Lindahl @ 2021-12-01 15:38 UTC (permalink / raw) To: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Jaehoon Chung Cc: Doug Anderson, kernel, linux-mmc, devicetree, linux-arm-kernel, linux-samsung-soc, Mårten Lindahl When running the ARTPEC-8 DWMMC IP version, and a data error interrupt comes during a data read transfer, there is no guarantee for the data transfer over interrupt (DTO) to come within the specified data timeout. This case is handled by the dto_timer handler which will complete the request with the comment: /* * If DTO interrupt does NOT come in sending data state, * we should notify the driver to terminate current transfer * and report a data timeout to the core. */ But since the ARTPEC-8 DWMMC IP version, supports an extended TMOUT register which allows longer timeouts than the non ARTPEC-8 version does, waiting for the dto_timer to complete the request in error cases may cause the request to take significantly longer time than necessary. This is specifically true for the failing steps during tuning of a device. Fix this by completing the request when the error interrupt comes. Signed-off-by: Mårten Lindahl <marten.lindahl@axis.com> --- drivers/mmc/host/dw_mmc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 45ea9fd97a6a..d6b76f47b1a2 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2777,11 +2777,19 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) if (pending & DW_MCI_DATA_ERROR_FLAGS) { spin_lock(&host->irq_lock); + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) + del_timer(&host->dto_timer); + /* if there is an error report DATA_ERROR */ mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); host->data_status = pending; smp_wmb(); /* drain writebuffer */ set_bit(EVENT_DATA_ERROR, &host->pending_events); + + if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) + /* In case of error, we cannot expect a DTO */ + set_bit(EVENT_DATA_COMPLETE, &host->pending_events); + tasklet_schedule(&host->tasklet); spin_unlock(&host->irq_lock); -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 18+ messages in thread
end of thread, other threads:[~2021-12-03 12:04 UTC | newest] Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-12-01 15:38 [PATCH 0/4] Add ARTPEC-8 support to DWMMC controller Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl 2021-12-01 15:38 ` [PATCH 1/4] dt-bindings: mmc: exynos-dw-mshc: Add support for ARTPEC-8 Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl 2021-12-02 8:41 ` Krzysztof Kozlowski 2021-12-02 8:41 ` Krzysztof Kozlowski 2021-12-03 12:00 ` Marten Lindahl 2021-12-03 12:00 ` Marten Lindahl 2021-12-01 15:38 ` [PATCH 2/4] mmc: dw_mmc-exynos: " Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl 2021-12-01 15:38 ` [PATCH 3/4] mmc: dw_mmc: Add quirk for extended data read timeout Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl 2021-12-02 8:39 ` Krzysztof Kozlowski 2021-12-02 8:39 ` Krzysztof Kozlowski 2021-12-03 12:02 ` Marten Lindahl 2021-12-03 12:02 ` Marten Lindahl 2021-12-01 15:38 ` [PATCH 4/4] mmc: dw_mmc: Do not wait for DTO in case of error Mårten Lindahl 2021-12-01 15:38 ` Mårten Lindahl
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