* [PATCHv3 0/2] arm: dts: socfpga: introduce "intel,socfpga-qspi" @ 2021-12-16 22:49 Dinh Nguyen 2021-12-16 22:49 ` [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" Dinh Nguyen 2021-12-16 22:49 ` [PATCHv3 2/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Dinh Nguyen 0 siblings, 2 replies; 6+ messages in thread From: Dinh Nguyen @ 2021-12-16 22:49 UTC (permalink / raw) To: devicetree; +Cc: dinguyen, robh+dt, p.yadav Introduce "intel,socfpga-qspi" as the compatible for the Cadence QSPI controller that is on all flavors of SoCFPGA devices: Cyclone5/Arria5/Arria10/Stratix10/Agilex/N5X The reason for this change is because the standard driver recently introduced a patch to write to the CQSPI_REG_WR_COMPLETION_CTRL without any condition. But the QSPI controller that is on the SoCFPGA platforms does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register, results in a kernel crash. I don't believe we need a chip specific compatible for each chip because the MODULE_ID for all flavors of SoCFPGA is identical. Thus, I think the "intel,socfpga-qspi" compatible is appropriate to cover all variants of the SoCFPGA platform. Dinh Nguyen (2): dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 + arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" 2021-12-16 22:49 [PATCHv3 0/2] arm: dts: socfpga: introduce "intel,socfpga-qspi" Dinh Nguyen @ 2021-12-16 22:49 ` Dinh Nguyen 2021-12-17 3:47 ` Rob Herring ` (2 more replies) 2021-12-16 22:49 ` [PATCHv3 2/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Dinh Nguyen 1 sibling, 3 replies; 6+ messages in thread From: Dinh Nguyen @ 2021-12-16 22:49 UTC (permalink / raw) To: devicetree; +Cc: dinguyen, robh+dt, p.yadav The QSPI controller on Intel's SoCFPGA platform does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash. Introduce the dts compatible "intel,socfpga-qspi" to differentiate the hardware. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: revert to "intel,socfpga-qspi" v2: change binding to "cdns,qspi-nor-0010" to be more generic for other platforms --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index ca155abbda7a..037f41f58503 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -29,6 +29,7 @@ properties: - ti,am654-ospi - intel,lgm-qspi - xlnx,versal-ospi-1.0 + - intel,socfpga-qspi - const: cdns,qspi-nor - const: cdns,qspi-nor -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" 2021-12-16 22:49 ` [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" Dinh Nguyen @ 2021-12-17 3:47 ` Rob Herring 2021-12-17 8:52 ` Pratyush Yadav 2021-12-21 17:05 ` Rob Herring 2 siblings, 0 replies; 6+ messages in thread From: Rob Herring @ 2021-12-17 3:47 UTC (permalink / raw) To: Dinh Nguyen; +Cc: robh+dt, p.yadav, devicetree On Thu, 16 Dec 2021 16:49:01 -0600, Dinh Nguyen wrote: > The QSPI controller on Intel's SoCFPGA platform does not implement the > CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register > results in a crash. > > Introduce the dts compatible "intel,socfpga-qspi" to differentiate the > hardware. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > v3: revert to "intel,socfpga-qspi" > v2: change binding to "cdns,qspi-nor-0010" to be more generic for other > platforms > --- > Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 + > 1 file changed, 1 insertion(+) > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/1569624 spi@ff705000: resets: [[6, 37]] is too short arch/arm/boot/dts/socfpga_arria5_socdk.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_socdk.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_sockit.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_socrates.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_sodia.dt.yaml arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dt.yaml arch/arm/boot/dts/socfpga_vt.dt.yaml ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" 2021-12-16 22:49 ` [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" Dinh Nguyen 2021-12-17 3:47 ` Rob Herring @ 2021-12-17 8:52 ` Pratyush Yadav 2021-12-21 17:05 ` Rob Herring 2 siblings, 0 replies; 6+ messages in thread From: Pratyush Yadav @ 2021-12-17 8:52 UTC (permalink / raw) To: Dinh Nguyen; +Cc: devicetree, robh+dt On 16/12/21 04:49PM, Dinh Nguyen wrote: > The QSPI controller on Intel's SoCFPGA platform does not implement the > CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register > results in a crash. > > Introduce the dts compatible "intel,socfpga-qspi" to differentiate the > hardware. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Pratyush Yadav <p.yadav@ti.com> -- Regards, Pratyush Yadav Texas Instruments Inc. ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" 2021-12-16 22:49 ` [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" Dinh Nguyen 2021-12-17 3:47 ` Rob Herring 2021-12-17 8:52 ` Pratyush Yadav @ 2021-12-21 17:05 ` Rob Herring 2 siblings, 0 replies; 6+ messages in thread From: Rob Herring @ 2021-12-21 17:05 UTC (permalink / raw) To: Dinh Nguyen; +Cc: devicetree, robh+dt, p.yadav On Thu, 16 Dec 2021 16:49:01 -0600, Dinh Nguyen wrote: > The QSPI controller on Intel's SoCFPGA platform does not implement the > CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register > results in a crash. > > Introduce the dts compatible "intel,socfpga-qspi" to differentiate the > hardware. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > v3: revert to "intel,socfpga-qspi" > v2: change binding to "cdns,qspi-nor-0010" to be more generic for other > platforms > --- > Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCHv3 2/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" 2021-12-16 22:49 [PATCHv3 0/2] arm: dts: socfpga: introduce "intel,socfpga-qspi" Dinh Nguyen 2021-12-16 22:49 ` [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" Dinh Nguyen @ 2021-12-16 22:49 ` Dinh Nguyen 1 sibling, 0 replies; 6+ messages in thread From: Dinh Nguyen @ 2021-12-16 22:49 UTC (permalink / raw) To: devicetree; +Cc: dinguyen, robh+dt, p.yadav Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"), which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register regardless of any condition. Well, the Cadence QuadSPI controller on Intel's SoCFPGA platforms does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash! So starting with v5.16, I introduced the patch 98d948eb833 ("spi: cadence-quadspi: fix write completion support"), which adds the dts compatible "intel,socfpga-qspi" that is specific for versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: revert back to "intel,socfpga-qspi" v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010" --- arch/arm/boot/dts/socfpga.dtsi | 2 +- arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 0b021eef0b53..7c1d6423d7f8 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -782,7 +782,7 @@ ocram: sram@ffff0000 { }; qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index a574ea91d9d3..3ba431dfa8c9 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -756,7 +756,7 @@ usb0-ecc@ff8c8800 { }; qspi: spi@ff809000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff809000 0x100>, diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index d301ac0d406b..3ec301bd08a9 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -594,7 +594,7 @@ emac0-tx-ecc@ff8c0400 { }; qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 163f33b46e4f..0dd2d2ee765a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -628,7 +628,7 @@ sdmmca-ecc@ff8c8c00 { }; qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff8d2000 0x100>, -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-12-21 17:05 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-12-16 22:49 [PATCHv3 0/2] arm: dts: socfpga: introduce "intel,socfpga-qspi" Dinh Nguyen 2021-12-16 22:49 ` [PATCHv3 1/2] dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" Dinh Nguyen 2021-12-17 3:47 ` Rob Herring 2021-12-17 8:52 ` Pratyush Yadav 2021-12-21 17:05 ` Rob Herring 2021-12-16 22:49 ` [PATCHv3 2/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Dinh Nguyen
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