From: <conor.dooley@microchip.com> To: <linus.walleij@linaro.org>, <bgolaszewski@baylibre.com>, <robh+dt@kernel.org>, <jassisinghbrar@gmail.com>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <a.zummo@towertech.it>, <alexandre.belloni@bootlin.com>, <broonie@kernel.org>, <gregkh@linuxfoundation.org>, <thierry.reding@gmail.com>, <u.kleine-koenig@pengutronix.de>, <lee.jones@linaro.org>, <linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-i2c@vger.kernel.org>, <linux-pwm@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-crypto@vger.kernel.org>, <linux-rtc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-usb@vger.kernel.org> Cc: <krzysztof.kozlowski@canonical.com>, <geert@linux-m68k.org>, <bin.meng@windriver.com>, <heiko@sntech.de>, <lewis.hanly@microchip.com>, <conor.dooley@microchip.com>, <daire.mcnamara@microchip.com>, <ivan.griffin@microchip.com>, <atish.patra@wdc.com> Subject: [PATCH v2 16/17] riscv: dts: microchip: update peripherals in icicle kit device tree Date: Fri, 17 Dec 2021 09:33:24 +0000 [thread overview] Message-ID: <20211217093325.30612-17-conor.dooley@microchip.com> (raw) In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> From: Conor Dooley <conor.dooley@microchip.com> Add new peripherals to the MPFS, and enable them in the Icicle kit device tree: 2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller, USB host & system controller. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 171 ++++++++++++++++++ 2 files changed, 224 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index f6542ef76046..13172dec8e9f 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -80,6 +80,26 @@ &mmc { sd-uhs-sdr104; }; +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + &mac0 { phy-mode = "sgmii"; phy-handle = <&phy0>; @@ -99,6 +119,39 @@ phy0: ethernet-phy@8 { }; }; +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; + +&mbox { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + &corePWM0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index d311c5ea27c9..2de9b23af46d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -276,6 +276,69 @@ mmc: mmc@20008000 { status = "disabled"; }; + spi0: spi@20108000 { + compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20108000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <54>; + clocks = <&clkcfg CLK_SPI0>; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + + spi1: spi@20109000 { + compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20109000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <55>; + clocks = <&clkcfg CLK_SPI1>; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + + qspi: spi@21000000 { + compatible = "microchip,mpfs-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21000000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <85>; + clocks = <&clkcfg CLK_QSPI>; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + + i2c0: i2c@2010a000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x0 0x2010a000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clkcfg CLK_I2C0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x0 0x2010b000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg CLK_I2C1>; + clock-frequency = <100000>; + status = "disabled"; + }; + mac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; @@ -301,5 +364,113 @@ mac1: ethernet@20112000 { clock-names = "pclk", "hclk"; status = "disabled"; }; + + gpio0: gpio@20120000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20120000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@20121000 { + compatible = "microchip,mpfs-gpio"; + reg = <000 0x20121000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + rtc: rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x0 0x20124000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <80>, <81>; + clocks = <&clkcfg CLK_RTC>; + clock-names = "rtc"; + status = "disabled"; + }; + + usb: usb@20201000 { + compatible = "microchip,mpfs-musb"; + reg = <0x0 0x20201000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <86>, <87>; + clocks = <&clkcfg CLK_USB>; + interrupt-names = "dma","mc"; + status = "disabled"; + }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; + clock-names = "fic0", "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + microchip,axi-m-atr0 = <0x10 0x0>; + status = "disabled"; + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + mbox: mailbox@37020000 { + compatible = "microchip,mpfs-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + interrupt-parent = <&plic>; + interrupts = <96>; + #mbox-cells = <1>; + status = "disabled"; + }; + + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller", "simple-mfd"; + mboxes = <&mbox 0>; + + hwrandom: hwrandom { + compatible = "microchip,mpfs-rng"; + }; + + sysserv: sysserv { + compatible = "microchip,mpfs-generic-service"; + }; + }; }; }; -- 2.33.1
WARNING: multiple messages have this Message-ID (diff)
From: <conor.dooley@microchip.com> To: <linus.walleij@linaro.org>, <bgolaszewski@baylibre.com>, <robh+dt@kernel.org>, <jassisinghbrar@gmail.com>, <paul.walmsley@sifive.com>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <a.zummo@towertech.it>, <alexandre.belloni@bootlin.com>, <broonie@kernel.org>, <gregkh@linuxfoundation.org>, <thierry.reding@gmail.com>, <u.kleine-koenig@pengutronix.de>, <lee.jones@linaro.org>, <linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-i2c@vger.kernel.org>, <linux-pwm@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-crypto@vger.kernel.org>, <linux-rtc@vger.kernel.org>, <linux-spi@vger.kernel.org>, <linux-usb@vger.kernel.org> Cc: <krzysztof.kozlowski@canonical.com>, <geert@linux-m68k.org>, <bin.meng@windriver.com>, <heiko@sntech.de>, <lewis.hanly@microchip.com>, <conor.dooley@microchip.com>, <daire.mcnamara@microchip.com>, <ivan.griffin@microchip.com>, <atish.patra@wdc.com> Subject: [PATCH v2 16/17] riscv: dts: microchip: update peripherals in icicle kit device tree Date: Fri, 17 Dec 2021 09:33:24 +0000 [thread overview] Message-ID: <20211217093325.30612-17-conor.dooley@microchip.com> (raw) In-Reply-To: <20211217093325.30612-1-conor.dooley@microchip.com> From: Conor Dooley <conor.dooley@microchip.com> Add new peripherals to the MPFS, and enable them in the Icicle kit device tree: 2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller, USB host & system controller. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- .../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 171 ++++++++++++++++++ 2 files changed, 224 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index f6542ef76046..13172dec8e9f 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -80,6 +80,26 @@ &mmc { sd-uhs-sdr104; }; +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + &mac0 { phy-mode = "sgmii"; phy-handle = <&phy0>; @@ -99,6 +119,39 @@ phy0: ethernet-phy@8 { }; }; +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; + +&mbox { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + &corePWM0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index d311c5ea27c9..2de9b23af46d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -276,6 +276,69 @@ mmc: mmc@20008000 { status = "disabled"; }; + spi0: spi@20108000 { + compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20108000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <54>; + clocks = <&clkcfg CLK_SPI0>; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + + spi1: spi@20109000 { + compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20109000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <55>; + clocks = <&clkcfg CLK_SPI1>; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + + qspi: spi@21000000 { + compatible = "microchip,mpfs-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21000000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <85>; + clocks = <&clkcfg CLK_QSPI>; + spi-max-frequency = <25000000>; + num-cs = <8>; + status = "disabled"; + }; + + i2c0: i2c@2010a000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x0 0x2010a000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clkcfg CLK_I2C0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x0 0x2010b000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg CLK_I2C1>; + clock-frequency = <100000>; + status = "disabled"; + }; + mac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; @@ -301,5 +364,113 @@ mac1: ethernet@20112000 { clock-names = "pclk", "hclk"; status = "disabled"; }; + + gpio0: gpio@20120000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20120000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@20121000 { + compatible = "microchip,mpfs-gpio"; + reg = <000 0x20121000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + rtc: rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x0 0x20124000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <80>, <81>; + clocks = <&clkcfg CLK_RTC>; + clock-names = "rtc"; + status = "disabled"; + }; + + usb: usb@20201000 { + compatible = "microchip,mpfs-musb"; + reg = <0x0 0x20201000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <86>, <87>; + clocks = <&clkcfg CLK_USB>; + interrupt-names = "dma","mc"; + status = "disabled"; + }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; + clock-names = "fic0", "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + microchip,axi-m-atr0 = <0x10 0x0>; + status = "disabled"; + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + mbox: mailbox@37020000 { + compatible = "microchip,mpfs-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + interrupt-parent = <&plic>; + interrupts = <96>; + #mbox-cells = <1>; + status = "disabled"; + }; + + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller", "simple-mfd"; + mboxes = <&mbox 0>; + + hwrandom: hwrandom { + compatible = "microchip,mpfs-rng"; + }; + + sysserv: sysserv { + compatible = "microchip,mpfs-generic-service"; + }; + }; }; }; -- 2.33.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-12-17 9:34 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-12-17 9:33 [PATCH v2 00/17] Update the Icicle Kit device tree conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 9:33 ` [PATCH v2 01/17] dt-bindings: interrupt-controller: create a header for RISC-V interrupts conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-21 17:47 ` Rob Herring 2021-12-21 17:47 ` Rob Herring 2021-12-17 9:33 ` [PATCH v2 02/17] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 13:24 ` Geert Uytterhoeven 2021-12-17 13:24 ` Geert Uytterhoeven 2021-12-17 14:21 ` Rob Herring 2021-12-17 14:21 ` Rob Herring 2021-12-17 9:33 ` [PATCH v2 03/17] dt-bindings: soc/microchip: make systemcontroller a mfd conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-21 17:55 ` Rob Herring 2021-12-21 17:55 ` Rob Herring 2021-12-21 23:50 ` conor dooley 2021-12-21 23:50 ` conor dooley 2021-12-17 9:33 ` [PATCH v2 04/17] mailbox: change mailbox-mpfs compatible string conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 13:25 ` Geert Uytterhoeven 2021-12-17 13:25 ` Geert Uytterhoeven 2021-12-17 9:33 ` [PATCH v2 05/17] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 14:21 ` Rob Herring 2021-12-17 14:21 ` Rob Herring 2021-12-17 9:33 ` [PATCH v2 06/17] dt-bindings: rng: add bindings for microchip mpfs rng conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 14:53 ` Krzysztof Kozlowski 2021-12-17 14:53 ` Krzysztof Kozlowski 2021-12-17 15:07 ` Krzysztof Kozlowski 2021-12-17 15:07 ` Krzysztof Kozlowski 2021-12-17 15:22 ` Conor.Dooley 2021-12-17 15:22 ` Conor.Dooley 2021-12-17 15:47 ` Krzysztof Kozlowski 2021-12-17 15:47 ` Krzysztof Kozlowski 2021-12-17 16:26 ` conor dooley 2021-12-17 16:26 ` conor dooley 2021-12-17 9:33 ` [PATCH v2 07/17] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 14:21 ` Rob Herring 2021-12-17 14:21 ` Rob Herring 2021-12-20 14:37 ` Rob Herring 2021-12-20 14:37 ` Rob Herring 2021-12-17 9:33 ` [PATCH v2 08/17] dt-bindings: soc/microchip: add bindings for mpfs system services conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 9:33 ` [PATCH v2 09/17] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 14:21 ` Rob Herring 2021-12-17 14:21 ` Rob Herring 2021-12-17 9:33 ` [PATCH v2 10/17] dt-bindings: spi: add bindings for microchip mpfs spi conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 11:17 ` Mark Brown 2021-12-17 11:17 ` Mark Brown 2021-12-17 11:40 ` Conor.Dooley 2021-12-17 11:40 ` Conor.Dooley 2021-12-17 11:43 ` Mark Brown 2021-12-17 11:43 ` Mark Brown 2021-12-20 8:05 ` Conor.Dooley 2021-12-20 8:05 ` Conor.Dooley 2021-12-17 14:21 ` Rob Herring 2021-12-17 14:21 ` Rob Herring 2021-12-17 9:33 ` [PATCH v2 11/17] dt-bindings: usb: add bindings for microchip mpfs musb conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 14:21 ` Rob Herring 2021-12-17 14:21 ` Rob Herring 2021-12-21 13:32 ` Rob Herring 2021-12-21 13:32 ` Rob Herring 2021-12-17 9:33 ` [PATCH v2 12/17] dt-bindings: pwm: add microchip corePWM binding conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 14:21 ` Rob Herring 2021-12-17 14:21 ` Rob Herring 2021-12-17 14:58 ` Krzysztof Kozlowski 2021-12-17 14:58 ` Krzysztof Kozlowski 2021-12-17 9:33 ` [PATCH v2 13/17] riscv: dts: microchip: use hart and clk defines for icicle kit conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 13:40 ` Geert Uytterhoeven 2021-12-17 13:40 ` Geert Uytterhoeven 2021-12-17 9:33 ` [PATCH v2 14/17] riscv: dts: microchip: add fpga fabric section to " conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 13:43 ` Geert Uytterhoeven 2021-12-17 13:43 ` Geert Uytterhoeven 2021-12-17 15:32 ` Conor.Dooley 2021-12-17 15:32 ` Conor.Dooley 2021-12-17 16:00 ` Geert Uytterhoeven 2021-12-17 16:00 ` Geert Uytterhoeven 2022-01-12 9:38 ` Conor.Dooley 2022-01-12 9:38 ` Conor.Dooley 2022-01-14 13:35 ` Conor.Dooley 2022-01-14 13:35 ` Conor.Dooley 2021-12-17 14:59 ` Krzysztof Kozlowski 2021-12-17 14:59 ` Krzysztof Kozlowski 2021-12-17 9:33 ` [PATCH v2 15/17] riscv: dts: microchip: refactor icicle kit device tree conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 15:04 ` Krzysztof Kozlowski 2021-12-17 15:04 ` Krzysztof Kozlowski 2021-12-17 15:23 ` Conor.Dooley 2021-12-17 15:23 ` Conor.Dooley 2021-12-17 9:33 ` conor.dooley [this message] 2021-12-17 9:33 ` [PATCH v2 16/17] riscv: dts: microchip: update peripherals in " conor.dooley 2021-12-17 9:33 ` [PATCH v2 17/17] MAINTAINERS: update riscv/microchip entry conor.dooley 2021-12-17 9:33 ` conor.dooley 2021-12-17 15:09 ` Krzysztof Kozlowski 2021-12-17 15:09 ` Krzysztof Kozlowski 2021-12-23 14:56 ` Conor.Dooley 2021-12-23 14:56 ` Conor.Dooley 2021-12-23 17:36 ` Palmer Dabbelt 2021-12-23 17:36 ` Palmer Dabbelt 2022-01-12 13:32 ` Lewis.Hanly 2022-01-12 13:32 ` Lewis.Hanly 2021-12-17 9:48 ` [PATCH v2 00/17] Update the Icicle Kit device tree Geert Uytterhoeven 2021-12-17 9:48 ` Geert Uytterhoeven
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20211217093325.30612-17-conor.dooley@microchip.com \ --to=conor.dooley@microchip.com \ --cc=a.zummo@towertech.it \ --cc=alexandre.belloni@bootlin.com \ --cc=aou@eecs.berkeley.edu \ --cc=atish.patra@wdc.com \ --cc=bgolaszewski@baylibre.com \ --cc=bin.meng@windriver.com \ --cc=broonie@kernel.org \ --cc=daire.mcnamara@microchip.com \ --cc=devicetree@vger.kernel.org \ --cc=geert@linux-m68k.org \ --cc=gregkh@linuxfoundation.org \ --cc=heiko@sntech.de \ --cc=ivan.griffin@microchip.com \ --cc=jassisinghbrar@gmail.com \ --cc=krzysztof.kozlowski@canonical.com \ --cc=lee.jones@linaro.org \ --cc=lewis.hanly@microchip.com \ --cc=linus.walleij@linaro.org \ --cc=linux-crypto@vger.kernel.org \ --cc=linux-gpio@vger.kernel.org \ --cc=linux-i2c@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-pwm@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=linux-rtc@vger.kernel.org \ --cc=linux-spi@vger.kernel.org \ --cc=linux-usb@vger.kernel.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=robh+dt@kernel.org \ --cc=thierry.reding@gmail.com \ --cc=u.kleine-koenig@pengutronix.de \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.