* [PATCH v8 00/14] Add support for Airoha EN7523 SoC
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Matthias Brugger; +Cc: john, linux-mediatek
This patchset adds support for the Airoha EN7523 SoC, intended primarily
for xPON/xDSL routers.
Felix Fietkau (4):
clk: en7523: Add clock driver for Airoha EN7523 SoC
ARM: dts: add clock support for Airoha EN7523
PCI: mediatek: Allow building for ARCH_AIROHA
ARM: dts: Add PCIe support for Airoha EN7523
John Crispin (10):
dt-bindings: Add vendor prefix for Airoha
dt-bindings: arm: airoha: Add binding for EN7523 SoC and EVB
ARM: dts: Add basic support for Airoha EN7523
ARM: Add basic support for Airoha EN7523 SoC
ARM: multi_v7_defconfig: Add support for Airoha EN7523 SoC
dt-bindings: Add en7523-scu device tree binding documentation
dt-bindings: PCI: Add support for Airoha EN7532
dt-bindings: arm: airoha: Add binding for Airoha GPIO controller
gpio: Add support for Airoha EN7523 GPIO controller
ARM: dts: add GPIO support for Airoha EN7523
.../devicetree/bindings/arm/airoha.yaml | 28 ++
.../bindings/clock/airoha,en7523-scu.yaml | 58 +++
.../bindings/gpio/airoha,en7523-gpio.yaml | 67 ++++
.../devicetree/bindings/pci/mediatek-pcie.txt | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm/Kconfig | 12 +
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/en7523-evb.dts | 43 +++
arch/arm/boot/dts/en7523.dtsi | 202 ++++++++++
arch/arm/configs/multi_v7_defconfig | 1 +
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-en7523.c | 350 ++++++++++++++++++
drivers/gpio/Kconfig | 9 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-en7523.c | 134 +++++++
drivers/pci/controller/Kconfig | 2 +-
include/dt-bindings/clock/en7523-clk.h | 17 +
18 files changed, 938 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/airoha.yaml
create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
create mode 100644 Documentation/devicetree/bindings/gpio/airoha,en7523-gpio.yaml
create mode 100644 arch/arm/boot/dts/en7523-evb.dts
create mode 100644 arch/arm/boot/dts/en7523.dtsi
create mode 100644 drivers/clk/clk-en7523.c
create mode 100644 drivers/gpio/gpio-en7523.c
create mode 100644 include/dt-bindings/clock/en7523-clk.h
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v8 01/14] dt-bindings: Add vendor prefix for Airoha
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring; +Cc: john, Rob Herring, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Add vendor prefix "airoha" for Airoha, a subsidiary of MediaTek
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 66d6432fd781..025df36aee5f 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -59,6 +59,8 @@ patternProperties:
description: Aeroflex Gaisler AB
"^aesop,.*":
description: AESOP Embedded Forum
+ "^airoha,.*":
+ description: Airoha
"^al,.*":
description: Annapurna Labs
"^alcatel,.*":
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 01/14] dt-bindings: Add vendor prefix for Airoha
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring; +Cc: john, Rob Herring, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Add vendor prefix "airoha" for Airoha, a subsidiary of MediaTek
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 66d6432fd781..025df36aee5f 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -59,6 +59,8 @@ patternProperties:
description: Aeroflex Gaisler AB
"^aesop,.*":
description: AESOP Embedded Forum
+ "^airoha,.*":
+ description: Airoha
"^al,.*":
description: Annapurna Labs
"^alcatel,.*":
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v8 01/14] dt-bindings: Add vendor prefix for Airoha
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-29 14:47 ` Matthias Brugger
-1 siblings, 0 replies; 60+ messages in thread
From: Matthias Brugger @ 2021-12-29 14:47 UTC (permalink / raw)
To: Felix Fietkau, linux-arm-kernel, Rob Herring
Cc: john, Rob Herring, devicetree, linux-kernel
On 20/12/2021 22:18, Felix Fietkau wrote:
> From: John Crispin <john@phrozen.org>
>
> Add vendor prefix "airoha" for Airoha, a subsidiary of MediaTek
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Bert Vermeulen <bert@biot.com>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
Applied to v5.16-tmp/dts32
Please add the linux mediatek mailinglist for any further patches so that I can
track them.
Regards,
Matthias
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 66d6432fd781..025df36aee5f 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -59,6 +59,8 @@ patternProperties:
> description: Aeroflex Gaisler AB
> "^aesop,.*":
> description: AESOP Embedded Forum
> + "^airoha,.*":
> + description: Airoha
> "^al,.*":
> description: Annapurna Labs
> "^alcatel,.*":
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 01/14] dt-bindings: Add vendor prefix for Airoha
@ 2021-12-29 14:47 ` Matthias Brugger
0 siblings, 0 replies; 60+ messages in thread
From: Matthias Brugger @ 2021-12-29 14:47 UTC (permalink / raw)
To: Felix Fietkau, linux-arm-kernel, Rob Herring
Cc: john, Rob Herring, devicetree, linux-kernel
On 20/12/2021 22:18, Felix Fietkau wrote:
> From: John Crispin <john@phrozen.org>
>
> Add vendor prefix "airoha" for Airoha, a subsidiary of MediaTek
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Bert Vermeulen <bert@biot.com>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
Applied to v5.16-tmp/dts32
Please add the linux mediatek mailinglist for any further patches so that I can
track them.
Regards,
Matthias
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 66d6432fd781..025df36aee5f 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -59,6 +59,8 @@ patternProperties:
> description: Aeroflex Gaisler AB
> "^aesop,.*":
> description: AESOP Embedded Forum
> + "^airoha,.*":
> + description: Airoha
> "^al,.*":
> description: Annapurna Labs
> "^alcatel,.*":
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v8 02/14] dt-bindings: arm: airoha: Add binding for EN7523 SoC and EVB
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring, John Crispin
Cc: Rob Herring, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Add devicetree binding for Airoha EN7523 SoC and evaluation board.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
.../devicetree/bindings/arm/airoha.yaml | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/airoha.yaml
diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml
new file mode 100644
index 000000000000..fc19b1a6f37b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/airoha.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/airoha.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha SoC based Platforms Device Tree Bindings
+
+maintainers:
+ - Felix Fietkau <nbd@nbd.name>
+ - John Crispin <john@phrozen.org>
+
+description:
+ Boards with an Airoha SoC shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - airoha,en7523-evb
+ - const: airoha,en7523
+
+additionalProperties: true
+
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 02/14] dt-bindings: arm: airoha: Add binding for EN7523 SoC and EVB
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring, John Crispin
Cc: Rob Herring, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Add devicetree binding for Airoha EN7523 SoC and evaluation board.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
.../devicetree/bindings/arm/airoha.yaml | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/airoha.yaml
diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml
new file mode 100644
index 000000000000..fc19b1a6f37b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/airoha.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/airoha.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha SoC based Platforms Device Tree Bindings
+
+maintainers:
+ - Felix Fietkau <nbd@nbd.name>
+ - John Crispin <john@phrozen.org>
+
+description:
+ Boards with an Airoha SoC shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - airoha,en7523-evb
+ - const: airoha,en7523
+
+additionalProperties: true
+
+...
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [PATCH v8 02/14] dt-bindings: arm: airoha: Add binding for EN7523 SoC and EVB
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-29 14:48 ` Matthias Brugger
-1 siblings, 0 replies; 60+ messages in thread
From: Matthias Brugger @ 2021-12-29 14:48 UTC (permalink / raw)
To: Felix Fietkau, linux-arm-kernel, Rob Herring, John Crispin
Cc: Rob Herring, devicetree, linux-kernel
On 20/12/2021 22:18, Felix Fietkau wrote:
> From: John Crispin <john@phrozen.org>
>
> Add devicetree binding for Airoha EN7523 SoC and evaluation board.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Bert Vermeulen <bert@biot.com>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
Now part of v5.17-tmp/dts32
Thanks.
> ---
> .../devicetree/bindings/arm/airoha.yaml | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/airoha.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml
> new file mode 100644
> index 000000000000..fc19b1a6f37b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/airoha.yaml
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/airoha.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha SoC based Platforms Device Tree Bindings
> +
> +maintainers:
> + - Felix Fietkau <nbd@nbd.name>
> + - John Crispin <john@phrozen.org>
> +
> +description:
> + Boards with an Airoha SoC shall have the following properties.
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - airoha,en7523-evb
> + - const: airoha,en7523
> +
> +additionalProperties: true
> +
> +...
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 02/14] dt-bindings: arm: airoha: Add binding for EN7523 SoC and EVB
@ 2021-12-29 14:48 ` Matthias Brugger
0 siblings, 0 replies; 60+ messages in thread
From: Matthias Brugger @ 2021-12-29 14:48 UTC (permalink / raw)
To: Felix Fietkau, linux-arm-kernel, Rob Herring, John Crispin
Cc: Rob Herring, devicetree, linux-kernel
On 20/12/2021 22:18, Felix Fietkau wrote:
> From: John Crispin <john@phrozen.org>
>
> Add devicetree binding for Airoha EN7523 SoC and evaluation board.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Bert Vermeulen <bert@biot.com>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
Now part of v5.17-tmp/dts32
Thanks.
> ---
> .../devicetree/bindings/arm/airoha.yaml | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/airoha.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml
> new file mode 100644
> index 000000000000..fc19b1a6f37b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/airoha.yaml
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/airoha.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha SoC based Platforms Device Tree Bindings
> +
> +maintainers:
> + - Felix Fietkau <nbd@nbd.name>
> + - John Crispin <john@phrozen.org>
> +
> +description:
> + Boards with an Airoha SoC shall have the following properties.
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - airoha,en7523-evb
> + - const: airoha,en7523
> +
> +additionalProperties: true
> +
> +...
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v8 03/14] ARM: dts: Add basic support for Airoha EN7523
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Arnd Bergmann, Olof Johansson, soc, Rob Herring
Cc: john, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Add basic support for Airoha EN7523, enough for booting to console.
The UART is basically 8250-compatible, except for the clock selection.
A clock-frequency value is synthesized to get this to run at 115200 bps.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++
arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++
3 files changed, 143 insertions(+)
create mode 100644 arch/arm/boot/dts/en7523-evb.dts
create mode 100644 arch/arm/boot/dts/en7523.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0de64f237cd8..81cb49f8d6fd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -186,6 +186,8 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-lego-ev3.dtb
dtb-$(CONFIG_ARCH_DIGICOLOR) += \
cx92755_equinox.dtb
+dtb-$(CONFIG_ARCH_AIROHA) += \
+ en7523-evb.dtb
dtb-$(CONFIG_ARCH_EXYNOS3) += \
exynos3250-artik5-eval.dtb \
exynos3250-monk.dtb \
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
new file mode 100644
index 000000000000..69754ef9a628
--- /dev/null
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+/* Bootloader installs ATF here */
+/memreserve/ 0x80000000 0x200000;
+
+#include "en7523.dtsi"
+
+/ {
+ model = "Airoha EN7523 Evaluation Board";
+ compatible = "airoha,en7523-evb", "airoha,en7523";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ stdout-path = "serial0:115200n8";
+ linux,usable-memory-range = <0x80200000 0x1fe00000>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
new file mode 100644
index 000000000000..7e17311a3f90
--- /dev/null
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ npu_binary@84000000 {
+ no-map;
+ reg = <0x84000000 0xA00000>;
+ };
+
+ npu_flag@84B0000 {
+ no-map;
+ reg = <0x84B00000 0x100000>;
+ };
+
+ npu_pkt@85000000 {
+ no-map;
+ reg = <0x85000000 0x1A00000>;
+ };
+
+ npu_phyaddr@86B00000 {
+ no-map;
+ reg = <0x86B00000 0x100000>;
+ };
+
+ npu_rxdesc@86D00000 {
+ no-map;
+ reg = <0x86D00000 0x100000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ gic: interrupt-controller@9000000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x09000000 0x20000>, <0x09080000 0x80000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <25000000>;
+ };
+
+ uart1: serial@1fbf0000 {
+ compatible = "ns16550";
+ reg = <0x1fbf0000 0x30>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <1843200>;
+ status = "okay";
+ };
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 03/14] ARM: dts: Add basic support for Airoha EN7523
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Arnd Bergmann, Olof Johansson, soc, Rob Herring
Cc: john, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Add basic support for Airoha EN7523, enough for booting to console.
The UART is basically 8250-compatible, except for the clock selection.
A clock-frequency value is synthesized to get this to run at 115200 bps.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++
arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++
3 files changed, 143 insertions(+)
create mode 100644 arch/arm/boot/dts/en7523-evb.dts
create mode 100644 arch/arm/boot/dts/en7523.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0de64f237cd8..81cb49f8d6fd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -186,6 +186,8 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-lego-ev3.dtb
dtb-$(CONFIG_ARCH_DIGICOLOR) += \
cx92755_equinox.dtb
+dtb-$(CONFIG_ARCH_AIROHA) += \
+ en7523-evb.dtb
dtb-$(CONFIG_ARCH_EXYNOS3) += \
exynos3250-artik5-eval.dtb \
exynos3250-monk.dtb \
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
new file mode 100644
index 000000000000..69754ef9a628
--- /dev/null
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+/* Bootloader installs ATF here */
+/memreserve/ 0x80000000 0x200000;
+
+#include "en7523.dtsi"
+
+/ {
+ model = "Airoha EN7523 Evaluation Board";
+ compatible = "airoha,en7523-evb", "airoha,en7523";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ stdout-path = "serial0:115200n8";
+ linux,usable-memory-range = <0x80200000 0x1fe00000>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
new file mode 100644
index 000000000000..7e17311a3f90
--- /dev/null
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ npu_binary@84000000 {
+ no-map;
+ reg = <0x84000000 0xA00000>;
+ };
+
+ npu_flag@84B0000 {
+ no-map;
+ reg = <0x84B00000 0x100000>;
+ };
+
+ npu_pkt@85000000 {
+ no-map;
+ reg = <0x85000000 0x1A00000>;
+ };
+
+ npu_phyaddr@86B00000 {
+ no-map;
+ reg = <0x86B00000 0x100000>;
+ };
+
+ npu_rxdesc@86D00000 {
+ no-map;
+ reg = <0x86D00000 0x100000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ gic: interrupt-controller@9000000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x09000000 0x20000>, <0x09080000 0x80000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <25000000>;
+ };
+
+ uart1: serial@1fbf0000 {
+ compatible = "ns16550";
+ reg = <0x1fbf0000 0x30>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <1843200>;
+ status = "okay";
+ };
+};
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v8 03/14] ARM: dts: Add basic support for Airoha EN7523
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-21 15:02 ` Marc Zyngier
-1 siblings, 0 replies; 60+ messages in thread
From: Marc Zyngier @ 2021-12-21 15:02 UTC (permalink / raw)
To: Felix Fietkau
Cc: linux-arm-kernel, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, john, devicetree, linux-kernel
On 2021-12-20 21:18, Felix Fietkau wrote:
> From: John Crispin <john@phrozen.org>
>
> Add basic support for Airoha EN7523, enough for booting to console.
>
> The UART is basically 8250-compatible, except for the clock selection.
> A clock-frequency value is synthesized to get this to run at 115200
> bps.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Bert Vermeulen <bert@biot.com>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++
> arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++
> 3 files changed, 143 insertions(+)
> create mode 100644 arch/arm/boot/dts/en7523-evb.dts
> create mode 100644 arch/arm/boot/dts/en7523.dtsi
>
[...]
> + gic: interrupt-controller@9000000 {
> + compatible = "arm,gic-v3";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x09000000 0x20000>, <0x09080000 0x80000>;
You are missing the 3 extra regions implemented by the A53 cores
(GICC, GICV, GICH). Please see the binding and the A53 TRM.
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
This is an ARMv8 CPU, even when used in 32bit mode.
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <25000000>;
Why isn't this properly configured by the firmware?
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 03/14] ARM: dts: Add basic support for Airoha EN7523
@ 2021-12-21 15:02 ` Marc Zyngier
0 siblings, 0 replies; 60+ messages in thread
From: Marc Zyngier @ 2021-12-21 15:02 UTC (permalink / raw)
To: Felix Fietkau
Cc: linux-arm-kernel, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, john, devicetree, linux-kernel
On 2021-12-20 21:18, Felix Fietkau wrote:
> From: John Crispin <john@phrozen.org>
>
> Add basic support for Airoha EN7523, enough for booting to console.
>
> The UART is basically 8250-compatible, except for the clock selection.
> A clock-frequency value is synthesized to get this to run at 115200
> bps.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Bert Vermeulen <bert@biot.com>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++
> arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++
> 3 files changed, 143 insertions(+)
> create mode 100644 arch/arm/boot/dts/en7523-evb.dts
> create mode 100644 arch/arm/boot/dts/en7523.dtsi
>
[...]
> + gic: interrupt-controller@9000000 {
> + compatible = "arm,gic-v3";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x09000000 0x20000>, <0x09080000 0x80000>;
You are missing the 3 extra regions implemented by the A53 cores
(GICC, GICV, GICH). Please see the binding and the A53 TRM.
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
This is an ARMv8 CPU, even when used in 32bit mode.
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <25000000>;
Why isn't this properly configured by the firmware?
M.
--
Jazz is not dead. It just smells funny...
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 03/14] ARM: dts: Add basic support for Airoha EN7523
2021-12-21 15:02 ` Marc Zyngier
@ 2021-12-22 16:04 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-22 16:04 UTC (permalink / raw)
To: Marc Zyngier
Cc: linux-arm-kernel, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, john, devicetree, linux-kernel
On 2021-12-21 16:02, Marc Zyngier wrote:
> On 2021-12-20 21:18, Felix Fietkau wrote:
>> From: John Crispin <john@phrozen.org>
>>
>> Add basic support for Airoha EN7523, enough for booting to console.
>>
>> The UART is basically 8250-compatible, except for the clock selection.
>> A clock-frequency value is synthesized to get this to run at 115200
>> bps.
>>
>> Signed-off-by: John Crispin <john@phrozen.org>
>> Signed-off-by: Bert Vermeulen <bert@biot.com>
>> Signed-off-by: Felix Fietkau <nbd@nbd.name>
>> ---
>> arch/arm/boot/dts/Makefile | 2 +
>> arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++
>> arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++
>> 3 files changed, 143 insertions(+)
>> create mode 100644 arch/arm/boot/dts/en7523-evb.dts
>> create mode 100644 arch/arm/boot/dts/en7523.dtsi
>>
>
> [...]
>
>> + gic: interrupt-controller@9000000 {
>> + compatible = "arm,gic-v3";
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + reg = <0x09000000 0x20000>, <0x09080000 0x80000>;
>
> You are missing the 3 extra regions implemented by the A53 cores
> (GICC, GICV, GICH). Please see the binding and the A53 TRM.
The SoC memory map documentation contains an address for GICC, but not
for the other two. Maybe this CPU doesn't implement them.
I will add GICC in v9
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv7-timer";
>
> This is an ARMv8 CPU, even when used in 32bit mode.
>
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>> + clock-frequency = <25000000>;
>
> Why isn't this properly configured by the firmware?
I don't know.
- Felix
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 03/14] ARM: dts: Add basic support for Airoha EN7523
@ 2021-12-22 16:04 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-22 16:04 UTC (permalink / raw)
To: Marc Zyngier
Cc: linux-arm-kernel, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, john, devicetree, linux-kernel
On 2021-12-21 16:02, Marc Zyngier wrote:
> On 2021-12-20 21:18, Felix Fietkau wrote:
>> From: John Crispin <john@phrozen.org>
>>
>> Add basic support for Airoha EN7523, enough for booting to console.
>>
>> The UART is basically 8250-compatible, except for the clock selection.
>> A clock-frequency value is synthesized to get this to run at 115200
>> bps.
>>
>> Signed-off-by: John Crispin <john@phrozen.org>
>> Signed-off-by: Bert Vermeulen <bert@biot.com>
>> Signed-off-by: Felix Fietkau <nbd@nbd.name>
>> ---
>> arch/arm/boot/dts/Makefile | 2 +
>> arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++
>> arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++
>> 3 files changed, 143 insertions(+)
>> create mode 100644 arch/arm/boot/dts/en7523-evb.dts
>> create mode 100644 arch/arm/boot/dts/en7523.dtsi
>>
>
> [...]
>
>> + gic: interrupt-controller@9000000 {
>> + compatible = "arm,gic-v3";
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + reg = <0x09000000 0x20000>, <0x09080000 0x80000>;
>
> You are missing the 3 extra regions implemented by the A53 cores
> (GICC, GICV, GICH). Please see the binding and the A53 TRM.
The SoC memory map documentation contains an address for GICC, but not
for the other two. Maybe this CPU doesn't implement them.
I will add GICC in v9
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv7-timer";
>
> This is an ARMv8 CPU, even when used in 32bit mode.
>
>> + interrupt-parent = <&gic>;
>> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>> + clock-frequency = <25000000>;
>
> Why isn't this properly configured by the firmware?
I don't know.
- Felix
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 03/14] ARM: dts: Add basic support for Airoha EN7523
2021-12-22 16:04 ` Felix Fietkau
@ 2021-12-22 18:07 ` Marc Zyngier
-1 siblings, 0 replies; 60+ messages in thread
From: Marc Zyngier @ 2021-12-22 18:07 UTC (permalink / raw)
To: Felix Fietkau
Cc: linux-arm-kernel, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, john, devicetree, linux-kernel
On Wed, 22 Dec 2021 16:04:07 +0000,
Felix Fietkau <nbd@nbd.name> wrote:
>
>
> On 2021-12-21 16:02, Marc Zyngier wrote:
> > On 2021-12-20 21:18, Felix Fietkau wrote:
> >> From: John Crispin <john@phrozen.org>
> >>
> >> Add basic support for Airoha EN7523, enough for booting to console.
> >>
> >> The UART is basically 8250-compatible, except for the clock selection.
> >> A clock-frequency value is synthesized to get this to run at 115200
> >> bps.
> >>
> >> Signed-off-by: John Crispin <john@phrozen.org>
> >> Signed-off-by: Bert Vermeulen <bert@biot.com>
> >> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> >> ---
> >> arch/arm/boot/dts/Makefile | 2 +
> >> arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++
> >> arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++
> >> 3 files changed, 143 insertions(+)
> >> create mode 100644 arch/arm/boot/dts/en7523-evb.dts
> >> create mode 100644 arch/arm/boot/dts/en7523.dtsi
> >>
> >
> > [...]
> >
> >> + gic: interrupt-controller@9000000 {
> >> + compatible = "arm,gic-v3";
> >> + interrupt-controller;
> >> + #interrupt-cells = <3>;
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + reg = <0x09000000 0x20000>, <0x09080000 0x80000>;
> >
> > You are missing the 3 extra regions implemented by the A53 cores
> > (GICC, GICV, GICH). Please see the binding and the A53 TRM.
> The SoC memory map documentation contains an address for GICC, but not
> for the other two. Maybe this CPU doesn't implement them.
Please read the CPU TRM (it is publicly available from the ARM web
site). GICC, GICV and GICH are all at a fixed offset form each other,
and are always implemented by the A53 when connected to a GICv3.
> I will add GICC in v9
Please add all 3 missing regions.
>
> >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> >> + };
> >> +
> >> + timer {
> >> + compatible = "arm,armv7-timer";
> >
> > This is an ARMv8 CPU, even when used in 32bit mode.
> >
> >> + interrupt-parent = <&gic>;
> >> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> >> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> >> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> >> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> >> + clock-frequency = <25000000>;
> >
> > Why isn't this properly configured by the firmware?
> I don't know.
Then drop it.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 03/14] ARM: dts: Add basic support for Airoha EN7523
@ 2021-12-22 18:07 ` Marc Zyngier
0 siblings, 0 replies; 60+ messages in thread
From: Marc Zyngier @ 2021-12-22 18:07 UTC (permalink / raw)
To: Felix Fietkau
Cc: linux-arm-kernel, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, john, devicetree, linux-kernel
On Wed, 22 Dec 2021 16:04:07 +0000,
Felix Fietkau <nbd@nbd.name> wrote:
>
>
> On 2021-12-21 16:02, Marc Zyngier wrote:
> > On 2021-12-20 21:18, Felix Fietkau wrote:
> >> From: John Crispin <john@phrozen.org>
> >>
> >> Add basic support for Airoha EN7523, enough for booting to console.
> >>
> >> The UART is basically 8250-compatible, except for the clock selection.
> >> A clock-frequency value is synthesized to get this to run at 115200
> >> bps.
> >>
> >> Signed-off-by: John Crispin <john@phrozen.org>
> >> Signed-off-by: Bert Vermeulen <bert@biot.com>
> >> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> >> ---
> >> arch/arm/boot/dts/Makefile | 2 +
> >> arch/arm/boot/dts/en7523-evb.dts | 27 ++++++++
> >> arch/arm/boot/dts/en7523.dtsi | 114 +++++++++++++++++++++++++++++++
> >> 3 files changed, 143 insertions(+)
> >> create mode 100644 arch/arm/boot/dts/en7523-evb.dts
> >> create mode 100644 arch/arm/boot/dts/en7523.dtsi
> >>
> >
> > [...]
> >
> >> + gic: interrupt-controller@9000000 {
> >> + compatible = "arm,gic-v3";
> >> + interrupt-controller;
> >> + #interrupt-cells = <3>;
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + reg = <0x09000000 0x20000>, <0x09080000 0x80000>;
> >
> > You are missing the 3 extra regions implemented by the A53 cores
> > (GICC, GICV, GICH). Please see the binding and the A53 TRM.
> The SoC memory map documentation contains an address for GICC, but not
> for the other two. Maybe this CPU doesn't implement them.
Please read the CPU TRM (it is publicly available from the ARM web
site). GICC, GICV and GICH are all at a fixed offset form each other,
and are always implemented by the A53 when connected to a GICv3.
> I will add GICC in v9
Please add all 3 missing regions.
>
> >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> >> + };
> >> +
> >> + timer {
> >> + compatible = "arm,armv7-timer";
> >
> > This is an ARMv8 CPU, even when used in 32bit mode.
> >
> >> + interrupt-parent = <&gic>;
> >> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> >> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> >> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> >> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> >> + clock-frequency = <25000000>;
> >
> > Why isn't this properly configured by the firmware?
> I don't know.
Then drop it.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v8 04/14] ARM: Add basic support for Airoha EN7523 SoC
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Russell King; +Cc: john, linux-kernel
From: John Crispin <john@phrozen.org>
EN7523 is an armv8 based silicon used inside broadband access type devices
such as xPON and xDSL. It shares various silicon blocks with MediaTek
silicon such as the MT7622.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/Kconfig | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f0f9e8bec83a..8dcd05ef31cc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -573,6 +573,18 @@ config ARCH_VIRT
select HAVE_ARM_ARCH_TIMER
select ARCH_SUPPORTS_BIG_ENDIAN
+config ARCH_AIROHA
+ bool "Airoha SoC Support"
+ depends on ARCH_MULTI_V7
+ select ARM_AMBA
+ select ARM_GIC
+ select ARM_GIC_V3
+ select ARM_PSCI
+ select HAVE_ARM_ARCH_TIMER
+ select COMMON_CLK
+ help
+ Support for Airoha EN7523 SoCs
+
#
# This is sorted alphabetically by mach-* pathname. However, plat-*
# Kconfigs may be included either alphabetically (according to the
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 04/14] ARM: Add basic support for Airoha EN7523 SoC
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Russell King; +Cc: john, linux-kernel
From: John Crispin <john@phrozen.org>
EN7523 is an armv8 based silicon used inside broadband access type devices
such as xPON and xDSL. It shares various silicon blocks with MediaTek
silicon such as the MT7622.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/Kconfig | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f0f9e8bec83a..8dcd05ef31cc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -573,6 +573,18 @@ config ARCH_VIRT
select HAVE_ARM_ARCH_TIMER
select ARCH_SUPPORTS_BIG_ENDIAN
+config ARCH_AIROHA
+ bool "Airoha SoC Support"
+ depends on ARCH_MULTI_V7
+ select ARM_AMBA
+ select ARM_GIC
+ select ARM_GIC_V3
+ select ARM_PSCI
+ select HAVE_ARM_ARCH_TIMER
+ select COMMON_CLK
+ help
+ Support for Airoha EN7523 SoCs
+
#
# This is sorted alphabetically by mach-* pathname. However, plat-*
# Kconfigs may be included either alphabetically (according to the
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [PATCH v8 04/14] ARM: Add basic support for Airoha EN7523 SoC
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-29 15:22 ` Matthias Brugger
-1 siblings, 0 replies; 60+ messages in thread
From: Matthias Brugger @ 2021-12-29 15:22 UTC (permalink / raw)
To: Felix Fietkau, linux-arm-kernel, Russell King; +Cc: john, linux-kernel
On 20/12/2021 22:18, Felix Fietkau wrote:
> From: John Crispin <john@phrozen.org>
>
> EN7523 is an armv8 based silicon used inside broadband access type devices
> such as xPON and xDSL. It shares various silicon blocks with MediaTek
> silicon such as the MT7622.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Bert Vermeulen <bert@biot.com>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> arch/arm/Kconfig | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index f0f9e8bec83a..8dcd05ef31cc 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -573,6 +573,18 @@ config ARCH_VIRT
> select HAVE_ARM_ARCH_TIMER
> select ARCH_SUPPORTS_BIG_ENDIAN
>
> +config ARCH_AIROHA
> + bool "Airoha SoC Support"
> + depends on ARCH_MULTI_V7
> + select ARM_AMBA
> + select ARM_GIC
> + select ARM_GIC_V3
> + select ARM_PSCI
> + select HAVE_ARM_ARCH_TIMER
> + select COMMON_CLK
> + help
> + Support for Airoha EN7523 SoCs
> +
We should add a new subfolder
arm/mach-airoha or add the config in arm/mach-mediatek, as it re-uses part of
the MediaTek IP.
Please merge this with 3/14
I also wonder if this actually boots. I suspect we need DT_MACHINE_START() macro
and the compatibles defined. It's many years ago I did this for MediaTek but I
remember that the system won't boot without that. Maybe things have changed over
time though.
Regards,
Matthias
> #
> # This is sorted alphabetically by mach-* pathname. However, plat-*
> # Kconfigs may be included either alphabetically (according to the
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 04/14] ARM: Add basic support for Airoha EN7523 SoC
@ 2021-12-29 15:22 ` Matthias Brugger
0 siblings, 0 replies; 60+ messages in thread
From: Matthias Brugger @ 2021-12-29 15:22 UTC (permalink / raw)
To: Felix Fietkau, linux-arm-kernel, Russell King; +Cc: john, linux-kernel
On 20/12/2021 22:18, Felix Fietkau wrote:
> From: John Crispin <john@phrozen.org>
>
> EN7523 is an armv8 based silicon used inside broadband access type devices
> such as xPON and xDSL. It shares various silicon blocks with MediaTek
> silicon such as the MT7622.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Bert Vermeulen <bert@biot.com>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> arch/arm/Kconfig | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index f0f9e8bec83a..8dcd05ef31cc 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -573,6 +573,18 @@ config ARCH_VIRT
> select HAVE_ARM_ARCH_TIMER
> select ARCH_SUPPORTS_BIG_ENDIAN
>
> +config ARCH_AIROHA
> + bool "Airoha SoC Support"
> + depends on ARCH_MULTI_V7
> + select ARM_AMBA
> + select ARM_GIC
> + select ARM_GIC_V3
> + select ARM_PSCI
> + select HAVE_ARM_ARCH_TIMER
> + select COMMON_CLK
> + help
> + Support for Airoha EN7523 SoCs
> +
We should add a new subfolder
arm/mach-airoha or add the config in arm/mach-mediatek, as it re-uses part of
the MediaTek IP.
Please merge this with 3/14
I also wonder if this actually boots. I suspect we need DT_MACHINE_START() macro
and the compatibles defined. It's many years ago I did this for MediaTek but I
remember that the system won't boot without that. Maybe things have changed over
time though.
Regards,
Matthias
> #
> # This is sorted alphabetically by mach-* pathname. However, plat-*
> # Kconfigs may be included either alphabetically (according to the
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v8 05/14] ARM: multi_v7_defconfig: Add support for Airoha EN7523 SoC
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Russell King; +Cc: john, linux-kernel
From: John Crispin <john@phrozen.org>
This enables basic bootup support for the Airoha EN7523 SoC.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c951aeed2138..912b3d60325b 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -32,6 +32,7 @@ CONFIG_MACH_BERLIN_BG2=y
CONFIG_MACH_BERLIN_BG2CD=y
CONFIG_MACH_BERLIN_BG2Q=y
CONFIG_ARCH_DIGICOLOR=y
+CONFIG_ARCH_AIROHA=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_HISI=y
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 05/14] ARM: multi_v7_defconfig: Add support for Airoha EN7523 SoC
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Russell King; +Cc: john, linux-kernel
From: John Crispin <john@phrozen.org>
This enables basic bootup support for the Airoha EN7523 SoC.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c951aeed2138..912b3d60325b 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -32,6 +32,7 @@ CONFIG_MACH_BERLIN_BG2=y
CONFIG_MACH_BERLIN_BG2CD=y
CONFIG_MACH_BERLIN_BG2Q=y
CONFIG_ARCH_DIGICOLOR=y
+CONFIG_ARCH_AIROHA=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_HISI=y
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 06/14] dt-bindings: Add en7523-scu device tree binding documentation
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Michael Turquette, Stephen Boyd, Rob Herring
Cc: john, Rob Herring, linux-clk, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Adds device tree binding documentation for clocks in the EN7523 SOC.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
.../bindings/clock/airoha,en7523-scu.yaml | 58 +++++++++++++++++++
include/dt-bindings/clock/en7523-clk.h | 17 ++++++
2 files changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
create mode 100644 include/dt-bindings/clock/en7523-clk.h
diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
new file mode 100644
index 000000000000..79660f8126fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EN7523 Clock Device Tree Bindings
+
+maintainers:
+ - Felix Fietkau <nbd@nbd.name>
+ - John Crispin <nbd@nbd.name>
+
+description: |
+ This node defines the System Control Unit of the EN7523 SoC,
+ a collection of registers configuring many different aspects of the SoC.
+
+ The clock driver uses it to read and configure settings of the
+ PLL controller, which provides clocks for the CPU, the bus and
+ other SoC internal peripherals.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify which clock they consume.
+
+ All these identifiers can be found in:
+ [1]: <include/dt-bindings/clock/en7523-clk.h>.
+
+ The clocks are provided inside a system controller node.
+
+properties:
+ compatible:
+ items:
+ - const: airoha,en7523-scu
+
+ reg:
+ maxItems: 2
+
+ "#clock-cells":
+ description:
+ The first cell indicates the clock number, see [1] for available
+ clocks.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/en7523-clk.h>
+ scu: scu@1fa20000 {
+ compatible = "airoha,en7523-scu";
+ reg = <0x1fa20000 0x400>,
+ <0x1fb00000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/clock/en7523-clk.h
new file mode 100644
index 000000000000..717d23a5e5ae
--- /dev/null
+++ b/include/dt-bindings/clock/en7523-clk.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
+#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
+
+#define EN7523_CLK_GSW 0
+#define EN7523_CLK_EMI 1
+#define EN7523_CLK_BUS 2
+#define EN7523_CLK_SLIC 3
+#define EN7523_CLK_SPI 4
+#define EN7523_CLK_NPU 5
+#define EN7523_CLK_CRYPTO 6
+#define EN7523_CLK_PCIE 7
+
+#define EN7523_NUM_CLOCKS 8
+
+#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 06/14] dt-bindings: Add en7523-scu device tree binding documentation
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Michael Turquette, Stephen Boyd, Rob Herring
Cc: john, Rob Herring, linux-clk, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Adds device tree binding documentation for clocks in the EN7523 SOC.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
.../bindings/clock/airoha,en7523-scu.yaml | 58 +++++++++++++++++++
include/dt-bindings/clock/en7523-clk.h | 17 ++++++
2 files changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
create mode 100644 include/dt-bindings/clock/en7523-clk.h
diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
new file mode 100644
index 000000000000..79660f8126fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EN7523 Clock Device Tree Bindings
+
+maintainers:
+ - Felix Fietkau <nbd@nbd.name>
+ - John Crispin <nbd@nbd.name>
+
+description: |
+ This node defines the System Control Unit of the EN7523 SoC,
+ a collection of registers configuring many different aspects of the SoC.
+
+ The clock driver uses it to read and configure settings of the
+ PLL controller, which provides clocks for the CPU, the bus and
+ other SoC internal peripherals.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify which clock they consume.
+
+ All these identifiers can be found in:
+ [1]: <include/dt-bindings/clock/en7523-clk.h>.
+
+ The clocks are provided inside a system controller node.
+
+properties:
+ compatible:
+ items:
+ - const: airoha,en7523-scu
+
+ reg:
+ maxItems: 2
+
+ "#clock-cells":
+ description:
+ The first cell indicates the clock number, see [1] for available
+ clocks.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/en7523-clk.h>
+ scu: scu@1fa20000 {
+ compatible = "airoha,en7523-scu";
+ reg = <0x1fa20000 0x400>,
+ <0x1fb00000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/en7523-clk.h b/include/dt-bindings/clock/en7523-clk.h
new file mode 100644
index 000000000000..717d23a5e5ae
--- /dev/null
+++ b/include/dt-bindings/clock/en7523-clk.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
+#define _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_
+
+#define EN7523_CLK_GSW 0
+#define EN7523_CLK_EMI 1
+#define EN7523_CLK_BUS 2
+#define EN7523_CLK_SLIC 3
+#define EN7523_CLK_SPI 4
+#define EN7523_CLK_NPU 5
+#define EN7523_CLK_CRYPTO 6
+#define EN7523_CLK_PCIE 7
+
+#define EN7523_NUM_CLOCKS 8
+
+#endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 07/14] clk: en7523: Add clock driver for Airoha EN7523 SoC
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Michael Turquette, Stephen Boyd
Cc: john, linux-kernel, linux-clk
This driver only registers fixed rate clocks, since the clocks are fully
initialized by the boot loader and should not be changed later, according
to Airoha.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-en7523.c | 350 +++++++++++++++++++++++++++++++++++++++
3 files changed, 360 insertions(+)
create mode 100644 drivers/clk/clk-en7523.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index c5b3dc97396a..c973ac1a4890 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -192,6 +192,15 @@ config COMMON_CLK_CS2000_CP
help
If you say yes here you get support for the CS2000 clock multiplier.
+config COMMON_CLK_EN7523
+ bool "Clock driver for Airoha EN7523 SoC system clocks"
+ depends on OF
+ depends on ARCH_AIROHA || COMPILE_TEST
+ default ARCH_AIROHA
+ help
+ This driver provides the fixed clocks and gates present on Airoha
+ ARM silicon.
+
config COMMON_CLK_FSL_FLEXSPI
tristate "Clock driver for FlexSPI on Layerscape SoCs"
depends on ARCH_LAYERSCAPE || COMPILE_TEST
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e42312121e51..be11d88c1603 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
+obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o
obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
new file mode 100644
index 000000000000..0ee44f6538e6
--- /dev/null
+++ b/drivers/clk/clk-en7523.c
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/regmap.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/en7523-clk.h>
+
+#define REG_PCI_CONTROL 0x88
+#define REG_PCI_CONTROL_PERSTOUT BIT(29)
+#define REG_PCI_CONTROL_PERSTOUT1 BIT(26)
+#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22)
+#define REG_GSW_CLK_DIV_SEL 0x1b4
+#define REG_EMI_CLK_DIV_SEL 0x1b8
+#define REG_BUS_CLK_DIV_SEL 0x1bc
+#define REG_SPI_CLK_DIV_SEL 0x1c4
+#define REG_SPI_CLK_FREQ_SEL 0x1c8
+#define REG_NPU_CLK_DIV_SEL 0x1fc
+#define REG_CRYPTO_CLKSRC 0x200
+#define REG_RESET_CONTROL 0x834
+#define REG_RESET_CONTROL_PCIEHB BIT(29)
+#define REG_RESET_CONTROL_PCIE1 BIT(27)
+#define REG_RESET_CONTROL_PCIE2 BIT(26)
+
+struct en_clk_desc {
+ int id;
+ const char *name;
+ u32 base_reg;
+ u32 base_bits;
+ u32 base_shift;
+ union {
+ const u32 *base_values;
+ u32 base_value;
+ };
+ int n_base_values;
+
+ u32 div_reg;
+ u32 div_bits;
+ u32 div_shift;
+ u32 div_val0;
+ u32 div_step;
+};
+
+struct en_clk_gate {
+ void __iomem *base;
+ struct clk_hw hw;
+};
+
+static const u32 gsw_base[] = { 400000000, 500000000 };
+static const u32 emi_base[] = { 333000000, 400000000 };
+static const u32 bus_base[] = { 500000000, 540000000 };
+static const u32 slic_base[] = { 100000000, 3125000 };
+static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
+
+static const struct en_clk_desc en7523_base_clks[] = {
+ {
+ .id = EN7523_CLK_GSW,
+ .name = "gsw",
+
+ .base_reg = REG_GSW_CLK_DIV_SEL,
+ .base_bits = 1,
+ .base_shift = 8,
+ .base_values = gsw_base,
+ .n_base_values = ARRAY_SIZE(gsw_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ }, {
+ .id = EN7523_CLK_EMI,
+ .name = "emi",
+
+ .base_reg = REG_EMI_CLK_DIV_SEL,
+ .base_bits = 1,
+ .base_shift = 8,
+ .base_values = emi_base,
+ .n_base_values = ARRAY_SIZE(emi_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ }, {
+ .id = EN7523_CLK_BUS,
+ .name = "bus",
+
+ .base_reg = REG_BUS_CLK_DIV_SEL,
+ .base_bits = 1,
+ .base_shift = 8,
+ .base_values = bus_base,
+ .n_base_values = ARRAY_SIZE(bus_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ }, {
+ .id = EN7523_CLK_SLIC,
+ .name = "slic",
+
+ .base_reg = REG_SPI_CLK_FREQ_SEL,
+ .base_bits = 1,
+ .base_shift = 0,
+ .base_values = slic_base,
+ .n_base_values = ARRAY_SIZE(slic_base),
+
+ .div_reg = REG_SPI_CLK_DIV_SEL,
+ .div_bits = 5,
+ .div_shift = 24,
+ .div_val0 = 20,
+ .div_step = 2,
+ }, {
+ .id = EN7523_CLK_SPI,
+ .name = "spi",
+
+ .base_reg = REG_SPI_CLK_DIV_SEL,
+
+ .base_value = 400000000,
+
+ .div_bits = 5,
+ .div_shift = 8,
+ .div_val0 = 40,
+ .div_step = 2,
+ }, {
+ .id = EN7523_CLK_NPU,
+ .name = "npu",
+
+ .base_reg = REG_NPU_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 8,
+ .base_values = npu_base,
+ .n_base_values = ARRAY_SIZE(npu_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ }, {
+ .id = EN7523_CLK_CRYPTO,
+ .name = "crypto",
+
+ .base_reg = REG_CRYPTO_CLKSRC,
+ .base_bits = 1,
+ .base_shift = 8,
+ .base_values = emi_base,
+ .n_base_values = ARRAY_SIZE(emi_base),
+ }
+};
+
+static const struct of_device_id of_match_clk_en7523[] = {
+ { .compatible = "airoha,en7523-scu", },
+ { /* sentinel */ }
+};
+
+static u32 en7523_get_base_rate(void __iomem *base, int i)
+{
+ const struct en_clk_desc *desc = &en7523_base_clks[i];
+ u32 val;
+
+ if (!desc->base_bits)
+ return desc->base_value;
+
+ val = readl(base + desc->base_reg);
+ val >>= desc->base_shift;
+ val &= (1 << desc->base_bits) - 1;
+
+ if (val >= desc->n_base_values)
+ return 0;
+
+ return desc->base_values[val];
+}
+
+static u32 en7523_get_div(void __iomem *base, int i)
+{
+ const struct en_clk_desc *desc = &en7523_base_clks[i];
+ u32 reg, val;
+
+ if (!desc->div_bits)
+ return 1;
+
+ reg = desc->div_reg ? desc->div_reg : desc->base_reg;
+ val = readl(base + reg);
+ val >>= desc->div_shift;
+ val &= (1 << desc->div_bits) - 1;
+
+ if (!val && desc->div_val0)
+ return desc->div_val0;
+
+ return (val + 1) * desc->div_step;
+}
+
+static int en7523_pci_is_enabled(struct clk_hw *hw)
+{
+ struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+
+ return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);
+}
+
+static int en7523_pci_enable(struct clk_hw *hw)
+{
+ struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ void __iomem *np_base = cg->base;
+ u32 val, mask;
+
+ /* Need to pull device low before reset */
+ val = readl(np_base + REG_PCI_CONTROL);
+ val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT);
+ writel(val, np_base + REG_PCI_CONTROL);
+ usleep_range(1000, 2000);
+
+ /* Enable PCIe port 1 */
+ val |= REG_PCI_CONTROL_REFCLK_EN1;
+ writel(val, np_base + REG_PCI_CONTROL);
+ usleep_range(1000, 2000);
+
+ /* Reset to default */
+ val = readl(np_base + REG_RESET_CONTROL);
+ mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
+ REG_RESET_CONTROL_PCIEHB;
+ writel(val & ~mask, np_base + REG_RESET_CONTROL);
+ usleep_range(1000, 2000);
+ writel(val | mask, np_base + REG_RESET_CONTROL);
+ msleep(100);
+ writel(val & ~mask, np_base + REG_RESET_CONTROL);
+ usleep_range(5000, 10000);
+
+ /* Release device */
+ mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
+ val = readl(np_base + REG_PCI_CONTROL);
+ writel(val & ~mask, np_base + REG_PCI_CONTROL);
+ usleep_range(1000, 2000);
+ writel(val | mask, np_base + REG_PCI_CONTROL);
+ msleep(250);
+
+ return 0;
+}
+
+static void en7523_pci_disable(struct clk_hw *hw)
+{
+ struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ void __iomem *np_base = cg->base;
+ u32 val;
+
+ val = readl(np_base + REG_PCI_CONTROL);
+ val &= ~REG_PCI_CONTROL_REFCLK_EN1;
+ writel(val, np_base + REG_PCI_CONTROL);
+}
+
+static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
+ void __iomem *np_base)
+{
+ static const struct clk_ops pcie_gate_ops = {
+ .is_enabled = en7523_pci_is_enabled,
+ .enable = en7523_pci_enable,
+ .disable = en7523_pci_disable,
+ };
+ struct clk_init_data init = {
+ .name = "pcie",
+ .ops = &pcie_gate_ops,
+ };
+ struct en_clk_gate *cg;
+
+ cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL);
+ if (!cg)
+ return NULL;
+
+ cg->base = np_base;
+ cg->hw.init = &init;
+ en7523_pci_disable(&cg->hw);
+
+ if (clk_hw_register(NULL, &cg->hw))
+ return NULL;
+
+ return &cg->hw;
+}
+
+static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
+ void __iomem *base, void __iomem *np_base)
+{
+ struct clk_hw *hw;
+ u32 rate;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
+ const struct en_clk_desc *desc = &en7523_base_clks[i];
+
+ rate = en7523_get_base_rate(base, i);
+ rate /= en7523_get_div(base, i);
+
+ hw = clk_hw_register_fixed_rate(NULL, desc->name, NULL, 0, rate);
+ if (IS_ERR(hw)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ desc->name, PTR_ERR(hw));
+ continue;
+ }
+
+ clk_data->hws[desc->id] = hw;
+ }
+
+ hw = en7523_register_pcie_clk(dev, np_base);
+ clk_data->hws[EN7523_CLK_PCIE] = hw;
+
+ clk_data->num = EN7523_NUM_CLOCKS;
+}
+
+static int en7523_clk_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct clk_hw_onecell_data *clk_data;
+ void __iomem *base, *np_base;
+ int r;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ np_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(base))
+ return PTR_ERR(np_base);
+
+ clk_data = devm_kzalloc(&pdev->dev,
+ struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_en7523_drv = {
+ .probe = en7523_clk_probe,
+ .driver = {
+ .name = "clk-en7523",
+ .of_match_table = of_match_clk_en7523,
+ },
+};
+
+static int clk_en7523_init(void)
+{
+ return platform_driver_register(&clk_en7523_drv);
+}
+
+arch_initcall(clk_en7523_init);
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 07/14] clk: en7523: Add clock driver for Airoha EN7523 SoC
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Michael Turquette, Stephen Boyd
Cc: john, linux-kernel, linux-clk
This driver only registers fixed rate clocks, since the clocks are fully
initialized by the boot loader and should not be changed later, according
to Airoha.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-en7523.c | 350 +++++++++++++++++++++++++++++++++++++++
3 files changed, 360 insertions(+)
create mode 100644 drivers/clk/clk-en7523.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index c5b3dc97396a..c973ac1a4890 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -192,6 +192,15 @@ config COMMON_CLK_CS2000_CP
help
If you say yes here you get support for the CS2000 clock multiplier.
+config COMMON_CLK_EN7523
+ bool "Clock driver for Airoha EN7523 SoC system clocks"
+ depends on OF
+ depends on ARCH_AIROHA || COMPILE_TEST
+ default ARCH_AIROHA
+ help
+ This driver provides the fixed clocks and gates present on Airoha
+ ARM silicon.
+
config COMMON_CLK_FSL_FLEXSPI
tristate "Clock driver for FlexSPI on Layerscape SoCs"
depends on ARCH_LAYERSCAPE || COMPILE_TEST
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index e42312121e51..be11d88c1603 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
+obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o
obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
new file mode 100644
index 000000000000..0ee44f6538e6
--- /dev/null
+++ b/drivers/clk/clk-en7523.c
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/regmap.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/en7523-clk.h>
+
+#define REG_PCI_CONTROL 0x88
+#define REG_PCI_CONTROL_PERSTOUT BIT(29)
+#define REG_PCI_CONTROL_PERSTOUT1 BIT(26)
+#define REG_PCI_CONTROL_REFCLK_EN1 BIT(22)
+#define REG_GSW_CLK_DIV_SEL 0x1b4
+#define REG_EMI_CLK_DIV_SEL 0x1b8
+#define REG_BUS_CLK_DIV_SEL 0x1bc
+#define REG_SPI_CLK_DIV_SEL 0x1c4
+#define REG_SPI_CLK_FREQ_SEL 0x1c8
+#define REG_NPU_CLK_DIV_SEL 0x1fc
+#define REG_CRYPTO_CLKSRC 0x200
+#define REG_RESET_CONTROL 0x834
+#define REG_RESET_CONTROL_PCIEHB BIT(29)
+#define REG_RESET_CONTROL_PCIE1 BIT(27)
+#define REG_RESET_CONTROL_PCIE2 BIT(26)
+
+struct en_clk_desc {
+ int id;
+ const char *name;
+ u32 base_reg;
+ u32 base_bits;
+ u32 base_shift;
+ union {
+ const u32 *base_values;
+ u32 base_value;
+ };
+ int n_base_values;
+
+ u32 div_reg;
+ u32 div_bits;
+ u32 div_shift;
+ u32 div_val0;
+ u32 div_step;
+};
+
+struct en_clk_gate {
+ void __iomem *base;
+ struct clk_hw hw;
+};
+
+static const u32 gsw_base[] = { 400000000, 500000000 };
+static const u32 emi_base[] = { 333000000, 400000000 };
+static const u32 bus_base[] = { 500000000, 540000000 };
+static const u32 slic_base[] = { 100000000, 3125000 };
+static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
+
+static const struct en_clk_desc en7523_base_clks[] = {
+ {
+ .id = EN7523_CLK_GSW,
+ .name = "gsw",
+
+ .base_reg = REG_GSW_CLK_DIV_SEL,
+ .base_bits = 1,
+ .base_shift = 8,
+ .base_values = gsw_base,
+ .n_base_values = ARRAY_SIZE(gsw_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ }, {
+ .id = EN7523_CLK_EMI,
+ .name = "emi",
+
+ .base_reg = REG_EMI_CLK_DIV_SEL,
+ .base_bits = 1,
+ .base_shift = 8,
+ .base_values = emi_base,
+ .n_base_values = ARRAY_SIZE(emi_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ }, {
+ .id = EN7523_CLK_BUS,
+ .name = "bus",
+
+ .base_reg = REG_BUS_CLK_DIV_SEL,
+ .base_bits = 1,
+ .base_shift = 8,
+ .base_values = bus_base,
+ .n_base_values = ARRAY_SIZE(bus_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ }, {
+ .id = EN7523_CLK_SLIC,
+ .name = "slic",
+
+ .base_reg = REG_SPI_CLK_FREQ_SEL,
+ .base_bits = 1,
+ .base_shift = 0,
+ .base_values = slic_base,
+ .n_base_values = ARRAY_SIZE(slic_base),
+
+ .div_reg = REG_SPI_CLK_DIV_SEL,
+ .div_bits = 5,
+ .div_shift = 24,
+ .div_val0 = 20,
+ .div_step = 2,
+ }, {
+ .id = EN7523_CLK_SPI,
+ .name = "spi",
+
+ .base_reg = REG_SPI_CLK_DIV_SEL,
+
+ .base_value = 400000000,
+
+ .div_bits = 5,
+ .div_shift = 8,
+ .div_val0 = 40,
+ .div_step = 2,
+ }, {
+ .id = EN7523_CLK_NPU,
+ .name = "npu",
+
+ .base_reg = REG_NPU_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 8,
+ .base_values = npu_base,
+ .n_base_values = ARRAY_SIZE(npu_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ }, {
+ .id = EN7523_CLK_CRYPTO,
+ .name = "crypto",
+
+ .base_reg = REG_CRYPTO_CLKSRC,
+ .base_bits = 1,
+ .base_shift = 8,
+ .base_values = emi_base,
+ .n_base_values = ARRAY_SIZE(emi_base),
+ }
+};
+
+static const struct of_device_id of_match_clk_en7523[] = {
+ { .compatible = "airoha,en7523-scu", },
+ { /* sentinel */ }
+};
+
+static u32 en7523_get_base_rate(void __iomem *base, int i)
+{
+ const struct en_clk_desc *desc = &en7523_base_clks[i];
+ u32 val;
+
+ if (!desc->base_bits)
+ return desc->base_value;
+
+ val = readl(base + desc->base_reg);
+ val >>= desc->base_shift;
+ val &= (1 << desc->base_bits) - 1;
+
+ if (val >= desc->n_base_values)
+ return 0;
+
+ return desc->base_values[val];
+}
+
+static u32 en7523_get_div(void __iomem *base, int i)
+{
+ const struct en_clk_desc *desc = &en7523_base_clks[i];
+ u32 reg, val;
+
+ if (!desc->div_bits)
+ return 1;
+
+ reg = desc->div_reg ? desc->div_reg : desc->base_reg;
+ val = readl(base + reg);
+ val >>= desc->div_shift;
+ val &= (1 << desc->div_bits) - 1;
+
+ if (!val && desc->div_val0)
+ return desc->div_val0;
+
+ return (val + 1) * desc->div_step;
+}
+
+static int en7523_pci_is_enabled(struct clk_hw *hw)
+{
+ struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+
+ return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);
+}
+
+static int en7523_pci_enable(struct clk_hw *hw)
+{
+ struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ void __iomem *np_base = cg->base;
+ u32 val, mask;
+
+ /* Need to pull device low before reset */
+ val = readl(np_base + REG_PCI_CONTROL);
+ val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT);
+ writel(val, np_base + REG_PCI_CONTROL);
+ usleep_range(1000, 2000);
+
+ /* Enable PCIe port 1 */
+ val |= REG_PCI_CONTROL_REFCLK_EN1;
+ writel(val, np_base + REG_PCI_CONTROL);
+ usleep_range(1000, 2000);
+
+ /* Reset to default */
+ val = readl(np_base + REG_RESET_CONTROL);
+ mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
+ REG_RESET_CONTROL_PCIEHB;
+ writel(val & ~mask, np_base + REG_RESET_CONTROL);
+ usleep_range(1000, 2000);
+ writel(val | mask, np_base + REG_RESET_CONTROL);
+ msleep(100);
+ writel(val & ~mask, np_base + REG_RESET_CONTROL);
+ usleep_range(5000, 10000);
+
+ /* Release device */
+ mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
+ val = readl(np_base + REG_PCI_CONTROL);
+ writel(val & ~mask, np_base + REG_PCI_CONTROL);
+ usleep_range(1000, 2000);
+ writel(val | mask, np_base + REG_PCI_CONTROL);
+ msleep(250);
+
+ return 0;
+}
+
+static void en7523_pci_disable(struct clk_hw *hw)
+{
+ struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ void __iomem *np_base = cg->base;
+ u32 val;
+
+ val = readl(np_base + REG_PCI_CONTROL);
+ val &= ~REG_PCI_CONTROL_REFCLK_EN1;
+ writel(val, np_base + REG_PCI_CONTROL);
+}
+
+static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
+ void __iomem *np_base)
+{
+ static const struct clk_ops pcie_gate_ops = {
+ .is_enabled = en7523_pci_is_enabled,
+ .enable = en7523_pci_enable,
+ .disable = en7523_pci_disable,
+ };
+ struct clk_init_data init = {
+ .name = "pcie",
+ .ops = &pcie_gate_ops,
+ };
+ struct en_clk_gate *cg;
+
+ cg = devm_kzalloc(dev, sizeof(*cg), GFP_KERNEL);
+ if (!cg)
+ return NULL;
+
+ cg->base = np_base;
+ cg->hw.init = &init;
+ en7523_pci_disable(&cg->hw);
+
+ if (clk_hw_register(NULL, &cg->hw))
+ return NULL;
+
+ return &cg->hw;
+}
+
+static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
+ void __iomem *base, void __iomem *np_base)
+{
+ struct clk_hw *hw;
+ u32 rate;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
+ const struct en_clk_desc *desc = &en7523_base_clks[i];
+
+ rate = en7523_get_base_rate(base, i);
+ rate /= en7523_get_div(base, i);
+
+ hw = clk_hw_register_fixed_rate(NULL, desc->name, NULL, 0, rate);
+ if (IS_ERR(hw)) {
+ pr_err("Failed to register clk %s: %ld\n",
+ desc->name, PTR_ERR(hw));
+ continue;
+ }
+
+ clk_data->hws[desc->id] = hw;
+ }
+
+ hw = en7523_register_pcie_clk(dev, np_base);
+ clk_data->hws[EN7523_CLK_PCIE] = hw;
+
+ clk_data->num = EN7523_NUM_CLOCKS;
+}
+
+static int en7523_clk_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct clk_hw_onecell_data *clk_data;
+ void __iomem *base, *np_base;
+ int r;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ np_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(base))
+ return PTR_ERR(np_base);
+
+ clk_data = devm_kzalloc(&pdev->dev,
+ struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ dev_err(&pdev->dev,
+ "could not register clock provider: %s: %d\n",
+ pdev->name, r);
+
+ return r;
+}
+
+static struct platform_driver clk_en7523_drv = {
+ .probe = en7523_clk_probe,
+ .driver = {
+ .name = "clk-en7523",
+ .of_match_table = of_match_clk_en7523,
+ },
+};
+
+static int clk_en7523_init(void)
+{
+ return platform_driver_register(&clk_en7523_drv);
+}
+
+arch_initcall(clk_en7523_init);
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v8 07/14] clk: en7523: Add clock driver for Airoha EN7523 SoC
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-21 14:06 ` Arnd Bergmann
-1 siblings, 0 replies; 60+ messages in thread
From: Arnd Bergmann @ 2021-12-21 14:06 UTC (permalink / raw)
To: Felix Fietkau
Cc: Linux ARM, Michael Turquette, Stephen Boyd, John Crispin,
Linux Kernel Mailing List, linux-clk
On Mon, Dec 20, 2021 at 10:18 PM Felix Fietkau <nbd@nbd.name> wrote:
>
> This driver only registers fixed rate clocks, since the clocks are fully
> initialized by the boot loader and should not be changed later, according
> to Airoha.
>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
I don't have any particular comments on the driver itself. I'm happy
to merge it through
the soc tree for the initial support of the clk maintainers are ok
with it and have reviewed
the actual code.
> drivers/clk/Kconfig | 9 +
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-en7523.c | 350 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 360 insertions(+)
> create mode 100644 drivers/clk/clk-en7523.c
I think this should go into drivers/clk/mediatek, as it probably shares
some of the logic with the mt762x drivers in there. I'd suggest adding the
maintainers for those drivers to Cc for additional review.
Arnd
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 07/14] clk: en7523: Add clock driver for Airoha EN7523 SoC
@ 2021-12-21 14:06 ` Arnd Bergmann
0 siblings, 0 replies; 60+ messages in thread
From: Arnd Bergmann @ 2021-12-21 14:06 UTC (permalink / raw)
To: Felix Fietkau
Cc: Linux ARM, Michael Turquette, Stephen Boyd, John Crispin,
Linux Kernel Mailing List, linux-clk
On Mon, Dec 20, 2021 at 10:18 PM Felix Fietkau <nbd@nbd.name> wrote:
>
> This driver only registers fixed rate clocks, since the clocks are fully
> initialized by the boot loader and should not be changed later, according
> to Airoha.
>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
I don't have any particular comments on the driver itself. I'm happy
to merge it through
the soc tree for the initial support of the clk maintainers are ok
with it and have reviewed
the actual code.
> drivers/clk/Kconfig | 9 +
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-en7523.c | 350 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 360 insertions(+)
> create mode 100644 drivers/clk/clk-en7523.c
I think this should go into drivers/clk/mediatek, as it probably shares
some of the logic with the mt762x drivers in there. I'd suggest adding the
maintainers for those drivers to Cc for additional review.
Arnd
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 07/14] clk: en7523: Add clock driver for Airoha EN7523 SoC
2021-12-21 14:06 ` Arnd Bergmann
@ 2021-12-22 15:35 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-22 15:35 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Linux ARM, Michael Turquette, Stephen Boyd, John Crispin,
Linux Kernel Mailing List, linux-clk
On 2021-12-21 15:06, Arnd Bergmann wrote:
> On Mon, Dec 20, 2021 at 10:18 PM Felix Fietkau <nbd@nbd.name> wrote:
>>
>> This driver only registers fixed rate clocks, since the clocks are fully
>> initialized by the boot loader and should not be changed later, according
>> to Airoha.
>>
>> Signed-off-by: Felix Fietkau <nbd@nbd.name>
>
> I don't have any particular comments on the driver itself. I'm happy
> to merge it through
> the soc tree for the initial support of the clk maintainers are ok
> with it and have reviewed
> the actual code.
>
>> drivers/clk/Kconfig | 9 +
>> drivers/clk/Makefile | 1 +
>> drivers/clk/clk-en7523.c | 350 +++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 360 insertions(+)
>> create mode 100644 drivers/clk/clk-en7523.c
>
> I think this should go into drivers/clk/mediatek, as it probably shares
> some of the logic with the mt762x drivers in there. I'd suggest adding the
> maintainers for those drivers to Cc for additional review.
I don't think it shares any logic with the other drivers, but since
Airoha is a subsidiary of Mediatek, I guess it makes sense to move it there.
- Felix
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 07/14] clk: en7523: Add clock driver for Airoha EN7523 SoC
@ 2021-12-22 15:35 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-22 15:35 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Linux ARM, Michael Turquette, Stephen Boyd, John Crispin,
Linux Kernel Mailing List, linux-clk
On 2021-12-21 15:06, Arnd Bergmann wrote:
> On Mon, Dec 20, 2021 at 10:18 PM Felix Fietkau <nbd@nbd.name> wrote:
>>
>> This driver only registers fixed rate clocks, since the clocks are fully
>> initialized by the boot loader and should not be changed later, according
>> to Airoha.
>>
>> Signed-off-by: Felix Fietkau <nbd@nbd.name>
>
> I don't have any particular comments on the driver itself. I'm happy
> to merge it through
> the soc tree for the initial support of the clk maintainers are ok
> with it and have reviewed
> the actual code.
>
>> drivers/clk/Kconfig | 9 +
>> drivers/clk/Makefile | 1 +
>> drivers/clk/clk-en7523.c | 350 +++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 360 insertions(+)
>> create mode 100644 drivers/clk/clk-en7523.c
>
> I think this should go into drivers/clk/mediatek, as it probably shares
> some of the logic with the mt762x drivers in there. I'd suggest adding the
> maintainers for those drivers to Cc for additional review.
I don't think it shares any logic with the other drivers, but since
Airoha is a subsidiary of Mediatek, I guess it makes sense to move it there.
- Felix
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v8 08/14] ARM: dts: add clock support for Airoha EN7523
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring; +Cc: john, devicetree, linux-kernel
This driver only registers fixed rate clocks, since the clocks are fully
initialized by the boot loader and should not be changed later, according
to Airoha.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/boot/dts/en7523.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
index 7e17311a3f90..0148958c607b 100644
--- a/arch/arm/boot/dts/en7523.dtsi
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -2,6 +2,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/en7523-clk.h>
/ {
interrupt-parent = <&gic>;
@@ -82,6 +83,13 @@ L2_0: l2-cache0 {
};
};
+ scu: scu@1fa20000 {
+ compatible = "airoha,en7523-scu";
+ reg = <0x1fa20000 0x400>,
+ <0x1fb00000 0x1000>;
+ #clock-cells = <1>;
+ };
+
gic: interrupt-controller@9000000 {
compatible = "arm,gic-v3";
interrupt-controller;
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 08/14] ARM: dts: add clock support for Airoha EN7523
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring; +Cc: john, devicetree, linux-kernel
This driver only registers fixed rate clocks, since the clocks are fully
initialized by the boot loader and should not be changed later, according
to Airoha.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/boot/dts/en7523.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
index 7e17311a3f90..0148958c607b 100644
--- a/arch/arm/boot/dts/en7523.dtsi
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -2,6 +2,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/en7523-clk.h>
/ {
interrupt-parent = <&gic>;
@@ -82,6 +83,13 @@ L2_0: l2-cache0 {
};
};
+ scu: scu@1fa20000 {
+ compatible = "airoha,en7523-scu";
+ reg = <0x1fa20000 0x400>,
+ <0x1fb00000 0x1000>;
+ #clock-cells = <1>;
+ };
+
gic: interrupt-controller@9000000 {
compatible = "arm,gic-v3";
interrupt-controller;
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 09/14] dt-bindings: PCI: Add support for Airoha EN7532
2021-12-20 21:18 ` Felix Fietkau
(?)
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Ryder Lee, Jianjun Wang, Bjorn Helgaas,
Rob Herring, Matthias Brugger
Cc: john, Rob Herring, linux-pci, linux-mediatek, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
EN7532 is an ARM based platform SoC integrating the same PCIe IP as
MT7622, add a binding for it.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index 57ae73462272..684227522267 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -7,6 +7,7 @@ Required properties:
"mediatek,mt7622-pcie"
"mediatek,mt7623-pcie"
"mediatek,mt7629-pcie"
+ "airoha,en7523-pcie"
- device_type: Must be "pci"
- reg: Base addresses and lengths of the root ports.
- reg-names: Names of the above areas to use during resource lookup.
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 09/14] dt-bindings: PCI: Add support for Airoha EN7532
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Ryder Lee, Jianjun Wang, Bjorn Helgaas,
Rob Herring, Matthias Brugger
Cc: john, Rob Herring, linux-pci, linux-mediatek, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
EN7532 is an ARM based platform SoC integrating the same PCIe IP as
MT7622, add a binding for it.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index 57ae73462272..684227522267 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -7,6 +7,7 @@ Required properties:
"mediatek,mt7622-pcie"
"mediatek,mt7623-pcie"
"mediatek,mt7629-pcie"
+ "airoha,en7523-pcie"
- device_type: Must be "pci"
- reg: Base addresses and lengths of the root ports.
- reg-names: Names of the above areas to use during resource lookup.
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 09/14] dt-bindings: PCI: Add support for Airoha EN7532
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Ryder Lee, Jianjun Wang, Bjorn Helgaas,
Rob Herring, Matthias Brugger
Cc: john, Rob Herring, linux-pci, linux-mediatek, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
EN7532 is an ARM based platform SoC integrating the same PCIe IP as
MT7622, add a binding for it.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
Documentation/devicetree/bindings/pci/mediatek-pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index 57ae73462272..684227522267 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -7,6 +7,7 @@ Required properties:
"mediatek,mt7622-pcie"
"mediatek,mt7623-pcie"
"mediatek,mt7629-pcie"
+ "airoha,en7523-pcie"
- device_type: Must be "pci"
- reg: Base addresses and lengths of the root ports.
- reg-names: Names of the above areas to use during resource lookup.
--
2.34.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 10/14] PCI: mediatek: Allow building for ARCH_AIROHA
2021-12-20 21:18 ` Felix Fietkau
(?)
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Lorenzo Pieralisi, Rob Herring,
Krzysztof Wilczyński, Bjorn Helgaas, Matthias Brugger
Cc: john, linux-pci, linux-kernel, linux-mediatek
Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the
Airoha EN7523 SoC uses the same controller as MT7622.
The driver itself is not modified. The PCIe controller DT node should use
mediatek,mt7622-pcie after airoha,en7523-pcie.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
drivers/pci/controller/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 93b141110537..f1342059c2a3 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP
config PCIE_MEDIATEK
tristate "MediaTek PCIe controller"
- depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
depends on OF
depends on PCI_MSI_IRQ_DOMAIN
help
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 10/14] PCI: mediatek: Allow building for ARCH_AIROHA
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Lorenzo Pieralisi, Rob Herring,
Krzysztof Wilczyński, Bjorn Helgaas, Matthias Brugger
Cc: john, linux-pci, linux-kernel, linux-mediatek
Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the
Airoha EN7523 SoC uses the same controller as MT7622.
The driver itself is not modified. The PCIe controller DT node should use
mediatek,mt7622-pcie after airoha,en7523-pcie.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
drivers/pci/controller/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 93b141110537..f1342059c2a3 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP
config PCIE_MEDIATEK
tristate "MediaTek PCIe controller"
- depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
depends on OF
depends on PCI_MSI_IRQ_DOMAIN
help
--
2.34.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 10/14] PCI: mediatek: Allow building for ARCH_AIROHA
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Lorenzo Pieralisi, Rob Herring,
Krzysztof Wilczyński, Bjorn Helgaas, Matthias Brugger
Cc: john, linux-pci, linux-kernel, linux-mediatek
Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the
Airoha EN7523 SoC uses the same controller as MT7622.
The driver itself is not modified. The PCIe controller DT node should use
mediatek,mt7622-pcie after airoha,en7523-pcie.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
drivers/pci/controller/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 93b141110537..f1342059c2a3 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP
config PCIE_MEDIATEK
tristate "MediaTek PCIe controller"
- depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
depends on OF
depends on PCI_MSI_IRQ_DOMAIN
help
--
2.34.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [PATCH v8 10/14] PCI: mediatek: Allow building for ARCH_AIROHA
2021-12-20 21:18 ` Felix Fietkau
(?)
@ 2022-01-05 14:50 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 60+ messages in thread
From: Lorenzo Pieralisi @ 2022-01-05 14:50 UTC (permalink / raw)
To: Felix Fietkau
Cc: linux-arm-kernel, Rob Herring, Krzysztof Wilczyński,
Bjorn Helgaas, Matthias Brugger, john, linux-pci, linux-kernel,
linux-mediatek
On Mon, Dec 20, 2021 at 10:18:50PM +0100, Felix Fietkau wrote:
> Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the
> Airoha EN7523 SoC uses the same controller as MT7622.
> The driver itself is not modified. The PCIe controller DT node should use
> mediatek,mt7622-pcie after airoha,en7523-pcie.
>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> drivers/pci/controller/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 93b141110537..f1342059c2a3 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP
>
> config PCIE_MEDIATEK
> tristate "MediaTek PCIe controller"
> - depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
> depends on OF
> depends on PCI_MSI_IRQ_DOMAIN
> help
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 10/14] PCI: mediatek: Allow building for ARCH_AIROHA
@ 2022-01-05 14:50 ` Lorenzo Pieralisi
0 siblings, 0 replies; 60+ messages in thread
From: Lorenzo Pieralisi @ 2022-01-05 14:50 UTC (permalink / raw)
To: Felix Fietkau
Cc: linux-arm-kernel, Rob Herring, Krzysztof Wilczyński,
Bjorn Helgaas, Matthias Brugger, john, linux-pci, linux-kernel,
linux-mediatek
On Mon, Dec 20, 2021 at 10:18:50PM +0100, Felix Fietkau wrote:
> Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the
> Airoha EN7523 SoC uses the same controller as MT7622.
> The driver itself is not modified. The PCIe controller DT node should use
> mediatek,mt7622-pcie after airoha,en7523-pcie.
>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> drivers/pci/controller/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 93b141110537..f1342059c2a3 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP
>
> config PCIE_MEDIATEK
> tristate "MediaTek PCIe controller"
> - depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
> depends on OF
> depends on PCI_MSI_IRQ_DOMAIN
> help
> --
> 2.34.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 10/14] PCI: mediatek: Allow building for ARCH_AIROHA
@ 2022-01-05 14:50 ` Lorenzo Pieralisi
0 siblings, 0 replies; 60+ messages in thread
From: Lorenzo Pieralisi @ 2022-01-05 14:50 UTC (permalink / raw)
To: Felix Fietkau
Cc: linux-arm-kernel, Rob Herring, Krzysztof Wilczyński,
Bjorn Helgaas, Matthias Brugger, john, linux-pci, linux-kernel,
linux-mediatek
On Mon, Dec 20, 2021 at 10:18:50PM +0100, Felix Fietkau wrote:
> Allow selecting the pcie-mediatek driver if ARCH_AIROHA is set, because the
> Airoha EN7523 SoC uses the same controller as MT7622.
> The driver itself is not modified. The PCIe controller DT node should use
> mediatek,mt7622-pcie after airoha,en7523-pcie.
>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> drivers/pci/controller/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 93b141110537..f1342059c2a3 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -233,7 +233,7 @@ config PCIE_ROCKCHIP_EP
>
> config PCIE_MEDIATEK
> tristate "MediaTek PCIe controller"
> - depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on ARCH_AIROHA || ARCH_MEDIATEK || COMPILE_TEST
> depends on OF
> depends on PCI_MSI_IRQ_DOMAIN
> help
> --
> 2.34.1
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v8 11/14] ARM: dts: Add PCIe support for Airoha EN7523
2021-12-20 21:18 ` Felix Fietkau
(?)
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring, Matthias Brugger
Cc: john, devicetree, linux-kernel, linux-mediatek
This uses the MediaTek MT7622 PCIe driver, since the PCIe IP block is nearly
identical to the one in MT7622
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/boot/dts/en7523-evb.dts | 8 +++++
arch/arm/boot/dts/en7523.dtsi | 60 ++++++++++++++++++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
index 69754ef9a628..0a79f5f6c311 100644
--- a/arch/arm/boot/dts/en7523-evb.dts
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -25,3 +25,11 @@ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
index 0148958c607b..862da104d6f2 100644
--- a/arch/arm/boot/dts/en7523.dtsi
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -119,4 +119,64 @@ uart1: serial@1fbf0000 {
clock-frequency = <1843200>;
status = "okay";
};
+
+
+ pcie0: pcie@1fa91000 {
+ compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0x1fa91000 0x1000>;
+ reg-names = "port0";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&scu EN7523_CLK_PCIE>;
+ clock-names = "sys_ck0";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1fa92000 {
+ compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0x1fa92000 0x1000>;
+ reg-names = "port1";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&scu EN7523_CLK_PCIE>;
+ clock-names = "sys_ck1";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
};
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 11/14] ARM: dts: Add PCIe support for Airoha EN7523
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring, Matthias Brugger
Cc: john, devicetree, linux-kernel, linux-mediatek
This uses the MediaTek MT7622 PCIe driver, since the PCIe IP block is nearly
identical to the one in MT7622
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/boot/dts/en7523-evb.dts | 8 +++++
arch/arm/boot/dts/en7523.dtsi | 60 ++++++++++++++++++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
index 69754ef9a628..0a79f5f6c311 100644
--- a/arch/arm/boot/dts/en7523-evb.dts
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -25,3 +25,11 @@ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
index 0148958c607b..862da104d6f2 100644
--- a/arch/arm/boot/dts/en7523.dtsi
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -119,4 +119,64 @@ uart1: serial@1fbf0000 {
clock-frequency = <1843200>;
status = "okay";
};
+
+
+ pcie0: pcie@1fa91000 {
+ compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0x1fa91000 0x1000>;
+ reg-names = "port0";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&scu EN7523_CLK_PCIE>;
+ clock-names = "sys_ck0";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1fa92000 {
+ compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0x1fa92000 0x1000>;
+ reg-names = "port1";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&scu EN7523_CLK_PCIE>;
+ clock-names = "sys_ck1";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
};
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 11/14] ARM: dts: Add PCIe support for Airoha EN7523
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring, Matthias Brugger
Cc: john, devicetree, linux-kernel, linux-mediatek
This uses the MediaTek MT7622 PCIe driver, since the PCIe IP block is nearly
identical to the one in MT7622
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/boot/dts/en7523-evb.dts | 8 +++++
arch/arm/boot/dts/en7523.dtsi | 60 ++++++++++++++++++++++++++++++++
2 files changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
index 69754ef9a628..0a79f5f6c311 100644
--- a/arch/arm/boot/dts/en7523-evb.dts
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -25,3 +25,11 @@ memory@80000000 {
reg = <0x80000000 0x20000000>;
};
};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
index 0148958c607b..862da104d6f2 100644
--- a/arch/arm/boot/dts/en7523.dtsi
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -119,4 +119,64 @@ uart1: serial@1fbf0000 {
clock-frequency = <1843200>;
status = "okay";
};
+
+
+ pcie0: pcie@1fa91000 {
+ compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0x1fa91000 0x1000>;
+ reg-names = "port0";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&scu EN7523_CLK_PCIE>;
+ clock-names = "sys_ck0";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x20000000 0 0x8000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ pcie1: pcie@1fa92000 {
+ compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
+ device_type = "pci";
+ reg = <0x1fa92000 0x1000>;
+ reg-names = "port1";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie_irq";
+ clocks = <&scu EN7523_CLK_PCIE>;
+ clock-names = "sys_ck1";
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28000000 0x28000000 0 0x8000000>;
+ status = "disabled";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+ <0 0 0 2 &pcie_intc1 1>,
+ <0 0 0 3 &pcie_intc1 2>,
+ <0 0 0 4 &pcie_intc1 3>;
+ pcie_intc1: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+
};
--
2.34.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 12/14] dt-bindings: arm: airoha: Add binding for Airoha GPIO controller
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Linus Walleij, Bartosz Golaszewski,
Rob Herring, John Crispin
Cc: Rob Herring, linux-gpio, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
GPIOs
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
.../bindings/gpio/airoha,en7523-gpio.yaml | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/airoha,en7523-gpio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/airoha,en7523-gpio.yaml b/Documentation/devicetree/bindings/gpio/airoha,en7523-gpio.yaml
new file mode 100644
index 000000000000..66c00ec85731
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/airoha,en7523-gpio.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/airoha,en7523-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7523 GPIO controller
+
+maintainers:
+ - John Crispin <john@phrozen.org>
+
+description: |
+ Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
+ GPIOs.
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - const: airoha,en7523-gpio
+
+ reg:
+ description: |
+ The first tuple points to the input register.
+ The second and third tuple point to the direction registers
+ The fourth tuple points to the output register
+ maxItems: 4
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - "#gpio-cells"
+ - gpio-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio0: gpio@1fbf0200 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0204 0x4>,
+ <0x1fbf0200 0x4>,
+ <0x1fbf0220 0x4>,
+ <0x1fbf0214 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio1: gpio@1fbf0270 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0270 0x4>,
+ <0x1fbf0260 0x4>,
+ <0x1fbf0264 0x4>,
+ <0x1fbf0278 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+
+...
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 12/14] dt-bindings: arm: airoha: Add binding for Airoha GPIO controller
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Linus Walleij, Bartosz Golaszewski,
Rob Herring, John Crispin
Cc: Rob Herring, linux-gpio, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
GPIOs
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
.../bindings/gpio/airoha,en7523-gpio.yaml | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/airoha,en7523-gpio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/airoha,en7523-gpio.yaml b/Documentation/devicetree/bindings/gpio/airoha,en7523-gpio.yaml
new file mode 100644
index 000000000000..66c00ec85731
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/airoha,en7523-gpio.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/airoha,en7523-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha EN7523 GPIO controller
+
+maintainers:
+ - John Crispin <john@phrozen.org>
+
+description: |
+ Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
+ GPIOs.
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - const: airoha,en7523-gpio
+
+ reg:
+ description: |
+ The first tuple points to the input register.
+ The second and third tuple point to the direction registers
+ The fourth tuple points to the output register
+ maxItems: 4
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - "#gpio-cells"
+ - gpio-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio0: gpio@1fbf0200 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0204 0x4>,
+ <0x1fbf0200 0x4>,
+ <0x1fbf0220 0x4>,
+ <0x1fbf0214 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio1: gpio@1fbf0270 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0270 0x4>,
+ <0x1fbf0260 0x4>,
+ <0x1fbf0264 0x4>,
+ <0x1fbf0278 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+
+...
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Linus Walleij, Bartosz Golaszewski
Cc: john, linux-kernel, linux-gpio
From: John Crispin <john@phrozen.org>
Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
GPIOs. Each instance in DT is for a single bank.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
drivers/gpio/Kconfig | 9 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-en7523.c | 134 +++++++++++++++++++++++++++++++++++++
3 files changed, 144 insertions(+)
create mode 100644 drivers/gpio/gpio-en7523.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 072ed610f9c6..e4a34272504f 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -247,6 +247,15 @@ config GPIO_EM
help
Say yes here to support GPIO on Renesas Emma Mobile SoCs.
+config GPIO_EN7523
+ tristate "Airoha GPIO support"
+ depends on ARCH_AIROHA
+ default ARCH_AIROHA
+ select GPIO_GENERIC
+ select GPIOLIB_IRQCHIP
+ help
+ Say yes here to support the GPIO controller on Airoha EN7523.
+
config GPIO_EP93XX
def_bool y
depends on ARCH_EP93XX
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 71ee9fc2ff83..d2269ee0948e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o
obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o
obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o
obj-$(CONFIG_GPIO_EM) += gpio-em.o
+obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o
obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o
obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
diff --git a/drivers/gpio/gpio-en7523.c b/drivers/gpio/gpio-en7523.c
new file mode 100644
index 000000000000..67631396cd93
--- /dev/null
+++ b/drivers/gpio/gpio-en7523.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/gpio/driver.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+
+#define AIROHA_GPIO_MAX 32
+
+/**
+ * airoha_gpio_ctrl - Airoha GPIO driver data
+ * @gc: Associated gpio_chip instance.
+ * @data: The data register.
+ * @dir0: The direction register for the lower 16 pins.
+ * @dir1: The direction register for the higher 16 pins.
+ * @output: The output enable register.
+ */
+struct airoha_gpio_ctrl {
+ struct gpio_chip gc;
+ void __iomem *data;
+ void __iomem *dir[2];
+ void __iomem *output;
+};
+
+static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc)
+{
+ return container_of(gc, struct airoha_gpio_ctrl, gc);
+}
+
+static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio,
+ int val, int out)
+{
+ struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
+ u32 dir = ioread32(ctrl->dir[gpio / 16]);
+ u32 output = ioread32(ctrl->output);
+ u32 mask = BIT((gpio % 16) * 2);
+
+ if (out) {
+ dir |= mask;
+ output |= BIT(gpio);
+ } else {
+ dir &= ~mask;
+ output &= ~BIT(gpio);
+ }
+
+ iowrite32(dir, ctrl->dir[gpio / 16]);
+
+ if (out)
+ gc->set(gc, gpio, val);
+
+ iowrite32(output, ctrl->output);
+
+ return 0;
+}
+
+static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio,
+ int val)
+{
+ return airoha_dir_set(gc, gpio, val, 1);
+}
+
+static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+ return airoha_dir_set(gc, gpio, 0, 0);
+}
+
+static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
+ u32 dir = ioread32(ctrl->dir[gpio / 16]);
+ u32 mask = BIT((gpio % 16) * 2);
+
+ return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
+}
+
+static const struct of_device_id airoha_gpio_of_match[] = {
+ { .compatible = "airoha,en7523-gpio" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, airoha_gpio_of_match);
+
+static int airoha_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct airoha_gpio_ctrl *ctrl;
+ int err;
+
+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
+ if (!ctrl)
+ return -ENOMEM;
+
+ ctrl->data = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(ctrl->data))
+ return PTR_ERR(ctrl->data);
+
+ ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(ctrl->dir[0]))
+ return PTR_ERR(ctrl->dir[0]);
+
+ ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2);
+ if (IS_ERR(ctrl->dir[1]))
+ return PTR_ERR(ctrl->dir[1]);
+
+ ctrl->output = devm_platform_ioremap_resource(pdev, 3);
+ if (IS_ERR(ctrl->output))
+ return PTR_ERR(ctrl->output);
+
+ err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL,
+ NULL, NULL, NULL, 0);
+ if (err)
+ return dev_err_probe(dev, err, "unable to init generic GPIO");
+
+ ctrl->gc.ngpio = AIROHA_GPIO_MAX;
+ ctrl->gc.owner = THIS_MODULE;
+ ctrl->gc.direction_output = airoha_dir_out;
+ ctrl->gc.direction_input = airoha_dir_in;
+ ctrl->gc.get_direction = airoha_get_dir;
+
+ return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
+}
+
+static struct platform_driver airoha_gpio_driver = {
+ .driver = {
+ .name = "airoha-gpio",
+ .of_match_table = airoha_gpio_of_match,
+ },
+ .probe = airoha_gpio_probe,
+};
+module_platform_driver(airoha_gpio_driver);
+
+MODULE_DESCRIPTION("Airoha GPIO support");
+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
+MODULE_LICENSE("GPL v2");
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Linus Walleij, Bartosz Golaszewski
Cc: john, linux-kernel, linux-gpio
From: John Crispin <john@phrozen.org>
Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
GPIOs. Each instance in DT is for a single bank.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
drivers/gpio/Kconfig | 9 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-en7523.c | 134 +++++++++++++++++++++++++++++++++++++
3 files changed, 144 insertions(+)
create mode 100644 drivers/gpio/gpio-en7523.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 072ed610f9c6..e4a34272504f 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -247,6 +247,15 @@ config GPIO_EM
help
Say yes here to support GPIO on Renesas Emma Mobile SoCs.
+config GPIO_EN7523
+ tristate "Airoha GPIO support"
+ depends on ARCH_AIROHA
+ default ARCH_AIROHA
+ select GPIO_GENERIC
+ select GPIOLIB_IRQCHIP
+ help
+ Say yes here to support the GPIO controller on Airoha EN7523.
+
config GPIO_EP93XX
def_bool y
depends on ARCH_EP93XX
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 71ee9fc2ff83..d2269ee0948e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o
obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o
obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o
obj-$(CONFIG_GPIO_EM) += gpio-em.o
+obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o
obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o
obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
diff --git a/drivers/gpio/gpio-en7523.c b/drivers/gpio/gpio-en7523.c
new file mode 100644
index 000000000000..67631396cd93
--- /dev/null
+++ b/drivers/gpio/gpio-en7523.c
@@ -0,0 +1,134 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/gpio/driver.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+
+#define AIROHA_GPIO_MAX 32
+
+/**
+ * airoha_gpio_ctrl - Airoha GPIO driver data
+ * @gc: Associated gpio_chip instance.
+ * @data: The data register.
+ * @dir0: The direction register for the lower 16 pins.
+ * @dir1: The direction register for the higher 16 pins.
+ * @output: The output enable register.
+ */
+struct airoha_gpio_ctrl {
+ struct gpio_chip gc;
+ void __iomem *data;
+ void __iomem *dir[2];
+ void __iomem *output;
+};
+
+static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc)
+{
+ return container_of(gc, struct airoha_gpio_ctrl, gc);
+}
+
+static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio,
+ int val, int out)
+{
+ struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
+ u32 dir = ioread32(ctrl->dir[gpio / 16]);
+ u32 output = ioread32(ctrl->output);
+ u32 mask = BIT((gpio % 16) * 2);
+
+ if (out) {
+ dir |= mask;
+ output |= BIT(gpio);
+ } else {
+ dir &= ~mask;
+ output &= ~BIT(gpio);
+ }
+
+ iowrite32(dir, ctrl->dir[gpio / 16]);
+
+ if (out)
+ gc->set(gc, gpio, val);
+
+ iowrite32(output, ctrl->output);
+
+ return 0;
+}
+
+static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio,
+ int val)
+{
+ return airoha_dir_set(gc, gpio, val, 1);
+}
+
+static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+ return airoha_dir_set(gc, gpio, 0, 0);
+}
+
+static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
+ u32 dir = ioread32(ctrl->dir[gpio / 16]);
+ u32 mask = BIT((gpio % 16) * 2);
+
+ return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
+}
+
+static const struct of_device_id airoha_gpio_of_match[] = {
+ { .compatible = "airoha,en7523-gpio" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, airoha_gpio_of_match);
+
+static int airoha_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct airoha_gpio_ctrl *ctrl;
+ int err;
+
+ ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
+ if (!ctrl)
+ return -ENOMEM;
+
+ ctrl->data = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(ctrl->data))
+ return PTR_ERR(ctrl->data);
+
+ ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(ctrl->dir[0]))
+ return PTR_ERR(ctrl->dir[0]);
+
+ ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2);
+ if (IS_ERR(ctrl->dir[1]))
+ return PTR_ERR(ctrl->dir[1]);
+
+ ctrl->output = devm_platform_ioremap_resource(pdev, 3);
+ if (IS_ERR(ctrl->output))
+ return PTR_ERR(ctrl->output);
+
+ err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL,
+ NULL, NULL, NULL, 0);
+ if (err)
+ return dev_err_probe(dev, err, "unable to init generic GPIO");
+
+ ctrl->gc.ngpio = AIROHA_GPIO_MAX;
+ ctrl->gc.owner = THIS_MODULE;
+ ctrl->gc.direction_output = airoha_dir_out;
+ ctrl->gc.direction_input = airoha_dir_in;
+ ctrl->gc.get_direction = airoha_get_dir;
+
+ return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
+}
+
+static struct platform_driver airoha_gpio_driver = {
+ .driver = {
+ .name = "airoha-gpio",
+ .of_match_table = airoha_gpio_of_match,
+ },
+ .probe = airoha_gpio_probe,
+};
+module_platform_driver(airoha_gpio_driver);
+
+MODULE_DESCRIPTION("Airoha GPIO support");
+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
+MODULE_LICENSE("GPL v2");
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-21 13:49 ` Arnd Bergmann
-1 siblings, 0 replies; 60+ messages in thread
From: Arnd Bergmann @ 2021-12-21 13:49 UTC (permalink / raw)
To: Felix Fietkau
Cc: Linux ARM, Linus Walleij, Bartosz Golaszewski, John Crispin,
Linux Kernel Mailing List, open list:GPIO SUBSYSTEM
On Mon, Dec 20, 2021 at 10:18 PM Felix Fietkau <nbd@nbd.name> wrote:
>
> From: John Crispin <john@phrozen.org>
>
> Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
> GPIOs. Each instance in DT is for a single bank.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This looks ok to me. If you want to merge the entire series through
the SoC tree,
it does need to be reviewed by the GPIO maintainers though. If you want to
go through individual subsystem trees, I would suggest you post this patch
and the DT binding separately from the rest.
Arnd
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
@ 2021-12-21 13:49 ` Arnd Bergmann
0 siblings, 0 replies; 60+ messages in thread
From: Arnd Bergmann @ 2021-12-21 13:49 UTC (permalink / raw)
To: Felix Fietkau
Cc: Linux ARM, Linus Walleij, Bartosz Golaszewski, John Crispin,
Linux Kernel Mailing List, open list:GPIO SUBSYSTEM
On Mon, Dec 20, 2021 at 10:18 PM Felix Fietkau <nbd@nbd.name> wrote:
>
> From: John Crispin <john@phrozen.org>
>
> Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
> GPIOs. Each instance in DT is for a single bank.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This looks ok to me. If you want to merge the entire series through
the SoC tree,
it does need to be reviewed by the GPIO maintainers though. If you want to
go through individual subsystem trees, I would suggest you post this patch
and the DT binding separately from the rest.
Arnd
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
2021-12-21 13:49 ` Arnd Bergmann
@ 2021-12-22 2:34 ` Linus Walleij
-1 siblings, 0 replies; 60+ messages in thread
From: Linus Walleij @ 2021-12-22 2:34 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Felix Fietkau, Linux ARM, Bartosz Golaszewski, John Crispin,
Linux Kernel Mailing List, open list:GPIO SUBSYSTEM
On Tue, Dec 21, 2021 at 2:50 PM Arnd Bergmann <arnd@arndb.de> wrote:
> On Mon, Dec 20, 2021 at 10:18 PM Felix Fietkau <nbd@nbd.name> wrote:
> >
> > From: John Crispin <john@phrozen.org>
> >
> > Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
> > GPIOs. Each instance in DT is for a single bank.
> >
> > Signed-off-by: John Crispin <john@phrozen.org>
> > Signed-off-by: Felix Fietkau <nbd@nbd.name>
>
> This looks ok to me. If you want to merge the entire series through
> the SoC tree,
> it does need to be reviewed by the GPIO maintainers though. If you want to
> go through individual subsystem trees, I would suggest you post this patch
> and the DT binding separately from the rest.
I reviewed a v7 version I think, anyways:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
@ 2021-12-22 2:34 ` Linus Walleij
0 siblings, 0 replies; 60+ messages in thread
From: Linus Walleij @ 2021-12-22 2:34 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Felix Fietkau, Linux ARM, Bartosz Golaszewski, John Crispin,
Linux Kernel Mailing List, open list:GPIO SUBSYSTEM
On Tue, Dec 21, 2021 at 2:50 PM Arnd Bergmann <arnd@arndb.de> wrote:
> On Mon, Dec 20, 2021 at 10:18 PM Felix Fietkau <nbd@nbd.name> wrote:
> >
> > From: John Crispin <john@phrozen.org>
> >
> > Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
> > GPIOs. Each instance in DT is for a single bank.
> >
> > Signed-off-by: John Crispin <john@phrozen.org>
> > Signed-off-by: Felix Fietkau <nbd@nbd.name>
>
> This looks ok to me. If you want to merge the entire series through
> the SoC tree,
> it does need to be reviewed by the GPIO maintainers though. If you want to
> go through individual subsystem trees, I would suggest you post this patch
> and the DT binding separately from the rest.
I reviewed a v7 version I think, anyways:
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-22 7:56 ` Bartosz Golaszewski
-1 siblings, 0 replies; 60+ messages in thread
From: Bartosz Golaszewski @ 2021-12-22 7:56 UTC (permalink / raw)
To: Felix Fietkau
Cc: Linux ARM, Linus Walleij, John Crispin,
Linux Kernel Mailing List, open list:GPIO SUBSYSTEM
On Mon, Dec 20, 2021 at 10:24 PM Felix Fietkau <nbd@nbd.name> wrote:
>
> From: John Crispin <john@phrozen.org>
>
> Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
> GPIOs. Each instance in DT is for a single bank.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
Acked-by: Bartosz Golaszewski <brgl@bgdev.pl>
Arnd: Please go ahead and take it through the arm-soc tree.
Bart
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
@ 2021-12-22 7:56 ` Bartosz Golaszewski
0 siblings, 0 replies; 60+ messages in thread
From: Bartosz Golaszewski @ 2021-12-22 7:56 UTC (permalink / raw)
To: Felix Fietkau
Cc: Linux ARM, Linus Walleij, John Crispin,
Linux Kernel Mailing List, open list:GPIO SUBSYSTEM
On Mon, Dec 20, 2021 at 10:24 PM Felix Fietkau <nbd@nbd.name> wrote:
>
> From: John Crispin <john@phrozen.org>
>
> Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
> GPIOs. Each instance in DT is for a single bank.
>
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
Acked-by: Bartosz Golaszewski <brgl@bgdev.pl>
Arnd: Please go ahead and take it through the arm-soc tree.
Bart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-22 12:03 ` Andy Shevchenko
-1 siblings, 0 replies; 60+ messages in thread
From: Andy Shevchenko @ 2021-12-22 12:03 UTC (permalink / raw)
To: Felix Fietkau
Cc: linux-arm Mailing List, Linus Walleij, Bartosz Golaszewski, john,
Linux Kernel Mailing List, open list:GPIO SUBSYSTEM
On Tue, Dec 21, 2021 at 12:02 AM Felix Fietkau <nbd@nbd.name> wrote:
>
> From: John Crispin <john@phrozen.org>
>
> Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
> GPIOs. Each instance in DT is for a single bank.
FWIW,
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
A couple of minor comments and one about headers below.
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> drivers/gpio/Kconfig | 9 +++
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-en7523.c | 134 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 144 insertions(+)
> create mode 100644 drivers/gpio/gpio-en7523.c
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 072ed610f9c6..e4a34272504f 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -247,6 +247,15 @@ config GPIO_EM
> help
> Say yes here to support GPIO on Renesas Emma Mobile SoCs.
>
> +config GPIO_EN7523
> + tristate "Airoha GPIO support"
> + depends on ARCH_AIROHA
> + default ARCH_AIROHA
> + select GPIO_GENERIC
> + select GPIOLIB_IRQCHIP
> + help
> + Say yes here to support the GPIO controller on Airoha EN7523.
Checkpatch nowadays wants a better description. Also add a paragraph
at the end, like many other drivers do, what the module would be if
selected as M.
> config GPIO_EP93XX
> def_bool y
> depends on ARCH_EP93XX
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 71ee9fc2ff83..d2269ee0948e 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o
> obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o
> obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o
> obj-$(CONFIG_GPIO_EM) += gpio-em.o
> +obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o
> obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
> obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o
> obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
> diff --git a/drivers/gpio/gpio-en7523.c b/drivers/gpio/gpio-en7523.c
> new file mode 100644
> index 000000000000..67631396cd93
> --- /dev/null
> +++ b/drivers/gpio/gpio-en7523.c
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include <linux/gpio/driver.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
Missed headers
types.h for _iomem, etc.
io.h for I/O accessors.
bits.h for BIT(), etc.
> +#define AIROHA_GPIO_MAX 32
> +
> +/**
> + * airoha_gpio_ctrl - Airoha GPIO driver data
> + * @gc: Associated gpio_chip instance.
> + * @data: The data register.
> + * @dir0: The direction register for the lower 16 pins.
> + * @dir1: The direction register for the higher 16 pins.
> + * @output: The output enable register.
> + */
> +struct airoha_gpio_ctrl {
> + struct gpio_chip gc;
> + void __iomem *data;
> + void __iomem *dir[2];
> + void __iomem *output;
> +};
> +
> +static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc)
> +{
> + return container_of(gc, struct airoha_gpio_ctrl, gc);
> +}
> +
> +static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio,
> + int val, int out)
> +{
> + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
> + u32 dir = ioread32(ctrl->dir[gpio / 16]);
> + u32 output = ioread32(ctrl->output);
> + u32 mask = BIT((gpio % 16) * 2);
> +
> + if (out) {
> + dir |= mask;
> + output |= BIT(gpio);
> + } else {
> + dir &= ~mask;
> + output &= ~BIT(gpio);
> + }
> +
> + iowrite32(dir, ctrl->dir[gpio / 16]);
> +
> + if (out)
> + gc->set(gc, gpio, val);
> +
> + iowrite32(output, ctrl->output);
> +
> + return 0;
> +}
> +
> +static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio,
> + int val)
> +{
> + return airoha_dir_set(gc, gpio, val, 1);
> +}
> +
> +static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio)
> +{
> + return airoha_dir_set(gc, gpio, 0, 0);
> +}
> +
> +static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio)
> +{
> + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
> + u32 dir = ioread32(ctrl->dir[gpio / 16]);
> + u32 mask = BIT((gpio % 16) * 2);
> +
> + return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
> +}
> +static const struct of_device_id airoha_gpio_of_match[] = {
> + { .compatible = "airoha,en7523-gpio" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, airoha_gpio_of_match);
Move this below, closer to its user.
> +static int airoha_gpio_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct airoha_gpio_ctrl *ctrl;
> + int err;
> +
> + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
> + if (!ctrl)
> + return -ENOMEM;
> +
> + ctrl->data = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(ctrl->data))
> + return PTR_ERR(ctrl->data);
> +
> + ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(ctrl->dir[0]))
> + return PTR_ERR(ctrl->dir[0]);
> +
> + ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2);
> + if (IS_ERR(ctrl->dir[1]))
> + return PTR_ERR(ctrl->dir[1]);
> +
> + ctrl->output = devm_platform_ioremap_resource(pdev, 3);
> + if (IS_ERR(ctrl->output))
> + return PTR_ERR(ctrl->output);
> +
> + err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL,
> + NULL, NULL, NULL, 0);
> + if (err)
> + return dev_err_probe(dev, err, "unable to init generic GPIO");
> +
> + ctrl->gc.ngpio = AIROHA_GPIO_MAX;
> + ctrl->gc.owner = THIS_MODULE;
> + ctrl->gc.direction_output = airoha_dir_out;
> + ctrl->gc.direction_input = airoha_dir_in;
> + ctrl->gc.get_direction = airoha_get_dir;
> +
> + return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
> +}
> +
> +static struct platform_driver airoha_gpio_driver = {
> + .driver = {
> + .name = "airoha-gpio",
> + .of_match_table = airoha_gpio_of_match,
> + },
> + .probe = airoha_gpio_probe,
> +};
> +module_platform_driver(airoha_gpio_driver);
> +
> +MODULE_DESCRIPTION("Airoha GPIO support");
> +MODULE_AUTHOR("John Crispin <john@phrozen.org>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.34.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v8 13/14] gpio: Add support for Airoha EN7523 GPIO controller
@ 2021-12-22 12:03 ` Andy Shevchenko
0 siblings, 0 replies; 60+ messages in thread
From: Andy Shevchenko @ 2021-12-22 12:03 UTC (permalink / raw)
To: Felix Fietkau
Cc: linux-arm Mailing List, Linus Walleij, Bartosz Golaszewski, john,
Linux Kernel Mailing List, open list:GPIO SUBSYSTEM
On Tue, Dec 21, 2021 at 12:02 AM Felix Fietkau <nbd@nbd.name> wrote:
>
> From: John Crispin <john@phrozen.org>
>
> Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
> GPIOs. Each instance in DT is for a single bank.
FWIW,
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
A couple of minor comments and one about headers below.
> Signed-off-by: John Crispin <john@phrozen.org>
> Signed-off-by: Felix Fietkau <nbd@nbd.name>
> ---
> drivers/gpio/Kconfig | 9 +++
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-en7523.c | 134 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 144 insertions(+)
> create mode 100644 drivers/gpio/gpio-en7523.c
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 072ed610f9c6..e4a34272504f 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -247,6 +247,15 @@ config GPIO_EM
> help
> Say yes here to support GPIO on Renesas Emma Mobile SoCs.
>
> +config GPIO_EN7523
> + tristate "Airoha GPIO support"
> + depends on ARCH_AIROHA
> + default ARCH_AIROHA
> + select GPIO_GENERIC
> + select GPIOLIB_IRQCHIP
> + help
> + Say yes here to support the GPIO controller on Airoha EN7523.
Checkpatch nowadays wants a better description. Also add a paragraph
at the end, like many other drivers do, what the module would be if
selected as M.
> config GPIO_EP93XX
> def_bool y
> depends on ARCH_EP93XX
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 71ee9fc2ff83..d2269ee0948e 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_DLN2) += gpio-dln2.o
> obj-$(CONFIG_GPIO_DWAPB) += gpio-dwapb.o
> obj-$(CONFIG_GPIO_EIC_SPRD) += gpio-eic-sprd.o
> obj-$(CONFIG_GPIO_EM) += gpio-em.o
> +obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o
> obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
> obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o
> obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
> diff --git a/drivers/gpio/gpio-en7523.c b/drivers/gpio/gpio-en7523.c
> new file mode 100644
> index 000000000000..67631396cd93
> --- /dev/null
> +++ b/drivers/gpio/gpio-en7523.c
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include <linux/gpio/driver.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
Missed headers
types.h for _iomem, etc.
io.h for I/O accessors.
bits.h for BIT(), etc.
> +#define AIROHA_GPIO_MAX 32
> +
> +/**
> + * airoha_gpio_ctrl - Airoha GPIO driver data
> + * @gc: Associated gpio_chip instance.
> + * @data: The data register.
> + * @dir0: The direction register for the lower 16 pins.
> + * @dir1: The direction register for the higher 16 pins.
> + * @output: The output enable register.
> + */
> +struct airoha_gpio_ctrl {
> + struct gpio_chip gc;
> + void __iomem *data;
> + void __iomem *dir[2];
> + void __iomem *output;
> +};
> +
> +static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc)
> +{
> + return container_of(gc, struct airoha_gpio_ctrl, gc);
> +}
> +
> +static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio,
> + int val, int out)
> +{
> + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
> + u32 dir = ioread32(ctrl->dir[gpio / 16]);
> + u32 output = ioread32(ctrl->output);
> + u32 mask = BIT((gpio % 16) * 2);
> +
> + if (out) {
> + dir |= mask;
> + output |= BIT(gpio);
> + } else {
> + dir &= ~mask;
> + output &= ~BIT(gpio);
> + }
> +
> + iowrite32(dir, ctrl->dir[gpio / 16]);
> +
> + if (out)
> + gc->set(gc, gpio, val);
> +
> + iowrite32(output, ctrl->output);
> +
> + return 0;
> +}
> +
> +static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio,
> + int val)
> +{
> + return airoha_dir_set(gc, gpio, val, 1);
> +}
> +
> +static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio)
> +{
> + return airoha_dir_set(gc, gpio, 0, 0);
> +}
> +
> +static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio)
> +{
> + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
> + u32 dir = ioread32(ctrl->dir[gpio / 16]);
> + u32 mask = BIT((gpio % 16) * 2);
> +
> + return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
> +}
> +static const struct of_device_id airoha_gpio_of_match[] = {
> + { .compatible = "airoha,en7523-gpio" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, airoha_gpio_of_match);
Move this below, closer to its user.
> +static int airoha_gpio_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct airoha_gpio_ctrl *ctrl;
> + int err;
> +
> + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
> + if (!ctrl)
> + return -ENOMEM;
> +
> + ctrl->data = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(ctrl->data))
> + return PTR_ERR(ctrl->data);
> +
> + ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1);
> + if (IS_ERR(ctrl->dir[0]))
> + return PTR_ERR(ctrl->dir[0]);
> +
> + ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2);
> + if (IS_ERR(ctrl->dir[1]))
> + return PTR_ERR(ctrl->dir[1]);
> +
> + ctrl->output = devm_platform_ioremap_resource(pdev, 3);
> + if (IS_ERR(ctrl->output))
> + return PTR_ERR(ctrl->output);
> +
> + err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL,
> + NULL, NULL, NULL, 0);
> + if (err)
> + return dev_err_probe(dev, err, "unable to init generic GPIO");
> +
> + ctrl->gc.ngpio = AIROHA_GPIO_MAX;
> + ctrl->gc.owner = THIS_MODULE;
> + ctrl->gc.direction_output = airoha_dir_out;
> + ctrl->gc.direction_input = airoha_dir_in;
> + ctrl->gc.get_direction = airoha_get_dir;
> +
> + return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
> +}
> +
> +static struct platform_driver airoha_gpio_driver = {
> + .driver = {
> + .name = "airoha-gpio",
> + .of_match_table = airoha_gpio_of_match,
> + },
> + .probe = airoha_gpio_probe,
> +};
> +module_platform_driver(airoha_gpio_driver);
> +
> +MODULE_DESCRIPTION("Airoha GPIO support");
> +MODULE_AUTHOR("John Crispin <john@phrozen.org>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.34.1
>
--
With Best Regards,
Andy Shevchenko
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v8 14/14] ARM: dts: add GPIO support for Airoha EN7523
2021-12-20 21:18 ` Felix Fietkau
@ 2021-12-20 21:18 ` Felix Fietkau
-1 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring; +Cc: john, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
GPIOs
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/boot/dts/en7523-evb.dts | 8 ++++++++
arch/arm/boot/dts/en7523.dtsi | 20 ++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
index 0a79f5f6c311..cd9cded5b564 100644
--- a/arch/arm/boot/dts/en7523-evb.dts
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -33,3 +33,11 @@ &pcie0 {
&pcie1 {
status = "okay";
};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
index 862da104d6f2..d9cc5a1b83b8 100644
--- a/arch/arm/boot/dts/en7523.dtsi
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/en7523-clk.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
interrupt-parent = <&gic>;
@@ -120,6 +121,25 @@ uart1: serial@1fbf0000 {
status = "okay";
};
+ gpio0: gpio@1fbf0200 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0204 0x4>,
+ <0x1fbf0200 0x4>,
+ <0x1fbf0220 0x4>,
+ <0x1fbf0214 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio1: gpio@1fbf0270 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0270 0x4>,
+ <0x1fbf0260 0x4>,
+ <0x1fbf0264 0x4>,
+ <0x1fbf0278 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
pcie0: pcie@1fa91000 {
compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
--
2.34.1
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v8 14/14] ARM: dts: add GPIO support for Airoha EN7523
@ 2021-12-20 21:18 ` Felix Fietkau
0 siblings, 0 replies; 60+ messages in thread
From: Felix Fietkau @ 2021-12-20 21:18 UTC (permalink / raw)
To: linux-arm-kernel, Rob Herring; +Cc: john, devicetree, linux-kernel
From: John Crispin <john@phrozen.org>
Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
GPIOs
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
arch/arm/boot/dts/en7523-evb.dts | 8 ++++++++
arch/arm/boot/dts/en7523.dtsi | 20 ++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
index 0a79f5f6c311..cd9cded5b564 100644
--- a/arch/arm/boot/dts/en7523-evb.dts
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -33,3 +33,11 @@ &pcie0 {
&pcie1 {
status = "okay";
};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
index 862da104d6f2..d9cc5a1b83b8 100644
--- a/arch/arm/boot/dts/en7523.dtsi
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/en7523-clk.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
interrupt-parent = <&gic>;
@@ -120,6 +121,25 @@ uart1: serial@1fbf0000 {
status = "okay";
};
+ gpio0: gpio@1fbf0200 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0204 0x4>,
+ <0x1fbf0200 0x4>,
+ <0x1fbf0220 0x4>,
+ <0x1fbf0214 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio1: gpio@1fbf0270 {
+ compatible = "airoha,en7523-gpio";
+ reg = <0x1fbf0270 0x4>,
+ <0x1fbf0260 0x4>,
+ <0x1fbf0264 0x4>,
+ <0x1fbf0278 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
pcie0: pcie@1fa91000 {
compatible = "airoha,en7523-pcie", "mediatek,mt7622-pcie";
--
2.34.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 60+ messages in thread