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From: Atish Patra <atishp@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Bin Meng <bin.meng@windriver.com>,
	Atish Patra <atishp@rivosinc.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function
Date: Thu,  6 Jan 2022 16:48:36 -0800	[thread overview]
Message-ID: <20220107004846.378859-2-atishp@rivosinc.com> (raw)
In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com>

From: Atish Patra <atish.patra@wdc.com>

The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.

Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/csr.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 146447eac5d5..53a621fdbaef 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -90,8 +90,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
             }
             break;
         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
-            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
-                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+            ctr_index = csrno - CSR_CYCLE;
+            if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                 get_field(env->mcounteren, 1 << ctr_index)) {
                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
             }
             break;
@@ -117,8 +118,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
                 }
                 break;
             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
-                if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
-                    get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+                ctr_index = csrno - CSR_CYCLEH;
+                if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                     get_field(env->mcounteren, 1 << ctr_index)) {
                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                 }
                 break;
-- 
2.30.2



WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>, Atish Patra <atishp@rivosinc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	qemu-riscv@nongnu.org
Subject: [PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function
Date: Thu,  6 Jan 2022 16:48:36 -0800	[thread overview]
Message-ID: <20220107004846.378859-2-atishp@rivosinc.com> (raw)
In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com>

From: Atish Patra <atish.patra@wdc.com>

The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.

Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/csr.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 146447eac5d5..53a621fdbaef 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -90,8 +90,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
             }
             break;
         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
-            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
-                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+            ctr_index = csrno - CSR_CYCLE;
+            if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                 get_field(env->mcounteren, 1 << ctr_index)) {
                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
             }
             break;
@@ -117,8 +118,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
                 }
                 break;
             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
-                if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
-                    get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+                ctr_index = csrno - CSR_CYCLEH;
+                if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                     get_field(env->mcounteren, 1 << ctr_index)) {
                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                 }
                 break;
-- 
2.30.2



  reply	other threads:[~2022-01-07  2:25 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-07  0:48 [PATCH v4 00/11] Improve PMU support Atish Patra
2022-01-07  0:48 ` Atish Patra
2022-01-07  0:48 ` Atish Patra [this message]
2022-01-07  0:48   ` [PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function Atish Patra
2022-01-07  0:48 ` [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  7:50   ` Bin Meng
2022-01-07  7:50     ` Bin Meng
2022-01-07  0:48 ` [PATCH v4 03/11] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  0:48 ` [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  7:50   ` Bin Meng
2022-01-07  7:50     ` Bin Meng
2022-01-10  6:46   ` Alistair Francis
2022-01-10  6:46     ` Alistair Francis
2022-01-07  0:48 ` [PATCH v4 05/11] target/riscv: Implement mcountinhibit CSR Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  0:48 ` [PATCH v4 06/11] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07 10:52   ` Bin Meng
2022-01-07 10:52     ` Bin Meng
2022-01-07  0:48 ` [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-10  7:25   ` Bin Meng
2022-01-10  7:25     ` Bin Meng
2022-01-11 19:57     ` Atish Patra
2022-01-11 19:57       ` Atish Patra
2022-01-12 14:01       ` Bin Meng
2022-01-12 14:01         ` Bin Meng
2022-01-07  0:48 ` [PATCH v4 08/11] target/riscv: Add sscofpmf extension support Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-10 11:34   ` Anup Patel
2022-01-10 11:34     ` Anup Patel
2022-01-10 22:38     ` Atish Kumar Patra
2022-01-10 22:38       ` Atish Kumar Patra
2022-01-07  0:48 ` [PATCH v4 09/11] target/riscv: Simplify counter predicate function Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-10  8:26   ` Bin Meng
2022-01-10  8:26     ` Bin Meng
2022-01-10 22:35     ` Atish Kumar Patra
2022-01-10 22:35       ` Atish Kumar Patra
2022-01-07  0:48 ` [PATCH v4 10/11] target/riscv: Add few cache related PMU events Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  0:48 ` [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07 13:51   ` Philippe Mathieu-Daudé
2022-01-07 13:51     ` Philippe Mathieu-Daudé
2022-01-10  1:23     ` Atish Patra
2022-01-10  1:23       ` Atish Patra
2022-01-10  7:55   ` Bin Meng
2022-01-10  7:55     ` Bin Meng
2022-01-10 22:42     ` Atish Kumar Patra
2022-01-10 22:42       ` Atish Kumar Patra

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