From: Atish Patra <atishp@rivosinc.com> To: qemu-devel@nongnu.org Cc: Atish Patra <atishp@rivosinc.com>, Bin Meng <bin.meng@windriver.com>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, qemu-riscv@nongnu.org Subject: [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode Date: Thu, 6 Jan 2022 16:48:37 -0800 [thread overview] Message-ID: <20220107004846.378859-3-atishp@rivosinc.com> (raw) In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> From: Atish Patra <atish.patra@wdc.com> Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/csr.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 53a621fdbaef..823cc306d74b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -63,12 +63,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); + int ctr_index; if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ return RISCV_EXCP_ILLEGAL_INST; } + if (env->priv == PRV_S) { + switch (csrno) { + case CSR_CYCLE: + if (!get_field(env->mcounteren, COUNTEREN_CY)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_TIME: + if (!get_field(env->mcounteren, COUNTEREN_TM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_INSTRET: + if (!get_field(env->mcounteren, COUNTEREN_IR)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: + ctr_index = csrno - CSR_CYCLE; + if (!get_field(env->mcounteren, 1 << ctr_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + } + if (riscv_cpu_is_32bit(env)) { + switch (csrno) { + case CSR_CYCLEH: + if (!get_field(env->mcounteren, COUNTEREN_CY)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_TIMEH: + if (!get_field(env->mcounteren, COUNTEREN_TM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_INSTRETH: + if (!get_field(env->mcounteren, COUNTEREN_IR)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: + ctr_index = csrno - CSR_CYCLEH; + if (!get_field(env->mcounteren, 1 << ctr_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + } + } + } + if (riscv_cpu_virt_enabled(env)) { switch (csrno) { case CSR_CYCLE: -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com> To: qemu-devel@nongnu.org Cc: Alistair Francis <alistair.francis@wdc.com>, Atish Patra <atishp@rivosinc.com>, Bin Meng <bin.meng@windriver.com>, Palmer Dabbelt <palmer@dabbelt.com>, qemu-riscv@nongnu.org Subject: [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode Date: Thu, 6 Jan 2022 16:48:37 -0800 [thread overview] Message-ID: <20220107004846.378859-3-atishp@rivosinc.com> (raw) In-Reply-To: <20220107004846.378859-1-atishp@rivosinc.com> From: Atish Patra <atish.patra@wdc.com> Currently, the predicate function for PMU related CSRs only works if virtualization is enabled. It also does not check mcounteren bits before before cycle/minstret/hpmcounterx access. Support supervisor mode access in the predicate function as well. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/csr.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 53a621fdbaef..823cc306d74b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -63,12 +63,64 @@ static RISCVException ctr(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); + int ctr_index; if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ return RISCV_EXCP_ILLEGAL_INST; } + if (env->priv == PRV_S) { + switch (csrno) { + case CSR_CYCLE: + if (!get_field(env->mcounteren, COUNTEREN_CY)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_TIME: + if (!get_field(env->mcounteren, COUNTEREN_TM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_INSTRET: + if (!get_field(env->mcounteren, COUNTEREN_IR)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: + ctr_index = csrno - CSR_CYCLE; + if (!get_field(env->mcounteren, 1 << ctr_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + } + if (riscv_cpu_is_32bit(env)) { + switch (csrno) { + case CSR_CYCLEH: + if (!get_field(env->mcounteren, COUNTEREN_CY)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_TIMEH: + if (!get_field(env->mcounteren, COUNTEREN_TM)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_INSTRETH: + if (!get_field(env->mcounteren, COUNTEREN_IR)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: + ctr_index = csrno - CSR_CYCLEH; + if (!get_field(env->mcounteren, 1 << ctr_index)) { + return RISCV_EXCP_ILLEGAL_INST; + } + break; + } + } + } + if (riscv_cpu_virt_enabled(env)) { switch (csrno) { case CSR_CYCLE: -- 2.30.2
next prev parent reply other threads:[~2022-01-07 2:17 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-07 0:48 [PATCH v4 00/11] Improve PMU support Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-07 0:48 ` [PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-07 0:48 ` Atish Patra [this message] 2022-01-07 0:48 ` [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra 2022-01-07 7:50 ` Bin Meng 2022-01-07 7:50 ` Bin Meng 2022-01-07 0:48 ` [PATCH v4 03/11] target/riscv: pmu: Rename the counters extension to pmu Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-07 0:48 ` [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-07 7:50 ` Bin Meng 2022-01-07 7:50 ` Bin Meng 2022-01-10 6:46 ` Alistair Francis 2022-01-10 6:46 ` Alistair Francis 2022-01-07 0:48 ` [PATCH v4 05/11] target/riscv: Implement mcountinhibit CSR Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-07 0:48 ` [PATCH v4 06/11] target/riscv: Add support for hpmcounters/hpmevents Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-07 10:52 ` Bin Meng 2022-01-07 10:52 ` Bin Meng 2022-01-07 0:48 ` [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-10 7:25 ` Bin Meng 2022-01-10 7:25 ` Bin Meng 2022-01-11 19:57 ` Atish Patra 2022-01-11 19:57 ` Atish Patra 2022-01-12 14:01 ` Bin Meng 2022-01-12 14:01 ` Bin Meng 2022-01-07 0:48 ` [PATCH v4 08/11] target/riscv: Add sscofpmf extension support Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-10 11:34 ` Anup Patel 2022-01-10 11:34 ` Anup Patel 2022-01-10 22:38 ` Atish Kumar Patra 2022-01-10 22:38 ` Atish Kumar Patra 2022-01-07 0:48 ` [PATCH v4 09/11] target/riscv: Simplify counter predicate function Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-10 8:26 ` Bin Meng 2022-01-10 8:26 ` Bin Meng 2022-01-10 22:35 ` Atish Kumar Patra 2022-01-10 22:35 ` Atish Kumar Patra 2022-01-07 0:48 ` [PATCH v4 10/11] target/riscv: Add few cache related PMU events Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-07 0:48 ` [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra 2022-01-07 0:48 ` Atish Patra 2022-01-07 13:51 ` Philippe Mathieu-Daudé 2022-01-07 13:51 ` Philippe Mathieu-Daudé 2022-01-10 1:23 ` Atish Patra 2022-01-10 1:23 ` Atish Patra 2022-01-10 7:55 ` Bin Meng 2022-01-10 7:55 ` Bin Meng 2022-01-10 22:42 ` Atish Kumar Patra 2022-01-10 22:42 ` Atish Kumar Patra
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