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From: Bin Meng <bmeng.cn@gmail.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable
Date: Fri, 7 Jan 2022 15:50:57 +0800	[thread overview]
Message-ID: <CAEUhbmUkpqeLntB_5d85+1nyjxWAs64FvbfmCft-qKvjK5t3dw@mail.gmail.com> (raw)
In-Reply-To: <20220107004846.378859-5-atishp@rivosinc.com>

On Fri, Jan 7, 2022 at 10:18 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> The RISC-V privilege specification provides flexibility to implement
> any number of counters from 29 programmable counters. However, the QEMU
> implements all the counters.
>
> Make it configurable through pmu config parameter which now will indicate
> how many programmable counters should be implemented by the cpu.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  target/riscv/cpu.c |  2 +-
>  target/riscv/cpu.h |  2 +-
>  target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++----------------
>  3 files changed, 65 insertions(+), 35 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <alistair.francis@wdc.com>,
	 Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 "open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable
Date: Fri, 7 Jan 2022 15:50:57 +0800	[thread overview]
Message-ID: <CAEUhbmUkpqeLntB_5d85+1nyjxWAs64FvbfmCft-qKvjK5t3dw@mail.gmail.com> (raw)
In-Reply-To: <20220107004846.378859-5-atishp@rivosinc.com>

On Fri, Jan 7, 2022 at 10:18 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> The RISC-V privilege specification provides flexibility to implement
> any number of counters from 29 programmable counters. However, the QEMU
> implements all the counters.
>
> Make it configurable through pmu config parameter which now will indicate
> how many programmable counters should be implemented by the cpu.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  target/riscv/cpu.c |  2 +-
>  target/riscv/cpu.h |  2 +-
>  target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++----------------
>  3 files changed, 65 insertions(+), 35 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


  reply	other threads:[~2022-01-07  7:57 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-07  0:48 [PATCH v4 00/11] Improve PMU support Atish Patra
2022-01-07  0:48 ` Atish Patra
2022-01-07  0:48 ` [PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  0:48 ` [PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  7:50   ` Bin Meng
2022-01-07  7:50     ` Bin Meng
2022-01-07  0:48 ` [PATCH v4 03/11] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  0:48 ` [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  7:50   ` Bin Meng [this message]
2022-01-07  7:50     ` Bin Meng
2022-01-10  6:46   ` Alistair Francis
2022-01-10  6:46     ` Alistair Francis
2022-01-07  0:48 ` [PATCH v4 05/11] target/riscv: Implement mcountinhibit CSR Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  0:48 ` [PATCH v4 06/11] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07 10:52   ` Bin Meng
2022-01-07 10:52     ` Bin Meng
2022-01-07  0:48 ` [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-10  7:25   ` Bin Meng
2022-01-10  7:25     ` Bin Meng
2022-01-11 19:57     ` Atish Patra
2022-01-11 19:57       ` Atish Patra
2022-01-12 14:01       ` Bin Meng
2022-01-12 14:01         ` Bin Meng
2022-01-07  0:48 ` [PATCH v4 08/11] target/riscv: Add sscofpmf extension support Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-10 11:34   ` Anup Patel
2022-01-10 11:34     ` Anup Patel
2022-01-10 22:38     ` Atish Kumar Patra
2022-01-10 22:38       ` Atish Kumar Patra
2022-01-07  0:48 ` [PATCH v4 09/11] target/riscv: Simplify counter predicate function Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-10  8:26   ` Bin Meng
2022-01-10  8:26     ` Bin Meng
2022-01-10 22:35     ` Atish Kumar Patra
2022-01-10 22:35       ` Atish Kumar Patra
2022-01-07  0:48 ` [PATCH v4 10/11] target/riscv: Add few cache related PMU events Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07  0:48 ` [PATCH v4 11/11] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-01-07  0:48   ` Atish Patra
2022-01-07 13:51   ` Philippe Mathieu-Daudé
2022-01-07 13:51     ` Philippe Mathieu-Daudé
2022-01-10  1:23     ` Atish Patra
2022-01-10  1:23       ` Atish Patra
2022-01-10  7:55   ` Bin Meng
2022-01-10  7:55     ` Bin Meng
2022-01-10 22:42     ` Atish Kumar Patra
2022-01-10 22:42       ` Atish Kumar Patra

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