[PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Peter Geis]

The hdmi-cec clock must be 32khz in order for cec to work correctly.
Ensure after enabling the clock we set it in order for the hardware to
work as expected.
Warn on failure, in case this is a static clock that is slighty off.
Fixes hdmi-cec support on Rockchip devices.

Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 54d8fdad395f..1a96da60e357 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -48,6 +48,9 @@
 
 #define HDMI14_MAX_TMDSCLK	340000000
 
+/* HDMI CEC needs a clock rate of 32khz */
+#define HDMI_CEC_CLK_RATE	32768
+
 enum hdmi_datamap {
 	RGB444_8B = 0x01,
 	RGB444_10B = 0x03,
@@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
 				ret);
 			goto err_iahb;
 		}
+
+		ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
+		if (ret)
+			dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
 	}
 
 	/* Product and revision IDs */
-- 
2.25.1

[PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Peter Geis]

The hdmi-cec clock must be 32khz in order for cec to work correctly.
Ensure after enabling the clock we set it in order for the hardware to
work as expected.
Warn on failure, in case this is a static clock that is slighty off.
Fixes hdmi-cec support on Rockchip devices.

Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 54d8fdad395f..1a96da60e357 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -48,6 +48,9 @@
 
 #define HDMI14_MAX_TMDSCLK	340000000
 
+/* HDMI CEC needs a clock rate of 32khz */
+#define HDMI_CEC_CLK_RATE	32768
+
 enum hdmi_datamap {
 	RGB444_8B = 0x01,
 	RGB444_10B = 0x03,
@@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
 				ret);
 			goto err_iahb;
 		}
+
+		ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
+		if (ret)
+			dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
 	}
 
 	/* Product and revision IDs */
-- 
2.25.1

[PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Peter Geis]

The hdmi-cec clock must be 32khz in order for cec to work correctly.
Ensure after enabling the clock we set it in order for the hardware to
work as expected.
Warn on failure, in case this is a static clock that is slighty off.
Fixes hdmi-cec support on Rockchip devices.

Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 54d8fdad395f..1a96da60e357 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -48,6 +48,9 @@
 
 #define HDMI14_MAX_TMDSCLK	340000000
 
+/* HDMI CEC needs a clock rate of 32khz */
+#define HDMI_CEC_CLK_RATE	32768
+
 enum hdmi_datamap {
 	RGB444_8B = 0x01,
 	RGB444_10B = 0x03,
@@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
 				ret);
 			goto err_iahb;
 		}
+
+		ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
+		if (ret)
+			dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
 	}
 
 	/* Product and revision IDs */
-- 
2.25.1


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Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Fabio Estevam]

On Wed, Jan 26, 2022 at 5:25 PM Peter Geis <pgwipeout@gmail.com> wrote:

> +
> +               ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> +               if (ret)
> +                       dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);

You are setting the cec clock rate after it has been enabled, which
can be glitchy.

Better to set the rate prior to enabling the clock.

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Fabio Estevam]

On Wed, Jan 26, 2022 at 5:25 PM Peter Geis <pgwipeout@gmail.com> wrote:

> +
> +               ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> +               if (ret)
> +                       dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);

You are setting the cec clock rate after it has been enabled, which
can be glitchy.

Better to set the rate prior to enabling the clock.

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Fabio Estevam]

On Wed, Jan 26, 2022 at 5:25 PM Peter Geis <pgwipeout@gmail.com> wrote:

> +
> +               ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> +               if (ret)
> +                       dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);

You are setting the cec clock rate after it has been enabled, which
can be glitchy.

Better to set the rate prior to enabling the clock.

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Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Sascha Hauer]

Hi Peter,

On Wed, Jan 26, 2022 at 03:24:26PM -0500, Peter Geis wrote:
> The hdmi-cec clock must be 32khz in order for cec to work correctly.
> Ensure after enabling the clock we set it in order for the hardware to
> work as expected.
> Warn on failure, in case this is a static clock that is slighty off.
> Fixes hdmi-cec support on Rockchip devices.

You removed this sentence in v2, but I just wanted to mention that
clk_set_rate() won't fail when the desired clock rate can't be
archieved. Instead, you will get the best rate that actually can be
reached. If you want to check that you are happy with the rate you'll
have to do a clk_round_rate() before setting the rate or a
clk_get_rate() afterwards.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Sascha Hauer]

Hi Peter,

On Wed, Jan 26, 2022 at 03:24:26PM -0500, Peter Geis wrote:
> The hdmi-cec clock must be 32khz in order for cec to work correctly.
> Ensure after enabling the clock we set it in order for the hardware to
> work as expected.
> Warn on failure, in case this is a static clock that is slighty off.
> Fixes hdmi-cec support on Rockchip devices.

You removed this sentence in v2, but I just wanted to mention that
clk_set_rate() won't fail when the desired clock rate can't be
archieved. Instead, you will get the best rate that actually can be
reached. If you want to check that you are happy with the rate you'll
have to do a clk_round_rate() before setting the rate or a
clk_get_rate() afterwards.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Sascha Hauer]

Hi Peter,

On Wed, Jan 26, 2022 at 03:24:26PM -0500, Peter Geis wrote:
> The hdmi-cec clock must be 32khz in order for cec to work correctly.
> Ensure after enabling the clock we set it in order for the hardware to
> work as expected.
> Warn on failure, in case this is a static clock that is slighty off.
> Fixes hdmi-cec support on Rockchip devices.

You removed this sentence in v2, but I just wanted to mention that
clk_set_rate() won't fail when the desired clock rate can't be
archieved. Instead, you will get the best rate that actually can be
reached. If you want to check that you are happy with the rate you'll
have to do a clk_round_rate() before setting the rate or a
clk_get_rate() afterwards.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Peter Geis]

On Thu, Jan 27, 2022 at 4:33 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> Hi Peter,
>
> On Wed, Jan 26, 2022 at 03:24:26PM -0500, Peter Geis wrote:
> > The hdmi-cec clock must be 32khz in order for cec to work correctly.
> > Ensure after enabling the clock we set it in order for the hardware to
> > work as expected.
> > Warn on failure, in case this is a static clock that is slighty off.
> > Fixes hdmi-cec support on Rockchip devices.
>
> You removed this sentence in v2, but I just wanted to mention that
> clk_set_rate() won't fail when the desired clock rate can't be
> archieved. Instead, you will get the best rate that actually can be
> reached. If you want to check that you are happy with the rate you'll
> have to do a clk_round_rate() before setting the rate or a
> clk_get_rate() afterwards.

Thanks, the behavior in v2 is actually what I'm looking for.
I dug into clk_set_rate while checking into its interaction with
clk_prepare and I came to this conclusion.



>
> Sascha
>
> --
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Peter Geis]

On Thu, Jan 27, 2022 at 4:33 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> Hi Peter,
>
> On Wed, Jan 26, 2022 at 03:24:26PM -0500, Peter Geis wrote:
> > The hdmi-cec clock must be 32khz in order for cec to work correctly.
> > Ensure after enabling the clock we set it in order for the hardware to
> > work as expected.
> > Warn on failure, in case this is a static clock that is slighty off.
> > Fixes hdmi-cec support on Rockchip devices.
>
> You removed this sentence in v2, but I just wanted to mention that
> clk_set_rate() won't fail when the desired clock rate can't be
> archieved. Instead, you will get the best rate that actually can be
> reached. If you want to check that you are happy with the rate you'll
> have to do a clk_round_rate() before setting the rate or a
> clk_get_rate() afterwards.

Thanks, the behavior in v2 is actually what I'm looking for.
I dug into clk_set_rate while checking into its interaction with
clk_prepare and I came to this conclusion.



>
> Sascha
>
> --
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Peter Geis]

On Thu, Jan 27, 2022 at 4:33 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> Hi Peter,
>
> On Wed, Jan 26, 2022 at 03:24:26PM -0500, Peter Geis wrote:
> > The hdmi-cec clock must be 32khz in order for cec to work correctly.
> > Ensure after enabling the clock we set it in order for the hardware to
> > work as expected.
> > Warn on failure, in case this is a static clock that is slighty off.
> > Fixes hdmi-cec support on Rockchip devices.
>
> You removed this sentence in v2, but I just wanted to mention that
> clk_set_rate() won't fail when the desired clock rate can't be
> archieved. Instead, you will get the best rate that actually can be
> reached. If you want to check that you are happy with the rate you'll
> have to do a clk_round_rate() before setting the rate or a
> clk_get_rate() afterwards.

Thanks, the behavior in v2 is actually what I'm looking for.
I dug into clk_set_rate while checking into its interaction with
clk_prepare and I came to this conclusion.



>
> Sascha
>
> --
> Pengutronix e.K.                           |                             |
> Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
> 31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Piotr Oniszczuk]

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 26.01.2022, o godz. 21:24:
> 
> The hdmi-cec clock must be 32khz in order for cec to work correctly.
> Ensure after enabling the clock we set it in order for the hardware to
> work as expected.
> Warn on failure, in case this is a static clock that is slighty off.
> Fixes hdmi-cec support on Rockchip devices.
> 
> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 54d8fdad395f..1a96da60e357 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -48,6 +48,9 @@
> 
> #define HDMI14_MAX_TMDSCLK	340000000
> 
> +/* HDMI CEC needs a clock rate of 32khz */
> +#define HDMI_CEC_CLK_RATE	32768
> +
> enum hdmi_datamap {
> 	RGB444_8B = 0x01,
> 	RGB444_10B = 0x03,
> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
> 				ret);
> 			goto err_iahb;
> 		}
> +
> +		ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> +		if (ret)
> +			dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
> 	}
> 
> 	/* Product and revision IDs */
> -- 
> 2.25.1
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Peter,

On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.

Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
 
I'm not sure how to move forward with this....
 
br

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Piotr Oniszczuk]

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 26.01.2022, o godz. 21:24:
> 
> The hdmi-cec clock must be 32khz in order for cec to work correctly.
> Ensure after enabling the clock we set it in order for the hardware to
> work as expected.
> Warn on failure, in case this is a static clock that is slighty off.
> Fixes hdmi-cec support on Rockchip devices.
> 
> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 54d8fdad395f..1a96da60e357 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -48,6 +48,9 @@
> 
> #define HDMI14_MAX_TMDSCLK	340000000
> 
> +/* HDMI CEC needs a clock rate of 32khz */
> +#define HDMI_CEC_CLK_RATE	32768
> +
> enum hdmi_datamap {
> 	RGB444_8B = 0x01,
> 	RGB444_10B = 0x03,
> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
> 				ret);
> 			goto err_iahb;
> 		}
> +
> +		ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> +		if (ret)
> +			dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
> 	}
> 
> 	/* Product and revision IDs */
> -- 
> 2.25.1
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Peter,

On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.

Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
 
I'm not sure how to move forward with this....
 
br

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Piotr Oniszczuk]

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 26.01.2022, o godz. 21:24:
> 
> The hdmi-cec clock must be 32khz in order for cec to work correctly.
> Ensure after enabling the clock we set it in order for the hardware to
> work as expected.
> Warn on failure, in case this is a static clock that is slighty off.
> Fixes hdmi-cec support on Rockchip devices.
> 
> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> index 54d8fdad395f..1a96da60e357 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> @@ -48,6 +48,9 @@
> 
> #define HDMI14_MAX_TMDSCLK	340000000
> 
> +/* HDMI CEC needs a clock rate of 32khz */
> +#define HDMI_CEC_CLK_RATE	32768
> +
> enum hdmi_datamap {
> 	RGB444_8B = 0x01,
> 	RGB444_10B = 0x03,
> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
> 				ret);
> 			goto err_iahb;
> 		}
> +
> +		ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> +		if (ret)
> +			dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
> 	}
> 
> 	/* Product and revision IDs */
> -- 
> 2.25.1
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Peter,

On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.

Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
 
I'm not sure how to move forward with this....
 
br
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Peter Geis]

On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
<piotr.oniszczuk@gmail.com> wrote:
>
>
>
> > Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 26.01.2022, o godz. 21:24:
> >
> > The hdmi-cec clock must be 32khz in order for cec to work correctly.
> > Ensure after enabling the clock we set it in order for the hardware to
> > work as expected.
> > Warn on failure, in case this is a static clock that is slighty off.
> > Fixes hdmi-cec support on Rockchip devices.
> >
> > Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > index 54d8fdad395f..1a96da60e357 100644
> > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > @@ -48,6 +48,9 @@
> >
> > #define HDMI14_MAX_TMDSCLK    340000000
> >
> > +/* HDMI CEC needs a clock rate of 32khz */
> > +#define HDMI_CEC_CLK_RATE    32768
> > +
> > enum hdmi_datamap {
> >       RGB444_8B = 0x01,
> >       RGB444_10B = 0x03,
> > @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
> >                               ret);
> >                       goto err_iahb;
> >               }
> > +
> > +             ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> > +             if (ret)
> > +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
> >       }
> >
> >       /* Product and revision IDs */
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > Linux-rockchip mailing list
> > Linux-rockchip@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
> Peter,
>
> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>
> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
>
> I'm not sure how to move forward with this....

I was worried about that, thanks for testing it.
Can you send me the cec_clk rate before and after this patch?

>
> br

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Peter Geis]

On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
<piotr.oniszczuk@gmail.com> wrote:
>
>
>
> > Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 26.01.2022, o godz. 21:24:
> >
> > The hdmi-cec clock must be 32khz in order for cec to work correctly.
> > Ensure after enabling the clock we set it in order for the hardware to
> > work as expected.
> > Warn on failure, in case this is a static clock that is slighty off.
> > Fixes hdmi-cec support on Rockchip devices.
> >
> > Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > index 54d8fdad395f..1a96da60e357 100644
> > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > @@ -48,6 +48,9 @@
> >
> > #define HDMI14_MAX_TMDSCLK    340000000
> >
> > +/* HDMI CEC needs a clock rate of 32khz */
> > +#define HDMI_CEC_CLK_RATE    32768
> > +
> > enum hdmi_datamap {
> >       RGB444_8B = 0x01,
> >       RGB444_10B = 0x03,
> > @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
> >                               ret);
> >                       goto err_iahb;
> >               }
> > +
> > +             ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> > +             if (ret)
> > +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
> >       }
> >
> >       /* Product and revision IDs */
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > Linux-rockchip mailing list
> > Linux-rockchip@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
> Peter,
>
> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>
> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
>
> I'm not sure how to move forward with this....

I was worried about that, thanks for testing it.
Can you send me the cec_clk rate before and after this patch?

>
> br

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Peter Geis]

On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
<piotr.oniszczuk@gmail.com> wrote:
>
>
>
> > Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 26.01.2022, o godz. 21:24:
> >
> > The hdmi-cec clock must be 32khz in order for cec to work correctly.
> > Ensure after enabling the clock we set it in order for the hardware to
> > work as expected.
> > Warn on failure, in case this is a static clock that is slighty off.
> > Fixes hdmi-cec support on Rockchip devices.
> >
> > Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > index 54d8fdad395f..1a96da60e357 100644
> > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > @@ -48,6 +48,9 @@
> >
> > #define HDMI14_MAX_TMDSCLK    340000000
> >
> > +/* HDMI CEC needs a clock rate of 32khz */
> > +#define HDMI_CEC_CLK_RATE    32768
> > +
> > enum hdmi_datamap {
> >       RGB444_8B = 0x01,
> >       RGB444_10B = 0x03,
> > @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
> >                               ret);
> >                       goto err_iahb;
> >               }
> > +
> > +             ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
> > +             if (ret)
> > +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
> >       }
> >
> >       /* Product and revision IDs */
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > Linux-rockchip mailing list
> > Linux-rockchip@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
> Peter,
>
> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>
> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
>
> I'm not sure how to move forward with this....

I was worried about that, thanks for testing it.
Can you send me the cec_clk rate before and after this patch?

>
> br

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Piotr Oniszczuk]

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 13.03.2022, o godz. 13:56:
> 
>> 
> 
> I was worried about that, thanks for testing it.
> Can you send me the cec_clk rate before and after this patch?
> 

Here it is:

working:
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
clk_hdmi_cec                      1        2        0       32743          0     0  50000         Y



non-working:
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
clk_hdmi_cec                      1        2        0       32768          0     0  50000         Y



dmesg
[   52.745988] cec-dw_hdmi: message 44 timed out
[   54.879307] cec-dw_hdmi: message 44 timed out
[   57.012654] cec-dw_hdmi: message 88 timed out
[   59.145973] cec-dw_hdmi: message 88 timed out



player:
2022-03-13 11:04:40.938355 E CECAdapter: CLinuxCECAdapterCommunication::Write - ioctl CEC_TRANSMIT failed - tx_status=00 errno=22
2022-03-13 11:04:40.938366 E CECAdapter: CLinuxCECAdapterCommunication::Write - ioctl CEC_TRANSMIT failed - tx_status=00 errno=22

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Piotr Oniszczuk]

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 13.03.2022, o godz. 13:56:
> 
>> 
> 
> I was worried about that, thanks for testing it.
> Can you send me the cec_clk rate before and after this patch?
> 

Here it is:

working:
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
clk_hdmi_cec                      1        2        0       32743          0     0  50000         Y



non-working:
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
clk_hdmi_cec                      1        2        0       32768          0     0  50000         Y



dmesg
[   52.745988] cec-dw_hdmi: message 44 timed out
[   54.879307] cec-dw_hdmi: message 44 timed out
[   57.012654] cec-dw_hdmi: message 88 timed out
[   59.145973] cec-dw_hdmi: message 88 timed out



player:
2022-03-13 11:04:40.938355 E CECAdapter: CLinuxCECAdapterCommunication::Write - ioctl CEC_TRANSMIT failed - tx_status=00 errno=22
2022-03-13 11:04:40.938366 E CECAdapter: CLinuxCECAdapterCommunication::Write - ioctl CEC_TRANSMIT failed - tx_status=00 errno=22

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Piotr Oniszczuk]

> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 13.03.2022, o godz. 13:56:
> 
>> 
> 
> I was worried about that, thanks for testing it.
> Can you send me the cec_clk rate before and after this patch?
> 

Here it is:

working:
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
clk_hdmi_cec                      1        2        0       32743          0     0  50000         Y



non-working:
                                 enable  prepare  protect                                duty  hardware
   clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
clk_hdmi_cec                      1        2        0       32768          0     0  50000         Y



dmesg
[   52.745988] cec-dw_hdmi: message 44 timed out
[   54.879307] cec-dw_hdmi: message 44 timed out
[   57.012654] cec-dw_hdmi: message 88 timed out
[   59.145973] cec-dw_hdmi: message 88 timed out



player:
2022-03-13 11:04:40.938355 E CECAdapter: CLinuxCECAdapterCommunication::Write - ioctl CEC_TRANSMIT failed - tx_status=00 errno=22
2022-03-13 11:04:40.938366 E CECAdapter: CLinuxCECAdapterCommunication::Write - ioctl CEC_TRANSMIT failed - tx_status=00 errno=22


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Robin Murphy]

On 2022-03-13 12:56, Peter Geis wrote:
> On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
> <piotr.oniszczuk@gmail.com> wrote:
>>
>>
>>
>>> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 26.01.2022, o godz. 21:24:
>>>
>>> The hdmi-cec clock must be 32khz in order for cec to work correctly.
>>> Ensure after enabling the clock we set it in order for the hardware to
>>> work as expected.
>>> Warn on failure, in case this is a static clock that is slighty off.
>>> Fixes hdmi-cec support on Rockchip devices.
>>>
>>> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
>>>
>>> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
>>> ---
>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>> index 54d8fdad395f..1a96da60e357 100644
>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>> @@ -48,6 +48,9 @@
>>>
>>> #define HDMI14_MAX_TMDSCLK    340000000
>>>
>>> +/* HDMI CEC needs a clock rate of 32khz */
>>> +#define HDMI_CEC_CLK_RATE    32768
>>> +
>>> enum hdmi_datamap {
>>>        RGB444_8B = 0x01,
>>>        RGB444_10B = 0x03,
>>> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
>>>                                ret);
>>>                        goto err_iahb;
>>>                }
>>> +
>>> +             ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
>>> +             if (ret)
>>> +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
>>>        }
>>>
>>>        /* Product and revision IDs */
>>> --
>>> 2.25.1
>>>
>>>
>>> _______________________________________________
>>> Linux-rockchip mailing list
>>> Linux-rockchip@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>
>> Peter,
>>
>> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
>> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>>
>> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
>>
>> I'm not sure how to move forward with this....
> 
> I was worried about that, thanks for testing it.
> Can you send me the cec_clk rate before and after this patch?

Hmm, looks like there might be a bug in the RK3399 clock driver - 
although it's treated as having mux_pll_p as parents, according to the 
public TRM the CEC clock appears unique in being backwards compared to 
every other mux of those two inputs. I'm now tempted to test this on my 
board tonight and see if I can see 24MHz on the CEC pin... :)

Robin.

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Robin Murphy]

On 2022-03-13 12:56, Peter Geis wrote:
> On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
> <piotr.oniszczuk@gmail.com> wrote:
>>
>>
>>
>>> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 26.01.2022, o godz. 21:24:
>>>
>>> The hdmi-cec clock must be 32khz in order for cec to work correctly.
>>> Ensure after enabling the clock we set it in order for the hardware to
>>> work as expected.
>>> Warn on failure, in case this is a static clock that is slighty off.
>>> Fixes hdmi-cec support on Rockchip devices.
>>>
>>> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
>>>
>>> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
>>> ---
>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>> index 54d8fdad395f..1a96da60e357 100644
>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>> @@ -48,6 +48,9 @@
>>>
>>> #define HDMI14_MAX_TMDSCLK    340000000
>>>
>>> +/* HDMI CEC needs a clock rate of 32khz */
>>> +#define HDMI_CEC_CLK_RATE    32768
>>> +
>>> enum hdmi_datamap {
>>>        RGB444_8B = 0x01,
>>>        RGB444_10B = 0x03,
>>> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
>>>                                ret);
>>>                        goto err_iahb;
>>>                }
>>> +
>>> +             ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
>>> +             if (ret)
>>> +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
>>>        }
>>>
>>>        /* Product and revision IDs */
>>> --
>>> 2.25.1
>>>
>>>
>>> _______________________________________________
>>> Linux-rockchip mailing list
>>> Linux-rockchip@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>
>> Peter,
>>
>> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
>> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>>
>> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
>>
>> I'm not sure how to move forward with this....
> 
> I was worried about that, thanks for testing it.
> Can you send me the cec_clk rate before and after this patch?

Hmm, looks like there might be a bug in the RK3399 clock driver - 
although it's treated as having mux_pll_p as parents, according to the 
public TRM the CEC clock appears unique in being backwards compared to 
every other mux of those two inputs. I'm now tempted to test this on my 
board tonight and see if I can see 24MHz on the CEC pin... :)

Robin.

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Robin Murphy]

On 2022-03-13 12:56, Peter Geis wrote:
> On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
> <piotr.oniszczuk@gmail.com> wrote:
>>
>>
>>
>>> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 26.01.2022, o godz. 21:24:
>>>
>>> The hdmi-cec clock must be 32khz in order for cec to work correctly.
>>> Ensure after enabling the clock we set it in order for the hardware to
>>> work as expected.
>>> Warn on failure, in case this is a static clock that is slighty off.
>>> Fixes hdmi-cec support on Rockchip devices.
>>>
>>> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
>>>
>>> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
>>> ---
>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>> index 54d8fdad395f..1a96da60e357 100644
>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>> @@ -48,6 +48,9 @@
>>>
>>> #define HDMI14_MAX_TMDSCLK    340000000
>>>
>>> +/* HDMI CEC needs a clock rate of 32khz */
>>> +#define HDMI_CEC_CLK_RATE    32768
>>> +
>>> enum hdmi_datamap {
>>>        RGB444_8B = 0x01,
>>>        RGB444_10B = 0x03,
>>> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
>>>                                ret);
>>>                        goto err_iahb;
>>>                }
>>> +
>>> +             ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
>>> +             if (ret)
>>> +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock rate: %d\n", ret);
>>>        }
>>>
>>>        /* Product and revision IDs */
>>> --
>>> 2.25.1
>>>
>>>
>>> _______________________________________________
>>> Linux-rockchip mailing list
>>> Linux-rockchip@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>
>> Peter,
>>
>> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes CEC working on rk3566.
>> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>>
>> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes with non working CEC
>>
>> I'm not sure how to move forward with this....
> 
> I was worried about that, thanks for testing it.
> Can you send me the cec_clk rate before and after this patch?

Hmm, looks like there might be a bug in the RK3399 clock driver - 
although it's treated as having mux_pll_p as parents, according to the 
public TRM the CEC clock appears unique in being backwards compared to 
every other mux of those two inputs. I'm now tempted to test this on my 
board tonight and see if I can see 24MHz on the CEC pin... :)

Robin.

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Robin Murphy]

On 2022-03-14 11:31, Robin Murphy wrote:
> On 2022-03-13 12:56, Peter Geis wrote:
>> On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
>> <piotr.oniszczuk@gmail.com> wrote:
>>>
>>>
>>>
>>>> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 
>>>> 26.01.2022, o godz. 21:24:
>>>>
>>>> The hdmi-cec clock must be 32khz in order for cec to work correctly.
>>>> Ensure after enabling the clock we set it in order for the hardware to
>>>> work as expected.
>>>> Warn on failure, in case this is a static clock that is slighty off.
>>>> Fixes hdmi-cec support on Rockchip devices.
>>>>
>>>> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
>>>>
>>>> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
>>>> ---
>>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
>>>> 1 file changed, 7 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
>>>> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>>> index 54d8fdad395f..1a96da60e357 100644
>>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>>> @@ -48,6 +48,9 @@
>>>>
>>>> #define HDMI14_MAX_TMDSCLK    340000000
>>>>
>>>> +/* HDMI CEC needs a clock rate of 32khz */
>>>> +#define HDMI_CEC_CLK_RATE    32768
>>>> +
>>>> enum hdmi_datamap {
>>>>        RGB444_8B = 0x01,
>>>>        RGB444_10B = 0x03,
>>>> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct 
>>>> platform_device *pdev,
>>>>                                ret);
>>>>                        goto err_iahb;
>>>>                }
>>>> +
>>>> +             ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
>>>> +             if (ret)
>>>> +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock 
>>>> rate: %d\n", ret);
>>>>        }
>>>>
>>>>        /* Product and revision IDs */
>>>> -- 
>>>> 2.25.1
>>>>
>>>>
>>>> _______________________________________________
>>>> Linux-rockchip mailing list
>>>> Linux-rockchip@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>>
>>> Peter,
>>>
>>> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes 
>>> CEC working on rk3566.
>>> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>>>
>>> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes 
>>> with non working CEC
>>>
>>> I'm not sure how to move forward with this....
>>
>> I was worried about that, thanks for testing it.
>> Can you send me the cec_clk rate before and after this patch?
> 
> Hmm, looks like there might be a bug in the RK3399 clock driver - 
> although it's treated as having mux_pll_p as parents, according to the 
> public TRM the CEC clock appears unique in being backwards compared to 
> every other mux of those two inputs. I'm now tempted to test this on my 
> board tonight and see if I can see 24MHz on the CEC pin... :)

Nope, turns out that's an error in the TRM and the mux is fine. The bug 
is between the clock driver blindly assuming xin32k is usable, and 
nearly all RK3399 boards forgetting to claim the pinctrl to actually 
enable the input :/

Robin.

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Robin Murphy]

On 2022-03-14 11:31, Robin Murphy wrote:
> On 2022-03-13 12:56, Peter Geis wrote:
>> On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
>> <piotr.oniszczuk@gmail.com> wrote:
>>>
>>>
>>>
>>>> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 
>>>> 26.01.2022, o godz. 21:24:
>>>>
>>>> The hdmi-cec clock must be 32khz in order for cec to work correctly.
>>>> Ensure after enabling the clock we set it in order for the hardware to
>>>> work as expected.
>>>> Warn on failure, in case this is a static clock that is slighty off.
>>>> Fixes hdmi-cec support on Rockchip devices.
>>>>
>>>> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
>>>>
>>>> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
>>>> ---
>>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
>>>> 1 file changed, 7 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
>>>> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>>> index 54d8fdad395f..1a96da60e357 100644
>>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>>> @@ -48,6 +48,9 @@
>>>>
>>>> #define HDMI14_MAX_TMDSCLK    340000000
>>>>
>>>> +/* HDMI CEC needs a clock rate of 32khz */
>>>> +#define HDMI_CEC_CLK_RATE    32768
>>>> +
>>>> enum hdmi_datamap {
>>>>        RGB444_8B = 0x01,
>>>>        RGB444_10B = 0x03,
>>>> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct 
>>>> platform_device *pdev,
>>>>                                ret);
>>>>                        goto err_iahb;
>>>>                }
>>>> +
>>>> +             ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
>>>> +             if (ret)
>>>> +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock 
>>>> rate: %d\n", ret);
>>>>        }
>>>>
>>>>        /* Product and revision IDs */
>>>> -- 
>>>> 2.25.1
>>>>
>>>>
>>>> _______________________________________________
>>>> Linux-rockchip mailing list
>>>> Linux-rockchip@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>>
>>> Peter,
>>>
>>> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes 
>>> CEC working on rk3566.
>>> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>>>
>>> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes 
>>> with non working CEC
>>>
>>> I'm not sure how to move forward with this....
>>
>> I was worried about that, thanks for testing it.
>> Can you send me the cec_clk rate before and after this patch?
> 
> Hmm, looks like there might be a bug in the RK3399 clock driver - 
> although it's treated as having mux_pll_p as parents, according to the 
> public TRM the CEC clock appears unique in being backwards compared to 
> every other mux of those two inputs. I'm now tempted to test this on my 
> board tonight and see if I can see 24MHz on the CEC pin... :)

Nope, turns out that's an error in the TRM and the mux is fine. The bug 
is between the clock driver blindly assuming xin32k is usable, and 
nearly all RK3399 boards forgetting to claim the pinctrl to actually 
enable the input :/

Robin.

_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH] drm/bridge: synopsys/dw-hdmi: set cec clock rate

[Robin Murphy]

On 2022-03-14 11:31, Robin Murphy wrote:
> On 2022-03-13 12:56, Peter Geis wrote:
>> On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
>> <piotr.oniszczuk@gmail.com> wrote:
>>>
>>>
>>>
>>>> Wiadomość napisana przez Peter Geis <pgwipeout@gmail.com> w dniu 
>>>> 26.01.2022, o godz. 21:24:
>>>>
>>>> The hdmi-cec clock must be 32khz in order for cec to work correctly.
>>>> Ensure after enabling the clock we set it in order for the hardware to
>>>> work as expected.
>>>> Warn on failure, in case this is a static clock that is slighty off.
>>>> Fixes hdmi-cec support on Rockchip devices.
>>>>
>>>> Fixes: ebe32c3e282a ("drm/bridge: synopsys/dw-hdmi: Enable cec clock")
>>>>
>>>> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
>>>> ---
>>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++
>>>> 1 file changed, 7 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
>>>> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>>> index 54d8fdad395f..1a96da60e357 100644
>>>> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>>> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>>>> @@ -48,6 +48,9 @@
>>>>
>>>> #define HDMI14_MAX_TMDSCLK    340000000
>>>>
>>>> +/* HDMI CEC needs a clock rate of 32khz */
>>>> +#define HDMI_CEC_CLK_RATE    32768
>>>> +
>>>> enum hdmi_datamap {
>>>>        RGB444_8B = 0x01,
>>>>        RGB444_10B = 0x03,
>>>> @@ -3347,6 +3350,10 @@ struct dw_hdmi *dw_hdmi_probe(struct 
>>>> platform_device *pdev,
>>>>                                ret);
>>>>                        goto err_iahb;
>>>>                }
>>>> +
>>>> +             ret = clk_set_rate(hdmi->cec_clk, HDMI_CEC_CLK_RATE);
>>>> +             if (ret)
>>>> +                     dev_warn(hdmi->dev, "Cannot set HDMI cec clock 
>>>> rate: %d\n", ret);
>>>>        }
>>>>
>>>>        /* Product and revision IDs */
>>>> -- 
>>>> 2.25.1
>>>>
>>>>
>>>> _______________________________________________
>>>> Linux-rockchip mailing list
>>>> Linux-rockchip@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>>
>>> Peter,
>>>
>>> On my 5.17-rc7 with applied rk356x VOP2 v8 series - this patch makes 
>>> CEC working on rk3566.
>>> Unfortunately it breaks working ok CEC on rk3399 rockpi-4b.
>>>
>>> Reverting this patch brings back CEC on rk3399 - but rk3366 becomes 
>>> with non working CEC
>>>
>>> I'm not sure how to move forward with this....
>>
>> I was worried about that, thanks for testing it.
>> Can you send me the cec_clk rate before and after this patch?
> 
> Hmm, looks like there might be a bug in the RK3399 clock driver - 
> although it's treated as having mux_pll_p as parents, according to the 
> public TRM the CEC clock appears unique in being backwards compared to 
> every other mux of those two inputs. I'm now tempted to test this on my 
> board tonight and see if I can see 24MHz on the CEC pin... :)

Nope, turns out that's an error in the TRM and the mux is fine. The bug 
is between the clock driver blindly assuming xin32k is usable, and 
nearly all RK3399 boards forgetting to claim the pinctrl to actually 
enable the input :/

Robin.