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From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: tvrtko.ursulin@linux.intel.com, michael.cheng@intel.com,
	wayne.boyer@intel.com, casey.g.bowman@intel.com,
	lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org
Subject: [PATCH v5 1/5] drm/i915/gt: Re-work intel_write_status_page
Date: Fri,  4 Feb 2022 08:37:07 -0800	[thread overview]
Message-ID: <20220204163711.439403-2-michael.cheng@intel.com> (raw)
In-Reply-To: <20220204163711.439403-1-michael.cheng@intel.com>

Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
 
 #include <asm/cacheflush.h>
 #include <drm/drm_util.h>
+#include <drm/drm_cache.h>
 
 #include <linux/hashtable.h>
 #include <linux/irq_work.h>
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 	 * of extra paranoia to try and ensure that the HWS takes the value
 	 * we give and that it doesn't end up trapped inside the CPU!
 	 */
-	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
-		mb();
-		clflush(&engine->status_page.addr[reg]);
-		engine->status_page.addr[reg] = value;
-		clflush(&engine->status_page.addr[reg]);
-		mb();
-	} else {
-		WRITE_ONCE(engine->status_page.addr[reg], value);
-	}
+	drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+	WRITE_ONCE(engine->status_page.addr[reg], value);
+	drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
 }
 
 /*
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
	dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v5 1/5] drm/i915/gt: Re-work intel_write_status_page
Date: Fri,  4 Feb 2022 08:37:07 -0800	[thread overview]
Message-ID: <20220204163711.439403-2-michael.cheng@intel.com> (raw)
In-Reply-To: <20220204163711.439403-1-michael.cheng@intel.com>

Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
 
 #include <asm/cacheflush.h>
 #include <drm/drm_util.h>
+#include <drm/drm_cache.h>
 
 #include <linux/hashtable.h>
 #include <linux/irq_work.h>
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 	 * of extra paranoia to try and ensure that the HWS takes the value
 	 * we give and that it doesn't end up trapped inside the CPU!
 	 */
-	if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
-		mb();
-		clflush(&engine->status_page.addr[reg]);
-		engine->status_page.addr[reg] = value;
-		clflush(&engine->status_page.addr[reg]);
-		mb();
-	} else {
-		WRITE_ONCE(engine->status_page.addr[reg], value);
-	}
+	drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+	WRITE_ONCE(engine->status_page.addr[reg], value);
+	drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
 }
 
 /*
-- 
2.25.1


  reply	other threads:[~2022-02-04 16:37 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-04 16:37 [PATCH v5 0/5] Use drm_clflush* instead of clflush Michael Cheng
2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` Michael Cheng [this message]
2022-02-04 16:37   ` [Intel-gfx] [PATCH v5 1/5] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-04 16:37 ` [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-07 11:57   ` Tvrtko Ursulin
2022-02-07 11:57     ` [Intel-gfx] " Tvrtko Ursulin
2022-02-07 18:47     ` Michael Cheng
2022-02-07 18:47       ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 3/5] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 4/5] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 5/5] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev4) Patchwork
2022-02-04 16:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-04 17:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-04 18:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-07 12:03 ` [PATCH v5 0/5] Use drm_clflush* instead of clflush Tvrtko Ursulin
2022-02-07 12:03   ` [Intel-gfx] " Tvrtko Ursulin
2022-02-07 12:44   ` Jani Nikula
2022-02-08  9:02     ` Tvrtko Ursulin

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