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From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: tvrtko.ursulin@linux.intel.com, michael.cheng@intel.com,
	wayne.boyer@intel.com, casey.g.bowman@intel.com,
	lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org
Subject: [PATCH v5 4/5] drm/i915/: Re-work clflush_write32
Date: Fri,  4 Feb 2022 08:37:10 -0800	[thread overview]
Message-ID: <20220204163711.439403-5-michael.cheng@intel.com> (raw)
In-Reply-To: <20220204163711.439403-1-michael.cheng@intel.com>

Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 {
 	if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
-		if (flushes & CLFLUSH_BEFORE) {
-			clflushopt(addr);
-			mb();
-		}
+		if (flushes & CLFLUSH_BEFORE)
+			drm_clflush_virt_range(addr, sizeof(addr));
 
 		*addr = value;
 
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 		 * to ensure ordering of clflush wrt to the system.
 		 */
 		if (flushes & CLFLUSH_AFTER)
-			clflushopt(addr);
+			drm_clflush_virt_range(addr, sizeof(addr));
 	} else
 		*addr = value;
 }
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
	dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v5 4/5] drm/i915/: Re-work clflush_write32
Date: Fri,  4 Feb 2022 08:37:10 -0800	[thread overview]
Message-ID: <20220204163711.439403-5-michael.cheng@intel.com> (raw)
In-Reply-To: <20220204163711.439403-1-michael.cheng@intel.com>

Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
 static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 {
 	if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
-		if (flushes & CLFLUSH_BEFORE) {
-			clflushopt(addr);
-			mb();
-		}
+		if (flushes & CLFLUSH_BEFORE)
+			drm_clflush_virt_range(addr, sizeof(addr));
 
 		*addr = value;
 
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
 		 * to ensure ordering of clflush wrt to the system.
 		 */
 		if (flushes & CLFLUSH_AFTER)
-			clflushopt(addr);
+			drm_clflush_virt_range(addr, sizeof(addr));
 	} else
 		*addr = value;
 }
-- 
2.25.1


  parent reply	other threads:[~2022-02-04 16:37 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-04 16:37 [PATCH v5 0/5] Use drm_clflush* instead of clflush Michael Cheng
2022-02-04 16:37 ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 1/5] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-07 11:57   ` Tvrtko Ursulin
2022-02-07 11:57     ` [Intel-gfx] " Tvrtko Ursulin
2022-02-07 18:47     ` Michael Cheng
2022-02-07 18:47       ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` [PATCH v5 3/5] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:37 ` Michael Cheng [this message]
2022-02-04 16:37   ` [Intel-gfx] [PATCH v5 4/5] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-04 16:37 ` [PATCH v5 5/5] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-04 16:37   ` [Intel-gfx] " Michael Cheng
2022-02-04 16:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev4) Patchwork
2022-02-04 16:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-04 17:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-04 18:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-07 12:03 ` [PATCH v5 0/5] Use drm_clflush* instead of clflush Tvrtko Ursulin
2022-02-07 12:03   ` [Intel-gfx] " Tvrtko Ursulin
2022-02-07 12:44   ` Jani Nikula
2022-02-08  9:02     ` Tvrtko Ursulin

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