From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 8/8] drm/i915: Rename QGV request/response bits
Date: Wed, 9 Mar 2022 18:49:48 +0200 [thread overview]
Message-ID: <20220309164948.10671-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220309164948.10671-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Name all the ICL_PCODE_SAGV_DE_MEM_SS_CONFIG request/response
bits in a manner that we can actually understand what they're
doing.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 9 +++++----
drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++------
2 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index b794545ff81d..395e48930b08 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -124,8 +124,8 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
/* bspec says to keep retrying for at least 1 ms */
ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
points_mask,
- ICL_PCODE_POINTS_RESTRICTED_MASK,
- ICL_PCODE_POINTS_RESTRICTED,
+ ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
+ ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
1);
if (ret < 0) {
@@ -833,7 +833,7 @@ static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
if (num_psf_gv_points > 0)
psf_points = GENMASK(num_psf_gv_points - 1, 0);
- return ADLS_QGV_PT(qgv_points) | ADLS_PSF_PT(psf_points);
+ return ICL_PCODE_REQ_QGV_PT(qgv_points) | ADLS_PCODE_REQ_PSF_PT(psf_points);
}
static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
@@ -1000,7 +1000,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
* actually accepts as a parameter.
*/
new_bw_state->qgv_points_mask =
- ~(ADLS_QGV_PT(qgv_points) | ADLS_PSF_PT(psf_points)) &
+ ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+ ADLS_PCODE_REQ_PSF_PT(psf_points)) &
icl_qgv_points_mask(dev_priv);
/*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 48a12f6c19b4..504499fad97d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6720,12 +6720,18 @@
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
-#define ICL_PCODE_POINTS_RESTRICTED 0x0
-#define ICL_PCODE_POINTS_RESTRICTED_MASK 0xf
-#define ADLS_QGV_PT_MASK REG_GENMASK(7, 0)
-#define ADLS_QGV_PT(x) REG_FIELD_PREP(ADLS_QGV_PT_MASK, (x))
-#define ADLS_PSF_PT_MASK REG_GENMASK(10, 8)
-#define ADLS_PSF_PT(x) REG_FIELD_PREP(ADLS_PSF_PT_MASK, (x))
+#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
+#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
+#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
+#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
+#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
+#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
+#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
+#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
+#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
+#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
+#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
+#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define ICL_PCODE_EXIT_TCCOLD 0x12
--
2.34.1
next prev parent reply other threads:[~2022-03-09 17:01 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 16:49 [Intel-gfx] [PATCH v2 0/8] drm/i915: SAGV block time fixes Ville Syrjala
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Treat SAGV block time 0 as SAGV disabled Ville Syrjala
2022-03-09 16:49 ` Ville Syrjala
2022-03-09 19:29 ` [Intel-gfx] " Lisovskiy, Stanislav
2022-03-09 20:35 ` Ville Syrjälä
2022-03-16 17:55 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Rework SAGV block time probing Ville Syrjala
2022-03-16 17:55 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Probe whether SAGV works on pre-icl Ville Syrjala
2022-03-16 17:57 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Reject excessive SAGV block time Ville Syrjala
2022-03-16 17:58 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 5/8] drm/i915: Rename pre-icl SAGV enable/disable functions Ville Syrjala
2022-03-16 17:57 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible Ville Syrjala
2022-03-09 16:49 ` Ville Syrjala
2022-03-09 18:59 ` Lisovskiy, Stanislav
2022-03-09 18:59 ` [Intel-gfx] " Lisovskiy, Stanislav
2022-03-09 19:08 ` Ville Syrjälä
2022-03-09 19:08 ` [Intel-gfx] " Ville Syrjälä
2022-03-09 19:34 ` Lisovskiy, Stanislav
2022-03-09 19:34 ` [Intel-gfx] " Lisovskiy, Stanislav
2022-03-09 20:21 ` Ville Syrjälä
2022-03-09 20:21 ` [Intel-gfx] " Ville Syrjälä
2022-03-16 18:01 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Unconfuses QGV vs. PSF point masks Ville Syrjala
2022-03-16 17:56 ` Lisovskiy, Stanislav
2022-03-09 16:49 ` Ville Syrjala [this message]
2022-03-16 17:57 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Rename QGV request/response bits Lisovskiy, Stanislav
2022-03-09 19:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: SAGV block time fixes (rev2) Patchwork
2022-03-09 20:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-10 5:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220309164948.10671-9-ville.syrjala@linux.intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.