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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org
Subject: [Intel-gfx] [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible
Date: Wed,  9 Mar 2022 18:49:46 +0200	[thread overview]
Message-ID: <20220309164948.10671-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220309164948.10671-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Don't just mask off all the PSF GV points when SAGV gets disabled.
This should in fact cause the Pcode to reject the request since
at least one PSF point must remain enabled at all times.

Cc: stable@vger.kernel.org
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ad1564ca7269..adf58c58513b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	 * cause.
 	 */
 	if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
-		allowed_points = BIT(max_bw_point);
+		allowed_points &= ADLS_PSF_PT_MASK;
+		allowed_points |= BIT(max_bw_point);
 		drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
 			    max_bw_point);
 	}
-- 
2.34.1


WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: stable@vger.kernel.org,
	Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Subject: [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible
Date: Wed,  9 Mar 2022 18:49:46 +0200	[thread overview]
Message-ID: <20220309164948.10671-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220309164948.10671-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Don't just mask off all the PSF GV points when SAGV gets disabled.
This should in fact cause the Pcode to reject the request since
at least one PSF point must remain enabled at all times.

Cc: stable@vger.kernel.org
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: 192fbfb76744 ("drm/i915: Implement PSF GV point support")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index ad1564ca7269..adf58c58513b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -992,7 +992,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	 * cause.
 	 */
 	if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
-		allowed_points = BIT(max_bw_point);
+		allowed_points &= ADLS_PSF_PT_MASK;
+		allowed_points |= BIT(max_bw_point);
 		drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
 			    max_bw_point);
 	}
-- 
2.34.1


  parent reply	other threads:[~2022-03-09 17:02 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-09 16:49 [Intel-gfx] [PATCH v2 0/8] drm/i915: SAGV block time fixes Ville Syrjala
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 1/8] drm/i915: Treat SAGV block time 0 as SAGV disabled Ville Syrjala
2022-03-09 16:49   ` Ville Syrjala
2022-03-09 19:29   ` [Intel-gfx] " Lisovskiy, Stanislav
2022-03-09 20:35     ` Ville Syrjälä
2022-03-16 17:55   ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 2/8] drm/i915: Rework SAGV block time probing Ville Syrjala
2022-03-16 17:55   ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 3/8] drm/i915: Probe whether SAGV works on pre-icl Ville Syrjala
2022-03-16 17:57   ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 4/8] drm/i915: Reject excessive SAGV block time Ville Syrjala
2022-03-16 17:58   ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 5/8] drm/i915: Rename pre-icl SAGV enable/disable functions Ville Syrjala
2022-03-16 17:57   ` Lisovskiy, Stanislav
2022-03-09 16:49 ` Ville Syrjala [this message]
2022-03-09 16:49   ` [PATCH v2 6/8] drm/i915: Fix PSF GV point mask when SAGV is not possible Ville Syrjala
2022-03-09 18:59   ` Lisovskiy, Stanislav
2022-03-09 18:59     ` [Intel-gfx] " Lisovskiy, Stanislav
2022-03-09 19:08     ` Ville Syrjälä
2022-03-09 19:08       ` [Intel-gfx] " Ville Syrjälä
2022-03-09 19:34       ` Lisovskiy, Stanislav
2022-03-09 19:34         ` [Intel-gfx] " Lisovskiy, Stanislav
2022-03-09 20:21         ` Ville Syrjälä
2022-03-09 20:21           ` [Intel-gfx] " Ville Syrjälä
2022-03-16 18:01         ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 7/8] drm/i915: Unconfuses QGV vs. PSF point masks Ville Syrjala
2022-03-16 17:56   ` Lisovskiy, Stanislav
2022-03-09 16:49 ` [Intel-gfx] [PATCH v2 8/8] drm/i915: Rename QGV request/response bits Ville Syrjala
2022-03-16 17:57   ` Lisovskiy, Stanislav
2022-03-09 19:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: SAGV block time fixes (rev2) Patchwork
2022-03-09 20:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-10  5:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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