From: Michael Cheng <michael.cheng@intel.com> To: intel-gfx@lists.freedesktop.org Cc: tvrtko.ursulin@linux.intel.com, thomas.hellstrom@linux.intel.com, michael.cheng@intel.com, wayne.boyer@intel.com, daniel.vetter@ffwll.ch, casey.g.bowman@intel.com, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org, chris@chris-wilson.co.uk Subject: [PATCH 2/4] Revert "drm/i915/gem: Almagamate clflushes on suspend" Date: Sat, 19 Mar 2022 12:42:25 -0700 [thread overview] Message-ID: <20220319194227.297639-3-michael.cheng@intel.com> (raw) In-Reply-To: <20220319194227.297639-1-michael.cheng@intel.com> As we are making i915 more architecture-neutral, lets revert this commit to the previous logic [1] to avoid using wbinvd_on_all_cpus. [1]. ac05a22cd07a ("drm/i915/gem: Almagamate clflushes on suspend") Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 41 +++++++++++++++++--------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c index 00359ec9d58b..3f20961bb59b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c @@ -13,13 +13,6 @@ #include "i915_driver.h" #include "i915_drv.h" -#if defined(CONFIG_X86) -#include <asm/smp.h> -#else -#define wbinvd_on_all_cpus() \ - pr_warn(DRIVER_NAME ": Missing cache flush in %s\n", __func__) -#endif - void i915_gem_suspend(struct drm_i915_private *i915) { GEM_TRACE("%s\n", dev_name(i915->drm.dev)); @@ -123,6 +116,13 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915) return ret; } +static struct drm_i915_gem_object *first_mm_object(struct list_head *list) +{ + return list_first_entry_or_null(list, + struct drm_i915_gem_object, + mm.link); +} + void i915_gem_suspend_late(struct drm_i915_private *i915) { struct drm_i915_gem_object *obj; @@ -132,7 +132,6 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) NULL }, **phase; unsigned long flags; - bool flush = false; /* * Neither the BIOS, ourselves or any other kernel @@ -158,15 +157,29 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) spin_lock_irqsave(&i915->mm.obj_lock, flags); for (phase = phases; *phase; phase++) { - list_for_each_entry(obj, *phase, mm.link) { - if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) - flush |= (obj->read_domains & I915_GEM_DOMAIN_CPU) == 0; - __start_cpu_write(obj); /* presume auto-hibernate */ + LIST_HEAD(keep); + + while ((obj = first_mm_object(*phase))) { + list_move_tail(&obj->mm.link, &keep); + + /* Beware the background _i915_gem_free_objects */ + if (!kref_get_unless_zero(&obj->base.refcount)) + continue; + + spin_unlock_irqrestore(&i915->mm.obj_lock, flags); + + i915_gem_object_lock(obj, NULL); + drm_WARN_ON(&i915->drm, + i915_gem_object_set_to_gtt_domain(obj, false)); + i915_gem_object_unlock(obj); + i915_gem_object_put(obj); + + spin_lock_irqsave(&i915->mm.obj_lock, flags); } + + list_splice_tail(&keep, *phase); } spin_unlock_irqrestore(&i915->mm.obj_lock, flags); - if (flush) - wbinvd_on_all_cpus(); } int i915_gem_freeze(struct drm_i915_private *i915) -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Cheng <michael.cheng@intel.com> To: intel-gfx@lists.freedesktop.org Cc: thomas.hellstrom@linux.intel.com, michael.cheng@intel.com, daniel.vetter@ffwll.ch, lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org, chris@chris-wilson.co.uk Subject: [Intel-gfx] [PATCH 2/4] Revert "drm/i915/gem: Almagamate clflushes on suspend" Date: Sat, 19 Mar 2022 12:42:25 -0700 [thread overview] Message-ID: <20220319194227.297639-3-michael.cheng@intel.com> (raw) In-Reply-To: <20220319194227.297639-1-michael.cheng@intel.com> As we are making i915 more architecture-neutral, lets revert this commit to the previous logic [1] to avoid using wbinvd_on_all_cpus. [1]. ac05a22cd07a ("drm/i915/gem: Almagamate clflushes on suspend") Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Michael Cheng <michael.cheng@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 41 +++++++++++++++++--------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c index 00359ec9d58b..3f20961bb59b 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c @@ -13,13 +13,6 @@ #include "i915_driver.h" #include "i915_drv.h" -#if defined(CONFIG_X86) -#include <asm/smp.h> -#else -#define wbinvd_on_all_cpus() \ - pr_warn(DRIVER_NAME ": Missing cache flush in %s\n", __func__) -#endif - void i915_gem_suspend(struct drm_i915_private *i915) { GEM_TRACE("%s\n", dev_name(i915->drm.dev)); @@ -123,6 +116,13 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915) return ret; } +static struct drm_i915_gem_object *first_mm_object(struct list_head *list) +{ + return list_first_entry_or_null(list, + struct drm_i915_gem_object, + mm.link); +} + void i915_gem_suspend_late(struct drm_i915_private *i915) { struct drm_i915_gem_object *obj; @@ -132,7 +132,6 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) NULL }, **phase; unsigned long flags; - bool flush = false; /* * Neither the BIOS, ourselves or any other kernel @@ -158,15 +157,29 @@ void i915_gem_suspend_late(struct drm_i915_private *i915) spin_lock_irqsave(&i915->mm.obj_lock, flags); for (phase = phases; *phase; phase++) { - list_for_each_entry(obj, *phase, mm.link) { - if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) - flush |= (obj->read_domains & I915_GEM_DOMAIN_CPU) == 0; - __start_cpu_write(obj); /* presume auto-hibernate */ + LIST_HEAD(keep); + + while ((obj = first_mm_object(*phase))) { + list_move_tail(&obj->mm.link, &keep); + + /* Beware the background _i915_gem_free_objects */ + if (!kref_get_unless_zero(&obj->base.refcount)) + continue; + + spin_unlock_irqrestore(&i915->mm.obj_lock, flags); + + i915_gem_object_lock(obj, NULL); + drm_WARN_ON(&i915->drm, + i915_gem_object_set_to_gtt_domain(obj, false)); + i915_gem_object_unlock(obj); + i915_gem_object_put(obj); + + spin_lock_irqsave(&i915->mm.obj_lock, flags); } + + list_splice_tail(&keep, *phase); } spin_unlock_irqrestore(&i915->mm.obj_lock, flags); - if (flush) - wbinvd_on_all_cpus(); } int i915_gem_freeze(struct drm_i915_private *i915) -- 2.25.1
next prev parent reply other threads:[~2022-03-19 19:42 UTC|newest] Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-19 19:42 [PATCH 0/4] Drop wbinvd_on_all_cpus usage Michael Cheng 2022-03-19 19:42 ` [Intel-gfx] " Michael Cheng 2022-03-19 19:42 ` [PATCH 1/4] i915/gem: drop " Michael Cheng 2022-03-19 19:42 ` [Intel-gfx] " Michael Cheng 2022-03-21 10:30 ` Tvrtko Ursulin 2022-03-21 10:30 ` [Intel-gfx] " Tvrtko Ursulin 2022-03-21 11:07 ` Thomas Hellström 2022-03-21 11:07 ` [Intel-gfx] " Thomas Hellström 2022-03-21 18:51 ` Michael Cheng 2022-03-21 18:51 ` [Intel-gfx] " Michael Cheng 2022-03-21 16:31 ` Michael Cheng 2022-03-21 16:31 ` [Intel-gfx] " Michael Cheng 2022-03-21 17:28 ` Tvrtko Ursulin 2022-03-21 17:28 ` [Intel-gfx] " Tvrtko Ursulin 2022-03-21 17:42 ` Michael Cheng 2022-03-21 17:42 ` [Intel-gfx] " Michael Cheng 2022-03-22 14:35 ` Daniel Vetter 2022-03-22 14:35 ` Daniel Vetter 2022-03-21 17:51 ` Michael Cheng 2022-03-21 17:51 ` [Intel-gfx] " Michael Cheng 2022-03-19 19:42 ` Michael Cheng [this message] 2022-03-19 19:42 ` [Intel-gfx] [PATCH 2/4] Revert "drm/i915/gem: Almagamate clflushes on suspend" Michael Cheng 2022-03-19 19:42 ` [PATCH 3/4] i915/gem: Revert i915_gem_freeze to previous logic Michael Cheng 2022-03-19 19:42 ` [Intel-gfx] " Michael Cheng 2022-03-19 19:42 ` [PATCH 4/4] drm/i915/gt: Revert ggtt_resume " Michael Cheng 2022-03-19 19:42 ` [Intel-gfx] " Michael Cheng 2022-03-19 20:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Drop wbinvd_on_all_cpus usage Patchwork 2022-03-19 20:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-03-19 20:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-03-19 22:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2022-03-21 10:27 ` [PATCH 0/4] " Tvrtko Ursulin 2022-03-21 10:27 ` [Intel-gfx] " Tvrtko Ursulin 2022-03-21 11:03 ` Thomas Hellström 2022-03-21 11:03 ` [Intel-gfx] " Thomas Hellström 2022-03-21 12:22 ` Tvrtko Ursulin 2022-03-21 12:22 ` [Intel-gfx] " Tvrtko Ursulin 2022-03-21 12:33 ` Thomas Hellström 2022-03-21 12:33 ` [Intel-gfx] " Thomas Hellström 2022-03-21 13:12 ` Tvrtko Ursulin 2022-03-21 13:12 ` [Intel-gfx] " Tvrtko Ursulin 2022-03-21 13:40 ` Thomas Hellström 2022-03-21 13:40 ` [Intel-gfx] " Thomas Hellström 2022-03-21 14:43 ` Tvrtko Ursulin 2022-03-21 14:43 ` [Intel-gfx] " Tvrtko Ursulin 2022-03-21 15:15 ` Thomas Hellström 2022-03-21 15:15 ` [Intel-gfx] " Thomas Hellström 2022-03-22 10:13 ` Tvrtko Ursulin 2022-03-22 10:13 ` [Intel-gfx] " Tvrtko Ursulin 2022-03-22 10:26 ` Thomas Hellström 2022-03-22 10:26 ` [Intel-gfx] " Thomas Hellström 2022-03-22 10:41 ` Thomas Hellström 2022-03-22 10:41 ` [Intel-gfx] " Thomas Hellström 2022-03-22 11:20 ` Tvrtko Ursulin 2022-03-22 11:20 ` [Intel-gfx] " Tvrtko Ursulin 2022-03-22 11:37 ` Thomas Hellström 2022-03-22 11:37 ` [Intel-gfx] " Thomas Hellström 2022-03-22 12:53 ` Tvrtko Ursulin 2022-03-22 12:53 ` [Intel-gfx] " Tvrtko Ursulin 2022-03-22 15:07 ` Thomas Hellström 2022-03-22 15:07 ` [Intel-gfx] " Thomas Hellström
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