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From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: tvrtko.ursulin@linux.intel.com, thomas.hellstrom@linux.intel.com,
	michael.cheng@intel.com, wayne.boyer@intel.com,
	daniel.vetter@ffwll.ch, casey.g.bowman@intel.com,
	lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org,
	chris@chris-wilson.co.uk
Subject: [PATCH 4/4] drm/i915/gt: Revert ggtt_resume to previous logic
Date: Sat, 19 Mar 2022 12:42:27 -0700	[thread overview]
Message-ID: <20220319194227.297639-5-michael.cheng@intel.com> (raw)
In-Reply-To: <20220319194227.297639-1-michael.cheng@intel.com>

To avoid having to call wbinvd_on_all_cpus, revert i915_ggtt_resume and
i915_ggtt_resume_vm to previous logic [1].

[1]. 64b95df91f44 drm/i915: Assume exclusive access to objects inside resume

Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 17 ++++++-----------
 drivers/gpu/drm/i915/gt/intel_gtt.h  |  2 +-
 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 04191fe2ee34..811bfd9d8d80 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1305,10 +1305,9 @@ void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
  * Returns %true if restoring the mapping for any object that was in a write
  * domain before suspend.
  */
-bool i915_ggtt_resume_vm(struct i915_address_space *vm)
+void i915_ggtt_resume_vm(struct i915_address_space *vm)
 {
 	struct i915_vma *vma;
-	bool write_domain_objs = false;
 
 	drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
 
@@ -1325,28 +1324,24 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm)
 		vma->ops->bind_vma(vm, NULL, vma->resource,
 				   obj ? obj->cache_level : 0,
 				   was_bound);
-		if (obj) { /* only used during resume => exclusive access */
-			write_domain_objs |= fetch_and_zero(&obj->write_domain);
-			obj->read_domains |= I915_GEM_DOMAIN_GTT;
+		if (obj) {
+			i915_gem_object_lock(obj, NULL);
+			WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
+			i915_gem_object_unlock(obj);
 		}
 	}
 
-	return write_domain_objs;
 }
 
 void i915_ggtt_resume(struct i915_ggtt *ggtt)
 {
-	bool flush;
 
 	intel_gt_check_and_clear_faults(ggtt->vm.gt);
 
-	flush = i915_ggtt_resume_vm(&ggtt->vm);
+	i915_ggtt_resume_vm(&ggtt->vm);
 
 	ggtt->invalidate(ggtt);
 
-	if (flush)
-		wbinvd_on_all_cpus();
-
 	if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
 		setup_private_pat(ggtt->vm.gt->uncore);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 4529b5e9f6e6..c86092054988 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -567,7 +567,7 @@ struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
 				     unsigned long lmem_pt_obj_flags);
 
 void i915_ggtt_suspend_vm(struct i915_address_space *vm);
-bool i915_ggtt_resume_vm(struct i915_address_space *vm);
+void i915_ggtt_resume_vm(struct i915_address_space *vm);
 void i915_ggtt_suspend(struct i915_ggtt *gtt);
 void i915_ggtt_resume(struct i915_ggtt *ggtt);
 
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: thomas.hellstrom@linux.intel.com, michael.cheng@intel.com,
	daniel.vetter@ffwll.ch, lucas.demarchi@intel.com,
	dri-devel@lists.freedesktop.org, chris@chris-wilson.co.uk
Subject: [Intel-gfx] [PATCH 4/4] drm/i915/gt: Revert ggtt_resume to previous logic
Date: Sat, 19 Mar 2022 12:42:27 -0700	[thread overview]
Message-ID: <20220319194227.297639-5-michael.cheng@intel.com> (raw)
In-Reply-To: <20220319194227.297639-1-michael.cheng@intel.com>

To avoid having to call wbinvd_on_all_cpus, revert i915_ggtt_resume and
i915_ggtt_resume_vm to previous logic [1].

[1]. 64b95df91f44 drm/i915: Assume exclusive access to objects inside resume

Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c | 17 ++++++-----------
 drivers/gpu/drm/i915/gt/intel_gtt.h  |  2 +-
 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 04191fe2ee34..811bfd9d8d80 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1305,10 +1305,9 @@ void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
  * Returns %true if restoring the mapping for any object that was in a write
  * domain before suspend.
  */
-bool i915_ggtt_resume_vm(struct i915_address_space *vm)
+void i915_ggtt_resume_vm(struct i915_address_space *vm)
 {
 	struct i915_vma *vma;
-	bool write_domain_objs = false;
 
 	drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt);
 
@@ -1325,28 +1324,24 @@ bool i915_ggtt_resume_vm(struct i915_address_space *vm)
 		vma->ops->bind_vma(vm, NULL, vma->resource,
 				   obj ? obj->cache_level : 0,
 				   was_bound);
-		if (obj) { /* only used during resume => exclusive access */
-			write_domain_objs |= fetch_and_zero(&obj->write_domain);
-			obj->read_domains |= I915_GEM_DOMAIN_GTT;
+		if (obj) {
+			i915_gem_object_lock(obj, NULL);
+			WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
+			i915_gem_object_unlock(obj);
 		}
 	}
 
-	return write_domain_objs;
 }
 
 void i915_ggtt_resume(struct i915_ggtt *ggtt)
 {
-	bool flush;
 
 	intel_gt_check_and_clear_faults(ggtt->vm.gt);
 
-	flush = i915_ggtt_resume_vm(&ggtt->vm);
+	i915_ggtt_resume_vm(&ggtt->vm);
 
 	ggtt->invalidate(ggtt);
 
-	if (flush)
-		wbinvd_on_all_cpus();
-
 	if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
 		setup_private_pat(ggtt->vm.gt->uncore);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 4529b5e9f6e6..c86092054988 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -567,7 +567,7 @@ struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
 				     unsigned long lmem_pt_obj_flags);
 
 void i915_ggtt_suspend_vm(struct i915_address_space *vm);
-bool i915_ggtt_resume_vm(struct i915_address_space *vm);
+void i915_ggtt_resume_vm(struct i915_address_space *vm);
 void i915_ggtt_suspend(struct i915_ggtt *gtt);
 void i915_ggtt_resume(struct i915_ggtt *ggtt);
 
-- 
2.25.1


  parent reply	other threads:[~2022-03-19 19:42 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-19 19:42 [PATCH 0/4] Drop wbinvd_on_all_cpus usage Michael Cheng
2022-03-19 19:42 ` [Intel-gfx] " Michael Cheng
2022-03-19 19:42 ` [PATCH 1/4] i915/gem: drop " Michael Cheng
2022-03-19 19:42   ` [Intel-gfx] " Michael Cheng
2022-03-21 10:30   ` Tvrtko Ursulin
2022-03-21 10:30     ` [Intel-gfx] " Tvrtko Ursulin
2022-03-21 11:07     ` Thomas Hellström
2022-03-21 11:07       ` [Intel-gfx] " Thomas Hellström
2022-03-21 18:51       ` Michael Cheng
2022-03-21 18:51         ` [Intel-gfx] " Michael Cheng
2022-03-21 16:31     ` Michael Cheng
2022-03-21 16:31       ` [Intel-gfx] " Michael Cheng
2022-03-21 17:28       ` Tvrtko Ursulin
2022-03-21 17:28         ` [Intel-gfx] " Tvrtko Ursulin
2022-03-21 17:42         ` Michael Cheng
2022-03-21 17:42           ` [Intel-gfx] " Michael Cheng
2022-03-22 14:35           ` Daniel Vetter
2022-03-22 14:35             ` Daniel Vetter
2022-03-21 17:51         ` Michael Cheng
2022-03-21 17:51           ` [Intel-gfx] " Michael Cheng
2022-03-19 19:42 ` [PATCH 2/4] Revert "drm/i915/gem: Almagamate clflushes on suspend" Michael Cheng
2022-03-19 19:42   ` [Intel-gfx] " Michael Cheng
2022-03-19 19:42 ` [PATCH 3/4] i915/gem: Revert i915_gem_freeze to previous logic Michael Cheng
2022-03-19 19:42   ` [Intel-gfx] " Michael Cheng
2022-03-19 19:42 ` Michael Cheng [this message]
2022-03-19 19:42   ` [Intel-gfx] [PATCH 4/4] drm/i915/gt: Revert ggtt_resume " Michael Cheng
2022-03-19 20:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Drop wbinvd_on_all_cpus usage Patchwork
2022-03-19 20:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-19 20:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-19 22:04 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-03-21 10:27 ` [PATCH 0/4] " Tvrtko Ursulin
2022-03-21 10:27   ` [Intel-gfx] " Tvrtko Ursulin
2022-03-21 11:03   ` Thomas Hellström
2022-03-21 11:03     ` [Intel-gfx] " Thomas Hellström
2022-03-21 12:22     ` Tvrtko Ursulin
2022-03-21 12:22       ` [Intel-gfx] " Tvrtko Ursulin
2022-03-21 12:33       ` Thomas Hellström
2022-03-21 12:33         ` [Intel-gfx] " Thomas Hellström
2022-03-21 13:12         ` Tvrtko Ursulin
2022-03-21 13:12           ` [Intel-gfx] " Tvrtko Ursulin
2022-03-21 13:40           ` Thomas Hellström
2022-03-21 13:40             ` [Intel-gfx] " Thomas Hellström
2022-03-21 14:43             ` Tvrtko Ursulin
2022-03-21 14:43               ` [Intel-gfx] " Tvrtko Ursulin
2022-03-21 15:15               ` Thomas Hellström
2022-03-21 15:15                 ` [Intel-gfx] " Thomas Hellström
2022-03-22 10:13                 ` Tvrtko Ursulin
2022-03-22 10:13                   ` [Intel-gfx] " Tvrtko Ursulin
2022-03-22 10:26                   ` Thomas Hellström
2022-03-22 10:26                     ` [Intel-gfx] " Thomas Hellström
2022-03-22 10:41                     ` Thomas Hellström
2022-03-22 10:41                       ` [Intel-gfx] " Thomas Hellström
2022-03-22 11:20                     ` Tvrtko Ursulin
2022-03-22 11:20                       ` [Intel-gfx] " Tvrtko Ursulin
2022-03-22 11:37                       ` Thomas Hellström
2022-03-22 11:37                         ` [Intel-gfx] " Thomas Hellström
2022-03-22 12:53                         ` Tvrtko Ursulin
2022-03-22 12:53                           ` [Intel-gfx] " Tvrtko Ursulin
2022-03-22 15:07                           ` Thomas Hellström
2022-03-22 15:07                             ` [Intel-gfx] " Thomas Hellström

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