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From: Atish Patra <atishp@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	qemu-riscv@nongnu.org
Subject: [PATCH v7 10/12] target/riscv: Add few cache related PMU events
Date: Wed, 30 Mar 2022 17:01:24 -0700	[thread overview]
Message-ID: <20220331000127.2107823-11-atishp@rivosinc.com> (raw)
In-Reply-To: <20220331000127.2107823-1-atishp@rivosinc.com>

From: Atish Patra <atish.patra@wdc.com>

Qemu can monitor the following cache related PMU events through
tlb_fill functions.

1. DTLB load/store miss
3. ITLB prefetch miss

Increment the PMU counter in tlb_fill function.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/cpu_helper.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1c60fb2e8057..ffc57e4cd0d4 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -21,10 +21,12 @@
 #include "qemu/log.h"
 #include "qemu/main-loop.h"
 #include "cpu.h"
+#include "pmu.h"
 #include "exec/exec-all.h"
 #include "tcg/tcg-op.h"
 #include "trace.h"
 #include "semihosting/common-semi.h"
+#include "cpu_bits.h"
 
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 {
@@ -1178,6 +1180,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 
+
+static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
+{
+    enum riscv_pmu_event_idx pmu_event_type;
+
+    switch (access_type) {
+    case MMU_INST_FETCH:
+        pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
+        break;
+    case MMU_DATA_LOAD:
+        pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
+        break;
+    case MMU_DATA_STORE:
+        pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
+        break;
+    default:
+        return;
+    }
+
+    riscv_pmu_incr_ctr(cpu, pmu_event_type);
+}
+
 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                         MMUAccessType access_type, int mmu_idx,
                         bool probe, uintptr_t retaddr)
@@ -1274,6 +1298,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             }
         }
     } else {
+        pmu_tlb_fill_incr_ctr(cpu, access_type);
         /* Single stage lookup */
         ret = get_physical_address(env, &pa, &prot, address, NULL,
                                    access_type, mmu_idx, true, false, false);
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Atish Patra <atishp@rivosinc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	qemu-riscv@nongnu.org
Subject: [PATCH v7 10/12] target/riscv: Add few cache related PMU events
Date: Wed, 30 Mar 2022 17:01:24 -0700	[thread overview]
Message-ID: <20220331000127.2107823-11-atishp@rivosinc.com> (raw)
In-Reply-To: <20220331000127.2107823-1-atishp@rivosinc.com>

From: Atish Patra <atish.patra@wdc.com>

Qemu can monitor the following cache related PMU events through
tlb_fill functions.

1. DTLB load/store miss
3. ITLB prefetch miss

Increment the PMU counter in tlb_fill function.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/cpu_helper.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1c60fb2e8057..ffc57e4cd0d4 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -21,10 +21,12 @@
 #include "qemu/log.h"
 #include "qemu/main-loop.h"
 #include "cpu.h"
+#include "pmu.h"
 #include "exec/exec-all.h"
 #include "tcg/tcg-op.h"
 #include "trace.h"
 #include "semihosting/common-semi.h"
+#include "cpu_bits.h"
 
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 {
@@ -1178,6 +1180,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
     riscv_raise_exception(env, cs->exception_index, retaddr);
 }
 
+
+static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
+{
+    enum riscv_pmu_event_idx pmu_event_type;
+
+    switch (access_type) {
+    case MMU_INST_FETCH:
+        pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
+        break;
+    case MMU_DATA_LOAD:
+        pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
+        break;
+    case MMU_DATA_STORE:
+        pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
+        break;
+    default:
+        return;
+    }
+
+    riscv_pmu_incr_ctr(cpu, pmu_event_type);
+}
+
 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                         MMUAccessType access_type, int mmu_idx,
                         bool probe, uintptr_t retaddr)
@@ -1274,6 +1298,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
             }
         }
     } else {
+        pmu_tlb_fill_incr_ctr(cpu, access_type);
         /* Single stage lookup */
         ret = get_physical_address(env, &pa, &prot, address, NULL,
                                    access_type, mmu_idx, true, false, false);
-- 
2.25.1



  parent reply	other threads:[~2022-03-31  0:19 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-31  0:01 [PATCH v7 00/12] Improve PMU support Atish Patra
2022-03-31  0:01 ` Atish Patra
2022-03-31  0:01 ` [PATCH v7 01/12] target/riscv: Fix PMU CSR predicate function Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-03-31  0:01 ` [PATCH v7 02/12] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-03-31  0:01 ` [PATCH v7 03/12] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-03-31  0:01 ` [PATCH v7 04/12] target/riscv: pmu: Make number of counters configurable Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-03-31  0:01 ` [PATCH v7 05/12] target/riscv: Implement mcountinhibit CSR Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-03-31  0:01 ` [PATCH v7 06/12] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-03-31  0:01 ` [PATCH v7 07/12] target/riscv: Support mcycle/minstret write operation Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-03-31  0:01 ` [PATCH v7 08/12] target/riscv: Add sscofpmf extension support Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-04-13  7:08   ` Alistair Francis
2022-04-13  7:08     ` Alistair Francis
2022-04-15 23:54     ` Atish Kumar Patra
2022-04-15 23:54       ` Atish Kumar Patra
2022-04-18 22:45       ` Alistair Francis
2022-04-18 22:45         ` Alistair Francis
2022-04-26 21:33         ` Atish Patra
2022-04-26 21:33           ` Atish Patra
2022-05-04 10:03           ` Alistair Francis
2022-05-04 10:06             ` Alistair Francis
2022-05-05  6:58               ` Atish Patra
2022-03-31  0:01 ` [PATCH v7 09/12] target/riscv: Simplify counter predicate function Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-03-31  0:01 ` Atish Patra [this message]
2022-03-31  0:01   ` [PATCH v7 10/12] target/riscv: Add few cache related PMU events Atish Patra
2022-03-31  0:01 ` [PATCH v7 11/12] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-04-08  7:03   ` Alistair Francis
2022-04-08  7:03     ` Alistair Francis
2022-03-31  0:01 ` [PATCH v7 12/12] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra
2022-03-31  0:01   ` Atish Patra
2022-04-13  7:08   ` Alistair Francis
2022-04-13  7:08     ` Alistair Francis
2022-04-07 22:39 ` [PATCH v7 00/12] Improve PMU support Atish Patra
2022-04-07 22:39   ` Atish Patra

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