From: Alistair Francis <alistair23@gmail.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v7 12/12] target/riscv: Update the privilege field for sscofpmf CSRs
Date: Wed, 13 Apr 2022 17:08:48 +1000 [thread overview]
Message-ID: <CAKmqyKPN9+y64=ujDsQ=X0ZGsRQ9WrDxjmMEfE5BABn_3Am1BQ@mail.gmail.com> (raw)
In-Reply-To: <20220331000127.2107823-13-atishp@rivosinc.com>
On Thu, Mar 31, 2022 at 10:31 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> The sscofpmf extension was ratified as a part of priv spec v1.12.
> Mark the csr_ops accordingly.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 90 ++++++++++++++++++++++++++++++----------------
> 1 file changed, 60 insertions(+), 30 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 20bdae7fe354..b2221b6beeeb 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3873,63 +3873,92 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> write_mhpmevent },
>
> [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT4H] = { "mhpmevent4h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT5H] = { "mhpmevent5h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT6H] = { "mhpmevent6h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT7H] = { "mhpmevent7h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT8H] = { "mhpmevent8h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT9H] = { "mhpmevent9h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT10H] = { "mhpmevent10h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT11H] = { "mhpmevent11h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT12H] = { "mhpmevent12h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT13H] = { "mhpmevent13h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT14H] = { "mhpmevent14h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT16H] = { "mhpmevent16h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT17H] = { "mhpmevent17h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT18H] = { "mhpmevent18h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT19H] = { "mhpmevent19h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT20H] = { "mhpmevent20h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT21H] = { "mhpmevent21h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT22H] = { "mhpmevent22h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT23H] = { "mhpmevent23h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT24H] = { "mhpmevent24h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT25H] = { "mhpmevent25h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT26H] = { "mhpmevent26h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT27H] = { "mhpmevent27h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT28H] = { "mhpmevent28h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT29H] = { "mhpmevent29h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT30H] = { "mhpmevent30h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT31H] = { "mhpmevent31h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
>
> [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
> [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
> @@ -4019,7 +4048,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> write_mhpmcounterh },
> [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
> write_mhpmcounterh },
> - [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf },
> + [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
>
> #endif /* !CONFIG_USER_ONLY */
> };
> --
> 2.25.1
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Atish Patra <atishp@rivosinc.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v7 12/12] target/riscv: Update the privilege field for sscofpmf CSRs
Date: Wed, 13 Apr 2022 17:08:48 +1000 [thread overview]
Message-ID: <CAKmqyKPN9+y64=ujDsQ=X0ZGsRQ9WrDxjmMEfE5BABn_3Am1BQ@mail.gmail.com> (raw)
In-Reply-To: <20220331000127.2107823-13-atishp@rivosinc.com>
On Thu, Mar 31, 2022 at 10:31 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> The sscofpmf extension was ratified as a part of priv spec v1.12.
> Mark the csr_ops accordingly.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 90 ++++++++++++++++++++++++++++++----------------
> 1 file changed, 60 insertions(+), 30 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 20bdae7fe354..b2221b6beeeb 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3873,63 +3873,92 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> write_mhpmevent },
>
> [CSR_MHPMEVENT3H] = { "mhpmevent3h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT4H] = { "mhpmevent4h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT5H] = { "mhpmevent5h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT6H] = { "mhpmevent6h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT7H] = { "mhpmevent7h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT8H] = { "mhpmevent8h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT9H] = { "mhpmevent9h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT10H] = { "mhpmevent10h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT11H] = { "mhpmevent11h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT12H] = { "mhpmevent12h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT13H] = { "mhpmevent13h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT14H] = { "mhpmevent14h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT15H] = { "mhpmevent15h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT16H] = { "mhpmevent16h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT17H] = { "mhpmevent17h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT18H] = { "mhpmevent18h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT19H] = { "mhpmevent19h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT20H] = { "mhpmevent20h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT21H] = { "mhpmevent21h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT22H] = { "mhpmevent22h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT23H] = { "mhpmevent23h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT24H] = { "mhpmevent24h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT25H] = { "mhpmevent25h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT26H] = { "mhpmevent26h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT27H] = { "mhpmevent27h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT28H] = { "mhpmevent28h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT29H] = { "mhpmevent29h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT30H] = { "mhpmevent30h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_MHPMEVENT31H] = { "mhpmevent31h", sscofpmf, read_mhpmeventh,
> - write_mhpmeventh},
> + write_mhpmeventh,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
>
> [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
> [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
> @@ -4019,7 +4048,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> write_mhpmcounterh },
> [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
> write_mhpmcounterh },
> - [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf },
> + [CSR_SCOUNTOVF] = { "scountovf", sscofpmf, read_scountovf,
> + .min_priv_ver = PRIV_VERSION_1_12_0 },
>
> #endif /* !CONFIG_USER_ONLY */
> };
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2022-04-13 7:13 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-31 0:01 [PATCH v7 00/12] Improve PMU support Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 01/12] target/riscv: Fix PMU CSR predicate function Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 02/12] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 03/12] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 04/12] target/riscv: pmu: Make number of counters configurable Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 05/12] target/riscv: Implement mcountinhibit CSR Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 06/12] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 07/12] target/riscv: Support mcycle/minstret write operation Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 08/12] target/riscv: Add sscofpmf extension support Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-04-13 7:08 ` Alistair Francis
2022-04-13 7:08 ` Alistair Francis
2022-04-15 23:54 ` Atish Kumar Patra
2022-04-15 23:54 ` Atish Kumar Patra
2022-04-18 22:45 ` Alistair Francis
2022-04-18 22:45 ` Alistair Francis
2022-04-26 21:33 ` Atish Patra
2022-04-26 21:33 ` Atish Patra
2022-05-04 10:03 ` Alistair Francis
2022-05-04 10:06 ` Alistair Francis
2022-05-05 6:58 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 09/12] target/riscv: Simplify counter predicate function Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 10/12] target/riscv: Add few cache related PMU events Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 11/12] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-04-08 7:03 ` Alistair Francis
2022-04-08 7:03 ` Alistair Francis
2022-03-31 0:01 ` [PATCH v7 12/12] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-04-13 7:08 ` Alistair Francis [this message]
2022-04-13 7:08 ` Alistair Francis
2022-04-07 22:39 ` [PATCH v7 00/12] Improve PMU support Atish Patra
2022-04-07 22:39 ` Atish Patra
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