From: Atish Patra <atishp@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, Bin Meng <bin.meng@windriver.com>,
Atish Patra <atishp@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v7 02/12] target/riscv: Implement PMU CSR predicate function for S-mode
Date: Wed, 30 Mar 2022 17:01:16 -0700 [thread overview]
Message-ID: <20220331000127.2107823-3-atishp@rivosinc.com> (raw)
In-Reply-To: <20220331000127.2107823-1-atishp@rivosinc.com>
From: Atish Patra <atish.patra@wdc.com>
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 254bab3715b7..914b3f96ef67 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -77,6 +77,57 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (env->priv == PRV_S) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
+ switch (csrno) {
+ case CSR_CYCLEH:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ }
+ }
+
if (riscv_cpu_virt_enabled(env)) {
switch (csrno) {
case CSR_CYCLE:
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Atish Patra <atishp@rivosinc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v7 02/12] target/riscv: Implement PMU CSR predicate function for S-mode
Date: Wed, 30 Mar 2022 17:01:16 -0700 [thread overview]
Message-ID: <20220331000127.2107823-3-atishp@rivosinc.com> (raw)
In-Reply-To: <20220331000127.2107823-1-atishp@rivosinc.com>
From: Atish Patra <atish.patra@wdc.com>
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 254bab3715b7..914b3f96ef67 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -77,6 +77,57 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (env->priv == PRV_S) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
+ switch (csrno) {
+ case CSR_CYCLEH:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ }
+ }
+
if (riscv_cpu_virt_enabled(env)) {
switch (csrno) {
case CSR_CYCLE:
--
2.25.1
next prev parent reply other threads:[~2022-03-31 0:06 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-31 0:01 [PATCH v7 00/12] Improve PMU support Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 01/12] target/riscv: Fix PMU CSR predicate function Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` Atish Patra [this message]
2022-03-31 0:01 ` [PATCH v7 02/12] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra
2022-03-31 0:01 ` [PATCH v7 03/12] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 04/12] target/riscv: pmu: Make number of counters configurable Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 05/12] target/riscv: Implement mcountinhibit CSR Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 06/12] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 07/12] target/riscv: Support mcycle/minstret write operation Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 08/12] target/riscv: Add sscofpmf extension support Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-04-13 7:08 ` Alistair Francis
2022-04-13 7:08 ` Alistair Francis
2022-04-15 23:54 ` Atish Kumar Patra
2022-04-15 23:54 ` Atish Kumar Patra
2022-04-18 22:45 ` Alistair Francis
2022-04-18 22:45 ` Alistair Francis
2022-04-26 21:33 ` Atish Patra
2022-04-26 21:33 ` Atish Patra
2022-05-04 10:03 ` Alistair Francis
2022-05-04 10:06 ` Alistair Francis
2022-05-05 6:58 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 09/12] target/riscv: Simplify counter predicate function Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 10/12] target/riscv: Add few cache related PMU events Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-03-31 0:01 ` [PATCH v7 11/12] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-04-08 7:03 ` Alistair Francis
2022-04-08 7:03 ` Alistair Francis
2022-03-31 0:01 ` [PATCH v7 12/12] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra
2022-03-31 0:01 ` Atish Patra
2022-04-13 7:08 ` Alistair Francis
2022-04-13 7:08 ` Alistair Francis
2022-04-07 22:39 ` [PATCH v7 00/12] Improve PMU support Atish Patra
2022-04-07 22:39 ` Atish Patra
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