From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>, lazyparser@gmail.com, luruibo2000@163.com, lustrew@foxmail.com Subject: [PATCH v10 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension Date: Sat, 16 Apr 2022 10:35:45 +0800 [thread overview] Message-ID: <20220416023549.28463-11-liweiwei@iscas.ac.cn> (raw) In-Reply-To: <20220416023549.28463-1-liweiwei@iscas.ac.cn> - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvk.c.inc | 53 +++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 02a0c71890..d9ebb138d1 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -868,3 +868,8 @@ sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r +# *** RV64 Zknh Standard Extension *** +sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2 +sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2 +sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2 +sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc index bb89a53f52..b1ce4f27cf 100644 --- a/target/riscv/insn_trans/trans_rvk.c.inc +++ b/target/riscv/insn_trans/trans_rvk.c.inc @@ -267,3 +267,56 @@ static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a) REQUIRE_ZKNH(ctx); return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19); } + +static bool gen_sha512_rv64(DisasContext *ctx, arg_r2 *a, DisasExtend ext, + void (*func)(TCGv_i64, TCGv_i64, int64_t), + int64_t num1, int64_t num2, int64_t num3) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, ext); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t0, src1); + tcg_gen_rotri_i64(t1, t0, num1); + tcg_gen_rotri_i64(t2, t0, num2); + tcg_gen_xor_i64(t1, t1, t2); + func(t2, t0, num3); + tcg_gen_xor_i64(t1, t1, t2); + tcg_gen_trunc_i64_tl(dest, t1); + + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + return true; +} + +static bool trans_sha512sig0(DisasContext *ctx, arg_sha512sig0 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZKNH(ctx); + return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 1, 8, 7); +} + +static bool trans_sha512sig1(DisasContext *ctx, arg_sha512sig1 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZKNH(ctx); + return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 19, 61, 6); +} + +static bool trans_sha512sum0(DisasContext *ctx, arg_sha512sum0 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZKNH(ctx); + return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 28, 34, 39); +} + +static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZKNH(ctx); + return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 14, 18, 41); +} -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn> To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, lustrew@foxmail.com, luruibo2000@163.com, Weiwei Li <liweiwei@iscas.ac.cn> Subject: [PATCH v10 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension Date: Sat, 16 Apr 2022 10:35:45 +0800 [thread overview] Message-ID: <20220416023549.28463-11-liweiwei@iscas.ac.cn> (raw) In-Reply-To: <20220416023549.28463-1-liweiwei@iscas.ac.cn> - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvk.c.inc | 53 +++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 02a0c71890..d9ebb138d1 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -868,3 +868,8 @@ sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r +# *** RV64 Zknh Standard Extension *** +sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2 +sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2 +sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2 +sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc index bb89a53f52..b1ce4f27cf 100644 --- a/target/riscv/insn_trans/trans_rvk.c.inc +++ b/target/riscv/insn_trans/trans_rvk.c.inc @@ -267,3 +267,56 @@ static bool trans_sha512sig1h(DisasContext *ctx, arg_sha512sig1h *a) REQUIRE_ZKNH(ctx); return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19); } + +static bool gen_sha512_rv64(DisasContext *ctx, arg_r2 *a, DisasExtend ext, + void (*func)(TCGv_i64, TCGv_i64, int64_t), + int64_t num1, int64_t num2, int64_t num3) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, ext); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t0, src1); + tcg_gen_rotri_i64(t1, t0, num1); + tcg_gen_rotri_i64(t2, t0, num2); + tcg_gen_xor_i64(t1, t1, t2); + func(t2, t0, num3); + tcg_gen_xor_i64(t1, t1, t2); + tcg_gen_trunc_i64_tl(dest, t1); + + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + return true; +} + +static bool trans_sha512sig0(DisasContext *ctx, arg_sha512sig0 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZKNH(ctx); + return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 1, 8, 7); +} + +static bool trans_sha512sig1(DisasContext *ctx, arg_sha512sig1 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZKNH(ctx); + return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 19, 61, 6); +} + +static bool trans_sha512sum0(DisasContext *ctx, arg_sha512sum0 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZKNH(ctx); + return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 28, 34, 39); +} + +static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZKNH(ctx); + return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 14, 18, 41); +} -- 2.17.1
next prev parent reply other threads:[~2022-04-16 2:38 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-16 2:35 [PATCH v10 00/14] support subsets of scalar crypto extension Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 01/14] target/riscv: rvk: add cfg properties for zbk* and zk* Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 02/14] target/riscv: rvk: add support for zbkb extension Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 03/14] target/riscv: rvk: add support for zbkc extension Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 04/14] target/riscv: rvk: add support for zbkx extension Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 05/14] crypto: move sm4_sbox from target/arm Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32 Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:50 ` Richard Henderson 2022-04-16 2:50 ` Richard Henderson 2022-04-16 2:35 ` [PATCH v10 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64 Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:51 ` Richard Henderson 2022-04-16 2:51 ` Richard Henderson 2022-04-16 2:35 ` [PATCH v10 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 " Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` Weiwei Li [this message] 2022-04-16 2:35 ` [PATCH v10 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 " Weiwei Li 2022-04-16 2:35 ` [PATCH v10 11/14] target/riscv: rvk: add support for zksed/zksh extension Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 12/14] target/riscv: rvk: add CSR support for Zkr Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions Weiwei Li 2022-04-16 2:35 ` Weiwei Li 2022-04-16 2:35 ` [PATCH v10 14/14] target/riscv: rvk: expose zbk* and zk* properties Weiwei Li 2022-04-16 2:35 ` Weiwei Li
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