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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, bin.meng@windriver.com,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, Weiwei Li <liweiwei@iscas.ac.cn>,
	lazyparser@gmail.com, luruibo2000@163.com, lustrew@foxmail.com
Subject: [PATCH v10 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*
Date: Sat, 16 Apr 2022 10:35:36 +0800	[thread overview]
Message-ID: <20220416023549.28463-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220416023549.28463-1-liweiwei@iscas.ac.cn>

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 23 +++++++++++++++++++++++
 target/riscv/cpu.h | 13 +++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index faa41217d2..365bdd5fe5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -611,6 +611,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             cpu->cfg.ext_zfinx = true;
         }
 
+        if (cpu->cfg.ext_zk) {
+            cpu->cfg.ext_zkn = true;
+            cpu->cfg.ext_zkr = true;
+            cpu->cfg.ext_zkt = true;
+        }
+
+        if (cpu->cfg.ext_zkn) {
+            cpu->cfg.ext_zbkb = true;
+            cpu->cfg.ext_zbkc = true;
+            cpu->cfg.ext_zbkx = true;
+            cpu->cfg.ext_zkne = true;
+            cpu->cfg.ext_zknd = true;
+            cpu->cfg.ext_zknh = true;
+        }
+
+        if (cpu->cfg.ext_zks) {
+            cpu->cfg.ext_zbkb = true;
+            cpu->cfg.ext_zbkc = true;
+            cpu->cfg.ext_zbkx = true;
+            cpu->cfg.ext_zksed = true;
+            cpu->cfg.ext_zksh = true;
+        }
+
         /* Set the ISA extensions, checks should have happened above */
         if (cpu->cfg.ext_i) {
             ext |= RVI;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index dd26b128a0..3064cb975e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -384,7 +384,20 @@ struct RISCVCPUConfig {
     bool ext_zba;
     bool ext_zbb;
     bool ext_zbc;
+    bool ext_zbkb;
+    bool ext_zbkc;
+    bool ext_zbkx;
     bool ext_zbs;
+    bool ext_zk;
+    bool ext_zkn;
+    bool ext_zknd;
+    bool ext_zkne;
+    bool ext_zknh;
+    bool ext_zkr;
+    bool ext_zks;
+    bool ext_zksed;
+    bool ext_zksh;
+    bool ext_zkt;
     bool ext_counters;
     bool ext_ifencei;
     bool ext_icsr;
-- 
2.17.1



WARNING: multiple messages have this Message-ID (diff)
From: Weiwei Li <liweiwei@iscas.ac.cn>
To: richard.henderson@linaro.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, bin.meng@windriver.com,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	lustrew@foxmail.com, luruibo2000@163.com,
	Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v10 01/14] target/riscv: rvk: add cfg properties for zbk* and zk*
Date: Sat, 16 Apr 2022 10:35:36 +0800	[thread overview]
Message-ID: <20220416023549.28463-2-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20220416023549.28463-1-liweiwei@iscas.ac.cn>

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 23 +++++++++++++++++++++++
 target/riscv/cpu.h | 13 +++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index faa41217d2..365bdd5fe5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -611,6 +611,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             cpu->cfg.ext_zfinx = true;
         }
 
+        if (cpu->cfg.ext_zk) {
+            cpu->cfg.ext_zkn = true;
+            cpu->cfg.ext_zkr = true;
+            cpu->cfg.ext_zkt = true;
+        }
+
+        if (cpu->cfg.ext_zkn) {
+            cpu->cfg.ext_zbkb = true;
+            cpu->cfg.ext_zbkc = true;
+            cpu->cfg.ext_zbkx = true;
+            cpu->cfg.ext_zkne = true;
+            cpu->cfg.ext_zknd = true;
+            cpu->cfg.ext_zknh = true;
+        }
+
+        if (cpu->cfg.ext_zks) {
+            cpu->cfg.ext_zbkb = true;
+            cpu->cfg.ext_zbkc = true;
+            cpu->cfg.ext_zbkx = true;
+            cpu->cfg.ext_zksed = true;
+            cpu->cfg.ext_zksh = true;
+        }
+
         /* Set the ISA extensions, checks should have happened above */
         if (cpu->cfg.ext_i) {
             ext |= RVI;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index dd26b128a0..3064cb975e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -384,7 +384,20 @@ struct RISCVCPUConfig {
     bool ext_zba;
     bool ext_zbb;
     bool ext_zbc;
+    bool ext_zbkb;
+    bool ext_zbkc;
+    bool ext_zbkx;
     bool ext_zbs;
+    bool ext_zk;
+    bool ext_zkn;
+    bool ext_zknd;
+    bool ext_zkne;
+    bool ext_zknh;
+    bool ext_zkr;
+    bool ext_zks;
+    bool ext_zksed;
+    bool ext_zksh;
+    bool ext_zkt;
     bool ext_counters;
     bool ext_ifencei;
     bool ext_icsr;
-- 
2.17.1



  reply	other threads:[~2022-04-16  2:38 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-16  2:35 [PATCH v10 00/14] support subsets of scalar crypto extension Weiwei Li
2022-04-16  2:35 ` Weiwei Li
2022-04-16  2:35 ` Weiwei Li [this message]
2022-04-16  2:35   ` [PATCH v10 01/14] target/riscv: rvk: add cfg properties for zbk* and zk* Weiwei Li
2022-04-16  2:35 ` [PATCH v10 02/14] target/riscv: rvk: add support for zbkb extension Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 03/14] target/riscv: rvk: add support for zbkc extension Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 04/14] target/riscv: rvk: add support for zbkx extension Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 05/14] crypto: move sm4_sbox from target/arm Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 06/14] target/riscv: rvk: add support for zknd/zkne extension in RV32 Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:50   ` Richard Henderson
2022-04-16  2:50     ` Richard Henderson
2022-04-16  2:35 ` [PATCH v10 07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64 Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:51   ` Richard Henderson
2022-04-16  2:51     ` Richard Henderson
2022-04-16  2:35 ` [PATCH v10 08/14] target/riscv: rvk: add support for sha256 related instructions in zknh extension Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 09/14] target/riscv: rvk: add support for sha512 related instructions for RV32 " Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 " Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 11/14] target/riscv: rvk: add support for zksed/zksh extension Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 12/14] target/riscv: rvk: add CSR support for Zkr Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 13/14] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions Weiwei Li
2022-04-16  2:35   ` Weiwei Li
2022-04-16  2:35 ` [PATCH v10 14/14] target/riscv: rvk: expose zbk* and zk* properties Weiwei Li
2022-04-16  2:35   ` Weiwei Li

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