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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
	Richard Henderson <richard.henderson@linaro.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults
Date: Fri, 22 Apr 2022 10:36:42 +1000	[thread overview]
Message-ID: <20220422003656.1648121-18-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220422003656.1648121-1-alistair.francis@opensource.wdc.com>

From: Richard Henderson <richard.henderson@linaro.org>

The riscv_raise_exception function stores its argument into
exception_index and then exits to the main loop.  When we
have already set exception_index, we can just exit directly.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220401125948.79292-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1c60fb2e80..126251d5da 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1150,7 +1150,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     env->badaddr = addr;
     env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
                             riscv_cpu_two_stage_lookup(mmu_idx);
-    riscv_raise_exception(&cpu->env, cs->exception_index, retaddr);
+    cpu_loop_exit_restore(cs, retaddr);
 }
 
 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
@@ -1175,7 +1175,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
     env->badaddr = addr;
     env->two_stage_lookup = riscv_cpu_virt_enabled(env) ||
                             riscv_cpu_two_stage_lookup(mmu_idx);
-    riscv_raise_exception(env, cs->exception_index, retaddr);
+    cpu_loop_exit_restore(cs, retaddr);
 }
 
 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@@ -1311,7 +1311,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                             first_stage_error,
                             riscv_cpu_virt_enabled(env) ||
                                 riscv_cpu_two_stage_lookup(mmu_idx));
-        riscv_raise_exception(env, cs->exception_index, retaddr);
+        cpu_loop_exit_restore(cs, retaddr);
     }
 
     return true;
-- 
2.35.1



  parent reply	other threads:[~2022-04-22  0:57 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22  0:36 [PULL v2 00/31] riscv-to-apply queue Alistair Francis
2022-04-22  0:36 ` [PULL v2 01/31] hw/ssi: Add Ibex SPI device model Alistair Francis
2022-05-12 16:37   ` Peter Maydell
2022-07-20  5:33     ` Alistair Francis
2022-04-22  0:36 ` [PULL v2 02/31] riscv: opentitan: Connect opentitan SPI Host Alistair Francis
2022-04-22  0:36 ` [PULL v2 03/31] target/riscv: Define simpler privileged spec version numbering Alistair Francis
2022-04-22  0:36 ` [PULL v2 04/31] target/riscv: Add the privileged spec version 1.12.0 Alistair Francis
2022-04-22  0:36 ` [PULL v2 05/31] target/riscv: Introduce privilege version field in the CSR ops Alistair Francis
2022-04-22  0:36 ` [PULL v2 06/31] target/riscv: Add support for mconfigptr Alistair Francis
2022-04-22  0:36 ` [PULL v2 07/31] target/riscv: Add *envcfg* CSRs support Alistair Francis
2022-04-22  0:36 ` [PULL v2 08/31] target/riscv: Enable privileged spec version 1.12 Alistair Francis
2022-04-22  0:36 ` [PULL v2 09/31] target/riscv: cpu: Fixup indentation Alistair Francis
2022-04-22  0:36 ` [PULL v2 10/31] target/riscv: Allow software access to MIP SEIP Alistair Francis
2022-04-22  0:36 ` [PULL v2 11/31] target/riscv: Add initial support for the Sdtrig extension Alistair Francis
2022-04-22  0:36 ` [PULL v2 12/31] target/riscv: optimize condition assign for scale < 0 Alistair Francis
2022-04-22  0:36 ` [PULL v2 13/31] target/riscv: optimize helper for vmv<nr>r.v Alistair Francis
2022-04-22  0:36 ` [PULL v2 14/31] target/riscv: misa to ISA string conversion fix Alistair Francis
2022-04-22  0:36 ` [PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree Alistair Francis
2022-04-22  0:36 ` [PULL v2 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Alistair Francis
2022-04-22  0:36 ` Alistair Francis [this message]
2022-04-22  0:36 ` [PULL v2 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM Alistair Francis
2022-04-22  0:36 ` [PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow Alistair Francis
2022-04-22  0:36 ` [PULL v2 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Alistair Francis
2022-04-22  0:36 ` [PULL v2 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT Alistair Francis
2022-04-22  0:36 ` [PULL v2 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " Alistair Francis
2022-04-22  0:36 ` [PULL v2 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable Alistair Francis
2022-04-22  0:36 ` [PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices Alistair Francis
2022-04-22  0:36 ` [PULL v2 25/31] target/riscv: debug: Implement debug related TCGCPUOps Alistair Francis
2022-04-22  0:36 ` [PULL v2 26/31] target/riscv: cpu: Add a config option for native debug Alistair Francis
2022-04-22  0:36 ` [PULL v2 27/31] target/riscv: csr: Hook debug CSR read/write Alistair Francis
2022-04-22  0:36 ` [PULL v2 28/31] target/riscv: machine: Add debug state description Alistair Francis
2022-04-22  0:36 ` [PULL v2 29/31] target/riscv: cpu: Enable native debug feature Alistair Francis
2022-04-22  0:36 ` [PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Alistair Francis
2022-04-22  0:36 ` [PULL v2 31/31] hw/riscv: boot: Support 64bit fdt address Alistair Francis
2022-04-22 10:54 ` [PULL v2 00/31] riscv-to-apply queue Richard Henderson

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