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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Atish Patra <atishp@rivosinc.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 06/31] target/riscv: Add support for mconfigptr
Date: Fri, 22 Apr 2022 10:36:31 +1000	[thread overview]
Message-ID: <20220422003656.1648121-7-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220422003656.1648121-1-alistair.francis@opensource.wdc.com>

From: Atish Patra <atishp@rivosinc.com>

RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-5-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 1 +
 target/riscv/csr.c      | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 0fe01d7da5..48d92a81c3 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -148,6 +148,7 @@
 #define CSR_MARCHID         0xf12
 #define CSR_MIMPID          0xf13
 #define CSR_MHARTID         0xf14
+#define CSR_MCONFIGPTR      0xf15
 
 /* Machine Trap Setup */
 #define CSR_MSTATUS         0x300
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1400027158..6590cc8aa7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3110,6 +3110,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
 
+    [CSR_MCONFIGPTR]  = { "mconfigptr", any,   read_zero,
+                                        .min_priv_ver = PRIV_VERSION_1_12_0 },
     /* Machine Trap Setup */
     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus, NULL,
                                                read_mstatus_i128                   },
-- 
2.35.1



  parent reply	other threads:[~2022-04-22  0:39 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22  0:36 [PULL v2 00/31] riscv-to-apply queue Alistair Francis
2022-04-22  0:36 ` [PULL v2 01/31] hw/ssi: Add Ibex SPI device model Alistair Francis
2022-05-12 16:37   ` Peter Maydell
2022-07-20  5:33     ` Alistair Francis
2022-04-22  0:36 ` [PULL v2 02/31] riscv: opentitan: Connect opentitan SPI Host Alistair Francis
2022-04-22  0:36 ` [PULL v2 03/31] target/riscv: Define simpler privileged spec version numbering Alistair Francis
2022-04-22  0:36 ` [PULL v2 04/31] target/riscv: Add the privileged spec version 1.12.0 Alistair Francis
2022-04-22  0:36 ` [PULL v2 05/31] target/riscv: Introduce privilege version field in the CSR ops Alistair Francis
2022-04-22  0:36 ` Alistair Francis [this message]
2022-04-22  0:36 ` [PULL v2 07/31] target/riscv: Add *envcfg* CSRs support Alistair Francis
2022-04-22  0:36 ` [PULL v2 08/31] target/riscv: Enable privileged spec version 1.12 Alistair Francis
2022-04-22  0:36 ` [PULL v2 09/31] target/riscv: cpu: Fixup indentation Alistair Francis
2022-04-22  0:36 ` [PULL v2 10/31] target/riscv: Allow software access to MIP SEIP Alistair Francis
2022-04-22  0:36 ` [PULL v2 11/31] target/riscv: Add initial support for the Sdtrig extension Alistair Francis
2022-04-22  0:36 ` [PULL v2 12/31] target/riscv: optimize condition assign for scale < 0 Alistair Francis
2022-04-22  0:36 ` [PULL v2 13/31] target/riscv: optimize helper for vmv<nr>r.v Alistair Francis
2022-04-22  0:36 ` [PULL v2 14/31] target/riscv: misa to ISA string conversion fix Alistair Francis
2022-04-22  0:36 ` [PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree Alistair Francis
2022-04-22  0:36 ` [PULL v2 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Alistair Francis
2022-04-22  0:36 ` [PULL v2 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults Alistair Francis
2022-04-22  0:36 ` [PULL v2 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM Alistair Francis
2022-04-22  0:36 ` [PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow Alistair Francis
2022-04-22  0:36 ` [PULL v2 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Alistair Francis
2022-04-22  0:36 ` [PULL v2 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT Alistair Francis
2022-04-22  0:36 ` [PULL v2 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " Alistair Francis
2022-04-22  0:36 ` [PULL v2 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable Alistair Francis
2022-04-22  0:36 ` [PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices Alistair Francis
2022-04-22  0:36 ` [PULL v2 25/31] target/riscv: debug: Implement debug related TCGCPUOps Alistair Francis
2022-04-22  0:36 ` [PULL v2 26/31] target/riscv: cpu: Add a config option for native debug Alistair Francis
2022-04-22  0:36 ` [PULL v2 27/31] target/riscv: csr: Hook debug CSR read/write Alistair Francis
2022-04-22  0:36 ` [PULL v2 28/31] target/riscv: machine: Add debug state description Alistair Francis
2022-04-22  0:36 ` [PULL v2 29/31] target/riscv: cpu: Enable native debug feature Alistair Francis
2022-04-22  0:36 ` [PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Alistair Francis
2022-04-22  0:36 ` [PULL v2 31/31] hw/riscv: boot: Support 64bit fdt address Alistair Francis
2022-04-22 10:54 ` [PULL v2 00/31] riscv-to-apply queue Richard Henderson

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