From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Atish Patra <atishp@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 07/31] target/riscv: Add *envcfg* CSRs support
Date: Fri, 22 Apr 2022 10:36:32 +1000 [thread overview]
Message-ID: <20220422003656.1648121-8-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220422003656.1648121-1-alistair.francis@opensource.wdc.com>
From: Atish Patra <atishp@rivosinc.com>
The RISC-V privileged specification v1.12 defines few execution
environment configuration CSRs that can be used enable/disable
extensions per privilege levels.
Add the basic support for these CSRs.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-6-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 ++
target/riscv/cpu_bits.h | 39 +++++++++++++++
target/riscv/csr.c | 107 ++++++++++++++++++++++++++++++++++++++++
target/riscv/machine.c | 23 +++++++++
4 files changed, 174 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5139110c4f..e129c3da7d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -304,6 +304,11 @@ struct CPUArchState {
target_ulong spmbase;
target_ulong upmmask;
target_ulong upmbase;
+
+ /* CSRs for execution enviornment configuration */
+ uint64_t menvcfg;
+ target_ulong senvcfg;
+ uint64_t henvcfg;
#endif
target_ulong cur_pmmask;
target_ulong cur_pmbase;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 48d92a81c3..4a9e4f7d09 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -202,6 +202,9 @@
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
+/* Supervisor Configuration CSRs */
+#define CSR_SENVCFG 0x10A
+
/* Supervisor Trap Handling */
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
@@ -247,6 +250,10 @@
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
+/* Hypervisor Configuration CSRs */
+#define CSR_HENVCFG 0x60A
+#define CSR_HENVCFGH 0x61A
+
/* Virtual CSRs */
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
@@ -290,6 +297,10 @@
#define CSR_VSIEH 0x214
#define CSR_VSIPH 0x254
+/* Machine Configuration CSRs */
+#define CSR_MENVCFG 0x30A
+#define CSR_MENVCFGH 0x31A
+
/* Enhanced Physical Memory Protection (ePMP) */
#define CSR_MSECCFG 0x747
#define CSR_MSECCFGH 0x757
@@ -663,6 +674,34 @@ typedef enum RISCVException {
#define PM_EXT_CLEAN 0x00000002ULL
#define PM_EXT_DIRTY 0x00000003ULL
+/* Execution enviornment configuration bits */
+#define MENVCFG_FIOM BIT(0)
+#define MENVCFG_CBIE (3UL << 4)
+#define MENVCFG_CBCFE BIT(6)
+#define MENVCFG_CBZE BIT(7)
+#define MENVCFG_PBMTE (1ULL << 62)
+#define MENVCFG_STCE (1ULL << 63)
+
+/* For RV32 */
+#define MENVCFGH_PBMTE BIT(30)
+#define MENVCFGH_STCE BIT(31)
+
+#define SENVCFG_FIOM MENVCFG_FIOM
+#define SENVCFG_CBIE MENVCFG_CBIE
+#define SENVCFG_CBCFE MENVCFG_CBCFE
+#define SENVCFG_CBZE MENVCFG_CBZE
+
+#define HENVCFG_FIOM MENVCFG_FIOM
+#define HENVCFG_CBIE MENVCFG_CBIE
+#define HENVCFG_CBCFE MENVCFG_CBCFE
+#define HENVCFG_CBZE MENVCFG_CBZE
+#define HENVCFG_PBMTE MENVCFG_PBMTE
+#define HENVCFG_STCE MENVCFG_STCE
+
+/* For RV32 */
+#define HENVCFGH_PBMTE MENVCFGH_PBMTE
+#define HENVCFGH_STCE MENVCFGH_STCE
+
/* Offsets for every pair of control bits per each priv level */
#define XS_OFFSET 0ULL
#define U_OFFSET 2ULL
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6590cc8aa7..84a398b205 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1398,6 +1398,101 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+/* Execution environment configuration setup */
+static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->menvcfg;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
+
+ if (riscv_cpu_mxl(env) == MXL_RV64) {
+ mask |= MENVCFG_PBMTE | MENVCFG_STCE;
+ }
+ env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
+
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->menvcfg >> 32;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
+ uint64_t valh = (uint64_t)val << 32;
+
+ env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
+
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->senvcfg;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
+
+ env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
+
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->henvcfg;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
+
+ if (riscv_cpu_mxl(env) == MXL_RV64) {
+ mask |= HENVCFG_PBMTE | HENVCFG_STCE;
+ }
+
+ env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
+
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = env->henvcfg >> 32;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
+ uint64_t valh = (uint64_t)val << 32;
+
+ env->henvcfg = (env->henvcfg & ~mask) | (valh & mask);
+
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
uint64_t *ret_val,
uint64_t new_val, uint64_t wr_mask)
@@ -3158,6 +3253,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MVIPH] = { "mviph", aia_any32, read_zero, write_ignore },
[CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
+ /* Execution environment configuration */
+ [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg,
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
+ [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh,
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
+ [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg,
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
+ [CSR_HENVCFG] = { "henvcfg", hmode, read_henvcfg, write_henvcfg,
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
+ [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh,
+ .min_priv_ver = PRIV_VERSION_1_12_0 },
+
/* Supervisor Trap Setup */
[CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL,
read_sstatus_i128 },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 5178b3fec9..243f567949 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -231,6 +231,28 @@ static int riscv_cpu_post_load(void *opaque, int version_id)
return 0;
}
+static bool envcfg_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return (env->priv_ver >= PRIV_VERSION_1_12_0 ? 1 : 0);
+}
+
+static const VMStateDescription vmstate_envcfg = {
+ .name = "cpu/envcfg",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = envcfg_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.menvcfg, RISCVCPU),
+ VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
+ VMSTATE_UINT64(env.henvcfg, RISCVCPU),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
@@ -292,6 +314,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_pointermasking,
&vmstate_rv128,
&vmstate_kvmtimer,
+ &vmstate_envcfg,
NULL
}
};
--
2.35.1
next prev parent reply other threads:[~2022-04-22 0:46 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-22 0:36 [PULL v2 00/31] riscv-to-apply queue Alistair Francis
2022-04-22 0:36 ` [PULL v2 01/31] hw/ssi: Add Ibex SPI device model Alistair Francis
2022-05-12 16:37 ` Peter Maydell
2022-07-20 5:33 ` Alistair Francis
2022-04-22 0:36 ` [PULL v2 02/31] riscv: opentitan: Connect opentitan SPI Host Alistair Francis
2022-04-22 0:36 ` [PULL v2 03/31] target/riscv: Define simpler privileged spec version numbering Alistair Francis
2022-04-22 0:36 ` [PULL v2 04/31] target/riscv: Add the privileged spec version 1.12.0 Alistair Francis
2022-04-22 0:36 ` [PULL v2 05/31] target/riscv: Introduce privilege version field in the CSR ops Alistair Francis
2022-04-22 0:36 ` [PULL v2 06/31] target/riscv: Add support for mconfigptr Alistair Francis
2022-04-22 0:36 ` Alistair Francis [this message]
2022-04-22 0:36 ` [PULL v2 08/31] target/riscv: Enable privileged spec version 1.12 Alistair Francis
2022-04-22 0:36 ` [PULL v2 09/31] target/riscv: cpu: Fixup indentation Alistair Francis
2022-04-22 0:36 ` [PULL v2 10/31] target/riscv: Allow software access to MIP SEIP Alistair Francis
2022-04-22 0:36 ` [PULL v2 11/31] target/riscv: Add initial support for the Sdtrig extension Alistair Francis
2022-04-22 0:36 ` [PULL v2 12/31] target/riscv: optimize condition assign for scale < 0 Alistair Francis
2022-04-22 0:36 ` [PULL v2 13/31] target/riscv: optimize helper for vmv<nr>r.v Alistair Francis
2022-04-22 0:36 ` [PULL v2 14/31] target/riscv: misa to ISA string conversion fix Alistair Francis
2022-04-22 0:36 ` [PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree Alistair Francis
2022-04-22 0:36 ` [PULL v2 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Alistair Francis
2022-04-22 0:36 ` [PULL v2 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults Alistair Francis
2022-04-22 0:36 ` [PULL v2 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM Alistair Francis
2022-04-22 0:36 ` [PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow Alistair Francis
2022-04-22 0:36 ` [PULL v2 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Alistair Francis
2022-04-22 0:36 ` [PULL v2 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT Alistair Francis
2022-04-22 0:36 ` [PULL v2 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " Alistair Francis
2022-04-22 0:36 ` [PULL v2 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable Alistair Francis
2022-04-22 0:36 ` [PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices Alistair Francis
2022-04-22 0:36 ` [PULL v2 25/31] target/riscv: debug: Implement debug related TCGCPUOps Alistair Francis
2022-04-22 0:36 ` [PULL v2 26/31] target/riscv: cpu: Add a config option for native debug Alistair Francis
2022-04-22 0:36 ` [PULL v2 27/31] target/riscv: csr: Hook debug CSR read/write Alistair Francis
2022-04-22 0:36 ` [PULL v2 28/31] target/riscv: machine: Add debug state description Alistair Francis
2022-04-22 0:36 ` [PULL v2 29/31] target/riscv: cpu: Enable native debug feature Alistair Francis
2022-04-22 0:36 ` [PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Alistair Francis
2022-04-22 0:36 ` [PULL v2 31/31] hw/riscv: boot: Support 64bit fdt address Alistair Francis
2022-04-22 10:54 ` [PULL v2 00/31] riscv-to-apply queue Richard Henderson
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