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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
	Jim Shu <jim.shu@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable
Date: Fri, 22 Apr 2022 10:36:48 +1000	[thread overview]
Message-ID: <20220422003656.1648121-24-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220422003656.1648121-1-alistair.francis@opensource.wdc.com>

From: Frank Chang <frank.chang@sifive.com>

RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.

This patch makes mtime to be writable by recording the time delta value
between the mtime value to be written and the timer value at the time
mtime is written. Time delta value is then added back whenever the timer
value is retrieved.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220420080901.14655-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/intc/riscv_aclint.h |  1 +
 target/riscv/cpu.h             |  8 ++--
 hw/intc/riscv_aclint.c         | 71 ++++++++++++++++++++++++----------
 target/riscv/cpu_helper.c      |  4 +-
 4 files changed, 57 insertions(+), 27 deletions(-)

diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h
index 229bd08d25..26d4048687 100644
--- a/include/hw/intc/riscv_aclint.h
+++ b/include/hw/intc/riscv_aclint.h
@@ -31,6 +31,7 @@
 typedef struct RISCVAclintMTimerState {
     /*< private >*/
     SysBusDevice parent_obj;
+    uint64_t time_delta;
 
     /*< public >*/
     MemoryRegion mmio;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ff3eee4087..5d1259d4ae 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -285,8 +285,8 @@ struct CPUArchState {
     type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM];
 
     /* machine specific rdtime callback */
-    uint64_t (*rdtime_fn)(uint32_t);
-    uint32_t rdtime_fn_arg;
+    uint64_t (*rdtime_fn)(void *);
+    void *rdtime_fn_arg;
 
     /* machine specific AIA ireg read-modify-write callback */
 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \
@@ -496,8 +496,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value);
 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
-                             uint32_t arg);
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
+                             void *arg);
 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
                                    int (*rmw_fn)(void *arg,
                                                  target_ulong reg,
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c
index ff082090fe..3b3ab548f6 100644
--- a/hw/intc/riscv_aclint.c
+++ b/hw/intc/riscv_aclint.c
@@ -38,12 +38,18 @@ typedef struct riscv_aclint_mtimer_callback {
     int num;
 } riscv_aclint_mtimer_callback;
 
-static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
+static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq)
 {
     return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
         timebase_freq, NANOSECONDS_PER_SECOND);
 }
 
+static uint64_t cpu_riscv_read_rtc(void *opaque)
+{
+    RISCVAclintMTimerState *mtimer = opaque;
+    return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta;
+}
+
 /*
  * Called when timecmp is written to update the QEMU timer or immediately
  * trigger timer interrupt if mtimecmp <= current timer value.
@@ -51,13 +57,13 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
 static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer,
                                               RISCVCPU *cpu,
                                               int hartid,
-                                              uint64_t value,
-                                              uint32_t timebase_freq)
+                                              uint64_t value)
 {
+    uint32_t timebase_freq = mtimer->timebase_freq;
     uint64_t next;
     uint64_t diff;
 
-    uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
+    uint64_t rtc_r = cpu_riscv_read_rtc(mtimer);
 
     cpu->env.timecmp = value;
     if (cpu->env.timecmp <= rtc_r) {
@@ -140,11 +146,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,
         }
     } else if (addr == mtimer->time_base) {
         /* time_lo for RV32/RV64 or timecmp for RV64 */
-        uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq);
+        uint64_t rtc = cpu_riscv_read_rtc(mtimer);
         return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc;
     } else if (addr == mtimer->time_base + 4) {
         /* time_hi */
-        return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF;
+        return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF;
     }
 
     qemu_log_mask(LOG_UNIMP,
@@ -157,6 +163,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
     uint64_t value, unsigned size)
 {
     RISCVAclintMTimerState *mtimer = opaque;
+    int i;
 
     if (addr >= mtimer->timecmp_base &&
         addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {
@@ -172,20 +179,18 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
                 /* timecmp_lo for RV32/RV64 */
                 uint64_t timecmp_hi = env->timecmp >> 32;
                 riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
-                    timecmp_hi << 32 | (value & 0xFFFFFFFF),
-                    mtimer->timebase_freq);
+                    timecmp_hi << 32 | (value & 0xFFFFFFFF));
             } else {
                 /* timecmp for RV64 */
                 riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
-                                                  value, mtimer->timebase_freq);
+                                                  value);
             }
         } else if ((addr & 0x7) == 4) {
             if (size == 4) {
                 /* timecmp_hi for RV32/RV64 */
                 uint64_t timecmp_lo = env->timecmp;
                 riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,
-                    value << 32 | (timecmp_lo & 0xFFFFFFFF),
-                    mtimer->timebase_freq);
+                    value << 32 | (timecmp_lo & 0xFFFFFFFF));
             } else {
                 qemu_log_mask(LOG_GUEST_ERROR,
                               "aclint-mtimer: invalid timecmp_hi write: %08x",
@@ -197,15 +202,39 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
                           (uint32_t)addr);
         }
         return;
-    } else if (addr == mtimer->time_base) {
-        /* time_lo */
-        qemu_log_mask(LOG_UNIMP,
-                      "aclint-mtimer: time_lo write not implemented");
-        return;
-    } else if (addr == mtimer->time_base + 4) {
-        /* time_hi */
-        qemu_log_mask(LOG_UNIMP,
-                      "aclint-mtimer: time_hi write not implemented");
+    } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) {
+        uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq);
+
+        if (addr == mtimer->time_base) {
+            if (size == 4) {
+                /* time_lo for RV32/RV64 */
+                mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r;
+            } else {
+                /* time for RV64 */
+                mtimer->time_delta = value - rtc_r;
+            }
+        } else {
+            if (size == 4) {
+                /* time_hi for RV32/RV64 */
+                mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r;
+            } else {
+                qemu_log_mask(LOG_GUEST_ERROR,
+                              "aclint-mtimer: invalid time_hi write: %08x",
+                              (uint32_t)addr);
+                return;
+            }
+        }
+
+        /* Check if timer interrupt is triggered for each hart. */
+        for (i = 0; i < mtimer->num_harts; i++) {
+            CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i);
+            CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+            if (!env) {
+                continue;
+            }
+            riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
+                                              i, env->timecmp);
+        }
         return;
     }
 
@@ -315,7 +344,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
             continue;
         }
         if (provide_rdtime) {
-            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
+            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev);
         }
 
         cb->s = RISCV_ACLINT_MTIMER(dev);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 126251d5da..e1aa4f2097 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -632,8 +632,8 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value)
     return old;
 }
 
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
-                             uint32_t arg)
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
+                             void *arg)
 {
     env->rdtime_fn = fn;
     env->rdtime_fn_arg = arg;
-- 
2.35.1



  parent reply	other threads:[~2022-04-22  0:54 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-22  0:36 [PULL v2 00/31] riscv-to-apply queue Alistair Francis
2022-04-22  0:36 ` [PULL v2 01/31] hw/ssi: Add Ibex SPI device model Alistair Francis
2022-05-12 16:37   ` Peter Maydell
2022-07-20  5:33     ` Alistair Francis
2022-04-22  0:36 ` [PULL v2 02/31] riscv: opentitan: Connect opentitan SPI Host Alistair Francis
2022-04-22  0:36 ` [PULL v2 03/31] target/riscv: Define simpler privileged spec version numbering Alistair Francis
2022-04-22  0:36 ` [PULL v2 04/31] target/riscv: Add the privileged spec version 1.12.0 Alistair Francis
2022-04-22  0:36 ` [PULL v2 05/31] target/riscv: Introduce privilege version field in the CSR ops Alistair Francis
2022-04-22  0:36 ` [PULL v2 06/31] target/riscv: Add support for mconfigptr Alistair Francis
2022-04-22  0:36 ` [PULL v2 07/31] target/riscv: Add *envcfg* CSRs support Alistair Francis
2022-04-22  0:36 ` [PULL v2 08/31] target/riscv: Enable privileged spec version 1.12 Alistair Francis
2022-04-22  0:36 ` [PULL v2 09/31] target/riscv: cpu: Fixup indentation Alistair Francis
2022-04-22  0:36 ` [PULL v2 10/31] target/riscv: Allow software access to MIP SEIP Alistair Francis
2022-04-22  0:36 ` [PULL v2 11/31] target/riscv: Add initial support for the Sdtrig extension Alistair Francis
2022-04-22  0:36 ` [PULL v2 12/31] target/riscv: optimize condition assign for scale < 0 Alistair Francis
2022-04-22  0:36 ` [PULL v2 13/31] target/riscv: optimize helper for vmv<nr>r.v Alistair Francis
2022-04-22  0:36 ` [PULL v2 14/31] target/riscv: misa to ISA string conversion fix Alistair Francis
2022-04-22  0:36 ` [PULL v2 15/31] target/riscv: Add isa extenstion strings to the device tree Alistair Francis
2022-04-22  0:36 ` [PULL v2 16/31] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Alistair Francis
2022-04-22  0:36 ` [PULL v2 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults Alistair Francis
2022-04-22  0:36 ` [PULL v2 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM Alistair Francis
2022-04-22  0:36 ` [PULL v2 19/31] target/riscv/pmp: fix NAPOT range computation overflow Alistair Francis
2022-04-22  0:36 ` [PULL v2 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Alistair Francis
2022-04-22  0:36 ` [PULL v2 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT Alistair Francis
2022-04-22  0:36 ` [PULL v2 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " Alistair Francis
2022-04-22  0:36 ` Alistair Francis [this message]
2022-04-22  0:36 ` [PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices Alistair Francis
2022-04-22  0:36 ` [PULL v2 25/31] target/riscv: debug: Implement debug related TCGCPUOps Alistair Francis
2022-04-22  0:36 ` [PULL v2 26/31] target/riscv: cpu: Add a config option for native debug Alistair Francis
2022-04-22  0:36 ` [PULL v2 27/31] target/riscv: csr: Hook debug CSR read/write Alistair Francis
2022-04-22  0:36 ` [PULL v2 28/31] target/riscv: machine: Add debug state description Alistair Francis
2022-04-22  0:36 ` [PULL v2 29/31] target/riscv: cpu: Enable native debug feature Alistair Francis
2022-04-22  0:36 ` [PULL v2 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Alistair Francis
2022-04-22  0:36 ` [PULL v2 31/31] hw/riscv: boot: Support 64bit fdt address Alistair Francis
2022-04-22 10:54 ` [PULL v2 00/31] riscv-to-apply queue Richard Henderson

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