From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
<angelogioacchino.delregno@collabora.com>,
<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V5 00/16] Cleanup MediaTek clk reset drivers and support MT8192/MT8195
Date: Thu, 28 Apr 2022 19:56:03 +0800 [thread overview]
Message-ID: <20220428115620.13512-1-rex-bc.chen@mediatek.com> (raw)
In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
folder. MediaTek clock reset driver is used to provide reset control
of modules controlled in clk, like infra_ao.
Changes for V5:
1. Add all infra reset bits for MT8192 and MT8195.
2. Fix reviewers' comments.
Changes for V4:
1. Abandon the implementation of reset-cell = 2, and use reset index to
determine which reset bit is used.
2. Add documentation for enum/structure/function in reset.h.
3. Combine binding/drvier support patch for MT8192 and MT8195.
4. The MT8195 DTS is accepted by Matthias, and I add new DTS patch to
support infracfg_ao reset for MT8195. The DTS of MT8195 is still
not merged into mainline. Please refer to [1].
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=for-next&id=37f2582883be7218dc69f9af135959a8e93de223
Changes for V3:
1. Modify drivers for reviewers' comments.
2. Add dt-binding patch for MT8192/MT8195 infra.
3. Add reset property of infra node for MT8192.
4. Use original function for simple operation.
Changes for V2:
1. Modify drivers for reviewers' comments.
2. Use simple reset to replace v1.
3. Recover v2 to set_clr.
4. Separate error handling to another patch.
5. Add support for input offset and bit from DT.
6. Add support for MT8192 and MT8195.
Rex-BC Chen (16):
clk: mediatek: reset: Add reset.h
clk: mediatek: reset: Fix written reset bit offset
clk: mediatek: reset: Refine and reorder functions in reset.c
clk: mediatek: reset: Extract common drivers to update function
clk: mediatek: reset: Merge and revise reset register function
clk: mediatek: reset: Revise structure to control reset register
clk: mediatek: reset: Support nonsequence base offsets of reset registers
clk: mediatek: reset: Change return type for clock reset register function
clk: mediatek: reset: Add new register reset function with device
clk: mediatek: reset: Add reset support for simple probe
dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195
dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195
dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192
clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
arm64: dts: mediatek: Add infra #reset-cells property for MT8192
arm64: dts: mediatek: Add infra #reset-cells property for MT8195
.../mediatek/mediatek,mt8192-sys-clock.yaml | 3 +
.../mediatek/mediatek,mt8195-sys-clock.yaml | 3 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +-
drivers/clk/mediatek/clk-mt2701-eth.c | 10 +-
drivers/clk/mediatek/clk-mt2701-g3d.c | 10 +-
drivers/clk/mediatek/clk-mt2701-hif.c | 10 +-
drivers/clk/mediatek/clk-mt2701.c | 22 ++-
drivers/clk/mediatek/clk-mt2712.c | 22 ++-
drivers/clk/mediatek/clk-mt7622-eth.c | 10 +-
drivers/clk/mediatek/clk-mt7622-hif.c | 12 +-
drivers/clk/mediatek/clk-mt7622.c | 22 ++-
drivers/clk/mediatek/clk-mt7629-eth.c | 10 +-
drivers/clk/mediatek/clk-mt7629-hif.c | 12 +-
drivers/clk/mediatek/clk-mt8135.c | 22 ++-
drivers/clk/mediatek/clk-mt8173.c | 22 ++-
drivers/clk/mediatek/clk-mt8183.c | 18 +-
drivers/clk/mediatek/clk-mt8192.c | 18 ++
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 15 ++
drivers/clk/mediatek/clk-mtk.c | 7 +
drivers/clk/mediatek/clk-mtk.h | 9 +-
drivers/clk/mediatek/reset.c | 172 ++++++++++++------
drivers/clk/mediatek/reset.h | 77 ++++++++
include/dt-bindings/reset/mt8192-resets.h | 163 +++++++++++++++++
include/dt-bindings/reset/mt8195-resets.h | 170 +++++++++++++++++
25 files changed, 759 insertions(+), 94 deletions(-)
create mode 100644 drivers/clk/mediatek/reset.h
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
<angelogioacchino.delregno@collabora.com>,
<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V5 00/16] Cleanup MediaTek clk reset drivers and support MT8192/MT8195
Date: Thu, 28 Apr 2022 19:56:03 +0800 [thread overview]
Message-ID: <20220428115620.13512-1-rex-bc.chen@mediatek.com> (raw)
In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
folder. MediaTek clock reset driver is used to provide reset control
of modules controlled in clk, like infra_ao.
Changes for V5:
1. Add all infra reset bits for MT8192 and MT8195.
2. Fix reviewers' comments.
Changes for V4:
1. Abandon the implementation of reset-cell = 2, and use reset index to
determine which reset bit is used.
2. Add documentation for enum/structure/function in reset.h.
3. Combine binding/drvier support patch for MT8192 and MT8195.
4. The MT8195 DTS is accepted by Matthias, and I add new DTS patch to
support infracfg_ao reset for MT8195. The DTS of MT8195 is still
not merged into mainline. Please refer to [1].
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=for-next&id=37f2582883be7218dc69f9af135959a8e93de223
Changes for V3:
1. Modify drivers for reviewers' comments.
2. Add dt-binding patch for MT8192/MT8195 infra.
3. Add reset property of infra node for MT8192.
4. Use original function for simple operation.
Changes for V2:
1. Modify drivers for reviewers' comments.
2. Use simple reset to replace v1.
3. Recover v2 to set_clr.
4. Separate error handling to another patch.
5. Add support for input offset and bit from DT.
6. Add support for MT8192 and MT8195.
Rex-BC Chen (16):
clk: mediatek: reset: Add reset.h
clk: mediatek: reset: Fix written reset bit offset
clk: mediatek: reset: Refine and reorder functions in reset.c
clk: mediatek: reset: Extract common drivers to update function
clk: mediatek: reset: Merge and revise reset register function
clk: mediatek: reset: Revise structure to control reset register
clk: mediatek: reset: Support nonsequence base offsets of reset registers
clk: mediatek: reset: Change return type for clock reset register function
clk: mediatek: reset: Add new register reset function with device
clk: mediatek: reset: Add reset support for simple probe
dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195
dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195
dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192
clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
arm64: dts: mediatek: Add infra #reset-cells property for MT8192
arm64: dts: mediatek: Add infra #reset-cells property for MT8195
.../mediatek/mediatek,mt8192-sys-clock.yaml | 3 +
.../mediatek/mediatek,mt8195-sys-clock.yaml | 3 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +-
drivers/clk/mediatek/clk-mt2701-eth.c | 10 +-
drivers/clk/mediatek/clk-mt2701-g3d.c | 10 +-
drivers/clk/mediatek/clk-mt2701-hif.c | 10 +-
drivers/clk/mediatek/clk-mt2701.c | 22 ++-
drivers/clk/mediatek/clk-mt2712.c | 22 ++-
drivers/clk/mediatek/clk-mt7622-eth.c | 10 +-
drivers/clk/mediatek/clk-mt7622-hif.c | 12 +-
drivers/clk/mediatek/clk-mt7622.c | 22 ++-
drivers/clk/mediatek/clk-mt7629-eth.c | 10 +-
drivers/clk/mediatek/clk-mt7629-hif.c | 12 +-
drivers/clk/mediatek/clk-mt8135.c | 22 ++-
drivers/clk/mediatek/clk-mt8173.c | 22 ++-
drivers/clk/mediatek/clk-mt8183.c | 18 +-
drivers/clk/mediatek/clk-mt8192.c | 18 ++
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 15 ++
drivers/clk/mediatek/clk-mtk.c | 7 +
drivers/clk/mediatek/clk-mtk.h | 9 +-
drivers/clk/mediatek/reset.c | 172 ++++++++++++------
drivers/clk/mediatek/reset.h | 77 ++++++++
include/dt-bindings/reset/mt8192-resets.h | 163 +++++++++++++++++
include/dt-bindings/reset/mt8195-resets.h | 170 +++++++++++++++++
25 files changed, 759 insertions(+), 94 deletions(-)
create mode 100644 drivers/clk/mediatek/reset.h
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
<angelogioacchino.delregno@collabora.com>,
<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V5 00/16] Cleanup MediaTek clk reset drivers and support MT8192/MT8195
Date: Thu, 28 Apr 2022 19:56:03 +0800 [thread overview]
Message-ID: <20220428115620.13512-1-rex-bc.chen@mediatek.com> (raw)
In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
folder. MediaTek clock reset driver is used to provide reset control
of modules controlled in clk, like infra_ao.
Changes for V5:
1. Add all infra reset bits for MT8192 and MT8195.
2. Fix reviewers' comments.
Changes for V4:
1. Abandon the implementation of reset-cell = 2, and use reset index to
determine which reset bit is used.
2. Add documentation for enum/structure/function in reset.h.
3. Combine binding/drvier support patch for MT8192 and MT8195.
4. The MT8195 DTS is accepted by Matthias, and I add new DTS patch to
support infracfg_ao reset for MT8195. The DTS of MT8195 is still
not merged into mainline. Please refer to [1].
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=for-next&id=37f2582883be7218dc69f9af135959a8e93de223
Changes for V3:
1. Modify drivers for reviewers' comments.
2. Add dt-binding patch for MT8192/MT8195 infra.
3. Add reset property of infra node for MT8192.
4. Use original function for simple operation.
Changes for V2:
1. Modify drivers for reviewers' comments.
2. Use simple reset to replace v1.
3. Recover v2 to set_clr.
4. Separate error handling to another patch.
5. Add support for input offset and bit from DT.
6. Add support for MT8192 and MT8195.
Rex-BC Chen (16):
clk: mediatek: reset: Add reset.h
clk: mediatek: reset: Fix written reset bit offset
clk: mediatek: reset: Refine and reorder functions in reset.c
clk: mediatek: reset: Extract common drivers to update function
clk: mediatek: reset: Merge and revise reset register function
clk: mediatek: reset: Revise structure to control reset register
clk: mediatek: reset: Support nonsequence base offsets of reset registers
clk: mediatek: reset: Change return type for clock reset register function
clk: mediatek: reset: Add new register reset function with device
clk: mediatek: reset: Add reset support for simple probe
dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195
dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195
dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192
clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
arm64: dts: mediatek: Add infra #reset-cells property for MT8192
arm64: dts: mediatek: Add infra #reset-cells property for MT8195
.../mediatek/mediatek,mt8192-sys-clock.yaml | 3 +
.../mediatek/mediatek,mt8195-sys-clock.yaml | 3 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +-
drivers/clk/mediatek/clk-mt2701-eth.c | 10 +-
drivers/clk/mediatek/clk-mt2701-g3d.c | 10 +-
drivers/clk/mediatek/clk-mt2701-hif.c | 10 +-
drivers/clk/mediatek/clk-mt2701.c | 22 ++-
drivers/clk/mediatek/clk-mt2712.c | 22 ++-
drivers/clk/mediatek/clk-mt7622-eth.c | 10 +-
drivers/clk/mediatek/clk-mt7622-hif.c | 12 +-
drivers/clk/mediatek/clk-mt7622.c | 22 ++-
drivers/clk/mediatek/clk-mt7629-eth.c | 10 +-
drivers/clk/mediatek/clk-mt7629-hif.c | 12 +-
drivers/clk/mediatek/clk-mt8135.c | 22 ++-
drivers/clk/mediatek/clk-mt8173.c | 22 ++-
drivers/clk/mediatek/clk-mt8183.c | 18 +-
drivers/clk/mediatek/clk-mt8192.c | 18 ++
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 15 ++
drivers/clk/mediatek/clk-mtk.c | 7 +
drivers/clk/mediatek/clk-mtk.h | 9 +-
drivers/clk/mediatek/reset.c | 172 ++++++++++++------
drivers/clk/mediatek/reset.h | 77 ++++++++
include/dt-bindings/reset/mt8192-resets.h | 163 +++++++++++++++++
include/dt-bindings/reset/mt8195-resets.h | 170 +++++++++++++++++
25 files changed, 759 insertions(+), 94 deletions(-)
create mode 100644 drivers/clk/mediatek/reset.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2022-04-28 11:56 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-28 11:56 Rex-BC Chen [this message]
2022-04-28 11:56 ` [PATCH V5 00/16] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 01/16] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 02/16] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 03/16] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 04/16] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 05/16] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 06/16] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 07/16] clk: mediatek: reset: Support nonsequence base offsets of reset registers Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:38 ` AngeloGioacchino Del Regno
2022-04-28 13:38 ` AngeloGioacchino Del Regno
2022-04-28 13:38 ` AngeloGioacchino Del Regno
2022-04-28 11:56 ` [PATCH V5 08/16] clk: mediatek: reset: Change return type for clock reset register function Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 09/16] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 10/16] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 11/16] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 12/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-29 21:13 ` Krzysztof Kozlowski
2022-04-29 21:13 ` Krzysztof Kozlowski
2022-04-29 21:13 ` Krzysztof Kozlowski
2022-05-02 8:54 ` AngeloGioacchino Del Regno
2022-05-02 8:54 ` AngeloGioacchino Del Regno
2022-05-02 8:54 ` AngeloGioacchino Del Regno
2022-05-03 2:54 ` Rex-BC Chen
2022-05-03 2:54 ` Rex-BC Chen
2022-05-03 2:54 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 13/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-29 21:14 ` Krzysztof Kozlowski
2022-04-29 21:14 ` Krzysztof Kozlowski
2022-04-29 21:14 ` Krzysztof Kozlowski
2022-04-28 11:56 ` [PATCH V5 14/16] clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 15/16] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:43 ` AngeloGioacchino Del Regno
2022-04-28 13:43 ` AngeloGioacchino Del Regno
2022-04-28 13:43 ` AngeloGioacchino Del Regno
2022-04-28 11:56 ` [PATCH V5 16/16] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:44 ` AngeloGioacchino Del Regno
2022-04-28 13:44 ` AngeloGioacchino Del Regno
2022-04-28 13:44 ` AngeloGioacchino Del Regno
2022-05-06 10:25 ` [PATCH V5 00/16] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-05-06 10:25 ` Rex-BC Chen
2022-05-06 10:25 ` Rex-BC Chen
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