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From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
	<angelogioacchino.delregno@collabora.com>,
	<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
	<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V5 01/16] clk: mediatek: reset: Add reset.h
Date: Thu, 28 Apr 2022 19:56:04 +0800	[thread overview]
Message-ID: <20220428115620.13512-2-rex-bc.chen@mediatek.com> (raw)
In-Reply-To: <20220428115620.13512-1-rex-bc.chen@mediatek.com>

Add a new file "reset.h" to place some definitions for clock reset.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mtk.h |  8 ++------
 drivers/clk/mediatek/reset.c   |  9 +--------
 drivers/clk/mediatek/reset.h   | 24 ++++++++++++++++++++++++
 3 files changed, 27 insertions(+), 14 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index bf6565aa7319..a6d0f24c62fa 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -13,6 +13,8 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#include "reset.h"
+
 #define MAX_MUX_GATE_BIT	31
 #define INVALID_MUX_GATE_BIT	(MAX_MUX_GATE_BIT + 1)
 
@@ -190,12 +192,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data);
 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 			const char *parent_name, void __iomem *reg);
 
-void mtk_register_reset_controller(struct device_node *np,
-			unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs);
-
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index bcec4b89f449..9f3cb22aea1b 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -8,16 +8,9 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
-#include <linux/reset-controller.h>
 #include <linux/slab.h>
 
-#include "clk-mtk.h"
-
-struct mtk_reset {
-	struct regmap *regmap;
-	int regofs;
-	struct reset_controller_dev rcdev;
-};
+#include "reset.h"
 
 static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
 	unsigned long id)
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
new file mode 100644
index 000000000000..764a8affe206
--- /dev/null
+++ b/drivers/clk/mediatek/reset.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_MTK_RESET_H
+#define __DRV_CLK_MTK_RESET_H
+
+#include <linux/reset-controller.h>
+#include <linux/types.h>
+
+struct mtk_reset {
+	struct regmap *regmap;
+	int regofs;
+	struct reset_controller_dev rcdev;
+};
+
+void mtk_register_reset_controller(struct device_node *np,
+				   unsigned int num_regs, int regofs);
+
+void mtk_register_reset_controller_set_clr(struct device_node *np,
+					   unsigned int num_regs, int regofs);
+
+#endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


WARNING: multiple messages have this Message-ID (diff)
From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
	<angelogioacchino.delregno@collabora.com>,
	<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
	<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	 <Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V5 01/16] clk: mediatek: reset: Add reset.h
Date: Thu, 28 Apr 2022 19:56:04 +0800	[thread overview]
Message-ID: <20220428115620.13512-2-rex-bc.chen@mediatek.com> (raw)
In-Reply-To: <20220428115620.13512-1-rex-bc.chen@mediatek.com>

Add a new file "reset.h" to place some definitions for clock reset.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mtk.h |  8 ++------
 drivers/clk/mediatek/reset.c   |  9 +--------
 drivers/clk/mediatek/reset.h   | 24 ++++++++++++++++++++++++
 3 files changed, 27 insertions(+), 14 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index bf6565aa7319..a6d0f24c62fa 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -13,6 +13,8 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#include "reset.h"
+
 #define MAX_MUX_GATE_BIT	31
 #define INVALID_MUX_GATE_BIT	(MAX_MUX_GATE_BIT + 1)
 
@@ -190,12 +192,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data);
 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 			const char *parent_name, void __iomem *reg);
 
-void mtk_register_reset_controller(struct device_node *np,
-			unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs);
-
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index bcec4b89f449..9f3cb22aea1b 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -8,16 +8,9 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
-#include <linux/reset-controller.h>
 #include <linux/slab.h>
 
-#include "clk-mtk.h"
-
-struct mtk_reset {
-	struct regmap *regmap;
-	int regofs;
-	struct reset_controller_dev rcdev;
-};
+#include "reset.h"
 
 static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
 	unsigned long id)
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
new file mode 100644
index 000000000000..764a8affe206
--- /dev/null
+++ b/drivers/clk/mediatek/reset.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_MTK_RESET_H
+#define __DRV_CLK_MTK_RESET_H
+
+#include <linux/reset-controller.h>
+#include <linux/types.h>
+
+struct mtk_reset {
+	struct regmap *regmap;
+	int regofs;
+	struct reset_controller_dev rcdev;
+};
+
+void mtk_register_reset_controller(struct device_node *np,
+				   unsigned int num_regs, int regofs);
+
+void mtk_register_reset_controller_set_clr(struct device_node *np,
+					   unsigned int num_regs, int regofs);
+
+#endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: Rex-BC Chen <rex-bc.chen@mediatek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
	<matthias.bgg@gmail.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>
Cc: <p.zabel@pengutronix.de>,
	<angelogioacchino.delregno@collabora.com>,
	<chun-jie.chen@mediatek.com>, <wenst@chromium.org>,
	<runyang.chen@mediatek.com>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-mediatek@lists.infradead.org>,
	 <Project_Global_Chrome_Upstream_Group@mediatek.com>,
	Rex-BC Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH V5 01/16] clk: mediatek: reset: Add reset.h
Date: Thu, 28 Apr 2022 19:56:04 +0800	[thread overview]
Message-ID: <20220428115620.13512-2-rex-bc.chen@mediatek.com> (raw)
In-Reply-To: <20220428115620.13512-1-rex-bc.chen@mediatek.com>

Add a new file "reset.h" to place some definitions for clock reset.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mtk.h |  8 ++------
 drivers/clk/mediatek/reset.c   |  9 +--------
 drivers/clk/mediatek/reset.h   | 24 ++++++++++++++++++++++++
 3 files changed, 27 insertions(+), 14 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index bf6565aa7319..a6d0f24c62fa 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -13,6 +13,8 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
+#include "reset.h"
+
 #define MAX_MUX_GATE_BIT	31
 #define INVALID_MUX_GATE_BIT	(MAX_MUX_GATE_BIT + 1)
 
@@ -190,12 +192,6 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data);
 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 			const char *parent_name, void __iomem *reg);
 
-void mtk_register_reset_controller(struct device_node *np,
-			unsigned int num_regs, int regofs);
-
-void mtk_register_reset_controller_set_clr(struct device_node *np,
-	unsigned int num_regs, int regofs);
-
 struct mtk_clk_desc {
 	const struct mtk_gate *clks;
 	size_t num_clks;
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index bcec4b89f449..9f3cb22aea1b 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -8,16 +8,9 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
-#include <linux/reset-controller.h>
 #include <linux/slab.h>
 
-#include "clk-mtk.h"
-
-struct mtk_reset {
-	struct regmap *regmap;
-	int regofs;
-	struct reset_controller_dev rcdev;
-};
+#include "reset.h"
 
 static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
 	unsigned long id)
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
new file mode 100644
index 000000000000..764a8affe206
--- /dev/null
+++ b/drivers/clk/mediatek/reset.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ */
+
+#ifndef __DRV_CLK_MTK_RESET_H
+#define __DRV_CLK_MTK_RESET_H
+
+#include <linux/reset-controller.h>
+#include <linux/types.h>
+
+struct mtk_reset {
+	struct regmap *regmap;
+	int regofs;
+	struct reset_controller_dev rcdev;
+};
+
+void mtk_register_reset_controller(struct device_node *np,
+				   unsigned int num_regs, int regofs);
+
+void mtk_register_reset_controller_set_clr(struct device_node *np,
+					   unsigned int num_regs, int regofs);
+
+#endif /* __DRV_CLK_MTK_RESET_H */
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-04-28 11:56 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-28 11:56 [PATCH V5 00/16] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen [this message]
2022-04-28 11:56   ` [PATCH V5 01/16] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 02/16] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 03/16] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 04/16] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 05/16] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 06/16] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 07/16] clk: mediatek: reset: Support nonsequence base offsets of reset registers Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 13:38   ` AngeloGioacchino Del Regno
2022-04-28 13:38     ` AngeloGioacchino Del Regno
2022-04-28 13:38     ` AngeloGioacchino Del Regno
2022-04-28 11:56 ` [PATCH V5 08/16] clk: mediatek: reset: Change return type for clock reset register function Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 09/16] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 10/16] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 11/16] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 12/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195 Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 13:42   ` AngeloGioacchino Del Regno
2022-04-28 13:42     ` AngeloGioacchino Del Regno
2022-04-28 13:42     ` AngeloGioacchino Del Regno
2022-04-29 21:13   ` Krzysztof Kozlowski
2022-04-29 21:13     ` Krzysztof Kozlowski
2022-04-29 21:13     ` Krzysztof Kozlowski
2022-05-02  8:54     ` AngeloGioacchino Del Regno
2022-05-02  8:54       ` AngeloGioacchino Del Regno
2022-05-02  8:54       ` AngeloGioacchino Del Regno
2022-05-03  2:54       ` Rex-BC Chen
2022-05-03  2:54         ` Rex-BC Chen
2022-05-03  2:54         ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 13/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192 Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 13:42   ` AngeloGioacchino Del Regno
2022-04-28 13:42     ` AngeloGioacchino Del Regno
2022-04-28 13:42     ` AngeloGioacchino Del Regno
2022-04-29 21:14   ` Krzysztof Kozlowski
2022-04-29 21:14     ` Krzysztof Kozlowski
2022-04-29 21:14     ` Krzysztof Kozlowski
2022-04-28 11:56 ` [PATCH V5 14/16] clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 15/16] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 13:43   ` AngeloGioacchino Del Regno
2022-04-28 13:43     ` AngeloGioacchino Del Regno
2022-04-28 13:43     ` AngeloGioacchino Del Regno
2022-04-28 11:56 ` [PATCH V5 16/16] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 11:56   ` Rex-BC Chen
2022-04-28 13:44   ` AngeloGioacchino Del Regno
2022-04-28 13:44     ` AngeloGioacchino Del Regno
2022-04-28 13:44     ` AngeloGioacchino Del Regno
2022-05-06 10:25 ` [PATCH V5 00/16] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-05-06 10:25   ` Rex-BC Chen
2022-05-06 10:25   ` Rex-BC Chen

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