From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>,
mturquette@baylibre.com, sboyd@kernel.org,
matthias.bgg@gmail.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: p.zabel@pengutronix.de, angelogioacchino.delregno@collabora.com,
chun-jie.chen@mediatek.com, wenst@chromium.org,
runyang.chen@mediatek.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH V5 12/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195
Date: Fri, 29 Apr 2022 23:13:31 +0200 [thread overview]
Message-ID: <839978c5-c337-7784-a04f-26b9883c703b@linaro.org> (raw)
In-Reply-To: <20220428115620.13512-13-rex-bc.chen@mediatek.com>
On 28/04/2022 13:56, Rex-BC Chen wrote:
> To support reset of infra_ao, add the bit definitions for MT8195.
> The infra_ao reset includes 5 banks and 32 bits for each bank.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
> include/dt-bindings/reset/mt8195-resets.h | 170 ++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..463114014483 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -7,6 +7,7 @@
> #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
> #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
>
> +/* TOPRGU resets */
> #define MT8195_TOPRGU_CONN_MCU_SW_RST 0
> #define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
> #define MT8195_TOPRGU_APU_SW_RST 2
> @@ -26,4 +27,173 @@
>
> #define MT8195_TOPRGU_SW_RST_NUM 16
>
> +/* INFRA RST0 */
> +#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
> +#define MT8195_INFRA_RST0_RSV0 1
> +#define MT8195_INFRA_RST0_DISP_PWM1_SWRST 2
> +#define MT8195_INFRA_RST0_RSV1 3
> +#define MT8195_INFRA_RST0_MSDC3_SWRST 4
> +#define MT8195_INFRA_RST0_MSDC2_SWRST 5
> +#define MT8195_INFRA_RST0_MSDC1_SWRST 6
> +#define MT8195_INFRA_RST0_MSDC0_SWRST 7
> +#define MT8195_INFRA_RST0_RSV2 8
> +#define MT8195_INFRA_RST0_AP_DMA_SWRST 9
> +#define MT8195_INFRA_RST0_MIPI_D_SWRST 10
> +#define MT8195_INFRA_RST0_RSV3 11
> +#define MT8195_INFRA_RST0_RSV4 12
> +#define MT8195_INFRA_RST0_SSUSB_TOP_SWRST 13
> +#define MT8195_INFRA_RST0_DISP_PWM_SWRST 14
> +#define MT8195_INFRA_RST0_AUXADC_SWRST 15
> +#define MT8195_INFRA_RST0_RSV5 16
> +#define MT8195_INFRA_RST0_RSV6 17
> +#define MT8195_INFRA_RST0_RSV7 18
> +#define MT8195_INFRA_RST0_RSV8 19
> +#define MT8195_INFRA_RST0_RSV9 20
> +#define MT8195_INFRA_RST0_RSV10 21
> +#define MT8195_INFRA_RST0_RSV11 22
> +#define MT8195_INFRA_RST0_RSV12 23
> +#define MT8195_INFRA_RST0_RSV13 24
> +#define MT8195_INFRA_RST0_RSV14 25
> +#define MT8195_INFRA_RST0_RSV15 26
> +#define MT8195_INFRA_RST0_RSV16 27
> +#define MT8195_INFRA_RST0_RSV17 28
> +#define MT8195_INFRA_RST0_RSV18 29
> +#define MT8195_INFRA_RST0_RSV19 30
> +#define MT8195_INFRA_RST0_RSV20 31
These are not proper IDs... don't work-around usage of bits with fake
reserved IDs...
Best regards,
Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>,
mturquette@baylibre.com, sboyd@kernel.org,
matthias.bgg@gmail.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: p.zabel@pengutronix.de, angelogioacchino.delregno@collabora.com,
chun-jie.chen@mediatek.com, wenst@chromium.org,
runyang.chen@mediatek.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH V5 12/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195
Date: Fri, 29 Apr 2022 23:13:31 +0200 [thread overview]
Message-ID: <839978c5-c337-7784-a04f-26b9883c703b@linaro.org> (raw)
In-Reply-To: <20220428115620.13512-13-rex-bc.chen@mediatek.com>
On 28/04/2022 13:56, Rex-BC Chen wrote:
> To support reset of infra_ao, add the bit definitions for MT8195.
> The infra_ao reset includes 5 banks and 32 bits for each bank.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
> include/dt-bindings/reset/mt8195-resets.h | 170 ++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..463114014483 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -7,6 +7,7 @@
> #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
> #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
>
> +/* TOPRGU resets */
> #define MT8195_TOPRGU_CONN_MCU_SW_RST 0
> #define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
> #define MT8195_TOPRGU_APU_SW_RST 2
> @@ -26,4 +27,173 @@
>
> #define MT8195_TOPRGU_SW_RST_NUM 16
>
> +/* INFRA RST0 */
> +#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
> +#define MT8195_INFRA_RST0_RSV0 1
> +#define MT8195_INFRA_RST0_DISP_PWM1_SWRST 2
> +#define MT8195_INFRA_RST0_RSV1 3
> +#define MT8195_INFRA_RST0_MSDC3_SWRST 4
> +#define MT8195_INFRA_RST0_MSDC2_SWRST 5
> +#define MT8195_INFRA_RST0_MSDC1_SWRST 6
> +#define MT8195_INFRA_RST0_MSDC0_SWRST 7
> +#define MT8195_INFRA_RST0_RSV2 8
> +#define MT8195_INFRA_RST0_AP_DMA_SWRST 9
> +#define MT8195_INFRA_RST0_MIPI_D_SWRST 10
> +#define MT8195_INFRA_RST0_RSV3 11
> +#define MT8195_INFRA_RST0_RSV4 12
> +#define MT8195_INFRA_RST0_SSUSB_TOP_SWRST 13
> +#define MT8195_INFRA_RST0_DISP_PWM_SWRST 14
> +#define MT8195_INFRA_RST0_AUXADC_SWRST 15
> +#define MT8195_INFRA_RST0_RSV5 16
> +#define MT8195_INFRA_RST0_RSV6 17
> +#define MT8195_INFRA_RST0_RSV7 18
> +#define MT8195_INFRA_RST0_RSV8 19
> +#define MT8195_INFRA_RST0_RSV9 20
> +#define MT8195_INFRA_RST0_RSV10 21
> +#define MT8195_INFRA_RST0_RSV11 22
> +#define MT8195_INFRA_RST0_RSV12 23
> +#define MT8195_INFRA_RST0_RSV13 24
> +#define MT8195_INFRA_RST0_RSV14 25
> +#define MT8195_INFRA_RST0_RSV15 26
> +#define MT8195_INFRA_RST0_RSV16 27
> +#define MT8195_INFRA_RST0_RSV17 28
> +#define MT8195_INFRA_RST0_RSV18 29
> +#define MT8195_INFRA_RST0_RSV19 30
> +#define MT8195_INFRA_RST0_RSV20 31
These are not proper IDs... don't work-around usage of bits with fake
reserved IDs...
Best regards,
Krzysztof
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Rex-BC Chen <rex-bc.chen@mediatek.com>,
mturquette@baylibre.com, sboyd@kernel.org,
matthias.bgg@gmail.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: p.zabel@pengutronix.de, angelogioacchino.delregno@collabora.com,
chun-jie.chen@mediatek.com, wenst@chromium.org,
runyang.chen@mediatek.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH V5 12/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195
Date: Fri, 29 Apr 2022 23:13:31 +0200 [thread overview]
Message-ID: <839978c5-c337-7784-a04f-26b9883c703b@linaro.org> (raw)
In-Reply-To: <20220428115620.13512-13-rex-bc.chen@mediatek.com>
On 28/04/2022 13:56, Rex-BC Chen wrote:
> To support reset of infra_ao, add the bit definitions for MT8195.
> The infra_ao reset includes 5 banks and 32 bits for each bank.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
> include/dt-bindings/reset/mt8195-resets.h | 170 ++++++++++++++++++++++
> 1 file changed, 170 insertions(+)
>
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> index a26bccc8b957..463114014483 100644
> --- a/include/dt-bindings/reset/mt8195-resets.h
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -7,6 +7,7 @@
> #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
> #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
>
> +/* TOPRGU resets */
> #define MT8195_TOPRGU_CONN_MCU_SW_RST 0
> #define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
> #define MT8195_TOPRGU_APU_SW_RST 2
> @@ -26,4 +27,173 @@
>
> #define MT8195_TOPRGU_SW_RST_NUM 16
>
> +/* INFRA RST0 */
> +#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
> +#define MT8195_INFRA_RST0_RSV0 1
> +#define MT8195_INFRA_RST0_DISP_PWM1_SWRST 2
> +#define MT8195_INFRA_RST0_RSV1 3
> +#define MT8195_INFRA_RST0_MSDC3_SWRST 4
> +#define MT8195_INFRA_RST0_MSDC2_SWRST 5
> +#define MT8195_INFRA_RST0_MSDC1_SWRST 6
> +#define MT8195_INFRA_RST0_MSDC0_SWRST 7
> +#define MT8195_INFRA_RST0_RSV2 8
> +#define MT8195_INFRA_RST0_AP_DMA_SWRST 9
> +#define MT8195_INFRA_RST0_MIPI_D_SWRST 10
> +#define MT8195_INFRA_RST0_RSV3 11
> +#define MT8195_INFRA_RST0_RSV4 12
> +#define MT8195_INFRA_RST0_SSUSB_TOP_SWRST 13
> +#define MT8195_INFRA_RST0_DISP_PWM_SWRST 14
> +#define MT8195_INFRA_RST0_AUXADC_SWRST 15
> +#define MT8195_INFRA_RST0_RSV5 16
> +#define MT8195_INFRA_RST0_RSV6 17
> +#define MT8195_INFRA_RST0_RSV7 18
> +#define MT8195_INFRA_RST0_RSV8 19
> +#define MT8195_INFRA_RST0_RSV9 20
> +#define MT8195_INFRA_RST0_RSV10 21
> +#define MT8195_INFRA_RST0_RSV11 22
> +#define MT8195_INFRA_RST0_RSV12 23
> +#define MT8195_INFRA_RST0_RSV13 24
> +#define MT8195_INFRA_RST0_RSV14 25
> +#define MT8195_INFRA_RST0_RSV15 26
> +#define MT8195_INFRA_RST0_RSV16 27
> +#define MT8195_INFRA_RST0_RSV17 28
> +#define MT8195_INFRA_RST0_RSV18 29
> +#define MT8195_INFRA_RST0_RSV19 30
> +#define MT8195_INFRA_RST0_RSV20 31
These are not proper IDs... don't work-around usage of bits with fake
reserved IDs...
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-04-29 21:13 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-28 11:56 [PATCH V5 00/16] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 01/16] clk: mediatek: reset: Add reset.h Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 02/16] clk: mediatek: reset: Fix written reset bit offset Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 03/16] clk: mediatek: reset: Refine and reorder functions in reset.c Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 04/16] clk: mediatek: reset: Extract common drivers to update function Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 05/16] clk: mediatek: reset: Merge and revise reset register function Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 06/16] clk: mediatek: reset: Revise structure to control reset register Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 07/16] clk: mediatek: reset: Support nonsequence base offsets of reset registers Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:38 ` AngeloGioacchino Del Regno
2022-04-28 13:38 ` AngeloGioacchino Del Regno
2022-04-28 13:38 ` AngeloGioacchino Del Regno
2022-04-28 11:56 ` [PATCH V5 08/16] clk: mediatek: reset: Change return type for clock reset register function Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 09/16] clk: mediatek: reset: Add new register reset function with device Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 10/16] clk: mediatek: reset: Add reset support for simple probe Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 11/16] dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 12/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-29 21:13 ` Krzysztof Kozlowski [this message]
2022-04-29 21:13 ` Krzysztof Kozlowski
2022-04-29 21:13 ` Krzysztof Kozlowski
2022-05-02 8:54 ` AngeloGioacchino Del Regno
2022-05-02 8:54 ` AngeloGioacchino Del Regno
2022-05-02 8:54 ` AngeloGioacchino Del Regno
2022-05-03 2:54 ` Rex-BC Chen
2022-05-03 2:54 ` Rex-BC Chen
2022-05-03 2:54 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 13/16] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-28 13:42 ` AngeloGioacchino Del Regno
2022-04-29 21:14 ` Krzysztof Kozlowski
2022-04-29 21:14 ` Krzysztof Kozlowski
2022-04-29 21:14 ` Krzysztof Kozlowski
2022-04-28 11:56 ` [PATCH V5 14/16] clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` [PATCH V5 15/16] arm64: dts: mediatek: Add infra #reset-cells property for MT8192 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:43 ` AngeloGioacchino Del Regno
2022-04-28 13:43 ` AngeloGioacchino Del Regno
2022-04-28 13:43 ` AngeloGioacchino Del Regno
2022-04-28 11:56 ` [PATCH V5 16/16] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 11:56 ` Rex-BC Chen
2022-04-28 13:44 ` AngeloGioacchino Del Regno
2022-04-28 13:44 ` AngeloGioacchino Del Regno
2022-04-28 13:44 ` AngeloGioacchino Del Regno
2022-05-06 10:25 ` [PATCH V5 00/16] Cleanup MediaTek clk reset drivers and support MT8192/MT8195 Rex-BC Chen
2022-05-06 10:25 ` Rex-BC Chen
2022-05-06 10:25 ` Rex-BC Chen
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