From: Andre Przywara <andre.przywara@arm.com> To: Jernej Skrabec <jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org>, Chen-Yu Tsai <wens@csie.org> Cc: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Icenowy Zheng <icenowy@aosc.io>, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, linux-clk@vger.kernel.org Subject: [PATCH v11 2/6] clk: sunxi-ng: h616: Add PLL derived 32KHz clock Date: Fri, 29 Apr 2022 00:09:29 +0100 [thread overview] Message-ID: <20220428230933.15262-3-andre.przywara@arm.com> (raw) In-Reply-To: <20220428230933.15262-1-andre.przywara@arm.com> The RTC section of the H616 manual mentions in a half-sentence the existence of a clock "32K divided by PLL_PERI(2X)". This is used as one of the possible inputs for the mux that selects the clock for the 32 KHz fanout pad. On the H616 this is routed to pin PG10, and some boards use that clock output to compensate for a missing 32KHz crystal. On the OrangePi Zero2 this is for instance connected to the LPO pin of the WiFi/BT chip. The new RTC clock binding requires this clock to be named as one input clock, so we need to expose this to the DT. In contrast to the D1 SoC there does not seem to be a gate for this clock, so just use a fixed divider clock, using a newly assigned clock number. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> --- drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 8 ++++++++ drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 2 +- include/dt-bindings/clock/sun50i-h616-ccu.h | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c index 49a2474cf314..21e918582aa5 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c @@ -704,6 +704,13 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x", pll_periph0_parents, 1, 2, 0); +static const struct clk_hw *pll_periph0_2x_hws[] = { + &pll_periph0_2x_clk.hw +}; + +static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k", + pll_periph0_2x_hws, 36621, 1, 0); + static const struct clk_hw *pll_periph1_parents[] = { &pll_periph1_clk.common.hw }; @@ -852,6 +859,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = { [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, + [CLK_PLL_SYSTEM_32K] = &pll_system_32k_clk.hw, [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h index dd671b413f22..fdd2f4d5103f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h @@ -51,6 +51,6 @@ #define CLK_BUS_DRAM 56 -#define CLK_NUMBER (CLK_BUS_HDCP + 1) +#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1) #endif /* _CCU_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 4fc08b0df2f3..1191aca53ac6 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -111,5 +111,6 @@ #define CLK_BUS_TVE0 125 #define CLK_HDCP 126 #define CLK_BUS_HDCP 127 +#define CLK_PLL_SYSTEM_32K 128 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ -- 2.35.3
WARNING: multiple messages have this Message-ID (diff)
From: Andre Przywara <andre.przywara@arm.com> To: Jernej Skrabec <jernej.skrabec@gmail.com>, Samuel Holland <samuel@sholland.org>, Chen-Yu Tsai <wens@csie.org> Cc: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Icenowy Zheng <icenowy@aosc.io>, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, linux-clk@vger.kernel.org Subject: [PATCH v11 2/6] clk: sunxi-ng: h616: Add PLL derived 32KHz clock Date: Fri, 29 Apr 2022 00:09:29 +0100 [thread overview] Message-ID: <20220428230933.15262-3-andre.przywara@arm.com> (raw) In-Reply-To: <20220428230933.15262-1-andre.przywara@arm.com> The RTC section of the H616 manual mentions in a half-sentence the existence of a clock "32K divided by PLL_PERI(2X)". This is used as one of the possible inputs for the mux that selects the clock for the 32 KHz fanout pad. On the H616 this is routed to pin PG10, and some boards use that clock output to compensate for a missing 32KHz crystal. On the OrangePi Zero2 this is for instance connected to the LPO pin of the WiFi/BT chip. The new RTC clock binding requires this clock to be named as one input clock, so we need to expose this to the DT. In contrast to the D1 SoC there does not seem to be a gate for this clock, so just use a fixed divider clock, using a newly assigned clock number. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> --- drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 8 ++++++++ drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 2 +- include/dt-bindings/clock/sun50i-h616-ccu.h | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c index 49a2474cf314..21e918582aa5 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c @@ -704,6 +704,13 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x", pll_periph0_parents, 1, 2, 0); +static const struct clk_hw *pll_periph0_2x_hws[] = { + &pll_periph0_2x_clk.hw +}; + +static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k", + pll_periph0_2x_hws, 36621, 1, 0); + static const struct clk_hw *pll_periph1_parents[] = { &pll_periph1_clk.common.hw }; @@ -852,6 +859,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = { [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, + [CLK_PLL_SYSTEM_32K] = &pll_system_32k_clk.hw, [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h index dd671b413f22..fdd2f4d5103f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h @@ -51,6 +51,6 @@ #define CLK_BUS_DRAM 56 -#define CLK_NUMBER (CLK_BUS_HDCP + 1) +#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1) #endif /* _CCU_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 4fc08b0df2f3..1191aca53ac6 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -111,5 +111,6 @@ #define CLK_BUS_TVE0 125 #define CLK_HDCP 126 #define CLK_BUS_HDCP 127 +#define CLK_PLL_SYSTEM_32K 128 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ -- 2.35.3 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-04-28 23:09 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-28 23:09 [PATCH v11 0/6] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-04-28 23:09 ` [PATCH v11 1/6] clk: sunxi-ng: h6-r: Add RTC gate clock Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-05-03 2:06 ` Samuel Holland 2022-05-03 2:06 ` Samuel Holland 2022-05-06 16:10 ` Jernej Škrabec 2022-05-06 16:10 ` Jernej Škrabec 2022-04-28 23:09 ` Andre Przywara [this message] 2022-04-28 23:09 ` [PATCH v11 2/6] clk: sunxi-ng: h616: Add PLL derived 32KHz clock Andre Przywara 2022-05-06 16:11 ` Jernej Škrabec 2022-05-06 16:11 ` Jernej Škrabec 2022-04-28 23:09 ` [PATCH v11 3/6] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-05-03 19:05 ` Jernej Škrabec 2022-05-03 19:05 ` Jernej Škrabec 2022-05-03 19:41 ` Jernej Škrabec 2022-05-03 19:41 ` Jernej Škrabec 2022-06-30 0:04 ` Andre Przywara 2022-06-30 0:04 ` Andre Przywara 2022-07-02 21:16 ` Jernej Škrabec 2022-07-02 21:16 ` Jernej Škrabec 2022-07-04 13:30 ` Andre Przywara 2022-07-04 13:30 ` Andre Przywara 2022-07-04 18:42 ` Jernej Škrabec 2022-07-04 18:42 ` Jernej Škrabec 2022-07-04 21:58 ` Andre Przywara 2022-07-04 21:58 ` Andre Przywara 2022-07-05 17:32 ` Jernej Škrabec 2022-07-05 17:32 ` Jernej Škrabec 2022-07-06 13:16 ` Andre Przywara 2022-07-06 13:16 ` Andre Przywara 2022-07-07 6:30 ` Samuel Holland 2022-07-07 6:30 ` Samuel Holland 2022-07-07 16:39 ` Jernej Škrabec 2022-07-07 16:39 ` Jernej Škrabec 2022-07-08 9:47 ` Andre Przywara 2022-07-08 9:47 ` Andre Przywara 2022-07-04 18:44 ` Samuel Holland 2022-07-04 18:44 ` Samuel Holland 2022-07-04 20:52 ` Andre Przywara 2022-07-04 20:52 ` Andre Przywara 2022-04-28 23:09 ` [PATCH v11 4/6] dt-bindings: arm: sunxi: Add two H616 board compatible strings Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-04-28 23:09 ` [PATCH v11 5/6] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-05-03 19:41 ` Jernej Škrabec 2022-05-03 19:41 ` Jernej Škrabec 2022-06-30 0:08 ` Andre Przywara 2022-06-30 0:08 ` Andre Przywara 2022-04-28 23:09 ` [PATCH v11 6/6] arm64: dts: allwinner: h616: Add X96 Mate TV box support Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-05-03 19:44 ` Jernej Škrabec 2022-05-03 19:44 ` Jernej Škrabec
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20220428230933.15262-3-andre.przywara@arm.com \ --to=andre.przywara@arm.com \ --cc=devicetree@vger.kernel.org \ --cc=icenowy@aosc.io \ --cc=jernej.skrabec@gmail.com \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-sunxi@lists.linux.dev \ --cc=mturquette@baylibre.com \ --cc=robh@kernel.org \ --cc=samuel@sholland.org \ --cc=sboyd@kernel.org \ --cc=wens@csie.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.