From: Samuel Holland <samuel@sholland.org> To: Andre Przywara <andre.przywara@arm.com>, Jernej Skrabec <jernej.skrabec@gmail.com>, Chen-Yu Tsai <wens@csie.org> Cc: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Icenowy Zheng <icenowy@aosc.io>, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, linux-clk@vger.kernel.org Subject: Re: [PATCH v11 1/6] clk: sunxi-ng: h6-r: Add RTC gate clock Date: Mon, 2 May 2022 21:06:59 -0500 [thread overview] Message-ID: <875fc3d6-fb45-903c-e52e-4abf43b46db2@sholland.org> (raw) In-Reply-To: <20220428230933.15262-2-andre.przywara@arm.com> On 4/28/22 6:09 PM, Andre Przywara wrote: > The H6 and H616 feature an (undocumented) bus clock gate for accessing > the RTC registers. This seems to be enabled at reset (or by the BootROM), > so we got away without it so far, but exists regardless. > Since the new RTC clock binding for the H616 requires this "bus" clock > to be specified in the DT, add this to R_CCU clock driver and expose it > on the DT side with a new number. > We do this for both the H6 and H616, but mark it as IGNORE_UNUSED, as we > cannot reference it in any H6 DTs. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> One tiny nit below, if you resend. > --- > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 5 +++++ > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 2 +- > include/dt-bindings/clock/sun50i-h6-r-ccu.h | 1 + > 3 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > index 712e103382d8..88509339031e 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > @@ -98,6 +98,8 @@ static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1", > 0x1cc, BIT(0), 0); > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1", > 0x1ec, BIT(0), 0); > +static SUNXI_CCU_GATE(r_apb1_rtc_clk, "r-apb1-rtc", "r-apb1", > + 0x20c, BIT(0), CLK_IGNORE_UNUSED); > > /* Information of IR(RX) mod clock is gathered from BSP source code */ > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; > @@ -147,6 +149,7 @@ static struct ccu_common *sun50i_h616_r_ccu_clks[] = { > &r_apb2_i2c_clk.common, > &r_apb2_rsb_clk.common, > &r_apb1_ir_clk.common, > + &r_apb1_rtc_clk.common, > &ir_clk.common, > }; > > @@ -163,6 +166,7 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { > [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, > [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw, > [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, > + [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw, > [CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw, The new clock should go after CLK_R_APB1_W1 to match the ordering above. > [CLK_IR] = &ir_clk.common.hw, > [CLK_W1] = &w1_clk.common.hw, > @@ -179,6 +183,7 @@ static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { > [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, > [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw, > [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, > + [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw, > [CLK_IR] = &ir_clk.common.hw, > }, > .num = CLK_NUMBER, > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h > index 7e290b840803..10e9b66afc6a 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h > @@ -14,6 +14,6 @@ > > #define CLK_R_APB2 3 > > -#define CLK_NUMBER (CLK_R_APB2_RSB + 1) > +#define CLK_NUMBER (CLK_R_APB1_RTC + 1) > > #endif /* _CCU_SUN50I_H6_R_H */ > diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h > index 890368d252c4..a96087abc86f 100644 > --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h > +++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h > @@ -22,5 +22,6 @@ > #define CLK_W1 12 > > #define CLK_R_APB2_RSB 13 > +#define CLK_R_APB1_RTC 14 > > #endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ >
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel@sholland.org> To: Andre Przywara <andre.przywara@arm.com>, Jernej Skrabec <jernej.skrabec@gmail.com>, Chen-Yu Tsai <wens@csie.org> Cc: Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Icenowy Zheng <icenowy@aosc.io>, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, linux-clk@vger.kernel.org Subject: Re: [PATCH v11 1/6] clk: sunxi-ng: h6-r: Add RTC gate clock Date: Mon, 2 May 2022 21:06:59 -0500 [thread overview] Message-ID: <875fc3d6-fb45-903c-e52e-4abf43b46db2@sholland.org> (raw) In-Reply-To: <20220428230933.15262-2-andre.przywara@arm.com> On 4/28/22 6:09 PM, Andre Przywara wrote: > The H6 and H616 feature an (undocumented) bus clock gate for accessing > the RTC registers. This seems to be enabled at reset (or by the BootROM), > so we got away without it so far, but exists regardless. > Since the new RTC clock binding for the H616 requires this "bus" clock > to be specified in the DT, add this to R_CCU clock driver and expose it > on the DT side with a new number. > We do this for both the H6 and H616, but mark it as IGNORE_UNUSED, as we > cannot reference it in any H6 DTs. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> One tiny nit below, if you resend. > --- > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 5 +++++ > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 2 +- > include/dt-bindings/clock/sun50i-h6-r-ccu.h | 1 + > 3 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > index 712e103382d8..88509339031e 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c > @@ -98,6 +98,8 @@ static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1", > 0x1cc, BIT(0), 0); > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1", > 0x1ec, BIT(0), 0); > +static SUNXI_CCU_GATE(r_apb1_rtc_clk, "r-apb1-rtc", "r-apb1", > + 0x20c, BIT(0), CLK_IGNORE_UNUSED); > > /* Information of IR(RX) mod clock is gathered from BSP source code */ > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; > @@ -147,6 +149,7 @@ static struct ccu_common *sun50i_h616_r_ccu_clks[] = { > &r_apb2_i2c_clk.common, > &r_apb2_rsb_clk.common, > &r_apb1_ir_clk.common, > + &r_apb1_rtc_clk.common, > &ir_clk.common, > }; > > @@ -163,6 +166,7 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = { > [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, > [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw, > [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, > + [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw, > [CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw, The new clock should go after CLK_R_APB1_W1 to match the ordering above. > [CLK_IR] = &ir_clk.common.hw, > [CLK_W1] = &w1_clk.common.hw, > @@ -179,6 +183,7 @@ static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = { > [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw, > [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw, > [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw, > + [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw, > [CLK_IR] = &ir_clk.common.hw, > }, > .num = CLK_NUMBER, > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h > index 7e290b840803..10e9b66afc6a 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h > @@ -14,6 +14,6 @@ > > #define CLK_R_APB2 3 > > -#define CLK_NUMBER (CLK_R_APB2_RSB + 1) > +#define CLK_NUMBER (CLK_R_APB1_RTC + 1) > > #endif /* _CCU_SUN50I_H6_R_H */ > diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h > index 890368d252c4..a96087abc86f 100644 > --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h > +++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h > @@ -22,5 +22,6 @@ > #define CLK_W1 12 > > #define CLK_R_APB2_RSB 13 > +#define CLK_R_APB1_RTC 14 > > #endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-03 2:07 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-28 23:09 [PATCH v11 0/6] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-04-28 23:09 ` [PATCH v11 1/6] clk: sunxi-ng: h6-r: Add RTC gate clock Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-05-03 2:06 ` Samuel Holland [this message] 2022-05-03 2:06 ` Samuel Holland 2022-05-06 16:10 ` Jernej Škrabec 2022-05-06 16:10 ` Jernej Škrabec 2022-04-28 23:09 ` [PATCH v11 2/6] clk: sunxi-ng: h616: Add PLL derived 32KHz clock Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-05-06 16:11 ` Jernej Škrabec 2022-05-06 16:11 ` Jernej Škrabec 2022-04-28 23:09 ` [PATCH v11 3/6] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-05-03 19:05 ` Jernej Škrabec 2022-05-03 19:05 ` Jernej Škrabec 2022-05-03 19:41 ` Jernej Škrabec 2022-05-03 19:41 ` Jernej Škrabec 2022-06-30 0:04 ` Andre Przywara 2022-06-30 0:04 ` Andre Przywara 2022-07-02 21:16 ` Jernej Škrabec 2022-07-02 21:16 ` Jernej Škrabec 2022-07-04 13:30 ` Andre Przywara 2022-07-04 13:30 ` Andre Przywara 2022-07-04 18:42 ` Jernej Škrabec 2022-07-04 18:42 ` Jernej Škrabec 2022-07-04 21:58 ` Andre Przywara 2022-07-04 21:58 ` Andre Przywara 2022-07-05 17:32 ` Jernej Škrabec 2022-07-05 17:32 ` Jernej Škrabec 2022-07-06 13:16 ` Andre Przywara 2022-07-06 13:16 ` Andre Przywara 2022-07-07 6:30 ` Samuel Holland 2022-07-07 6:30 ` Samuel Holland 2022-07-07 16:39 ` Jernej Škrabec 2022-07-07 16:39 ` Jernej Škrabec 2022-07-08 9:47 ` Andre Przywara 2022-07-08 9:47 ` Andre Przywara 2022-07-04 18:44 ` Samuel Holland 2022-07-04 18:44 ` Samuel Holland 2022-07-04 20:52 ` Andre Przywara 2022-07-04 20:52 ` Andre Przywara 2022-04-28 23:09 ` [PATCH v11 4/6] dt-bindings: arm: sunxi: Add two H616 board compatible strings Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-04-28 23:09 ` [PATCH v11 5/6] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-05-03 19:41 ` Jernej Škrabec 2022-05-03 19:41 ` Jernej Škrabec 2022-06-30 0:08 ` Andre Przywara 2022-06-30 0:08 ` Andre Przywara 2022-04-28 23:09 ` [PATCH v11 6/6] arm64: dts: allwinner: h616: Add X96 Mate TV box support Andre Przywara 2022-04-28 23:09 ` Andre Przywara 2022-05-03 19:44 ` Jernej Škrabec 2022-05-03 19:44 ` Jernej Škrabec
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