* [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
Cpufreq is a DVFS driver used for power saving to scale the clock frequency
and supply the voltage for CPUs. This series do some cleanup for MediaTek
cpufreq drivers and add support for MediaTek SVS[2] and MediaTek CCI
devfreq[3] which are supported in MT8183 and MT8186.
Changes for v6:
1. Reorder patches in this series.
2. Add a new patch to do unregister platform device.
3. Modify drivers from maintainer's advice.
Changes for v5:
1. Modify the description for the reason we need to use mediatek,cci.
2. Drop [07/14] cpufreq: mediatek: Add .get function.
Changes for V4:
1. Revise drivers from reviewers' suggestion.
2. Fix name of opp table issue.
Changes for V3:
1. Rebased to linux-next-20220414.
2. Drop accepted patches.
3. Drop "cpufreq: mediatek: Use maximum voltage in init stage" because we
make sure the voltage we set is safe for both mediatek cci and cpufreq.
4. Rename cci property to mediatek,cci.
5. Adjust order of cleanup patches.
6. Add new patches for cleanup, handle infinite loop and MT8183 dts.
7. Revise drivers from reviewers' suggestion.
8. Revise commit message of some patches to avoid confusion and misunderstand.
9. Revise "cpufreq: mediatek: Link CCI device to CPU".
We do not return successful to pretend we set the target frequency done
when cci is not ready. Instead, we find and set a safe voltage so that we
can set the target cpufrequency.
Changes for V2:
1. Drop the modification of transforming cpufreq-mediatek into yaml and
only add the MediaTek CCI property for MediaTek cpufreq.
2. Split the original patches into several patches.
Reference series:
[1]: V1 of this series is present by Jia-Wei Chang.
https://lore.kernel.org/all/20220307122151.11666-1-jia-wei.chang@mediatek.com/
[2]: The MediaTek CCI devfreq driver is introduced in another series.
https://lore.kernel.org/all/20220425125546.4129-1-johnson.wang@mediatek.com/
[3]: The MediaTek SVS driver is introduced in another series.
https://lore.kernel.org/all/20220420102044.10832-1-roger.lu@mediatek.com/
Jia-Wei Chang (2):
cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()
cpufreq: mediatek: Add support for MT8186
Rex-BC Chen (8):
dt-bindings: cpufreq: mediatek: Add MediaTek CCI property
cpufreq: mediatek: Add platform_device_unregister when driver exit
cpufreq: mediatek: Move voltage limits to platform data
cpufreq: mediatek: Add opp notification support
cpufreq: mediatek: Link CCI device to CPU
arm64: dts: mediatek: Add opp table and clock property for MT8183
cpufreq
arm64: dts: mediatek: Add MediaTek CCI node for MT8183
arm64: dts: mediatek: Add mediatek,cci property for MT8183 cpufreq
.../bindings/cpufreq/cpufreq-mediatek.txt | 7 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++
.../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 285 +++++++++++++
drivers/cpufreq/mediatek-cpufreq.c | 400 ++++++++++++------
5 files changed, 609 insertions(+), 123 deletions(-)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread* [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
Cpufreq is a DVFS driver used for power saving to scale the clock frequency
and supply the voltage for CPUs. This series do some cleanup for MediaTek
cpufreq drivers and add support for MediaTek SVS[2] and MediaTek CCI
devfreq[3] which are supported in MT8183 and MT8186.
Changes for v6:
1. Reorder patches in this series.
2. Add a new patch to do unregister platform device.
3. Modify drivers from maintainer's advice.
Changes for v5:
1. Modify the description for the reason we need to use mediatek,cci.
2. Drop [07/14] cpufreq: mediatek: Add .get function.
Changes for V4:
1. Revise drivers from reviewers' suggestion.
2. Fix name of opp table issue.
Changes for V3:
1. Rebased to linux-next-20220414.
2. Drop accepted patches.
3. Drop "cpufreq: mediatek: Use maximum voltage in init stage" because we
make sure the voltage we set is safe for both mediatek cci and cpufreq.
4. Rename cci property to mediatek,cci.
5. Adjust order of cleanup patches.
6. Add new patches for cleanup, handle infinite loop and MT8183 dts.
7. Revise drivers from reviewers' suggestion.
8. Revise commit message of some patches to avoid confusion and misunderstand.
9. Revise "cpufreq: mediatek: Link CCI device to CPU".
We do not return successful to pretend we set the target frequency done
when cci is not ready. Instead, we find and set a safe voltage so that we
can set the target cpufrequency.
Changes for V2:
1. Drop the modification of transforming cpufreq-mediatek into yaml and
only add the MediaTek CCI property for MediaTek cpufreq.
2. Split the original patches into several patches.
Reference series:
[1]: V1 of this series is present by Jia-Wei Chang.
https://lore.kernel.org/all/20220307122151.11666-1-jia-wei.chang@mediatek.com/
[2]: The MediaTek CCI devfreq driver is introduced in another series.
https://lore.kernel.org/all/20220425125546.4129-1-johnson.wang@mediatek.com/
[3]: The MediaTek SVS driver is introduced in another series.
https://lore.kernel.org/all/20220420102044.10832-1-roger.lu@mediatek.com/
Jia-Wei Chang (2):
cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()
cpufreq: mediatek: Add support for MT8186
Rex-BC Chen (8):
dt-bindings: cpufreq: mediatek: Add MediaTek CCI property
cpufreq: mediatek: Add platform_device_unregister when driver exit
cpufreq: mediatek: Move voltage limits to platform data
cpufreq: mediatek: Add opp notification support
cpufreq: mediatek: Link CCI device to CPU
arm64: dts: mediatek: Add opp table and clock property for MT8183
cpufreq
arm64: dts: mediatek: Add MediaTek CCI node for MT8183
arm64: dts: mediatek: Add mediatek,cci property for MT8183 cpufreq
.../bindings/cpufreq/cpufreq-mediatek.txt | 7 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++
.../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 285 +++++++++++++
drivers/cpufreq/mediatek-cpufreq.c | 400 ++++++++++++------
5 files changed, 609 insertions(+), 123 deletions(-)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread* [PATCH v6 01/10] dt-bindings: cpufreq: mediatek: Add MediaTek CCI property
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module
for scaling clock frequency and adjust voltage.
The phandle could be linked between CPU and MediaTek CCI for some
MediaTek SoCs, like MT8183 and MT8186.
The reason we need the link status between cpufreq and MediaTek cci is
cpufreq and mediatek cci could share the same regulator in some MediaTek
SoCs. Therefore, to prevent the issue of high frequency and low voltage,
we need to use this to make sure mediatek cci is ready.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
index b8233ec91d3d..e0a4ba599abc 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
@@ -20,6 +20,13 @@ Optional properties:
Vsram to fit SoC specific needs. When absent, the voltage scaling
flow is handled by hardware, hence no software "voltage tracking" is
needed.
+- mediatek,cci:
+ Used to confirm the link status between cpufreq and mediatek cci. Because
+ cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
+ To prevent the issue of high frequency and low voltage, we need to use this
+ property to make sure mediatek cci is ready.
+ For details of mediatek cci, please refer to
+ Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
- #cooling-cells:
For details, please refer to
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH v6 01/10] dt-bindings: cpufreq: mediatek: Add MediaTek CCI property
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module
for scaling clock frequency and adjust voltage.
The phandle could be linked between CPU and MediaTek CCI for some
MediaTek SoCs, like MT8183 and MT8186.
The reason we need the link status between cpufreq and MediaTek cci is
cpufreq and mediatek cci could share the same regulator in some MediaTek
SoCs. Therefore, to prevent the issue of high frequency and low voltage,
we need to use this to make sure mediatek cci is ready.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
index b8233ec91d3d..e0a4ba599abc 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
@@ -20,6 +20,13 @@ Optional properties:
Vsram to fit SoC specific needs. When absent, the voltage scaling
flow is handled by hardware, hence no software "voltage tracking" is
needed.
+- mediatek,cci:
+ Used to confirm the link status between cpufreq and mediatek cci. Because
+ cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
+ To prevent the issue of high frequency and low voltage, we need to use this
+ property to make sure mediatek cci is ready.
+ For details of mediatek cci, please refer to
+ Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
- #cooling-cells:
For details, please refer to
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH v6 01/10] dt-bindings: cpufreq: mediatek: Add MediaTek CCI property
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module
for scaling clock frequency and adjust voltage.
The phandle could be linked between CPU and MediaTek CCI for some
MediaTek SoCs, like MT8183 and MT8186.
The reason we need the link status between cpufreq and MediaTek cci is
cpufreq and mediatek cci could share the same regulator in some MediaTek
SoCs. Therefore, to prevent the issue of high frequency and low voltage,
we need to use this to make sure mediatek cci is ready.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
index b8233ec91d3d..e0a4ba599abc 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
@@ -20,6 +20,13 @@ Optional properties:
Vsram to fit SoC specific needs. When absent, the voltage scaling
flow is handled by hardware, hence no software "voltage tracking" is
needed.
+- mediatek,cci:
+ Used to confirm the link status between cpufreq and mediatek cci. Because
+ cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
+ To prevent the issue of high frequency and low voltage, we need to use this
+ property to make sure mediatek cci is ready.
+ For details of mediatek cci, please refer to
+ Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
- #cooling-cells:
For details, please refer to
Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread
* Re: [PATCH v6 01/10] dt-bindings: cpufreq: mediatek: Add MediaTek CCI property
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-11 14:37 ` Rob Herring
-1 siblings, 0 replies; 96+ messages in thread
From: Rob Herring @ 2022-05-11 14:37 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, roger.lu, krzk+dt, robh+dt, hsinyi,
angelogioacchino.delregno, linux-arm-kernel, linux-kernel,
matthias.bgg, devicetree, linux-mediatek, khilman, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, linux-pm, viresh.kumar
On Thu, 05 May 2022 19:52:17 +0800, Rex-BC Chen wrote:
> MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module
> for scaling clock frequency and adjust voltage.
> The phandle could be linked between CPU and MediaTek CCI for some
> MediaTek SoCs, like MT8183 and MT8186.
>
> The reason we need the link status between cpufreq and MediaTek cci is
> cpufreq and mediatek cci could share the same regulator in some MediaTek
> SoCs. Therefore, to prevent the issue of high frequency and low voltage,
> we need to use this to make sure mediatek cci is ready.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 01/10] dt-bindings: cpufreq: mediatek: Add MediaTek CCI property
@ 2022-05-11 14:37 ` Rob Herring
0 siblings, 0 replies; 96+ messages in thread
From: Rob Herring @ 2022-05-11 14:37 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, roger.lu, krzk+dt, robh+dt, hsinyi,
angelogioacchino.delregno, linux-arm-kernel, linux-kernel,
matthias.bgg, devicetree, linux-mediatek, khilman, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, linux-pm, viresh.kumar
On Thu, 05 May 2022 19:52:17 +0800, Rex-BC Chen wrote:
> MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module
> for scaling clock frequency and adjust voltage.
> The phandle could be linked between CPU and MediaTek CCI for some
> MediaTek SoCs, like MT8183 and MT8186.
>
> The reason we need the link status between cpufreq and MediaTek cci is
> cpufreq and mediatek cci could share the same regulator in some MediaTek
> SoCs. Therefore, to prevent the issue of high frequency and low voltage,
> we need to use this to make sure mediatek cci is ready.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 01/10] dt-bindings: cpufreq: mediatek: Add MediaTek CCI property
@ 2022-05-11 14:37 ` Rob Herring
0 siblings, 0 replies; 96+ messages in thread
From: Rob Herring @ 2022-05-11 14:37 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, roger.lu, krzk+dt, robh+dt, hsinyi,
angelogioacchino.delregno, linux-arm-kernel, linux-kernel,
matthias.bgg, devicetree, linux-mediatek, khilman, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, linux-pm, viresh.kumar
On Thu, 05 May 2022 19:52:17 +0800, Rex-BC Chen wrote:
> MediaTek Cache Coherent Interconnect (CCI) uses software devfreq module
> for scaling clock frequency and adjust voltage.
> The phandle could be linked between CPU and MediaTek CCI for some
> MediaTek SoCs, like MT8183 and MT8186.
>
> The reason we need the link status between cpufreq and MediaTek cci is
> cpufreq and mediatek cci could share the same regulator in some MediaTek
> SoCs. Therefore, to prevent the issue of high frequency and low voltage,
> we need to use this to make sure mediatek cci is ready.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
We register the platform device when driver inits. However, we do not
unregister it when driver exits.
To resolve this, we declare the platform data to be a global static
variable and rename it to be "cpufreq_pdev".
With this global variable, we can do platform_device_unregister() when
driver exits.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 901042e9a240..d15cbef4a72e 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -43,6 +43,8 @@ struct mtk_cpu_dvfs_info {
int pre_vproc;
};
+static struct platform_device *cpufreq_pdev;
+
static LIST_HEAD(dvfs_info_list);
static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
@@ -578,7 +580,6 @@ static int __init mtk_cpufreq_driver_init(void)
{
struct device_node *np;
const struct of_device_id *match;
- struct platform_device *pdev;
int err;
np = of_find_node_by_path("/");
@@ -602,11 +603,11 @@ static int __init mtk_cpufreq_driver_init(void)
* and the device registration codes are put here to handle defer
* probing.
*/
- pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
- if (IS_ERR(pdev)) {
+ cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
+ if (IS_ERR(cpufreq_pdev)) {
pr_err("failed to register mtk-cpufreq platform device\n");
platform_driver_unregister(&mtk_cpufreq_platdrv);
- return PTR_ERR(pdev);
+ return PTR_ERR(cpufreq_pdev);
}
return 0;
@@ -615,6 +616,7 @@ module_init(mtk_cpufreq_driver_init)
static void __exit mtk_cpufreq_driver_exit(void)
{
+ platform_device_unregister(cpufreq_pdev);
platform_driver_unregister(&mtk_cpufreq_platdrv);
}
module_exit(mtk_cpufreq_driver_exit)
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
We register the platform device when driver inits. However, we do not
unregister it when driver exits.
To resolve this, we declare the platform data to be a global static
variable and rename it to be "cpufreq_pdev".
With this global variable, we can do platform_device_unregister() when
driver exits.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 901042e9a240..d15cbef4a72e 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -43,6 +43,8 @@ struct mtk_cpu_dvfs_info {
int pre_vproc;
};
+static struct platform_device *cpufreq_pdev;
+
static LIST_HEAD(dvfs_info_list);
static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
@@ -578,7 +580,6 @@ static int __init mtk_cpufreq_driver_init(void)
{
struct device_node *np;
const struct of_device_id *match;
- struct platform_device *pdev;
int err;
np = of_find_node_by_path("/");
@@ -602,11 +603,11 @@ static int __init mtk_cpufreq_driver_init(void)
* and the device registration codes are put here to handle defer
* probing.
*/
- pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
- if (IS_ERR(pdev)) {
+ cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
+ if (IS_ERR(cpufreq_pdev)) {
pr_err("failed to register mtk-cpufreq platform device\n");
platform_driver_unregister(&mtk_cpufreq_platdrv);
- return PTR_ERR(pdev);
+ return PTR_ERR(cpufreq_pdev);
}
return 0;
@@ -615,6 +616,7 @@ module_init(mtk_cpufreq_driver_init)
static void __exit mtk_cpufreq_driver_exit(void)
{
+ platform_device_unregister(cpufreq_pdev);
platform_driver_unregister(&mtk_cpufreq_platdrv);
}
module_exit(mtk_cpufreq_driver_exit)
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
We register the platform device when driver inits. However, we do not
unregister it when driver exits.
To resolve this, we declare the platform data to be a global static
variable and rename it to be "cpufreq_pdev".
With this global variable, we can do platform_device_unregister() when
driver exits.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 901042e9a240..d15cbef4a72e 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -43,6 +43,8 @@ struct mtk_cpu_dvfs_info {
int pre_vproc;
};
+static struct platform_device *cpufreq_pdev;
+
static LIST_HEAD(dvfs_info_list);
static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
@@ -578,7 +580,6 @@ static int __init mtk_cpufreq_driver_init(void)
{
struct device_node *np;
const struct of_device_id *match;
- struct platform_device *pdev;
int err;
np = of_find_node_by_path("/");
@@ -602,11 +603,11 @@ static int __init mtk_cpufreq_driver_init(void)
* and the device registration codes are put here to handle defer
* probing.
*/
- pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
- if (IS_ERR(pdev)) {
+ cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
+ if (IS_ERR(cpufreq_pdev)) {
pr_err("failed to register mtk-cpufreq platform device\n");
platform_driver_unregister(&mtk_cpufreq_platdrv);
- return PTR_ERR(pdev);
+ return PTR_ERR(cpufreq_pdev);
}
return 0;
@@ -615,6 +616,7 @@ module_init(mtk_cpufreq_driver_init)
static void __exit mtk_cpufreq_driver_exit(void)
{
+ platform_device_unregister(cpufreq_pdev);
platform_driver_unregister(&mtk_cpufreq_platdrv);
}
module_exit(mtk_cpufreq_driver_exit)
--
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread* Re: [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 15:04 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 96+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-05-05 15:04 UTC (permalink / raw)
To: Rex-BC Chen, rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
Il 05/05/22 13:52, Rex-BC Chen ha scritto:
> We register the platform device when driver inits. However, we do not
> unregister it when driver exits.
> To resolve this, we declare the platform data to be a global static
> variable and rename it to be "cpufreq_pdev".
> With this global variable, we can do platform_device_unregister() when
> driver exits.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Hello Rex,
this commit needs a Fixes: tag.
Cheers,
Angelo
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
@ 2022-05-05 15:04 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 96+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-05-05 15:04 UTC (permalink / raw)
To: Rex-BC Chen, rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
Il 05/05/22 13:52, Rex-BC Chen ha scritto:
> We register the platform device when driver inits. However, we do not
> unregister it when driver exits.
> To resolve this, we declare the platform data to be a global static
> variable and rename it to be "cpufreq_pdev".
> With this global variable, we can do platform_device_unregister() when
> driver exits.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Hello Rex,
this commit needs a Fixes: tag.
Cheers,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
@ 2022-05-05 15:04 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 96+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-05-05 15:04 UTC (permalink / raw)
To: Rex-BC Chen, rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
Il 05/05/22 13:52, Rex-BC Chen ha scritto:
> We register the platform device when driver inits. However, we do not
> unregister it when driver exits.
> To resolve this, we declare the platform data to be a global static
> variable and rename it to be "cpufreq_pdev".
> With this global variable, we can do platform_device_unregister() when
> driver exits.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Hello Rex,
this commit needs a Fixes: tag.
Cheers,
Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
2022-05-05 15:04 ` AngeloGioacchino Del Regno
(?)
@ 2022-05-06 1:49 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 1:49 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, rafael, viresh.kumar, robh+dt,
krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-05 at 17:04 +0200, AngeloGioacchino Del Regno wrote:
> Il 05/05/22 13:52, Rex-BC Chen ha scritto:
> > We register the platform device when driver inits. However, we do
> > not
> > unregister it when driver exits.
> > To resolve this, we declare the platform data to be a global static
> > variable and rename it to be "cpufreq_pdev".
> > With this global variable, we can do platform_device_unregister()
> > when
> > driver exits.
> >
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>
> Hello Rex,
> this commit needs a Fixes: tag.
>
> Cheers,
> Angelo
>
Hello Angelo,
Thanks for the reminder.
I will add "Fixes: 501c574f4e3a ("cpufreq: mediatek: Add support of
cpufreq to MT2701/MT7623 SoC")"
BRs,
Rex
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
@ 2022-05-06 1:49 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 1:49 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, rafael, viresh.kumar, robh+dt,
krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-05 at 17:04 +0200, AngeloGioacchino Del Regno wrote:
> Il 05/05/22 13:52, Rex-BC Chen ha scritto:
> > We register the platform device when driver inits. However, we do
> > not
> > unregister it when driver exits.
> > To resolve this, we declare the platform data to be a global static
> > variable and rename it to be "cpufreq_pdev".
> > With this global variable, we can do platform_device_unregister()
> > when
> > driver exits.
> >
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>
> Hello Rex,
> this commit needs a Fixes: tag.
>
> Cheers,
> Angelo
>
Hello Angelo,
Thanks for the reminder.
I will add "Fixes: 501c574f4e3a ("cpufreq: mediatek: Add support of
cpufreq to MT2701/MT7623 SoC")"
BRs,
Rex
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
@ 2022-05-06 1:49 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 1:49 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, rafael, viresh.kumar, robh+dt,
krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-05 at 17:04 +0200, AngeloGioacchino Del Regno wrote:
> Il 05/05/22 13:52, Rex-BC Chen ha scritto:
> > We register the platform device when driver inits. However, we do
> > not
> > unregister it when driver exits.
> > To resolve this, we declare the platform data to be a global static
> > variable and rename it to be "cpufreq_pdev".
> > With this global variable, we can do platform_device_unregister()
> > when
> > driver exits.
> >
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
>
> Hello Rex,
> this commit needs a Fixes: tag.
>
> Cheers,
> Angelo
>
Hello Angelo,
Thanks for the reminder.
I will add "Fixes: 501c574f4e3a ("cpufreq: mediatek: Add support of
cpufreq to MT2701/MT7623 SoC")"
BRs,
Rex
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-06 4:09 ` Viresh Kumar
-1 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:09 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 05-05-22, 19:52, Rex-BC Chen wrote:
> We register the platform device when driver inits. However, we do not
> unregister it when driver exits.
> To resolve this, we declare the platform data to be a global static
> variable and rename it to be "cpufreq_pdev".
> With this global variable, we can do platform_device_unregister() when
> driver exits.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
Applied. Thanks.
--
viresh
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
@ 2022-05-06 4:09 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:09 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 05-05-22, 19:52, Rex-BC Chen wrote:
> We register the platform device when driver inits. However, we do not
> unregister it when driver exits.
> To resolve this, we declare the platform data to be a global static
> variable and rename it to be "cpufreq_pdev".
> With this global variable, we can do platform_device_unregister() when
> driver exits.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
Applied. Thanks.
--
viresh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 02/10] cpufreq: mediatek: Add platform_device_unregister when driver exit
@ 2022-05-06 4:09 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:09 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 05-05-22, 19:52, Rex-BC Chen wrote:
> We register the platform device when driver inits. However, we do not
> unregister it when driver exits.
> To resolve this, we declare the platform data to be a global static
> variable and rename it to be "cpufreq_pdev".
> With this global variable, we can do platform_device_unregister() when
> driver exits.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
Applied. Thanks.
--
viresh
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* [PATCH v6 03/10] cpufreq: mediatek: Move voltage limits to platform data
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
Voltages and shifts are defined as macros originally.
There are different requirements of these values for each MediaTek SoCs.
Therefore, we add the platform data and move these values into it.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++---------
1 file changed, 58 insertions(+), 26 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index d15cbef4a72e..0b6c3479c8cc 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -10,15 +10,21 @@
#include <linux/cpumask.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
-#define MIN_VOLT_SHIFT (100000)
-#define MAX_VOLT_SHIFT (200000)
-#define MAX_VOLT_LIMIT (1150000)
#define VOLT_TOL (10000)
+struct mtk_cpufreq_platform_data {
+ int min_volt_shift;
+ int max_volt_shift;
+ int proc_max_volt;
+ int sram_min_volt;
+ int sram_max_volt;
+};
+
/*
* The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
* on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
@@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info {
int intermediate_voltage;
bool need_voltage_tracking;
int pre_vproc;
+ const struct mtk_cpufreq_platform_data *soc_data;
};
static struct platform_device *cpufreq_pdev;
@@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
int new_vproc)
{
+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
struct regulator *proc_reg = info->proc_reg;
struct regulator *sram_reg = info->sram_reg;
int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
@@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
return pre_vproc;
}
/* Vsram should not exceed the maximum allowed voltage of SoC. */
- new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
+ new_vsram = min(new_vproc + soc_data->min_volt_shift,
+ soc_data->sram_max_volt);
if (pre_vproc < new_vproc) {
/*
@@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
return pre_vproc;
}
- vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT);
+ vsram = min(new_vsram,
+ pre_vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
- vsram = MAX_VOLT_LIMIT;
+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
+ vsram = soc_data->sram_max_volt;
/*
* If the target Vsram hits the maximum voltage,
@@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
ret = regulator_set_voltage(sram_reg, vsram,
vsram + VOLT_TOL);
- vproc = vsram - MIN_VOLT_SHIFT;
+ vproc = vsram - soc_data->min_volt_shift;
}
if (ret)
return ret;
@@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
return pre_vsram;
}
- vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT);
+ vproc = max(new_vproc,
+ pre_vsram - soc_data->max_volt_shift);
ret = regulator_set_voltage(proc_reg, vproc,
vproc + VOLT_TOL);
if (ret)
@@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
if (vproc == new_vproc)
vsram = new_vsram;
else
- vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
+ vsram = max(new_vsram,
+ vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
- vsram = MAX_VOLT_LIMIT;
+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
+ vsram = soc_data->sram_max_volt;
/*
* If the target Vsram hits the maximum voltage,
@@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
{
+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
int ret;
if (info->need_voltage_tracking)
ret = mtk_cpufreq_voltage_tracking(info, vproc);
else
ret = regulator_set_voltage(info->proc_reg, vproc,
- MAX_VOLT_LIMIT);
+ soc_data->proc_max_volt);
if (!ret)
info->pre_vproc = vproc;
@@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq_driver = {
static int mtk_cpufreq_probe(struct platform_device *pdev)
{
+ const struct mtk_cpufreq_platform_data *data;
struct mtk_cpu_dvfs_info *info, *tmp;
int cpu, ret;
+ data = dev_get_platdata(&pdev->dev);
+ if (!data) {
+ dev_err(&pdev->dev,
+ "failed to get mtk cpufreq platform data\n");
+ return -ENODEV;
+ }
+
for_each_possible_cpu(cpu) {
info = mtk_cpu_dvfs_info_lookup(cpu);
if (info)
@@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct platform_device *pdev)
goto release_dvfs_info_list;
}
+ info->soc_data = data;
ret = mtk_cpu_dvfs_info_init(info, cpu);
if (ret) {
dev_err(&pdev->dev,
@@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufreq_platdrv = {
.probe = mtk_cpufreq_probe,
};
+static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1150000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+};
+
/* List of machines supported by this driver */
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- { .compatible = "mediatek,mt2701", },
- { .compatible = "mediatek,mt2712", },
- { .compatible = "mediatek,mt7622", },
- { .compatible = "mediatek,mt7623", },
- { .compatible = "mediatek,mt8167", },
- { .compatible = "mediatek,mt817x", },
- { .compatible = "mediatek,mt8173", },
- { .compatible = "mediatek,mt8176", },
- { .compatible = "mediatek,mt8183", },
- { .compatible = "mediatek,mt8365", },
- { .compatible = "mediatek,mt8516", },
-
+ { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
{ }
};
MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
@@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_init(void)
{
struct device_node *np;
const struct of_device_id *match;
+ const struct mtk_cpufreq_platform_data *data;
int err;
np = of_find_node_by_path("/");
@@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_init(void)
pr_debug("Machine is not compatible with mtk-cpufreq\n");
return -ENODEV;
}
+ data = match->data;
err = platform_driver_register(&mtk_cpufreq_platdrv);
if (err)
@@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_init(void)
* and the device registration codes are put here to handle defer
* probing.
*/
- cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
+ cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
+ data, sizeof(*data));
if (IS_ERR(cpufreq_pdev)) {
pr_err("failed to register mtk-cpufreq platform device\n");
platform_driver_unregister(&mtk_cpufreq_platdrv);
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 03/10] cpufreq: mediatek: Move voltage limits to platform data
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
Voltages and shifts are defined as macros originally.
There are different requirements of these values for each MediaTek SoCs.
Therefore, we add the platform data and move these values into it.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++---------
1 file changed, 58 insertions(+), 26 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index d15cbef4a72e..0b6c3479c8cc 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -10,15 +10,21 @@
#include <linux/cpumask.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
-#define MIN_VOLT_SHIFT (100000)
-#define MAX_VOLT_SHIFT (200000)
-#define MAX_VOLT_LIMIT (1150000)
#define VOLT_TOL (10000)
+struct mtk_cpufreq_platform_data {
+ int min_volt_shift;
+ int max_volt_shift;
+ int proc_max_volt;
+ int sram_min_volt;
+ int sram_max_volt;
+};
+
/*
* The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
* on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
@@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info {
int intermediate_voltage;
bool need_voltage_tracking;
int pre_vproc;
+ const struct mtk_cpufreq_platform_data *soc_data;
};
static struct platform_device *cpufreq_pdev;
@@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
int new_vproc)
{
+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
struct regulator *proc_reg = info->proc_reg;
struct regulator *sram_reg = info->sram_reg;
int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
@@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
return pre_vproc;
}
/* Vsram should not exceed the maximum allowed voltage of SoC. */
- new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
+ new_vsram = min(new_vproc + soc_data->min_volt_shift,
+ soc_data->sram_max_volt);
if (pre_vproc < new_vproc) {
/*
@@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
return pre_vproc;
}
- vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT);
+ vsram = min(new_vsram,
+ pre_vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
- vsram = MAX_VOLT_LIMIT;
+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
+ vsram = soc_data->sram_max_volt;
/*
* If the target Vsram hits the maximum voltage,
@@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
ret = regulator_set_voltage(sram_reg, vsram,
vsram + VOLT_TOL);
- vproc = vsram - MIN_VOLT_SHIFT;
+ vproc = vsram - soc_data->min_volt_shift;
}
if (ret)
return ret;
@@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
return pre_vsram;
}
- vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT);
+ vproc = max(new_vproc,
+ pre_vsram - soc_data->max_volt_shift);
ret = regulator_set_voltage(proc_reg, vproc,
vproc + VOLT_TOL);
if (ret)
@@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
if (vproc == new_vproc)
vsram = new_vsram;
else
- vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
+ vsram = max(new_vsram,
+ vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
- vsram = MAX_VOLT_LIMIT;
+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
+ vsram = soc_data->sram_max_volt;
/*
* If the target Vsram hits the maximum voltage,
@@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
{
+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
int ret;
if (info->need_voltage_tracking)
ret = mtk_cpufreq_voltage_tracking(info, vproc);
else
ret = regulator_set_voltage(info->proc_reg, vproc,
- MAX_VOLT_LIMIT);
+ soc_data->proc_max_volt);
if (!ret)
info->pre_vproc = vproc;
@@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq_driver = {
static int mtk_cpufreq_probe(struct platform_device *pdev)
{
+ const struct mtk_cpufreq_platform_data *data;
struct mtk_cpu_dvfs_info *info, *tmp;
int cpu, ret;
+ data = dev_get_platdata(&pdev->dev);
+ if (!data) {
+ dev_err(&pdev->dev,
+ "failed to get mtk cpufreq platform data\n");
+ return -ENODEV;
+ }
+
for_each_possible_cpu(cpu) {
info = mtk_cpu_dvfs_info_lookup(cpu);
if (info)
@@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct platform_device *pdev)
goto release_dvfs_info_list;
}
+ info->soc_data = data;
ret = mtk_cpu_dvfs_info_init(info, cpu);
if (ret) {
dev_err(&pdev->dev,
@@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufreq_platdrv = {
.probe = mtk_cpufreq_probe,
};
+static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1150000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+};
+
/* List of machines supported by this driver */
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- { .compatible = "mediatek,mt2701", },
- { .compatible = "mediatek,mt2712", },
- { .compatible = "mediatek,mt7622", },
- { .compatible = "mediatek,mt7623", },
- { .compatible = "mediatek,mt8167", },
- { .compatible = "mediatek,mt817x", },
- { .compatible = "mediatek,mt8173", },
- { .compatible = "mediatek,mt8176", },
- { .compatible = "mediatek,mt8183", },
- { .compatible = "mediatek,mt8365", },
- { .compatible = "mediatek,mt8516", },
-
+ { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
{ }
};
MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
@@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_init(void)
{
struct device_node *np;
const struct of_device_id *match;
+ const struct mtk_cpufreq_platform_data *data;
int err;
np = of_find_node_by_path("/");
@@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_init(void)
pr_debug("Machine is not compatible with mtk-cpufreq\n");
return -ENODEV;
}
+ data = match->data;
err = platform_driver_register(&mtk_cpufreq_platdrv);
if (err)
@@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_init(void)
* and the device registration codes are put here to handle defer
* probing.
*/
- cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
+ cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
+ data, sizeof(*data));
if (IS_ERR(cpufreq_pdev)) {
pr_err("failed to register mtk-cpufreq platform device\n");
platform_driver_unregister(&mtk_cpufreq_platdrv);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 03/10] cpufreq: mediatek: Move voltage limits to platform data
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
Voltages and shifts are defined as macros originally.
There are different requirements of these values for each MediaTek SoCs.
Therefore, we add the platform data and move these values into it.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++---------
1 file changed, 58 insertions(+), 26 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index d15cbef4a72e..0b6c3479c8cc 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -10,15 +10,21 @@
#include <linux/cpumask.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
-#define MIN_VOLT_SHIFT (100000)
-#define MAX_VOLT_SHIFT (200000)
-#define MAX_VOLT_LIMIT (1150000)
#define VOLT_TOL (10000)
+struct mtk_cpufreq_platform_data {
+ int min_volt_shift;
+ int max_volt_shift;
+ int proc_max_volt;
+ int sram_min_volt;
+ int sram_max_volt;
+};
+
/*
* The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
* on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
@@ -41,6 +47,7 @@ struct mtk_cpu_dvfs_info {
int intermediate_voltage;
bool need_voltage_tracking;
int pre_vproc;
+ const struct mtk_cpufreq_platform_data *soc_data;
};
static struct platform_device *cpufreq_pdev;
@@ -62,6 +69,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
int new_vproc)
{
+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
struct regulator *proc_reg = info->proc_reg;
struct regulator *sram_reg = info->sram_reg;
int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
@@ -73,7 +81,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
return pre_vproc;
}
/* Vsram should not exceed the maximum allowed voltage of SoC. */
- new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
+ new_vsram = min(new_vproc + soc_data->min_volt_shift,
+ soc_data->sram_max_volt);
if (pre_vproc < new_vproc) {
/*
@@ -96,10 +105,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
return pre_vproc;
}
- vsram = min(new_vsram, pre_vproc + MAX_VOLT_SHIFT);
+ vsram = min(new_vsram,
+ pre_vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
- vsram = MAX_VOLT_LIMIT;
+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
+ vsram = soc_data->sram_max_volt;
/*
* If the target Vsram hits the maximum voltage,
@@ -117,7 +127,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
ret = regulator_set_voltage(sram_reg, vsram,
vsram + VOLT_TOL);
- vproc = vsram - MIN_VOLT_SHIFT;
+ vproc = vsram - soc_data->min_volt_shift;
}
if (ret)
return ret;
@@ -151,7 +161,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
return pre_vsram;
}
- vproc = max(new_vproc, pre_vsram - MAX_VOLT_SHIFT);
+ vproc = max(new_vproc,
+ pre_vsram - soc_data->max_volt_shift);
ret = regulator_set_voltage(proc_reg, vproc,
vproc + VOLT_TOL);
if (ret)
@@ -160,10 +171,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
if (vproc == new_vproc)
vsram = new_vsram;
else
- vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
+ vsram = max(new_vsram,
+ vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
- vsram = MAX_VOLT_LIMIT;
+ if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
+ vsram = soc_data->sram_max_volt;
/*
* If the target Vsram hits the maximum voltage,
@@ -194,13 +206,14 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
{
+ const struct mtk_cpufreq_platform_data *soc_data = info->soc_data;
int ret;
if (info->need_voltage_tracking)
ret = mtk_cpufreq_voltage_tracking(info, vproc);
else
ret = regulator_set_voltage(info->proc_reg, vproc,
- MAX_VOLT_LIMIT);
+ soc_data->proc_max_volt);
if (!ret)
info->pre_vproc = vproc;
@@ -509,9 +522,17 @@ static struct cpufreq_driver mtk_cpufreq_driver = {
static int mtk_cpufreq_probe(struct platform_device *pdev)
{
+ const struct mtk_cpufreq_platform_data *data;
struct mtk_cpu_dvfs_info *info, *tmp;
int cpu, ret;
+ data = dev_get_platdata(&pdev->dev);
+ if (!data) {
+ dev_err(&pdev->dev,
+ "failed to get mtk cpufreq platform data\n");
+ return -ENODEV;
+ }
+
for_each_possible_cpu(cpu) {
info = mtk_cpu_dvfs_info_lookup(cpu);
if (info)
@@ -523,6 +544,7 @@ static int mtk_cpufreq_probe(struct platform_device *pdev)
goto release_dvfs_info_list;
}
+ info->soc_data = data;
ret = mtk_cpu_dvfs_info_init(info, cpu);
if (ret) {
dev_err(&pdev->dev,
@@ -558,20 +580,27 @@ static struct platform_driver mtk_cpufreq_platdrv = {
.probe = mtk_cpufreq_probe,
};
+static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1150000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+};
+
/* List of machines supported by this driver */
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
- { .compatible = "mediatek,mt2701", },
- { .compatible = "mediatek,mt2712", },
- { .compatible = "mediatek,mt7622", },
- { .compatible = "mediatek,mt7623", },
- { .compatible = "mediatek,mt8167", },
- { .compatible = "mediatek,mt817x", },
- { .compatible = "mediatek,mt8173", },
- { .compatible = "mediatek,mt8176", },
- { .compatible = "mediatek,mt8183", },
- { .compatible = "mediatek,mt8365", },
- { .compatible = "mediatek,mt8516", },
-
+ { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt7622", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt7623", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8167", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
{ }
};
MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
@@ -580,6 +609,7 @@ static int __init mtk_cpufreq_driver_init(void)
{
struct device_node *np;
const struct of_device_id *match;
+ const struct mtk_cpufreq_platform_data *data;
int err;
np = of_find_node_by_path("/");
@@ -592,6 +622,7 @@ static int __init mtk_cpufreq_driver_init(void)
pr_debug("Machine is not compatible with mtk-cpufreq\n");
return -ENODEV;
}
+ data = match->data;
err = platform_driver_register(&mtk_cpufreq_platdrv);
if (err)
@@ -603,7 +634,8 @@ static int __init mtk_cpufreq_driver_init(void)
* and the device registration codes are put here to handle defer
* probing.
*/
- cpufreq_pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
+ cpufreq_pdev = platform_device_register_data(NULL, "mtk-cpufreq", -1,
+ data, sizeof(*data));
if (IS_ERR(cpufreq_pdev)) {
pr_err("failed to register mtk-cpufreq platform device\n");
platform_driver_unregister(&mtk_cpufreq_platdrv);
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread* Re: [PATCH v6 03/10] cpufreq: mediatek: Move voltage limits to platform data
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-06 4:10 ` Viresh Kumar
-1 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:10 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 05-05-22, 19:52, Rex-BC Chen wrote:
> Voltages and shifts are defined as macros originally.
> There are different requirements of these values for each MediaTek SoCs.
> Therefore, we add the platform data and move these values into it.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++---------
> 1 file changed, 58 insertions(+), 26 deletions(-)
Applied. Thanks.
--
viresh
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 03/10] cpufreq: mediatek: Move voltage limits to platform data
@ 2022-05-06 4:10 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:10 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 05-05-22, 19:52, Rex-BC Chen wrote:
> Voltages and shifts are defined as macros originally.
> There are different requirements of these values for each MediaTek SoCs.
> Therefore, we add the platform data and move these values into it.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++---------
> 1 file changed, 58 insertions(+), 26 deletions(-)
Applied. Thanks.
--
viresh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 03/10] cpufreq: mediatek: Move voltage limits to platform data
@ 2022-05-06 4:10 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:10 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 05-05-22, 19:52, Rex-BC Chen wrote:
> Voltages and shifts are defined as macros originally.
> There are different requirements of these values for each MediaTek SoCs.
> Therefore, we add the platform data and move these values into it.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 84 +++++++++++++++++++++---------
> 1 file changed, 58 insertions(+), 26 deletions(-)
Applied. Thanks.
--
viresh
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* [PATCH v6 04/10] cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Because the difference of sram and proc should in a range of min_volt_shift
and max_volt_shift. We need to adjust the sram and proc step by step.
We replace VOLT_TOL (voltage tolerance) with the platform data and update the
logic to determine the voltage boundary and invoking regulator_set_voltage.
- Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary
of sram regulator.
- Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the
voltage boundary of vproc regulator.
Moreover, to prevent infinite loop when tracking voltage, we calculate the
maximum value for each platform data.
We assume min voltage is 0 and tracking target voltage using
min_volt_shift for each iteration.
The retry_max is 3 times of expeted iteration count.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++-------------------
1 file changed, 51 insertions(+), 96 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 0b6c3479c8cc..fe205eca657d 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -8,6 +8,7 @@
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/cpumask.h>
+#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
@@ -15,8 +16,6 @@
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
-#define VOLT_TOL (10000)
-
struct mtk_cpufreq_platform_data {
int min_volt_shift;
int max_volt_shift;
@@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info {
bool need_voltage_tracking;
int pre_vproc;
const struct mtk_cpufreq_platform_data *soc_data;
+ int vtrack_max;
};
static struct platform_device *cpufreq_pdev;
@@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
struct regulator *proc_reg = info->proc_reg;
struct regulator *sram_reg = info->sram_reg;
int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
+ int retry = info->vtrack_max;
pre_vproc = regulator_get_voltage(proc_reg);
if (pre_vproc < 0) {
@@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
"invalid Vproc value: %d\n", pre_vproc);
return pre_vproc;
}
- /* Vsram should not exceed the maximum allowed voltage of SoC. */
- new_vsram = min(new_vproc + soc_data->min_volt_shift,
- soc_data->sram_max_volt);
-
- if (pre_vproc < new_vproc) {
- /*
- * When scaling up voltages, Vsram and Vproc scale up step
- * by step. At each step, set Vsram to (Vproc + 200mV) first,
- * then set Vproc to (Vsram - 100mV).
- * Keep doing it until Vsram and Vproc hit target voltages.
- */
- do {
- pre_vsram = regulator_get_voltage(sram_reg);
- if (pre_vsram < 0) {
- dev_err(info->cpu_dev,
- "invalid Vsram value: %d\n", pre_vsram);
- return pre_vsram;
- }
- pre_vproc = regulator_get_voltage(proc_reg);
- if (pre_vproc < 0) {
- dev_err(info->cpu_dev,
- "invalid Vproc value: %d\n", pre_vproc);
- return pre_vproc;
- }
-
- vsram = min(new_vsram,
- pre_vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
- vsram = soc_data->sram_max_volt;
+ pre_vsram = regulator_get_voltage(sram_reg);
+ if (pre_vsram < 0) {
+ dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
+ return pre_vsram;
+ }
- /*
- * If the target Vsram hits the maximum voltage,
- * try to set the exact voltage value first.
- */
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram);
- if (ret)
- ret = regulator_set_voltage(sram_reg,
- vsram - VOLT_TOL,
- vsram);
+ new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
+ soc_data->sram_min_volt, soc_data->sram_max_volt);
- vproc = new_vproc;
- } else {
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram + VOLT_TOL);
+ do {
+ if (pre_vproc <= new_vproc) {
+ vsram = clamp(pre_vproc + soc_data->max_volt_shift,
+ soc_data->sram_min_volt, new_vsram);
+ ret = regulator_set_voltage(sram_reg, vsram,
+ soc_data->sram_max_volt);
- vproc = vsram - soc_data->min_volt_shift;
- }
if (ret)
return ret;
+ if (vsram == soc_data->sram_max_volt ||
+ new_vsram == soc_data->sram_min_volt)
+ vproc = new_vproc;
+ else
+ vproc = vsram - soc_data->min_volt_shift;
+
ret = regulator_set_voltage(proc_reg, vproc,
- vproc + VOLT_TOL);
+ soc_data->proc_max_volt);
if (ret) {
regulator_set_voltage(sram_reg, pre_vsram,
- pre_vsram);
+ soc_data->sram_max_volt);
return ret;
}
- } while (vproc < new_vproc || vsram < new_vsram);
- } else if (pre_vproc > new_vproc) {
- /*
- * When scaling down voltages, Vsram and Vproc scale down step
- * by step. At each step, set Vproc to (Vsram - 200mV) first,
- * then set Vproc to (Vproc + 100mV).
- * Keep doing it until Vsram and Vproc hit target voltages.
- */
- do {
- pre_vproc = regulator_get_voltage(proc_reg);
- if (pre_vproc < 0) {
- dev_err(info->cpu_dev,
- "invalid Vproc value: %d\n", pre_vproc);
- return pre_vproc;
- }
- pre_vsram = regulator_get_voltage(sram_reg);
- if (pre_vsram < 0) {
- dev_err(info->cpu_dev,
- "invalid Vsram value: %d\n", pre_vsram);
- return pre_vsram;
- }
-
+ } else if (pre_vproc > new_vproc) {
vproc = max(new_vproc,
pre_vsram - soc_data->max_volt_shift);
ret = regulator_set_voltage(proc_reg, vproc,
- vproc + VOLT_TOL);
+ soc_data->proc_max_volt);
if (ret)
return ret;
@@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
vsram = max(new_vsram,
vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
- vsram = soc_data->sram_max_volt;
-
- /*
- * If the target Vsram hits the maximum voltage,
- * try to set the exact voltage value first.
- */
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram);
- if (ret)
- ret = regulator_set_voltage(sram_reg,
- vsram - VOLT_TOL,
- vsram);
- } else {
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram + VOLT_TOL);
- }
-
+ ret = regulator_set_voltage(sram_reg, vsram,
+ soc_data->sram_max_volt);
if (ret) {
regulator_set_voltage(proc_reg, pre_vproc,
- pre_vproc);
+ soc_data->proc_max_volt);
return ret;
}
- } while (vproc > new_vproc + VOLT_TOL ||
- vsram > new_vsram + VOLT_TOL);
- }
+ }
+
+ pre_vproc = vproc;
+ pre_vsram = vsram;
+
+ if (--retry < 0) {
+ dev_err(info->cpu_dev,
+ "over loop count, failed to set voltage\n");
+ return -EINVAL;
+ }
+ } while (vproc != new_vproc || vsram != new_vsram);
return 0;
}
@@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
* If the new voltage or the intermediate voltage is higher than the
* current voltage, scale up voltage first.
*/
- target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
- if (pre_vproc < target_vproc) {
+ target_vproc = max(inter_vproc, vproc);
+ if (pre_vproc <= target_vproc) {
ret = mtk_cpufreq_set_voltage(info, target_vproc);
if (ret) {
dev_err(cpu_dev,
@@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
*/
info->need_voltage_tracking = (info->sram_reg != NULL);
+ /*
+ * We assume min voltage is 0 and tracking target voltage using
+ * min_volt_shift for each iteration.
+ * The vtrack_max is 3 times of expeted iteration count.
+ */
+ info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
+ info->soc_data->proc_max_volt),
+ info->soc_data->min_volt_shift);
+
return 0;
out_disable_inter_clock:
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 04/10] cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Because the difference of sram and proc should in a range of min_volt_shift
and max_volt_shift. We need to adjust the sram and proc step by step.
We replace VOLT_TOL (voltage tolerance) with the platform data and update the
logic to determine the voltage boundary and invoking regulator_set_voltage.
- Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary
of sram regulator.
- Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the
voltage boundary of vproc regulator.
Moreover, to prevent infinite loop when tracking voltage, we calculate the
maximum value for each platform data.
We assume min voltage is 0 and tracking target voltage using
min_volt_shift for each iteration.
The retry_max is 3 times of expeted iteration count.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++-------------------
1 file changed, 51 insertions(+), 96 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 0b6c3479c8cc..fe205eca657d 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -8,6 +8,7 @@
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/cpumask.h>
+#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
@@ -15,8 +16,6 @@
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
-#define VOLT_TOL (10000)
-
struct mtk_cpufreq_platform_data {
int min_volt_shift;
int max_volt_shift;
@@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info {
bool need_voltage_tracking;
int pre_vproc;
const struct mtk_cpufreq_platform_data *soc_data;
+ int vtrack_max;
};
static struct platform_device *cpufreq_pdev;
@@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
struct regulator *proc_reg = info->proc_reg;
struct regulator *sram_reg = info->sram_reg;
int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
+ int retry = info->vtrack_max;
pre_vproc = regulator_get_voltage(proc_reg);
if (pre_vproc < 0) {
@@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
"invalid Vproc value: %d\n", pre_vproc);
return pre_vproc;
}
- /* Vsram should not exceed the maximum allowed voltage of SoC. */
- new_vsram = min(new_vproc + soc_data->min_volt_shift,
- soc_data->sram_max_volt);
-
- if (pre_vproc < new_vproc) {
- /*
- * When scaling up voltages, Vsram and Vproc scale up step
- * by step. At each step, set Vsram to (Vproc + 200mV) first,
- * then set Vproc to (Vsram - 100mV).
- * Keep doing it until Vsram and Vproc hit target voltages.
- */
- do {
- pre_vsram = regulator_get_voltage(sram_reg);
- if (pre_vsram < 0) {
- dev_err(info->cpu_dev,
- "invalid Vsram value: %d\n", pre_vsram);
- return pre_vsram;
- }
- pre_vproc = regulator_get_voltage(proc_reg);
- if (pre_vproc < 0) {
- dev_err(info->cpu_dev,
- "invalid Vproc value: %d\n", pre_vproc);
- return pre_vproc;
- }
-
- vsram = min(new_vsram,
- pre_vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
- vsram = soc_data->sram_max_volt;
+ pre_vsram = regulator_get_voltage(sram_reg);
+ if (pre_vsram < 0) {
+ dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
+ return pre_vsram;
+ }
- /*
- * If the target Vsram hits the maximum voltage,
- * try to set the exact voltage value first.
- */
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram);
- if (ret)
- ret = regulator_set_voltage(sram_reg,
- vsram - VOLT_TOL,
- vsram);
+ new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
+ soc_data->sram_min_volt, soc_data->sram_max_volt);
- vproc = new_vproc;
- } else {
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram + VOLT_TOL);
+ do {
+ if (pre_vproc <= new_vproc) {
+ vsram = clamp(pre_vproc + soc_data->max_volt_shift,
+ soc_data->sram_min_volt, new_vsram);
+ ret = regulator_set_voltage(sram_reg, vsram,
+ soc_data->sram_max_volt);
- vproc = vsram - soc_data->min_volt_shift;
- }
if (ret)
return ret;
+ if (vsram == soc_data->sram_max_volt ||
+ new_vsram == soc_data->sram_min_volt)
+ vproc = new_vproc;
+ else
+ vproc = vsram - soc_data->min_volt_shift;
+
ret = regulator_set_voltage(proc_reg, vproc,
- vproc + VOLT_TOL);
+ soc_data->proc_max_volt);
if (ret) {
regulator_set_voltage(sram_reg, pre_vsram,
- pre_vsram);
+ soc_data->sram_max_volt);
return ret;
}
- } while (vproc < new_vproc || vsram < new_vsram);
- } else if (pre_vproc > new_vproc) {
- /*
- * When scaling down voltages, Vsram and Vproc scale down step
- * by step. At each step, set Vproc to (Vsram - 200mV) first,
- * then set Vproc to (Vproc + 100mV).
- * Keep doing it until Vsram and Vproc hit target voltages.
- */
- do {
- pre_vproc = regulator_get_voltage(proc_reg);
- if (pre_vproc < 0) {
- dev_err(info->cpu_dev,
- "invalid Vproc value: %d\n", pre_vproc);
- return pre_vproc;
- }
- pre_vsram = regulator_get_voltage(sram_reg);
- if (pre_vsram < 0) {
- dev_err(info->cpu_dev,
- "invalid Vsram value: %d\n", pre_vsram);
- return pre_vsram;
- }
-
+ } else if (pre_vproc > new_vproc) {
vproc = max(new_vproc,
pre_vsram - soc_data->max_volt_shift);
ret = regulator_set_voltage(proc_reg, vproc,
- vproc + VOLT_TOL);
+ soc_data->proc_max_volt);
if (ret)
return ret;
@@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
vsram = max(new_vsram,
vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
- vsram = soc_data->sram_max_volt;
-
- /*
- * If the target Vsram hits the maximum voltage,
- * try to set the exact voltage value first.
- */
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram);
- if (ret)
- ret = regulator_set_voltage(sram_reg,
- vsram - VOLT_TOL,
- vsram);
- } else {
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram + VOLT_TOL);
- }
-
+ ret = regulator_set_voltage(sram_reg, vsram,
+ soc_data->sram_max_volt);
if (ret) {
regulator_set_voltage(proc_reg, pre_vproc,
- pre_vproc);
+ soc_data->proc_max_volt);
return ret;
}
- } while (vproc > new_vproc + VOLT_TOL ||
- vsram > new_vsram + VOLT_TOL);
- }
+ }
+
+ pre_vproc = vproc;
+ pre_vsram = vsram;
+
+ if (--retry < 0) {
+ dev_err(info->cpu_dev,
+ "over loop count, failed to set voltage\n");
+ return -EINVAL;
+ }
+ } while (vproc != new_vproc || vsram != new_vsram);
return 0;
}
@@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
* If the new voltage or the intermediate voltage is higher than the
* current voltage, scale up voltage first.
*/
- target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
- if (pre_vproc < target_vproc) {
+ target_vproc = max(inter_vproc, vproc);
+ if (pre_vproc <= target_vproc) {
ret = mtk_cpufreq_set_voltage(info, target_vproc);
if (ret) {
dev_err(cpu_dev,
@@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
*/
info->need_voltage_tracking = (info->sram_reg != NULL);
+ /*
+ * We assume min voltage is 0 and tracking target voltage using
+ * min_volt_shift for each iteration.
+ * The vtrack_max is 3 times of expeted iteration count.
+ */
+ info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
+ info->soc_data->proc_max_volt),
+ info->soc_data->min_volt_shift);
+
return 0;
out_disable_inter_clock:
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 04/10] cpufreq: mediatek: Refine mtk_cpufreq_voltage_tracking()
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Because the difference of sram and proc should in a range of min_volt_shift
and max_volt_shift. We need to adjust the sram and proc step by step.
We replace VOLT_TOL (voltage tolerance) with the platform data and update the
logic to determine the voltage boundary and invoking regulator_set_voltage.
- Use 'sram_min_volt' and 'sram_max_volt' to determine the voltage boundary
of sram regulator.
- Use (sram_min_volt - min_volt_shift) and 'proc_max_volt' to determine the
voltage boundary of vproc regulator.
Moreover, to prevent infinite loop when tracking voltage, we calculate the
maximum value for each platform data.
We assume min voltage is 0 and tracking target voltage using
min_volt_shift for each iteration.
The retry_max is 3 times of expeted iteration count.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 147 ++++++++++-------------------
1 file changed, 51 insertions(+), 96 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 0b6c3479c8cc..fe205eca657d 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -8,6 +8,7 @@
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/cpumask.h>
+#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
@@ -15,8 +16,6 @@
#include <linux/pm_opp.h>
#include <linux/regulator/consumer.h>
-#define VOLT_TOL (10000)
-
struct mtk_cpufreq_platform_data {
int min_volt_shift;
int max_volt_shift;
@@ -48,6 +47,7 @@ struct mtk_cpu_dvfs_info {
bool need_voltage_tracking;
int pre_vproc;
const struct mtk_cpufreq_platform_data *soc_data;
+ int vtrack_max;
};
static struct platform_device *cpufreq_pdev;
@@ -73,6 +73,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
struct regulator *proc_reg = info->proc_reg;
struct regulator *sram_reg = info->sram_reg;
int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret;
+ int retry = info->vtrack_max;
pre_vproc = regulator_get_voltage(proc_reg);
if (pre_vproc < 0) {
@@ -80,91 +81,44 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
"invalid Vproc value: %d\n", pre_vproc);
return pre_vproc;
}
- /* Vsram should not exceed the maximum allowed voltage of SoC. */
- new_vsram = min(new_vproc + soc_data->min_volt_shift,
- soc_data->sram_max_volt);
-
- if (pre_vproc < new_vproc) {
- /*
- * When scaling up voltages, Vsram and Vproc scale up step
- * by step. At each step, set Vsram to (Vproc + 200mV) first,
- * then set Vproc to (Vsram - 100mV).
- * Keep doing it until Vsram and Vproc hit target voltages.
- */
- do {
- pre_vsram = regulator_get_voltage(sram_reg);
- if (pre_vsram < 0) {
- dev_err(info->cpu_dev,
- "invalid Vsram value: %d\n", pre_vsram);
- return pre_vsram;
- }
- pre_vproc = regulator_get_voltage(proc_reg);
- if (pre_vproc < 0) {
- dev_err(info->cpu_dev,
- "invalid Vproc value: %d\n", pre_vproc);
- return pre_vproc;
- }
-
- vsram = min(new_vsram,
- pre_vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
- vsram = soc_data->sram_max_volt;
+ pre_vsram = regulator_get_voltage(sram_reg);
+ if (pre_vsram < 0) {
+ dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram);
+ return pre_vsram;
+ }
- /*
- * If the target Vsram hits the maximum voltage,
- * try to set the exact voltage value first.
- */
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram);
- if (ret)
- ret = regulator_set_voltage(sram_reg,
- vsram - VOLT_TOL,
- vsram);
+ new_vsram = clamp(new_vproc + soc_data->min_volt_shift,
+ soc_data->sram_min_volt, soc_data->sram_max_volt);
- vproc = new_vproc;
- } else {
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram + VOLT_TOL);
+ do {
+ if (pre_vproc <= new_vproc) {
+ vsram = clamp(pre_vproc + soc_data->max_volt_shift,
+ soc_data->sram_min_volt, new_vsram);
+ ret = regulator_set_voltage(sram_reg, vsram,
+ soc_data->sram_max_volt);
- vproc = vsram - soc_data->min_volt_shift;
- }
if (ret)
return ret;
+ if (vsram == soc_data->sram_max_volt ||
+ new_vsram == soc_data->sram_min_volt)
+ vproc = new_vproc;
+ else
+ vproc = vsram - soc_data->min_volt_shift;
+
ret = regulator_set_voltage(proc_reg, vproc,
- vproc + VOLT_TOL);
+ soc_data->proc_max_volt);
if (ret) {
regulator_set_voltage(sram_reg, pre_vsram,
- pre_vsram);
+ soc_data->sram_max_volt);
return ret;
}
- } while (vproc < new_vproc || vsram < new_vsram);
- } else if (pre_vproc > new_vproc) {
- /*
- * When scaling down voltages, Vsram and Vproc scale down step
- * by step. At each step, set Vproc to (Vsram - 200mV) first,
- * then set Vproc to (Vproc + 100mV).
- * Keep doing it until Vsram and Vproc hit target voltages.
- */
- do {
- pre_vproc = regulator_get_voltage(proc_reg);
- if (pre_vproc < 0) {
- dev_err(info->cpu_dev,
- "invalid Vproc value: %d\n", pre_vproc);
- return pre_vproc;
- }
- pre_vsram = regulator_get_voltage(sram_reg);
- if (pre_vsram < 0) {
- dev_err(info->cpu_dev,
- "invalid Vsram value: %d\n", pre_vsram);
- return pre_vsram;
- }
-
+ } else if (pre_vproc > new_vproc) {
vproc = max(new_vproc,
pre_vsram - soc_data->max_volt_shift);
ret = regulator_set_voltage(proc_reg, vproc,
- vproc + VOLT_TOL);
+ soc_data->proc_max_volt);
if (ret)
return ret;
@@ -174,32 +128,24 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
vsram = max(new_vsram,
vproc + soc_data->min_volt_shift);
- if (vsram + VOLT_TOL >= soc_data->sram_max_volt) {
- vsram = soc_data->sram_max_volt;
-
- /*
- * If the target Vsram hits the maximum voltage,
- * try to set the exact voltage value first.
- */
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram);
- if (ret)
- ret = regulator_set_voltage(sram_reg,
- vsram - VOLT_TOL,
- vsram);
- } else {
- ret = regulator_set_voltage(sram_reg, vsram,
- vsram + VOLT_TOL);
- }
-
+ ret = regulator_set_voltage(sram_reg, vsram,
+ soc_data->sram_max_volt);
if (ret) {
regulator_set_voltage(proc_reg, pre_vproc,
- pre_vproc);
+ soc_data->proc_max_volt);
return ret;
}
- } while (vproc > new_vproc + VOLT_TOL ||
- vsram > new_vsram + VOLT_TOL);
- }
+ }
+
+ pre_vproc = vproc;
+ pre_vsram = vsram;
+
+ if (--retry < 0) {
+ dev_err(info->cpu_dev,
+ "over loop count, failed to set voltage\n");
+ return -EINVAL;
+ }
+ } while (vproc != new_vproc || vsram != new_vsram);
return 0;
}
@@ -261,8 +207,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
* If the new voltage or the intermediate voltage is higher than the
* current voltage, scale up voltage first.
*/
- target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
- if (pre_vproc < target_vproc) {
+ target_vproc = max(inter_vproc, vproc);
+ if (pre_vproc <= target_vproc) {
ret = mtk_cpufreq_set_voltage(info, target_vproc);
if (ret) {
dev_err(cpu_dev,
@@ -417,6 +363,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
*/
info->need_voltage_tracking = (info->sram_reg != NULL);
+ /*
+ * We assume min voltage is 0 and tracking target voltage using
+ * min_volt_shift for each iteration.
+ * The vtrack_max is 3 times of expeted iteration count.
+ */
+ info->vtrack_max = 3 * DIV_ROUND_UP(max(info->soc_data->sram_max_volt,
+ info->soc_data->proc_max_volt),
+ info->soc_data->min_volt_shift);
+
return 0;
out_disable_inter_clock:
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen,
Andrew-sh . Cheng
From this opp notifier, cpufreq should listen to opp notification and do
proper actions when receiving events of disable and voltage adjustment.
One of the user for this opp notifier is MediaTek SVS.
The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates
suitable SVS bank voltages to OPP voltage table.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++---
1 file changed, 83 insertions(+), 8 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index fe205eca657d..06d80ee06bbf 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
int intermediate_voltage;
bool need_voltage_tracking;
int pre_vproc;
+ /* Avoid race condition for regulators between notify and policy */
+ struct mutex reg_lock;
+ struct notifier_block opp_nb;
+ unsigned int opp_cpu;
+ unsigned long opp_freq;
const struct mtk_cpufreq_platform_data *soc_data;
int vtrack_max;
};
@@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
pre_freq_hz = clk_get_rate(cpu_clk);
+ mutex_lock(&info->reg_lock);
+
if (unlikely(info->pre_vproc <= 0))
pre_vproc = regulator_get_voltage(info->proc_reg);
else
@@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
dev_err(cpu_dev,
"cpu%d: failed to scale up voltage!\n", policy->cpu);
mtk_cpufreq_set_voltage(info, pre_vproc);
- return ret;
+ goto out;
}
}
@@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
dev_err(cpu_dev,
"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
mtk_cpufreq_set_voltage(info, pre_vproc);
- WARN_ON(1);
- return ret;
+ goto out;
}
/* Set the original PLL to target rate. */
@@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
clk_set_parent(cpu_clk, armpll);
mtk_cpufreq_set_voltage(info, pre_vproc);
- return ret;
+ goto out;
}
/* Set parent of CPU clock back to the original PLL. */
@@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
dev_err(cpu_dev,
"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
mtk_cpufreq_set_voltage(info, inter_vproc);
- WARN_ON(1);
- return ret;
+ goto out;
}
/*
@@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
clk_set_parent(cpu_clk, info->inter_clk);
clk_set_rate(armpll, pre_freq_hz);
clk_set_parent(cpu_clk, armpll);
- return ret;
+ goto out;
}
}
- return 0;
+ info->opp_freq = freq_hz;
+
+out:
+ mutex_unlock(&info->reg_lock);
+
+ return ret;
}
#define DYNAMIC_POWER "dynamic-power-coefficient"
+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct dev_pm_opp *new_opp;
+ struct mtk_cpu_dvfs_info *info;
+ unsigned long freq, volt;
+ struct cpufreq_policy *policy;
+ int ret = 0;
+
+ info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ mutex_lock(&info->reg_lock);
+ if (info->opp_freq == freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ ret = mtk_cpufreq_set_voltage(info, volt);
+ if (ret)
+ dev_err(info->cpu_dev,
+ "failed to scale voltage: %d\n", ret);
+ }
+ mutex_unlock(&info->reg_lock);
+ } else if (event == OPP_EVENT_DISABLE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ /* case of current opp item is disabled */
+ if (info->opp_freq == freq) {
+ freq = 1;
+ new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
+ &freq);
+ if (IS_ERR(new_opp)) {
+ dev_err(info->cpu_dev,
+ "all opp items are disabled\n");
+ ret = PTR_ERR(new_opp);
+ return notifier_from_errno(ret);
+ }
+
+ dev_pm_opp_put(new_opp);
+ policy = cpufreq_cpu_get(info->opp_cpu);
+ if (policy) {
+ cpufreq_driver_target(policy, freq / 1000,
+ CPUFREQ_RELATION_L);
+ cpufreq_cpu_put(policy);
+ }
+ }
+ }
+
+ return notifier_from_errno(ret);
+}
+
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
{
struct device *cpu_dev;
@@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ mutex_init(&info->reg_lock);
+
+ info->opp_cpu = cpu;
+ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
+ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
+ if (ret) {
+ dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
+ goto out_disable_inter_clock;
+ }
+
+ info->opp_freq = clk_get_rate(info->cpu_clk);
+
/*
* If SRAM regulator is present, software "voltage tracking" is needed
* for this CPU power domain.
@@ -421,6 +495,7 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
}
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
+ dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
}
static int mtk_cpufreq_init(struct cpufreq_policy *policy)
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen,
Andrew-sh . Cheng
From this opp notifier, cpufreq should listen to opp notification and do
proper actions when receiving events of disable and voltage adjustment.
One of the user for this opp notifier is MediaTek SVS.
The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates
suitable SVS bank voltages to OPP voltage table.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++---
1 file changed, 83 insertions(+), 8 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index fe205eca657d..06d80ee06bbf 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
int intermediate_voltage;
bool need_voltage_tracking;
int pre_vproc;
+ /* Avoid race condition for regulators between notify and policy */
+ struct mutex reg_lock;
+ struct notifier_block opp_nb;
+ unsigned int opp_cpu;
+ unsigned long opp_freq;
const struct mtk_cpufreq_platform_data *soc_data;
int vtrack_max;
};
@@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
pre_freq_hz = clk_get_rate(cpu_clk);
+ mutex_lock(&info->reg_lock);
+
if (unlikely(info->pre_vproc <= 0))
pre_vproc = regulator_get_voltage(info->proc_reg);
else
@@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
dev_err(cpu_dev,
"cpu%d: failed to scale up voltage!\n", policy->cpu);
mtk_cpufreq_set_voltage(info, pre_vproc);
- return ret;
+ goto out;
}
}
@@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
dev_err(cpu_dev,
"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
mtk_cpufreq_set_voltage(info, pre_vproc);
- WARN_ON(1);
- return ret;
+ goto out;
}
/* Set the original PLL to target rate. */
@@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
clk_set_parent(cpu_clk, armpll);
mtk_cpufreq_set_voltage(info, pre_vproc);
- return ret;
+ goto out;
}
/* Set parent of CPU clock back to the original PLL. */
@@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
dev_err(cpu_dev,
"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
mtk_cpufreq_set_voltage(info, inter_vproc);
- WARN_ON(1);
- return ret;
+ goto out;
}
/*
@@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
clk_set_parent(cpu_clk, info->inter_clk);
clk_set_rate(armpll, pre_freq_hz);
clk_set_parent(cpu_clk, armpll);
- return ret;
+ goto out;
}
}
- return 0;
+ info->opp_freq = freq_hz;
+
+out:
+ mutex_unlock(&info->reg_lock);
+
+ return ret;
}
#define DYNAMIC_POWER "dynamic-power-coefficient"
+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct dev_pm_opp *new_opp;
+ struct mtk_cpu_dvfs_info *info;
+ unsigned long freq, volt;
+ struct cpufreq_policy *policy;
+ int ret = 0;
+
+ info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ mutex_lock(&info->reg_lock);
+ if (info->opp_freq == freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ ret = mtk_cpufreq_set_voltage(info, volt);
+ if (ret)
+ dev_err(info->cpu_dev,
+ "failed to scale voltage: %d\n", ret);
+ }
+ mutex_unlock(&info->reg_lock);
+ } else if (event == OPP_EVENT_DISABLE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ /* case of current opp item is disabled */
+ if (info->opp_freq == freq) {
+ freq = 1;
+ new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
+ &freq);
+ if (IS_ERR(new_opp)) {
+ dev_err(info->cpu_dev,
+ "all opp items are disabled\n");
+ ret = PTR_ERR(new_opp);
+ return notifier_from_errno(ret);
+ }
+
+ dev_pm_opp_put(new_opp);
+ policy = cpufreq_cpu_get(info->opp_cpu);
+ if (policy) {
+ cpufreq_driver_target(policy, freq / 1000,
+ CPUFREQ_RELATION_L);
+ cpufreq_cpu_put(policy);
+ }
+ }
+ }
+
+ return notifier_from_errno(ret);
+}
+
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
{
struct device *cpu_dev;
@@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ mutex_init(&info->reg_lock);
+
+ info->opp_cpu = cpu;
+ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
+ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
+ if (ret) {
+ dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
+ goto out_disable_inter_clock;
+ }
+
+ info->opp_freq = clk_get_rate(info->cpu_clk);
+
/*
* If SRAM regulator is present, software "voltage tracking" is needed
* for this CPU power domain.
@@ -421,6 +495,7 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
}
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
+ dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
}
static int mtk_cpufreq_init(struct cpufreq_policy *policy)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen,
Andrew-sh . Cheng
From this opp notifier, cpufreq should listen to opp notification and do
proper actions when receiving events of disable and voltage adjustment.
One of the user for this opp notifier is MediaTek SVS.
The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates
suitable SVS bank voltages to OPP voltage table.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++---
1 file changed, 83 insertions(+), 8 deletions(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index fe205eca657d..06d80ee06bbf 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
int intermediate_voltage;
bool need_voltage_tracking;
int pre_vproc;
+ /* Avoid race condition for regulators between notify and policy */
+ struct mutex reg_lock;
+ struct notifier_block opp_nb;
+ unsigned int opp_cpu;
+ unsigned long opp_freq;
const struct mtk_cpufreq_platform_data *soc_data;
int vtrack_max;
};
@@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
pre_freq_hz = clk_get_rate(cpu_clk);
+ mutex_lock(&info->reg_lock);
+
if (unlikely(info->pre_vproc <= 0))
pre_vproc = regulator_get_voltage(info->proc_reg);
else
@@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
dev_err(cpu_dev,
"cpu%d: failed to scale up voltage!\n", policy->cpu);
mtk_cpufreq_set_voltage(info, pre_vproc);
- return ret;
+ goto out;
}
}
@@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
dev_err(cpu_dev,
"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
mtk_cpufreq_set_voltage(info, pre_vproc);
- WARN_ON(1);
- return ret;
+ goto out;
}
/* Set the original PLL to target rate. */
@@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
"cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
clk_set_parent(cpu_clk, armpll);
mtk_cpufreq_set_voltage(info, pre_vproc);
- return ret;
+ goto out;
}
/* Set parent of CPU clock back to the original PLL. */
@@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
dev_err(cpu_dev,
"cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
mtk_cpufreq_set_voltage(info, inter_vproc);
- WARN_ON(1);
- return ret;
+ goto out;
}
/*
@@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
clk_set_parent(cpu_clk, info->inter_clk);
clk_set_rate(armpll, pre_freq_hz);
clk_set_parent(cpu_clk, armpll);
- return ret;
+ goto out;
}
}
- return 0;
+ info->opp_freq = freq_hz;
+
+out:
+ mutex_unlock(&info->reg_lock);
+
+ return ret;
}
#define DYNAMIC_POWER "dynamic-power-coefficient"
+static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct dev_pm_opp *new_opp;
+ struct mtk_cpu_dvfs_info *info;
+ unsigned long freq, volt;
+ struct cpufreq_policy *policy;
+ int ret = 0;
+
+ info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ mutex_lock(&info->reg_lock);
+ if (info->opp_freq == freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ ret = mtk_cpufreq_set_voltage(info, volt);
+ if (ret)
+ dev_err(info->cpu_dev,
+ "failed to scale voltage: %d\n", ret);
+ }
+ mutex_unlock(&info->reg_lock);
+ } else if (event == OPP_EVENT_DISABLE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ /* case of current opp item is disabled */
+ if (info->opp_freq == freq) {
+ freq = 1;
+ new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
+ &freq);
+ if (IS_ERR(new_opp)) {
+ dev_err(info->cpu_dev,
+ "all opp items are disabled\n");
+ ret = PTR_ERR(new_opp);
+ return notifier_from_errno(ret);
+ }
+
+ dev_pm_opp_put(new_opp);
+ policy = cpufreq_cpu_get(info->opp_cpu);
+ if (policy) {
+ cpufreq_driver_target(policy, freq / 1000,
+ CPUFREQ_RELATION_L);
+ cpufreq_cpu_put(policy);
+ }
+ }
+ }
+
+ return notifier_from_errno(ret);
+}
+
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
{
struct device *cpu_dev;
@@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ mutex_init(&info->reg_lock);
+
+ info->opp_cpu = cpu;
+ info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
+ ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
+ if (ret) {
+ dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
+ goto out_disable_inter_clock;
+ }
+
+ info->opp_freq = clk_get_rate(info->cpu_clk);
+
/*
* If SRAM regulator is present, software "voltage tracking" is needed
* for this CPU power domain.
@@ -421,6 +495,7 @@ static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
}
dev_pm_opp_of_cpumask_remove_table(&info->cpus);
+ dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
}
static int mtk_cpufreq_init(struct cpufreq_policy *policy)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-06 1:46 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 1:46 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> From this opp notifier, cpufreq should listen to opp notification and
> do
Hello Viresh,
There is still ">" in this patch...
I think the root cause could be the "From" word in the beginning of
this message.
I will not use "From" in next version..
BRs,
Rex
> proper actions when receiving events of disable and voltage
> adjustment.
>
> One of the user for this opp notifier is MediaTek SVS.
> The MediaTek Smart Voltage Scaling (SVS) is a hardware which
> calculates
> suitable SVS bank voltages to OPP voltage table.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++-
> --
> 1 file changed, 83 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> b/drivers/cpufreq/mediatek-cpufreq.c
> index fe205eca657d..06d80ee06bbf 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> int intermediate_voltage;
> bool need_voltage_tracking;
> int pre_vproc;
> + /* Avoid race condition for regulators between notify and
> policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + unsigned int opp_cpu;
> + unsigned long opp_freq;
> const struct mtk_cpufreq_platform_data *soc_data;
> int vtrack_max;
> };
> @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
>
> pre_freq_hz = clk_get_rate(cpu_clk);
>
> + mutex_lock(&info->reg_lock);
> +
> if (unlikely(info->pre_vproc <= 0))
> pre_vproc = regulator_get_voltage(info->proc_reg);
> else
> @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to scale up voltage!\n",
> policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
> }
>
> @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n",
> policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /* Set the original PLL to target rate. */
> @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> "cpu%d: failed to scale cpu clock rate!\n",
> policy->cpu);
> clk_set_parent(cpu_clk, armpll);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
>
> /* Set parent of CPU clock back to the original PLL. */
> @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n",
> policy->cpu);
> mtk_cpufreq_set_voltage(info, inter_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /*
> @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> clk_set_parent(cpu_clk, info->inter_clk);
> clk_set_rate(armpll, pre_freq_hz);
> clk_set_parent(cpu_clk, armpll);
> - return ret;
> + goto out;
> }
> }
>
> - return 0;
> + info->opp_freq = freq_hz;
> +
> +out:
> + mutex_unlock(&info->reg_lock);
> +
> + return ret;
> }
>
> #define DYNAMIC_POWER "dynamic-power-coefficient"
>
> +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct dev_pm_opp *new_opp;
> + struct mtk_cpu_dvfs_info *info;
> + unsigned long freq, volt;
> + struct cpufreq_policy *policy;
> + int ret = 0;
> +
> + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&info->reg_lock);
> + if (info->opp_freq == freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + ret = mtk_cpufreq_set_voltage(info, volt);
> + if (ret)
> + dev_err(info->cpu_dev,
> + "failed to scale voltage:
> %d\n", ret);
> + }
> + mutex_unlock(&info->reg_lock);
> + } else if (event == OPP_EVENT_DISABLE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + /* case of current opp item is disabled */
> + if (info->opp_freq == freq) {
> + freq = 1;
> + new_opp = dev_pm_opp_find_freq_ceil(info-
> >cpu_dev,
> + &freq);
> + if (IS_ERR(new_opp)) {
> + dev_err(info->cpu_dev,
> + "all opp items are
> disabled\n");
> + ret = PTR_ERR(new_opp);
> + return notifier_from_errno(ret);
> + }
> +
> + dev_pm_opp_put(new_opp);
> + policy = cpufreq_cpu_get(info->opp_cpu);
> + if (policy) {
> + cpufreq_driver_target(policy, freq /
> 1000,
> + CPUFREQ_RELATION_
> L);
> + cpufreq_cpu_put(policy);
> + }
> + }
> + }
> +
> + return notifier_from_errno(ret);
> +}
> +
> static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info,
> int cpu)
> {
> struct device *cpu_dev;
> @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct
> mtk_cpu_dvfs_info *info, int cpu)
> info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> dev_pm_opp_put(opp);
>
> + mutex_init(&info->reg_lock);
> +
> + info->opp_cpu = cpu;
> + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> + if (ret) {
> + dev_err(cpu_dev, "cpu%d: failed to register opp
> notifier\n", cpu);
> + goto out_disable_inter_clock;
> + }
> +
> + info->opp_freq = clk_get_rate(info->cpu_clk);
> +
> /*
> * If SRAM regulator is present, software "voltage tracking" is
> needed
> * for this CPU power domain.
> @@ -421,6 +495,7 @@ static void mtk_cpu_dvfs_info_release(struct
> mtk_cpu_dvfs_info *info)
> }
>
> dev_pm_opp_of_cpumask_remove_table(&info->cpus);
> + dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
> }
>
> static int mtk_cpufreq_init(struct cpufreq_policy *policy)
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 1:46 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 1:46 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> From this opp notifier, cpufreq should listen to opp notification and
> do
Hello Viresh,
There is still ">" in this patch...
I think the root cause could be the "From" word in the beginning of
this message.
I will not use "From" in next version..
BRs,
Rex
> proper actions when receiving events of disable and voltage
> adjustment.
>
> One of the user for this opp notifier is MediaTek SVS.
> The MediaTek Smart Voltage Scaling (SVS) is a hardware which
> calculates
> suitable SVS bank voltages to OPP voltage table.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++-
> --
> 1 file changed, 83 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> b/drivers/cpufreq/mediatek-cpufreq.c
> index fe205eca657d..06d80ee06bbf 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> int intermediate_voltage;
> bool need_voltage_tracking;
> int pre_vproc;
> + /* Avoid race condition for regulators between notify and
> policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + unsigned int opp_cpu;
> + unsigned long opp_freq;
> const struct mtk_cpufreq_platform_data *soc_data;
> int vtrack_max;
> };
> @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
>
> pre_freq_hz = clk_get_rate(cpu_clk);
>
> + mutex_lock(&info->reg_lock);
> +
> if (unlikely(info->pre_vproc <= 0))
> pre_vproc = regulator_get_voltage(info->proc_reg);
> else
> @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to scale up voltage!\n",
> policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
> }
>
> @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n",
> policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /* Set the original PLL to target rate. */
> @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> "cpu%d: failed to scale cpu clock rate!\n",
> policy->cpu);
> clk_set_parent(cpu_clk, armpll);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
>
> /* Set parent of CPU clock back to the original PLL. */
> @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n",
> policy->cpu);
> mtk_cpufreq_set_voltage(info, inter_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /*
> @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> clk_set_parent(cpu_clk, info->inter_clk);
> clk_set_rate(armpll, pre_freq_hz);
> clk_set_parent(cpu_clk, armpll);
> - return ret;
> + goto out;
> }
> }
>
> - return 0;
> + info->opp_freq = freq_hz;
> +
> +out:
> + mutex_unlock(&info->reg_lock);
> +
> + return ret;
> }
>
> #define DYNAMIC_POWER "dynamic-power-coefficient"
>
> +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct dev_pm_opp *new_opp;
> + struct mtk_cpu_dvfs_info *info;
> + unsigned long freq, volt;
> + struct cpufreq_policy *policy;
> + int ret = 0;
> +
> + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&info->reg_lock);
> + if (info->opp_freq == freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + ret = mtk_cpufreq_set_voltage(info, volt);
> + if (ret)
> + dev_err(info->cpu_dev,
> + "failed to scale voltage:
> %d\n", ret);
> + }
> + mutex_unlock(&info->reg_lock);
> + } else if (event == OPP_EVENT_DISABLE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + /* case of current opp item is disabled */
> + if (info->opp_freq == freq) {
> + freq = 1;
> + new_opp = dev_pm_opp_find_freq_ceil(info-
> >cpu_dev,
> + &freq);
> + if (IS_ERR(new_opp)) {
> + dev_err(info->cpu_dev,
> + "all opp items are
> disabled\n");
> + ret = PTR_ERR(new_opp);
> + return notifier_from_errno(ret);
> + }
> +
> + dev_pm_opp_put(new_opp);
> + policy = cpufreq_cpu_get(info->opp_cpu);
> + if (policy) {
> + cpufreq_driver_target(policy, freq /
> 1000,
> + CPUFREQ_RELATION_
> L);
> + cpufreq_cpu_put(policy);
> + }
> + }
> + }
> +
> + return notifier_from_errno(ret);
> +}
> +
> static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info,
> int cpu)
> {
> struct device *cpu_dev;
> @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct
> mtk_cpu_dvfs_info *info, int cpu)
> info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> dev_pm_opp_put(opp);
>
> + mutex_init(&info->reg_lock);
> +
> + info->opp_cpu = cpu;
> + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> + if (ret) {
> + dev_err(cpu_dev, "cpu%d: failed to register opp
> notifier\n", cpu);
> + goto out_disable_inter_clock;
> + }
> +
> + info->opp_freq = clk_get_rate(info->cpu_clk);
> +
> /*
> * If SRAM regulator is present, software "voltage tracking" is
> needed
> * for this CPU power domain.
> @@ -421,6 +495,7 @@ static void mtk_cpu_dvfs_info_release(struct
> mtk_cpu_dvfs_info *info)
> }
>
> dev_pm_opp_of_cpumask_remove_table(&info->cpus);
> + dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
> }
>
> static int mtk_cpufreq_init(struct cpufreq_policy *policy)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 1:46 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 1:46 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> From this opp notifier, cpufreq should listen to opp notification and
> do
Hello Viresh,
There is still ">" in this patch...
I think the root cause could be the "From" word in the beginning of
this message.
I will not use "From" in next version..
BRs,
Rex
> proper actions when receiving events of disable and voltage
> adjustment.
>
> One of the user for this opp notifier is MediaTek SVS.
> The MediaTek Smart Voltage Scaling (SVS) is a hardware which
> calculates
> suitable SVS bank voltages to OPP voltage table.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++-
> --
> 1 file changed, 83 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> b/drivers/cpufreq/mediatek-cpufreq.c
> index fe205eca657d..06d80ee06bbf 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> int intermediate_voltage;
> bool need_voltage_tracking;
> int pre_vproc;
> + /* Avoid race condition for regulators between notify and
> policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + unsigned int opp_cpu;
> + unsigned long opp_freq;
> const struct mtk_cpufreq_platform_data *soc_data;
> int vtrack_max;
> };
> @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
>
> pre_freq_hz = clk_get_rate(cpu_clk);
>
> + mutex_lock(&info->reg_lock);
> +
> if (unlikely(info->pre_vproc <= 0))
> pre_vproc = regulator_get_voltage(info->proc_reg);
> else
> @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to scale up voltage!\n",
> policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
> }
>
> @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n",
> policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /* Set the original PLL to target rate. */
> @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> "cpu%d: failed to scale cpu clock rate!\n",
> policy->cpu);
> clk_set_parent(cpu_clk, armpll);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
>
> /* Set parent of CPU clock back to the original PLL. */
> @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n",
> policy->cpu);
> mtk_cpufreq_set_voltage(info, inter_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /*
> @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
> cpufreq_policy *policy,
> clk_set_parent(cpu_clk, info->inter_clk);
> clk_set_rate(armpll, pre_freq_hz);
> clk_set_parent(cpu_clk, armpll);
> - return ret;
> + goto out;
> }
> }
>
> - return 0;
> + info->opp_freq = freq_hz;
> +
> +out:
> + mutex_unlock(&info->reg_lock);
> +
> + return ret;
> }
>
> #define DYNAMIC_POWER "dynamic-power-coefficient"
>
> +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct dev_pm_opp *new_opp;
> + struct mtk_cpu_dvfs_info *info;
> + unsigned long freq, volt;
> + struct cpufreq_policy *policy;
> + int ret = 0;
> +
> + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&info->reg_lock);
> + if (info->opp_freq == freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + ret = mtk_cpufreq_set_voltage(info, volt);
> + if (ret)
> + dev_err(info->cpu_dev,
> + "failed to scale voltage:
> %d\n", ret);
> + }
> + mutex_unlock(&info->reg_lock);
> + } else if (event == OPP_EVENT_DISABLE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + /* case of current opp item is disabled */
> + if (info->opp_freq == freq) {
> + freq = 1;
> + new_opp = dev_pm_opp_find_freq_ceil(info-
> >cpu_dev,
> + &freq);
> + if (IS_ERR(new_opp)) {
> + dev_err(info->cpu_dev,
> + "all opp items are
> disabled\n");
> + ret = PTR_ERR(new_opp);
> + return notifier_from_errno(ret);
> + }
> +
> + dev_pm_opp_put(new_opp);
> + policy = cpufreq_cpu_get(info->opp_cpu);
> + if (policy) {
> + cpufreq_driver_target(policy, freq /
> 1000,
> + CPUFREQ_RELATION_
> L);
> + cpufreq_cpu_put(policy);
> + }
> + }
> + }
> +
> + return notifier_from_errno(ret);
> +}
> +
> static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info,
> int cpu)
> {
> struct device *cpu_dev;
> @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct
> mtk_cpu_dvfs_info *info, int cpu)
> info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> dev_pm_opp_put(opp);
>
> + mutex_init(&info->reg_lock);
> +
> + info->opp_cpu = cpu;
> + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> + if (ret) {
> + dev_err(cpu_dev, "cpu%d: failed to register opp
> notifier\n", cpu);
> + goto out_disable_inter_clock;
> + }
> +
> + info->opp_freq = clk_get_rate(info->cpu_clk);
> +
> /*
> * If SRAM regulator is present, software "voltage tracking" is
> needed
> * for this CPU power domain.
> @@ -421,6 +495,7 @@ static void mtk_cpu_dvfs_info_release(struct
> mtk_cpu_dvfs_info *info)
> }
>
> dev_pm_opp_of_cpumask_remove_table(&info->cpus);
> + dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
> }
>
> static int mtk_cpufreq_init(struct cpufreq_policy *policy)
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
2022-05-06 1:46 ` Rex-BC Chen
(?)
@ 2022-05-06 3:22 ` Chen-Yu Tsai
-1 siblings, 0 replies; 96+ messages in thread
From: Chen-Yu Tsai @ 2022-05-06 3:22 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Fri, May 6, 2022 at 9:56 AM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
>
> On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> > From this opp notifier, cpufreq should listen to opp notification and
> > do
>
> Hello Viresh,
>
> There is still ">" in this patch...
> I think the root cause could be the "From" word in the beginning of
> this message.
> I will not use "From" in next version..
Could this be a bug in lore?
I'm not seeing this extra ">" in either the email in my inbox, viewed
raw, nor the patch downloaded from patchwork [1].
ChenYu
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220505115226.20130-6-rex-bc.chen@mediatek.com/mbox/
>
> BRs,
> Rex
>
> > proper actions when receiving events of disable and voltage
> > adjustment.
> >
> > One of the user for this opp notifier is MediaTek SVS.
> > The MediaTek Smart Voltage Scaling (SVS) is a hardware which
> > calculates
> > suitable SVS bank voltages to OPP voltage table.
> >
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++-
> > --
> > 1 file changed, 83 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> > b/drivers/cpufreq/mediatek-cpufreq.c
> > index fe205eca657d..06d80ee06bbf 100644
> > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> > int intermediate_voltage;
> > bool need_voltage_tracking;
> > int pre_vproc;
> > + /* Avoid race condition for regulators between notify and
> > policy */
> > + struct mutex reg_lock;
> > + struct notifier_block opp_nb;
> > + unsigned int opp_cpu;
> > + unsigned long opp_freq;
> > const struct mtk_cpufreq_platform_data *soc_data;
> > int vtrack_max;
> > };
> > @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> >
> > pre_freq_hz = clk_get_rate(cpu_clk);
> >
> > + mutex_lock(&info->reg_lock);
> > +
> > if (unlikely(info->pre_vproc <= 0))
> > pre_vproc = regulator_get_voltage(info->proc_reg);
> > else
> > @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to scale up voltage!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set the original PLL to target rate. */
> > @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > "cpu%d: failed to scale cpu clock rate!\n",
> > policy->cpu);
> > clk_set_parent(cpu_clk, armpll);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set parent of CPU clock back to the original PLL. */
> > @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, inter_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /*
> > @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > clk_set_parent(cpu_clk, info->inter_clk);
> > clk_set_rate(armpll, pre_freq_hz);
> > clk_set_parent(cpu_clk, armpll);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > - return 0;
> > + info->opp_freq = freq_hz;
> > +
> > +out:
> > + mutex_unlock(&info->reg_lock);
> > +
> > + return ret;
> > }
> >
> > #define DYNAMIC_POWER "dynamic-power-coefficient"
> >
> > +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> > + unsigned long event, void *data)
> > +{
> > + struct dev_pm_opp *opp = data;
> > + struct dev_pm_opp *new_opp;
> > + struct mtk_cpu_dvfs_info *info;
> > + unsigned long freq, volt;
> > + struct cpufreq_policy *policy;
> > + int ret = 0;
> > +
> > + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> > +
> > + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + mutex_lock(&info->reg_lock);
> > + if (info->opp_freq == freq) {
> > + volt = dev_pm_opp_get_voltage(opp);
> > + ret = mtk_cpufreq_set_voltage(info, volt);
> > + if (ret)
> > + dev_err(info->cpu_dev,
> > + "failed to scale voltage:
> > %d\n", ret);
> > + }
> > + mutex_unlock(&info->reg_lock);
> > + } else if (event == OPP_EVENT_DISABLE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + /* case of current opp item is disabled */
> > + if (info->opp_freq == freq) {
> > + freq = 1;
> > + new_opp = dev_pm_opp_find_freq_ceil(info-
> > >cpu_dev,
> > + &freq);
> > + if (IS_ERR(new_opp)) {
> > + dev_err(info->cpu_dev,
> > + "all opp items are
> > disabled\n");
> > + ret = PTR_ERR(new_opp);
> > + return notifier_from_errno(ret);
> > + }
> > +
> > + dev_pm_opp_put(new_opp);
> > + policy = cpufreq_cpu_get(info->opp_cpu);
> > + if (policy) {
> > + cpufreq_driver_target(policy, freq /
> > 1000,
> > + CPUFREQ_RELATION_
> > L);
> > + cpufreq_cpu_put(policy);
> > + }
> > + }
> > + }
> > +
> > + return notifier_from_errno(ret);
> > +}
> > +
> > static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info,
> > int cpu)
> > {
> > struct device *cpu_dev;
> > @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct
> > mtk_cpu_dvfs_info *info, int cpu)
> > info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> > dev_pm_opp_put(opp);
> >
> > + mutex_init(&info->reg_lock);
> > +
> > + info->opp_cpu = cpu;
> > + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> > + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> > + if (ret) {
> > + dev_err(cpu_dev, "cpu%d: failed to register opp
> > notifier\n", cpu);
> > + goto out_disable_inter_clock;
> > + }
> > +
> > + info->opp_freq = clk_get_rate(info->cpu_clk);
> > +
> > /*
> > * If SRAM regulator is present, software "voltage tracking" is
> > needed
> > * for this CPU power domain.
> > @@ -421,6 +495,7 @@ static void mtk_cpu_dvfs_info_release(struct
> > mtk_cpu_dvfs_info *info)
> > }
> >
> > dev_pm_opp_of_cpumask_remove_table(&info->cpus);
> > + dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
> > }
> >
> > static int mtk_cpufreq_init(struct cpufreq_policy *policy)
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 3:22 ` Chen-Yu Tsai
0 siblings, 0 replies; 96+ messages in thread
From: Chen-Yu Tsai @ 2022-05-06 3:22 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Fri, May 6, 2022 at 9:56 AM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
>
> On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> > From this opp notifier, cpufreq should listen to opp notification and
> > do
>
> Hello Viresh,
>
> There is still ">" in this patch...
> I think the root cause could be the "From" word in the beginning of
> this message.
> I will not use "From" in next version..
Could this be a bug in lore?
I'm not seeing this extra ">" in either the email in my inbox, viewed
raw, nor the patch downloaded from patchwork [1].
ChenYu
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220505115226.20130-6-rex-bc.chen@mediatek.com/mbox/
>
> BRs,
> Rex
>
> > proper actions when receiving events of disable and voltage
> > adjustment.
> >
> > One of the user for this opp notifier is MediaTek SVS.
> > The MediaTek Smart Voltage Scaling (SVS) is a hardware which
> > calculates
> > suitable SVS bank voltages to OPP voltage table.
> >
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++-
> > --
> > 1 file changed, 83 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> > b/drivers/cpufreq/mediatek-cpufreq.c
> > index fe205eca657d..06d80ee06bbf 100644
> > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> > int intermediate_voltage;
> > bool need_voltage_tracking;
> > int pre_vproc;
> > + /* Avoid race condition for regulators between notify and
> > policy */
> > + struct mutex reg_lock;
> > + struct notifier_block opp_nb;
> > + unsigned int opp_cpu;
> > + unsigned long opp_freq;
> > const struct mtk_cpufreq_platform_data *soc_data;
> > int vtrack_max;
> > };
> > @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> >
> > pre_freq_hz = clk_get_rate(cpu_clk);
> >
> > + mutex_lock(&info->reg_lock);
> > +
> > if (unlikely(info->pre_vproc <= 0))
> > pre_vproc = regulator_get_voltage(info->proc_reg);
> > else
> > @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to scale up voltage!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set the original PLL to target rate. */
> > @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > "cpu%d: failed to scale cpu clock rate!\n",
> > policy->cpu);
> > clk_set_parent(cpu_clk, armpll);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set parent of CPU clock back to the original PLL. */
> > @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, inter_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /*
> > @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > clk_set_parent(cpu_clk, info->inter_clk);
> > clk_set_rate(armpll, pre_freq_hz);
> > clk_set_parent(cpu_clk, armpll);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > - return 0;
> > + info->opp_freq = freq_hz;
> > +
> > +out:
> > + mutex_unlock(&info->reg_lock);
> > +
> > + return ret;
> > }
> >
> > #define DYNAMIC_POWER "dynamic-power-coefficient"
> >
> > +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> > + unsigned long event, void *data)
> > +{
> > + struct dev_pm_opp *opp = data;
> > + struct dev_pm_opp *new_opp;
> > + struct mtk_cpu_dvfs_info *info;
> > + unsigned long freq, volt;
> > + struct cpufreq_policy *policy;
> > + int ret = 0;
> > +
> > + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> > +
> > + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + mutex_lock(&info->reg_lock);
> > + if (info->opp_freq == freq) {
> > + volt = dev_pm_opp_get_voltage(opp);
> > + ret = mtk_cpufreq_set_voltage(info, volt);
> > + if (ret)
> > + dev_err(info->cpu_dev,
> > + "failed to scale voltage:
> > %d\n", ret);
> > + }
> > + mutex_unlock(&info->reg_lock);
> > + } else if (event == OPP_EVENT_DISABLE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + /* case of current opp item is disabled */
> > + if (info->opp_freq == freq) {
> > + freq = 1;
> > + new_opp = dev_pm_opp_find_freq_ceil(info-
> > >cpu_dev,
> > + &freq);
> > + if (IS_ERR(new_opp)) {
> > + dev_err(info->cpu_dev,
> > + "all opp items are
> > disabled\n");
> > + ret = PTR_ERR(new_opp);
> > + return notifier_from_errno(ret);
> > + }
> > +
> > + dev_pm_opp_put(new_opp);
> > + policy = cpufreq_cpu_get(info->opp_cpu);
> > + if (policy) {
> > + cpufreq_driver_target(policy, freq /
> > 1000,
> > + CPUFREQ_RELATION_
> > L);
> > + cpufreq_cpu_put(policy);
> > + }
> > + }
> > + }
> > +
> > + return notifier_from_errno(ret);
> > +}
> > +
> > static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info,
> > int cpu)
> > {
> > struct device *cpu_dev;
> > @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct
> > mtk_cpu_dvfs_info *info, int cpu)
> > info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> > dev_pm_opp_put(opp);
> >
> > + mutex_init(&info->reg_lock);
> > +
> > + info->opp_cpu = cpu;
> > + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> > + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> > + if (ret) {
> > + dev_err(cpu_dev, "cpu%d: failed to register opp
> > notifier\n", cpu);
> > + goto out_disable_inter_clock;
> > + }
> > +
> > + info->opp_freq = clk_get_rate(info->cpu_clk);
> > +
> > /*
> > * If SRAM regulator is present, software "voltage tracking" is
> > needed
> > * for this CPU power domain.
> > @@ -421,6 +495,7 @@ static void mtk_cpu_dvfs_info_release(struct
> > mtk_cpu_dvfs_info *info)
> > }
> >
> > dev_pm_opp_of_cpumask_remove_table(&info->cpus);
> > + dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
> > }
> >
> > static int mtk_cpufreq_init(struct cpufreq_policy *policy)
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 3:22 ` Chen-Yu Tsai
0 siblings, 0 replies; 96+ messages in thread
From: Chen-Yu Tsai @ 2022-05-06 3:22 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Fri, May 6, 2022 at 9:56 AM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
>
> On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> > From this opp notifier, cpufreq should listen to opp notification and
> > do
>
> Hello Viresh,
>
> There is still ">" in this patch...
> I think the root cause could be the "From" word in the beginning of
> this message.
> I will not use "From" in next version..
Could this be a bug in lore?
I'm not seeing this extra ">" in either the email in my inbox, viewed
raw, nor the patch downloaded from patchwork [1].
ChenYu
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220505115226.20130-6-rex-bc.chen@mediatek.com/mbox/
>
> BRs,
> Rex
>
> > proper actions when receiving events of disable and voltage
> > adjustment.
> >
> > One of the user for this opp notifier is MediaTek SVS.
> > The MediaTek Smart Voltage Scaling (SVS) is a hardware which
> > calculates
> > suitable SVS bank voltages to OPP voltage table.
> >
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++-
> > --
> > 1 file changed, 83 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> > b/drivers/cpufreq/mediatek-cpufreq.c
> > index fe205eca657d..06d80ee06bbf 100644
> > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> > int intermediate_voltage;
> > bool need_voltage_tracking;
> > int pre_vproc;
> > + /* Avoid race condition for regulators between notify and
> > policy */
> > + struct mutex reg_lock;
> > + struct notifier_block opp_nb;
> > + unsigned int opp_cpu;
> > + unsigned long opp_freq;
> > const struct mtk_cpufreq_platform_data *soc_data;
> > int vtrack_max;
> > };
> > @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> >
> > pre_freq_hz = clk_get_rate(cpu_clk);
> >
> > + mutex_lock(&info->reg_lock);
> > +
> > if (unlikely(info->pre_vproc <= 0))
> > pre_vproc = regulator_get_voltage(info->proc_reg);
> > else
> > @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to scale up voltage!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set the original PLL to target rate. */
> > @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > "cpu%d: failed to scale cpu clock rate!\n",
> > policy->cpu);
> > clk_set_parent(cpu_clk, armpll);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set parent of CPU clock back to the original PLL. */
> > @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, inter_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /*
> > @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > clk_set_parent(cpu_clk, info->inter_clk);
> > clk_set_rate(armpll, pre_freq_hz);
> > clk_set_parent(cpu_clk, armpll);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > - return 0;
> > + info->opp_freq = freq_hz;
> > +
> > +out:
> > + mutex_unlock(&info->reg_lock);
> > +
> > + return ret;
> > }
> >
> > #define DYNAMIC_POWER "dynamic-power-coefficient"
> >
> > +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> > + unsigned long event, void *data)
> > +{
> > + struct dev_pm_opp *opp = data;
> > + struct dev_pm_opp *new_opp;
> > + struct mtk_cpu_dvfs_info *info;
> > + unsigned long freq, volt;
> > + struct cpufreq_policy *policy;
> > + int ret = 0;
> > +
> > + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> > +
> > + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + mutex_lock(&info->reg_lock);
> > + if (info->opp_freq == freq) {
> > + volt = dev_pm_opp_get_voltage(opp);
> > + ret = mtk_cpufreq_set_voltage(info, volt);
> > + if (ret)
> > + dev_err(info->cpu_dev,
> > + "failed to scale voltage:
> > %d\n", ret);
> > + }
> > + mutex_unlock(&info->reg_lock);
> > + } else if (event == OPP_EVENT_DISABLE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + /* case of current opp item is disabled */
> > + if (info->opp_freq == freq) {
> > + freq = 1;
> > + new_opp = dev_pm_opp_find_freq_ceil(info-
> > >cpu_dev,
> > + &freq);
> > + if (IS_ERR(new_opp)) {
> > + dev_err(info->cpu_dev,
> > + "all opp items are
> > disabled\n");
> > + ret = PTR_ERR(new_opp);
> > + return notifier_from_errno(ret);
> > + }
> > +
> > + dev_pm_opp_put(new_opp);
> > + policy = cpufreq_cpu_get(info->opp_cpu);
> > + if (policy) {
> > + cpufreq_driver_target(policy, freq /
> > 1000,
> > + CPUFREQ_RELATION_
> > L);
> > + cpufreq_cpu_put(policy);
> > + }
> > + }
> > + }
> > +
> > + return notifier_from_errno(ret);
> > +}
> > +
> > static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info,
> > int cpu)
> > {
> > struct device *cpu_dev;
> > @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct
> > mtk_cpu_dvfs_info *info, int cpu)
> > info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> > dev_pm_opp_put(opp);
> >
> > + mutex_init(&info->reg_lock);
> > +
> > + info->opp_cpu = cpu;
> > + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> > + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> > + if (ret) {
> > + dev_err(cpu_dev, "cpu%d: failed to register opp
> > notifier\n", cpu);
> > + goto out_disable_inter_clock;
> > + }
> > +
> > + info->opp_freq = clk_get_rate(info->cpu_clk);
> > +
> > /*
> > * If SRAM regulator is present, software "voltage tracking" is
> > needed
> > * for this CPU power domain.
> > @@ -421,6 +495,7 @@ static void mtk_cpu_dvfs_info_release(struct
> > mtk_cpu_dvfs_info *info)
> > }
> >
> > dev_pm_opp_of_cpumask_remove_table(&info->cpus);
> > + dev_pm_opp_unregister_notifier(info->cpu_dev, &info->opp_nb);
> > }
> >
> > static int mtk_cpufreq_init(struct cpufreq_policy *policy)
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
2022-05-06 3:22 ` Chen-Yu Tsai
(?)
@ 2022-05-06 3:32 ` Viresh Kumar
-1 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 3:32 UTC (permalink / raw)
To: Chen-Yu Tsai, Konstantin Ryabitsev
Cc: Rex-BC Chen, rafael, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
+Konstantin
On 06-05-22, 11:22, Chen-Yu Tsai wrote:
> On Fri, May 6, 2022 at 9:56 AM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
> >
> > On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> > > From this opp notifier, cpufreq should listen to opp notification and
> > > do
> >
> > Hello Viresh,
> >
> > There is still ">" in this patch...
> > I think the root cause could be the "From" word in the beginning of
> > this message.
> > I will not use "From" in next version..
>
> Could this be a bug in lore?
>
> I'm not seeing this extra ">" in either the email in my inbox, viewed
> raw, nor the patch downloaded from patchwork [1].
>
>
> ChenYu
>
> [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220505115226.20130-6-rex-bc.chen@mediatek.com/mbox/
Interesting.
Konstantin, we are witnessing an additional ">" symbol in the first
line of the commit log for this particular patch for some reason.
https://lore.kernel.org/lkml/20220505115226.20130-6-rex-bc.chen@mediatek.com/raw
Any idea ?
--
viresh
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 3:32 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 3:32 UTC (permalink / raw)
To: Chen-Yu Tsai, Konstantin Ryabitsev
Cc: Rex-BC Chen, rafael, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
+Konstantin
On 06-05-22, 11:22, Chen-Yu Tsai wrote:
> On Fri, May 6, 2022 at 9:56 AM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
> >
> > On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> > > From this opp notifier, cpufreq should listen to opp notification and
> > > do
> >
> > Hello Viresh,
> >
> > There is still ">" in this patch...
> > I think the root cause could be the "From" word in the beginning of
> > this message.
> > I will not use "From" in next version..
>
> Could this be a bug in lore?
>
> I'm not seeing this extra ">" in either the email in my inbox, viewed
> raw, nor the patch downloaded from patchwork [1].
>
>
> ChenYu
>
> [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220505115226.20130-6-rex-bc.chen@mediatek.com/mbox/
Interesting.
Konstantin, we are witnessing an additional ">" symbol in the first
line of the commit log for this particular patch for some reason.
https://lore.kernel.org/lkml/20220505115226.20130-6-rex-bc.chen@mediatek.com/raw
Any idea ?
--
viresh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 3:32 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 3:32 UTC (permalink / raw)
To: Chen-Yu Tsai, Konstantin Ryabitsev
Cc: Rex-BC Chen, rafael, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
+Konstantin
On 06-05-22, 11:22, Chen-Yu Tsai wrote:
> On Fri, May 6, 2022 at 9:56 AM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
> >
> > On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> > > From this opp notifier, cpufreq should listen to opp notification and
> > > do
> >
> > Hello Viresh,
> >
> > There is still ">" in this patch...
> > I think the root cause could be the "From" word in the beginning of
> > this message.
> > I will not use "From" in next version..
>
> Could this be a bug in lore?
>
> I'm not seeing this extra ">" in either the email in my inbox, viewed
> raw, nor the patch downloaded from patchwork [1].
>
>
> ChenYu
>
> [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20220505115226.20130-6-rex-bc.chen@mediatek.com/mbox/
Interesting.
Konstantin, we are witnessing an additional ">" symbol in the first
line of the commit log for this particular patch for some reason.
https://lore.kernel.org/lkml/20220505115226.20130-6-rex-bc.chen@mediatek.com/raw
Any idea ?
--
viresh
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-06 4:15 ` Viresh Kumar
-1 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:15 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On 05-05-22, 19:52, Rex-BC Chen wrote:
> >From this opp notifier, cpufreq should listen to opp notification and do
> proper actions when receiving events of disable and voltage adjustment.
>
> One of the user for this opp notifier is MediaTek SVS.
> The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates
> suitable SVS bank voltages to OPP voltage table.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++---
> 1 file changed, 83 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> index fe205eca657d..06d80ee06bbf 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> int intermediate_voltage;
> bool need_voltage_tracking;
> int pre_vproc;
> + /* Avoid race condition for regulators between notify and policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + unsigned int opp_cpu;
> + unsigned long opp_freq;
The name opp_freq doesn't fit well, I renamed it to current_freq.
> const struct mtk_cpufreq_platform_data *soc_data;
> int vtrack_max;
> };
> @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
>
> pre_freq_hz = clk_get_rate(cpu_clk);
>
> + mutex_lock(&info->reg_lock);
> +
> if (unlikely(info->pre_vproc <= 0))
> pre_vproc = regulator_get_voltage(info->proc_reg);
> else
> @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to scale up voltage!\n", policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
> }
>
> @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /* Set the original PLL to target rate. */
> @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> "cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
> clk_set_parent(cpu_clk, armpll);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
>
> /* Set parent of CPU clock back to the original PLL. */
> @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
> mtk_cpufreq_set_voltage(info, inter_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /*
> @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> clk_set_parent(cpu_clk, info->inter_clk);
> clk_set_rate(armpll, pre_freq_hz);
> clk_set_parent(cpu_clk, armpll);
> - return ret;
> + goto out;
> }
> }
>
> - return 0;
> + info->opp_freq = freq_hz;
> +
> +out:
> + mutex_unlock(&info->reg_lock);
> +
> + return ret;
> }
>
> #define DYNAMIC_POWER "dynamic-power-coefficient"
>
> +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct dev_pm_opp *new_opp;
> + struct mtk_cpu_dvfs_info *info;
> + unsigned long freq, volt;
> + struct cpufreq_policy *policy;
> + int ret = 0;
> +
> + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&info->reg_lock);
> + if (info->opp_freq == freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + ret = mtk_cpufreq_set_voltage(info, volt);
> + if (ret)
> + dev_err(info->cpu_dev,
> + "failed to scale voltage: %d\n", ret);
> + }
> + mutex_unlock(&info->reg_lock);
> + } else if (event == OPP_EVENT_DISABLE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + /* case of current opp item is disabled */
> + if (info->opp_freq == freq) {
> + freq = 1;
> + new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
> + &freq);
> + if (IS_ERR(new_opp)) {
> + dev_err(info->cpu_dev,
> + "all opp items are disabled\n");
> + ret = PTR_ERR(new_opp);
> + return notifier_from_errno(ret);
> + }
> +
> + dev_pm_opp_put(new_opp);
> + policy = cpufreq_cpu_get(info->opp_cpu);
> + if (policy) {
> + cpufreq_driver_target(policy, freq / 1000,
> + CPUFREQ_RELATION_L);
> + cpufreq_cpu_put(policy);
> + }
> + }
> + }
> +
> + return notifier_from_errno(ret);
> +}
> +
> static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
> {
> struct device *cpu_dev;
> @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
> info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> dev_pm_opp_put(opp);
>
> + mutex_init(&info->reg_lock);
> +
> + info->opp_cpu = cpu;
> + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> + if (ret) {
> + dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
> + goto out_disable_inter_clock;
> + }
> +
> + info->opp_freq = clk_get_rate(info->cpu_clk);
This is a resource as well, which should have been initialized before
registering notifier.
Applied with above changes. Thanks.
--
viresh
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 4:15 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:15 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On 05-05-22, 19:52, Rex-BC Chen wrote:
> >From this opp notifier, cpufreq should listen to opp notification and do
> proper actions when receiving events of disable and voltage adjustment.
>
> One of the user for this opp notifier is MediaTek SVS.
> The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates
> suitable SVS bank voltages to OPP voltage table.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++---
> 1 file changed, 83 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> index fe205eca657d..06d80ee06bbf 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> int intermediate_voltage;
> bool need_voltage_tracking;
> int pre_vproc;
> + /* Avoid race condition for regulators between notify and policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + unsigned int opp_cpu;
> + unsigned long opp_freq;
The name opp_freq doesn't fit well, I renamed it to current_freq.
> const struct mtk_cpufreq_platform_data *soc_data;
> int vtrack_max;
> };
> @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
>
> pre_freq_hz = clk_get_rate(cpu_clk);
>
> + mutex_lock(&info->reg_lock);
> +
> if (unlikely(info->pre_vproc <= 0))
> pre_vproc = regulator_get_voltage(info->proc_reg);
> else
> @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to scale up voltage!\n", policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
> }
>
> @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /* Set the original PLL to target rate. */
> @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> "cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
> clk_set_parent(cpu_clk, armpll);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
>
> /* Set parent of CPU clock back to the original PLL. */
> @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
> mtk_cpufreq_set_voltage(info, inter_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /*
> @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> clk_set_parent(cpu_clk, info->inter_clk);
> clk_set_rate(armpll, pre_freq_hz);
> clk_set_parent(cpu_clk, armpll);
> - return ret;
> + goto out;
> }
> }
>
> - return 0;
> + info->opp_freq = freq_hz;
> +
> +out:
> + mutex_unlock(&info->reg_lock);
> +
> + return ret;
> }
>
> #define DYNAMIC_POWER "dynamic-power-coefficient"
>
> +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct dev_pm_opp *new_opp;
> + struct mtk_cpu_dvfs_info *info;
> + unsigned long freq, volt;
> + struct cpufreq_policy *policy;
> + int ret = 0;
> +
> + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&info->reg_lock);
> + if (info->opp_freq == freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + ret = mtk_cpufreq_set_voltage(info, volt);
> + if (ret)
> + dev_err(info->cpu_dev,
> + "failed to scale voltage: %d\n", ret);
> + }
> + mutex_unlock(&info->reg_lock);
> + } else if (event == OPP_EVENT_DISABLE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + /* case of current opp item is disabled */
> + if (info->opp_freq == freq) {
> + freq = 1;
> + new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
> + &freq);
> + if (IS_ERR(new_opp)) {
> + dev_err(info->cpu_dev,
> + "all opp items are disabled\n");
> + ret = PTR_ERR(new_opp);
> + return notifier_from_errno(ret);
> + }
> +
> + dev_pm_opp_put(new_opp);
> + policy = cpufreq_cpu_get(info->opp_cpu);
> + if (policy) {
> + cpufreq_driver_target(policy, freq / 1000,
> + CPUFREQ_RELATION_L);
> + cpufreq_cpu_put(policy);
> + }
> + }
> + }
> +
> + return notifier_from_errno(ret);
> +}
> +
> static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
> {
> struct device *cpu_dev;
> @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
> info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> dev_pm_opp_put(opp);
>
> + mutex_init(&info->reg_lock);
> +
> + info->opp_cpu = cpu;
> + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> + if (ret) {
> + dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
> + goto out_disable_inter_clock;
> + }
> +
> + info->opp_freq = clk_get_rate(info->cpu_clk);
This is a resource as well, which should have been initialized before
registering notifier.
Applied with above changes. Thanks.
--
viresh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 4:15 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:15 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On 05-05-22, 19:52, Rex-BC Chen wrote:
> >From this opp notifier, cpufreq should listen to opp notification and do
> proper actions when receiving events of disable and voltage adjustment.
>
> One of the user for this opp notifier is MediaTek SVS.
> The MediaTek Smart Voltage Scaling (SVS) is a hardware which calculates
> suitable SVS bank voltages to OPP voltage table.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/cpufreq/mediatek-cpufreq.c | 91 +++++++++++++++++++++++++++---
> 1 file changed, 83 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
> index fe205eca657d..06d80ee06bbf 100644
> --- a/drivers/cpufreq/mediatek-cpufreq.c
> +++ b/drivers/cpufreq/mediatek-cpufreq.c
> @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> int intermediate_voltage;
> bool need_voltage_tracking;
> int pre_vproc;
> + /* Avoid race condition for regulators between notify and policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + unsigned int opp_cpu;
> + unsigned long opp_freq;
The name opp_freq doesn't fit well, I renamed it to current_freq.
> const struct mtk_cpufreq_platform_data *soc_data;
> int vtrack_max;
> };
> @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
>
> pre_freq_hz = clk_get_rate(cpu_clk);
>
> + mutex_lock(&info->reg_lock);
> +
> if (unlikely(info->pre_vproc <= 0))
> pre_vproc = regulator_get_voltage(info->proc_reg);
> else
> @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to scale up voltage!\n", policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
> }
>
> @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /* Set the original PLL to target rate. */
> @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> "cpu%d: failed to scale cpu clock rate!\n", policy->cpu);
> clk_set_parent(cpu_clk, armpll);
> mtk_cpufreq_set_voltage(info, pre_vproc);
> - return ret;
> + goto out;
> }
>
> /* Set parent of CPU clock back to the original PLL. */
> @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> dev_err(cpu_dev,
> "cpu%d: failed to re-parent cpu clock!\n", policy->cpu);
> mtk_cpufreq_set_voltage(info, inter_vproc);
> - WARN_ON(1);
> - return ret;
> + goto out;
> }
>
> /*
> @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
> clk_set_parent(cpu_clk, info->inter_clk);
> clk_set_rate(armpll, pre_freq_hz);
> clk_set_parent(cpu_clk, armpll);
> - return ret;
> + goto out;
> }
> }
>
> - return 0;
> + info->opp_freq = freq_hz;
> +
> +out:
> + mutex_unlock(&info->reg_lock);
> +
> + return ret;
> }
>
> #define DYNAMIC_POWER "dynamic-power-coefficient"
>
> +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct dev_pm_opp *new_opp;
> + struct mtk_cpu_dvfs_info *info;
> + unsigned long freq, volt;
> + struct cpufreq_policy *policy;
> + int ret = 0;
> +
> + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&info->reg_lock);
> + if (info->opp_freq == freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + ret = mtk_cpufreq_set_voltage(info, volt);
> + if (ret)
> + dev_err(info->cpu_dev,
> + "failed to scale voltage: %d\n", ret);
> + }
> + mutex_unlock(&info->reg_lock);
> + } else if (event == OPP_EVENT_DISABLE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + /* case of current opp item is disabled */
> + if (info->opp_freq == freq) {
> + freq = 1;
> + new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev,
> + &freq);
> + if (IS_ERR(new_opp)) {
> + dev_err(info->cpu_dev,
> + "all opp items are disabled\n");
> + ret = PTR_ERR(new_opp);
> + return notifier_from_errno(ret);
> + }
> +
> + dev_pm_opp_put(new_opp);
> + policy = cpufreq_cpu_get(info->opp_cpu);
> + if (policy) {
> + cpufreq_driver_target(policy, freq / 1000,
> + CPUFREQ_RELATION_L);
> + cpufreq_cpu_put(policy);
> + }
> + }
> + }
> +
> + return notifier_from_errno(ret);
> +}
> +
> static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
> {
> struct device *cpu_dev;
> @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
> info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> dev_pm_opp_put(opp);
>
> + mutex_init(&info->reg_lock);
> +
> + info->opp_cpu = cpu;
> + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> + if (ret) {
> + dev_err(cpu_dev, "cpu%d: failed to register opp notifier\n", cpu);
> + goto out_disable_inter_clock;
> + }
> +
> + info->opp_freq = clk_get_rate(info->cpu_clk);
This is a resource as well, which should have been initialized before
registering notifier.
Applied with above changes. Thanks.
--
viresh
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
2022-05-06 4:15 ` Viresh Kumar
(?)
@ 2022-05-06 6:21 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 6:21 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Fri, 2022-05-06 at 09:45 +0530, Viresh Kumar wrote:
> On 05-05-22, 19:52, Rex-BC Chen wrote:
> > > From this opp notifier, cpufreq should listen to opp notification
> > > and do
> >
> > proper actions when receiving events of disable and voltage
> > adjustment.
> >
> > One of the user for this opp notifier is MediaTek SVS.
> > The MediaTek Smart Voltage Scaling (SVS) is a hardware which
> > calculates
> > suitable SVS bank voltages to OPP voltage table.
> >
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/cpufreq/mediatek-cpufreq.c | 91
> > +++++++++++++++++++++++++++---
> > 1 file changed, 83 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> > b/drivers/cpufreq/mediatek-cpufreq.c
> > index fe205eca657d..06d80ee06bbf 100644
> > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> > int intermediate_voltage;
> > bool need_voltage_tracking;
> > int pre_vproc;
> > + /* Avoid race condition for regulators between notify and
> > policy */
> > + struct mutex reg_lock;
> > + struct notifier_block opp_nb;
> > + unsigned int opp_cpu;
> > + unsigned long opp_freq;
>
> The name opp_freq doesn't fit well, I renamed it to current_freq.
>
> > const struct mtk_cpufreq_platform_data *soc_data;
> > int vtrack_max;
> > };
> > @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> >
> > pre_freq_hz = clk_get_rate(cpu_clk);
> >
> > + mutex_lock(&info->reg_lock);
> > +
> > if (unlikely(info->pre_vproc <= 0))
> > pre_vproc = regulator_get_voltage(info->proc_reg);
> > else
> > @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to scale up voltage!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set the original PLL to target rate. */
> > @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > "cpu%d: failed to scale cpu clock rate!\n",
> > policy->cpu);
> > clk_set_parent(cpu_clk, armpll);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set parent of CPU clock back to the original PLL. */
> > @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, inter_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /*
> > @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > clk_set_parent(cpu_clk, info->inter_clk);
> > clk_set_rate(armpll, pre_freq_hz);
> > clk_set_parent(cpu_clk, armpll);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > - return 0;
> > + info->opp_freq = freq_hz;
> > +
> > +out:
> > + mutex_unlock(&info->reg_lock);
> > +
> > + return ret;
> > }
> >
> > #define DYNAMIC_POWER "dynamic-power-coefficient"
> >
> > +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> > + unsigned long event, void *data)
> > +{
> > + struct dev_pm_opp *opp = data;
> > + struct dev_pm_opp *new_opp;
> > + struct mtk_cpu_dvfs_info *info;
> > + unsigned long freq, volt;
> > + struct cpufreq_policy *policy;
> > + int ret = 0;
> > +
> > + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> > +
> > + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + mutex_lock(&info->reg_lock);
> > + if (info->opp_freq == freq) {
> > + volt = dev_pm_opp_get_voltage(opp);
> > + ret = mtk_cpufreq_set_voltage(info, volt);
> > + if (ret)
> > + dev_err(info->cpu_dev,
> > + "failed to scale voltage:
> > %d\n", ret);
> > + }
> > + mutex_unlock(&info->reg_lock);
> > + } else if (event == OPP_EVENT_DISABLE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + /* case of current opp item is disabled */
> > + if (info->opp_freq == freq) {
> > + freq = 1;
> > + new_opp = dev_pm_opp_find_freq_ceil(info-
> > >cpu_dev,
> > + &freq);
> > + if (IS_ERR(new_opp)) {
> > + dev_err(info->cpu_dev,
> > + "all opp items are
> > disabled\n");
> > + ret = PTR_ERR(new_opp);
> > + return notifier_from_errno(ret);
> > + }
> > +
> > + dev_pm_opp_put(new_opp);
> > + policy = cpufreq_cpu_get(info->opp_cpu);
> > + if (policy) {
> > + cpufreq_driver_target(policy, freq /
> > 1000,
> > + CPUFREQ_RELATION_
> > L);
> > + cpufreq_cpu_put(policy);
> > + }
> > + }
> > + }
> > +
> > + return notifier_from_errno(ret);
> > +}
> > +
> > static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info,
> > int cpu)
> > {
> > struct device *cpu_dev;
> > @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct
> > mtk_cpu_dvfs_info *info, int cpu)
> > info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> > dev_pm_opp_put(opp);
> >
> > + mutex_init(&info->reg_lock);
> > +
> > + info->opp_cpu = cpu;
> > + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> > + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> > + if (ret) {
> > + dev_err(cpu_dev, "cpu%d: failed to register opp
> > notifier\n", cpu);
> > + goto out_disable_inter_clock;
> > + }
> > +
> > + info->opp_freq = clk_get_rate(info->cpu_clk);
>
> This is a resource as well, which should have been initialized before
> registering notifier.
>
> Applied with above changes. Thanks.
>
Hello Viresh,
Thanks for your help!
BRs,
Rex
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 6:21 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 6:21 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Fri, 2022-05-06 at 09:45 +0530, Viresh Kumar wrote:
> On 05-05-22, 19:52, Rex-BC Chen wrote:
> > > From this opp notifier, cpufreq should listen to opp notification
> > > and do
> >
> > proper actions when receiving events of disable and voltage
> > adjustment.
> >
> > One of the user for this opp notifier is MediaTek SVS.
> > The MediaTek Smart Voltage Scaling (SVS) is a hardware which
> > calculates
> > suitable SVS bank voltages to OPP voltage table.
> >
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/cpufreq/mediatek-cpufreq.c | 91
> > +++++++++++++++++++++++++++---
> > 1 file changed, 83 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> > b/drivers/cpufreq/mediatek-cpufreq.c
> > index fe205eca657d..06d80ee06bbf 100644
> > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> > int intermediate_voltage;
> > bool need_voltage_tracking;
> > int pre_vproc;
> > + /* Avoid race condition for regulators between notify and
> > policy */
> > + struct mutex reg_lock;
> > + struct notifier_block opp_nb;
> > + unsigned int opp_cpu;
> > + unsigned long opp_freq;
>
> The name opp_freq doesn't fit well, I renamed it to current_freq.
>
> > const struct mtk_cpufreq_platform_data *soc_data;
> > int vtrack_max;
> > };
> > @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> >
> > pre_freq_hz = clk_get_rate(cpu_clk);
> >
> > + mutex_lock(&info->reg_lock);
> > +
> > if (unlikely(info->pre_vproc <= 0))
> > pre_vproc = regulator_get_voltage(info->proc_reg);
> > else
> > @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to scale up voltage!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set the original PLL to target rate. */
> > @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > "cpu%d: failed to scale cpu clock rate!\n",
> > policy->cpu);
> > clk_set_parent(cpu_clk, armpll);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set parent of CPU clock back to the original PLL. */
> > @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, inter_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /*
> > @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > clk_set_parent(cpu_clk, info->inter_clk);
> > clk_set_rate(armpll, pre_freq_hz);
> > clk_set_parent(cpu_clk, armpll);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > - return 0;
> > + info->opp_freq = freq_hz;
> > +
> > +out:
> > + mutex_unlock(&info->reg_lock);
> > +
> > + return ret;
> > }
> >
> > #define DYNAMIC_POWER "dynamic-power-coefficient"
> >
> > +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> > + unsigned long event, void *data)
> > +{
> > + struct dev_pm_opp *opp = data;
> > + struct dev_pm_opp *new_opp;
> > + struct mtk_cpu_dvfs_info *info;
> > + unsigned long freq, volt;
> > + struct cpufreq_policy *policy;
> > + int ret = 0;
> > +
> > + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> > +
> > + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + mutex_lock(&info->reg_lock);
> > + if (info->opp_freq == freq) {
> > + volt = dev_pm_opp_get_voltage(opp);
> > + ret = mtk_cpufreq_set_voltage(info, volt);
> > + if (ret)
> > + dev_err(info->cpu_dev,
> > + "failed to scale voltage:
> > %d\n", ret);
> > + }
> > + mutex_unlock(&info->reg_lock);
> > + } else if (event == OPP_EVENT_DISABLE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + /* case of current opp item is disabled */
> > + if (info->opp_freq == freq) {
> > + freq = 1;
> > + new_opp = dev_pm_opp_find_freq_ceil(info-
> > >cpu_dev,
> > + &freq);
> > + if (IS_ERR(new_opp)) {
> > + dev_err(info->cpu_dev,
> > + "all opp items are
> > disabled\n");
> > + ret = PTR_ERR(new_opp);
> > + return notifier_from_errno(ret);
> > + }
> > +
> > + dev_pm_opp_put(new_opp);
> > + policy = cpufreq_cpu_get(info->opp_cpu);
> > + if (policy) {
> > + cpufreq_driver_target(policy, freq /
> > 1000,
> > + CPUFREQ_RELATION_
> > L);
> > + cpufreq_cpu_put(policy);
> > + }
> > + }
> > + }
> > +
> > + return notifier_from_errno(ret);
> > +}
> > +
> > static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info,
> > int cpu)
> > {
> > struct device *cpu_dev;
> > @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct
> > mtk_cpu_dvfs_info *info, int cpu)
> > info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> > dev_pm_opp_put(opp);
> >
> > + mutex_init(&info->reg_lock);
> > +
> > + info->opp_cpu = cpu;
> > + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> > + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> > + if (ret) {
> > + dev_err(cpu_dev, "cpu%d: failed to register opp
> > notifier\n", cpu);
> > + goto out_disable_inter_clock;
> > + }
> > +
> > + info->opp_freq = clk_get_rate(info->cpu_clk);
>
> This is a resource as well, which should have been initialized before
> registering notifier.
>
> Applied with above changes. Thanks.
>
Hello Viresh,
Thanks for your help!
BRs,
Rex
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 05/10] cpufreq: mediatek: Add opp notification support
@ 2022-05-06 6:21 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 6:21 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Fri, 2022-05-06 at 09:45 +0530, Viresh Kumar wrote:
> On 05-05-22, 19:52, Rex-BC Chen wrote:
> > > From this opp notifier, cpufreq should listen to opp notification
> > > and do
> >
> > proper actions when receiving events of disable and voltage
> > adjustment.
> >
> > One of the user for this opp notifier is MediaTek SVS.
> > The MediaTek Smart Voltage Scaling (SVS) is a hardware which
> > calculates
> > suitable SVS bank voltages to OPP voltage table.
> >
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > drivers/cpufreq/mediatek-cpufreq.c | 91
> > +++++++++++++++++++++++++++---
> > 1 file changed, 83 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/cpufreq/mediatek-cpufreq.c
> > b/drivers/cpufreq/mediatek-cpufreq.c
> > index fe205eca657d..06d80ee06bbf 100644
> > --- a/drivers/cpufreq/mediatek-cpufreq.c
> > +++ b/drivers/cpufreq/mediatek-cpufreq.c
> > @@ -46,6 +46,11 @@ struct mtk_cpu_dvfs_info {
> > int intermediate_voltage;
> > bool need_voltage_tracking;
> > int pre_vproc;
> > + /* Avoid race condition for regulators between notify and
> > policy */
> > + struct mutex reg_lock;
> > + struct notifier_block opp_nb;
> > + unsigned int opp_cpu;
> > + unsigned long opp_freq;
>
> The name opp_freq doesn't fit well, I renamed it to current_freq.
>
> > const struct mtk_cpufreq_platform_data *soc_data;
> > int vtrack_max;
> > };
> > @@ -182,6 +187,8 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> >
> > pre_freq_hz = clk_get_rate(cpu_clk);
> >
> > + mutex_lock(&info->reg_lock);
> > +
> > if (unlikely(info->pre_vproc <= 0))
> > pre_vproc = regulator_get_voltage(info->proc_reg);
> > else
> > @@ -214,7 +221,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to scale up voltage!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > @@ -224,8 +231,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set the original PLL to target rate. */
> > @@ -235,7 +241,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > "cpu%d: failed to scale cpu clock rate!\n",
> > policy->cpu);
> > clk_set_parent(cpu_clk, armpll);
> > mtk_cpufreq_set_voltage(info, pre_vproc);
> > - return ret;
> > + goto out;
> > }
> >
> > /* Set parent of CPU clock back to the original PLL. */
> > @@ -244,8 +250,7 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > dev_err(cpu_dev,
> > "cpu%d: failed to re-parent cpu clock!\n",
> > policy->cpu);
> > mtk_cpufreq_set_voltage(info, inter_vproc);
> > - WARN_ON(1);
> > - return ret;
> > + goto out;
> > }
> >
> > /*
> > @@ -260,15 +265,72 @@ static int mtk_cpufreq_set_target(struct
> > cpufreq_policy *policy,
> > clk_set_parent(cpu_clk, info->inter_clk);
> > clk_set_rate(armpll, pre_freq_hz);
> > clk_set_parent(cpu_clk, armpll);
> > - return ret;
> > + goto out;
> > }
> > }
> >
> > - return 0;
> > + info->opp_freq = freq_hz;
> > +
> > +out:
> > + mutex_unlock(&info->reg_lock);
> > +
> > + return ret;
> > }
> >
> > #define DYNAMIC_POWER "dynamic-power-coefficient"
> >
> > +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
> > + unsigned long event, void *data)
> > +{
> > + struct dev_pm_opp *opp = data;
> > + struct dev_pm_opp *new_opp;
> > + struct mtk_cpu_dvfs_info *info;
> > + unsigned long freq, volt;
> > + struct cpufreq_policy *policy;
> > + int ret = 0;
> > +
> > + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb);
> > +
> > + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + mutex_lock(&info->reg_lock);
> > + if (info->opp_freq == freq) {
> > + volt = dev_pm_opp_get_voltage(opp);
> > + ret = mtk_cpufreq_set_voltage(info, volt);
> > + if (ret)
> > + dev_err(info->cpu_dev,
> > + "failed to scale voltage:
> > %d\n", ret);
> > + }
> > + mutex_unlock(&info->reg_lock);
> > + } else if (event == OPP_EVENT_DISABLE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + /* case of current opp item is disabled */
> > + if (info->opp_freq == freq) {
> > + freq = 1;
> > + new_opp = dev_pm_opp_find_freq_ceil(info-
> > >cpu_dev,
> > + &freq);
> > + if (IS_ERR(new_opp)) {
> > + dev_err(info->cpu_dev,
> > + "all opp items are
> > disabled\n");
> > + ret = PTR_ERR(new_opp);
> > + return notifier_from_errno(ret);
> > + }
> > +
> > + dev_pm_opp_put(new_opp);
> > + policy = cpufreq_cpu_get(info->opp_cpu);
> > + if (policy) {
> > + cpufreq_driver_target(policy, freq /
> > 1000,
> > + CPUFREQ_RELATION_
> > L);
> > + cpufreq_cpu_put(policy);
> > + }
> > + }
> > + }
> > +
> > + return notifier_from_errno(ret);
> > +}
> > +
> > static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info,
> > int cpu)
> > {
> > struct device *cpu_dev;
> > @@ -357,6 +419,18 @@ static int mtk_cpu_dvfs_info_init(struct
> > mtk_cpu_dvfs_info *info, int cpu)
> > info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
> > dev_pm_opp_put(opp);
> >
> > + mutex_init(&info->reg_lock);
> > +
> > + info->opp_cpu = cpu;
> > + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier;
> > + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb);
> > + if (ret) {
> > + dev_err(cpu_dev, "cpu%d: failed to register opp
> > notifier\n", cpu);
> > + goto out_disable_inter_clock;
> > + }
> > +
> > + info->opp_freq = clk_get_rate(info->cpu_clk);
>
> This is a resource as well, which should have been initialized before
> registering notifier.
>
> Applied with above changes. Thanks.
>
Hello Viresh,
Thanks for your help!
BRs,
Rex
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* [PATCH v6 06/10] cpufreq: mediatek: Link CCI device to CPU
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
In some MediaTek SoCs, like MT8183, CPU and CCI share the same power
supplies. Cpufreq needs to check if CCI devfreq exists and wait until
CCI devfreq ready before scaling frequency.
Before CCI devfreq is ready, we record the voltage when booting to
kernel and use the max(cpu target voltage, booting voltage) to
prevent cpufreq adjust to the lower voltage which will cause the CCI
crash because of high frequency and low voltage.
- Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start
DVFS when CCI is ready.
- Add platform data for MT8183.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 06d80ee06bbf..5fd3c88c2a82 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data {
int proc_max_volt;
int sram_min_volt;
int sram_max_volt;
+ bool ccifreq_supported;
};
/*
@@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data {
struct mtk_cpu_dvfs_info {
struct cpumask cpus;
struct device *cpu_dev;
+ struct device *cci_dev;
struct regulator *proc_reg;
struct regulator *sram_reg;
struct clk *cpu_clk;
@@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info {
struct list_head list_head;
int intermediate_voltage;
bool need_voltage_tracking;
+ int vproc_on_boot;
int pre_vproc;
/* Avoid race condition for regulators between notify and policy */
struct mutex reg_lock;
@@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info {
unsigned long opp_freq;
const struct mtk_cpufreq_platform_data *soc_data;
int vtrack_max;
+ bool ccifreq_bound;
};
static struct platform_device *cpufreq_pdev;
@@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
return ret;
}
+static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
+{
+ struct device_link *sup_link;
+
+ if (info->ccifreq_bound)
+ return true;
+
+ sup_link = device_link_add(info->cpu_dev, info->cci_dev,
+ DL_FLAG_AUTOREMOVE_CONSUMER);
+ if (!sup_link) {
+ dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
+ return false;
+ }
+
+ if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
+ return false;
+
+ info->ccifreq_bound = true;
+
+ return true;
+}
+
static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
unsigned int index)
{
@@ -210,6 +236,14 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
vproc = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ /*
+ * If MediaTek cci is supported but is not ready, we will use the value
+ * of max(target cpu voltage, booting voltage) to prevent high freqeuncy
+ * low voltage crash.
+ */
+ if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
+ vproc = max(vproc, info->vproc_on_boot);
+
/*
* If the new voltage or the intermediate voltage is higher than the
* current voltage, scale up voltage first.
@@ -331,6 +365,23 @@ static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
return notifier_from_errno(ret);
}
+static struct device *of_get_cci(struct device *cpu_dev)
+{
+ struct device_node *np;
+ struct platform_device *pdev;
+
+ np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
+ if (IS_ERR_OR_NULL(np))
+ return NULL;
+
+ pdev = of_find_device_by_node(np);
+ of_node_put(np);
+ if (IS_ERR_OR_NULL(pdev))
+ return NULL;
+
+ return &pdev->dev;
+}
+
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
{
struct device *cpu_dev;
@@ -345,6 +396,16 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
}
info->cpu_dev = cpu_dev;
+ info->ccifreq_bound = false;
+ if (info->soc_data->ccifreq_supported) {
+ info->cci_dev = of_get_cci(info->cpu_dev);
+ if (IS_ERR_OR_NULL(info->cci_dev)) {
+ ret = PTR_ERR(info->cci_dev);
+ dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
+ return -ENODEV;
+ }
+ }
+
info->cpu_clk = clk_get(cpu_dev, "cpu");
if (IS_ERR(info->cpu_clk)) {
ret = PTR_ERR(info->cpu_clk);
@@ -408,6 +469,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
if (ret)
goto out_disable_mux_clock;
+ if (info->soc_data->ccifreq_supported) {
+ info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
+ if (info->vproc_on_boot < 0) {
+ dev_err(info->cpu_dev,
+ "invalid Vproc value: %d\n", info->vproc_on_boot);
+ goto out_disable_inter_clock;
+ }
+ }
+
/* Search a safe voltage for intermediate frequency. */
rate = clk_get_rate(info->inter_clk);
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
@@ -616,6 +686,16 @@ static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
.proc_max_volt = 1150000,
.sram_min_volt = 0,
.sram_max_volt = 1150000,
+ .ccifreq_supported = false,
+};
+
+static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1150000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+ .ccifreq_supported = true,
};
/* List of machines supported by this driver */
@@ -628,7 +708,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
{ }
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 06/10] cpufreq: mediatek: Link CCI device to CPU
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
In some MediaTek SoCs, like MT8183, CPU and CCI share the same power
supplies. Cpufreq needs to check if CCI devfreq exists and wait until
CCI devfreq ready before scaling frequency.
Before CCI devfreq is ready, we record the voltage when booting to
kernel and use the max(cpu target voltage, booting voltage) to
prevent cpufreq adjust to the lower voltage which will cause the CCI
crash because of high frequency and low voltage.
- Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start
DVFS when CCI is ready.
- Add platform data for MT8183.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 06d80ee06bbf..5fd3c88c2a82 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data {
int proc_max_volt;
int sram_min_volt;
int sram_max_volt;
+ bool ccifreq_supported;
};
/*
@@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data {
struct mtk_cpu_dvfs_info {
struct cpumask cpus;
struct device *cpu_dev;
+ struct device *cci_dev;
struct regulator *proc_reg;
struct regulator *sram_reg;
struct clk *cpu_clk;
@@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info {
struct list_head list_head;
int intermediate_voltage;
bool need_voltage_tracking;
+ int vproc_on_boot;
int pre_vproc;
/* Avoid race condition for regulators between notify and policy */
struct mutex reg_lock;
@@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info {
unsigned long opp_freq;
const struct mtk_cpufreq_platform_data *soc_data;
int vtrack_max;
+ bool ccifreq_bound;
};
static struct platform_device *cpufreq_pdev;
@@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
return ret;
}
+static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
+{
+ struct device_link *sup_link;
+
+ if (info->ccifreq_bound)
+ return true;
+
+ sup_link = device_link_add(info->cpu_dev, info->cci_dev,
+ DL_FLAG_AUTOREMOVE_CONSUMER);
+ if (!sup_link) {
+ dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
+ return false;
+ }
+
+ if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
+ return false;
+
+ info->ccifreq_bound = true;
+
+ return true;
+}
+
static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
unsigned int index)
{
@@ -210,6 +236,14 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
vproc = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ /*
+ * If MediaTek cci is supported but is not ready, we will use the value
+ * of max(target cpu voltage, booting voltage) to prevent high freqeuncy
+ * low voltage crash.
+ */
+ if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
+ vproc = max(vproc, info->vproc_on_boot);
+
/*
* If the new voltage or the intermediate voltage is higher than the
* current voltage, scale up voltage first.
@@ -331,6 +365,23 @@ static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
return notifier_from_errno(ret);
}
+static struct device *of_get_cci(struct device *cpu_dev)
+{
+ struct device_node *np;
+ struct platform_device *pdev;
+
+ np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
+ if (IS_ERR_OR_NULL(np))
+ return NULL;
+
+ pdev = of_find_device_by_node(np);
+ of_node_put(np);
+ if (IS_ERR_OR_NULL(pdev))
+ return NULL;
+
+ return &pdev->dev;
+}
+
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
{
struct device *cpu_dev;
@@ -345,6 +396,16 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
}
info->cpu_dev = cpu_dev;
+ info->ccifreq_bound = false;
+ if (info->soc_data->ccifreq_supported) {
+ info->cci_dev = of_get_cci(info->cpu_dev);
+ if (IS_ERR_OR_NULL(info->cci_dev)) {
+ ret = PTR_ERR(info->cci_dev);
+ dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
+ return -ENODEV;
+ }
+ }
+
info->cpu_clk = clk_get(cpu_dev, "cpu");
if (IS_ERR(info->cpu_clk)) {
ret = PTR_ERR(info->cpu_clk);
@@ -408,6 +469,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
if (ret)
goto out_disable_mux_clock;
+ if (info->soc_data->ccifreq_supported) {
+ info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
+ if (info->vproc_on_boot < 0) {
+ dev_err(info->cpu_dev,
+ "invalid Vproc value: %d\n", info->vproc_on_boot);
+ goto out_disable_inter_clock;
+ }
+ }
+
/* Search a safe voltage for intermediate frequency. */
rate = clk_get_rate(info->inter_clk);
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
@@ -616,6 +686,16 @@ static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
.proc_max_volt = 1150000,
.sram_min_volt = 0,
.sram_max_volt = 1150000,
+ .ccifreq_supported = false,
+};
+
+static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1150000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+ .ccifreq_supported = true,
};
/* List of machines supported by this driver */
@@ -628,7 +708,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
{ }
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 06/10] cpufreq: mediatek: Link CCI device to CPU
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
In some MediaTek SoCs, like MT8183, CPU and CCI share the same power
supplies. Cpufreq needs to check if CCI devfreq exists and wait until
CCI devfreq ready before scaling frequency.
Before CCI devfreq is ready, we record the voltage when booting to
kernel and use the max(cpu target voltage, booting voltage) to
prevent cpufreq adjust to the lower voltage which will cause the CCI
crash because of high frequency and low voltage.
- Add is_ccifreq_ready() to link CCI device to CPI, and CPU will start
DVFS when CCI is ready.
- Add platform data for MT8183.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 82 +++++++++++++++++++++++++++++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 06d80ee06bbf..5fd3c88c2a82 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -22,6 +22,7 @@ struct mtk_cpufreq_platform_data {
int proc_max_volt;
int sram_min_volt;
int sram_max_volt;
+ bool ccifreq_supported;
};
/*
@@ -38,6 +39,7 @@ struct mtk_cpufreq_platform_data {
struct mtk_cpu_dvfs_info {
struct cpumask cpus;
struct device *cpu_dev;
+ struct device *cci_dev;
struct regulator *proc_reg;
struct regulator *sram_reg;
struct clk *cpu_clk;
@@ -45,6 +47,7 @@ struct mtk_cpu_dvfs_info {
struct list_head list_head;
int intermediate_voltage;
bool need_voltage_tracking;
+ int vproc_on_boot;
int pre_vproc;
/* Avoid race condition for regulators between notify and policy */
struct mutex reg_lock;
@@ -53,6 +56,7 @@ struct mtk_cpu_dvfs_info {
unsigned long opp_freq;
const struct mtk_cpufreq_platform_data *soc_data;
int vtrack_max;
+ bool ccifreq_bound;
};
static struct platform_device *cpufreq_pdev;
@@ -171,6 +175,28 @@ static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
return ret;
}
+static bool is_ccifreq_ready(struct mtk_cpu_dvfs_info *info)
+{
+ struct device_link *sup_link;
+
+ if (info->ccifreq_bound)
+ return true;
+
+ sup_link = device_link_add(info->cpu_dev, info->cci_dev,
+ DL_FLAG_AUTOREMOVE_CONSUMER);
+ if (!sup_link) {
+ dev_err(info->cpu_dev, "cpu%d: sup_link is NULL\n", info->opp_cpu);
+ return false;
+ }
+
+ if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
+ return false;
+
+ info->ccifreq_bound = true;
+
+ return true;
+}
+
static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
unsigned int index)
{
@@ -210,6 +236,14 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
vproc = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
+ /*
+ * If MediaTek cci is supported but is not ready, we will use the value
+ * of max(target cpu voltage, booting voltage) to prevent high freqeuncy
+ * low voltage crash.
+ */
+ if (info->soc_data->ccifreq_supported && !is_ccifreq_ready(info))
+ vproc = max(vproc, info->vproc_on_boot);
+
/*
* If the new voltage or the intermediate voltage is higher than the
* current voltage, scale up voltage first.
@@ -331,6 +365,23 @@ static int mtk_cpufreq_opp_notifier(struct notifier_block *nb,
return notifier_from_errno(ret);
}
+static struct device *of_get_cci(struct device *cpu_dev)
+{
+ struct device_node *np;
+ struct platform_device *pdev;
+
+ np = of_parse_phandle(cpu_dev->of_node, "mediatek,cci", 0);
+ if (IS_ERR_OR_NULL(np))
+ return NULL;
+
+ pdev = of_find_device_by_node(np);
+ of_node_put(np);
+ if (IS_ERR_OR_NULL(pdev))
+ return NULL;
+
+ return &pdev->dev;
+}
+
static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
{
struct device *cpu_dev;
@@ -345,6 +396,16 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
}
info->cpu_dev = cpu_dev;
+ info->ccifreq_bound = false;
+ if (info->soc_data->ccifreq_supported) {
+ info->cci_dev = of_get_cci(info->cpu_dev);
+ if (IS_ERR_OR_NULL(info->cci_dev)) {
+ ret = PTR_ERR(info->cci_dev);
+ dev_err(cpu_dev, "cpu%d: failed to get cci device\n", cpu);
+ return -ENODEV;
+ }
+ }
+
info->cpu_clk = clk_get(cpu_dev, "cpu");
if (IS_ERR(info->cpu_clk)) {
ret = PTR_ERR(info->cpu_clk);
@@ -408,6 +469,15 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
if (ret)
goto out_disable_mux_clock;
+ if (info->soc_data->ccifreq_supported) {
+ info->vproc_on_boot = regulator_get_voltage(info->proc_reg);
+ if (info->vproc_on_boot < 0) {
+ dev_err(info->cpu_dev,
+ "invalid Vproc value: %d\n", info->vproc_on_boot);
+ goto out_disable_inter_clock;
+ }
+ }
+
/* Search a safe voltage for intermediate frequency. */
rate = clk_get_rate(info->inter_clk);
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
@@ -616,6 +686,16 @@ static const struct mtk_cpufreq_platform_data mt2701_platform_data = {
.proc_max_volt = 1150000,
.sram_min_volt = 0,
.sram_max_volt = 1150000,
+ .ccifreq_supported = false,
+};
+
+static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1150000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+ .ccifreq_supported = true,
};
/* List of machines supported by this driver */
@@ -628,7 +708,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
- { .compatible = "mediatek,mt8183", .data = &mt2701_platform_data },
+ { .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
{ }
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH v6 07/10] cpufreq: mediatek: Add support for MT8186
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
The platform data of MT8186 is different from previous MediaTek SoCs,
so we add a new compatible and platform data for it.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 5fd3c88c2a82..e32228bbad3d 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -698,6 +698,15 @@ static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
.ccifreq_supported = true,
};
+static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 250000,
+ .proc_max_volt = 1118750,
+ .sram_min_volt = 850000,
+ .sram_max_volt = 1118750,
+ .ccifreq_supported = true,
+};
+
/* List of machines supported by this driver */
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
@@ -709,6 +718,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
+ { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
{ }
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 07/10] cpufreq: mediatek: Add support for MT8186
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
The platform data of MT8186 is different from previous MediaTek SoCs,
so we add a new compatible and platform data for it.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 5fd3c88c2a82..e32228bbad3d 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -698,6 +698,15 @@ static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
.ccifreq_supported = true,
};
+static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 250000,
+ .proc_max_volt = 1118750,
+ .sram_min_volt = 850000,
+ .sram_max_volt = 1118750,
+ .ccifreq_supported = true,
+};
+
/* List of machines supported by this driver */
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
@@ -709,6 +718,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
+ { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
{ }
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 07/10] cpufreq: mediatek: Add support for MT8186
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
From: Jia-Wei Chang <jia-wei.chang@mediatek.com>
The platform data of MT8186 is different from previous MediaTek SoCs,
so we add a new compatible and platform data for it.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c
index 5fd3c88c2a82..e32228bbad3d 100644
--- a/drivers/cpufreq/mediatek-cpufreq.c
+++ b/drivers/cpufreq/mediatek-cpufreq.c
@@ -698,6 +698,15 @@ static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
.ccifreq_supported = true,
};
+static const struct mtk_cpufreq_platform_data mt8186_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 250000,
+ .proc_max_volt = 1118750,
+ .sram_min_volt = 850000,
+ .sram_max_volt = 1118750,
+ .ccifreq_supported = true,
+};
+
/* List of machines supported by this driver */
static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt2701", .data = &mt2701_platform_data },
@@ -709,6 +718,7 @@ static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8176", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8183", .data = &mt8183_platform_data },
+ { .compatible = "mediatek,mt8186", .data = &mt8186_platform_data },
{ .compatible = "mediatek,mt8365", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8516", .data = &mt2701_platform_data },
{ }
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread
* [PATCH v6 08/10] arm64: dts: mediatek: Add opp table and clock property for MT8183 cpufreq
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen,
Andrew-sh . Cheng
- Add cpufreq opp table.
- Add MediaTek cci opp table.
- Add property of opp table and clock fro cpufreq.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 32 +++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 270 ++++++++++++++++++++
2 files changed, 302 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index f3fd3cca23e9..8953dbf84f3e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -412,6 +412,38 @@
};
+&cpu0 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu4 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu5 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu6 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu7 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 01e650251928..cecf96b628b7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -42,6 +42,244 @@
rdma1 = &rdma1;
};
+ cluster0_opp: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp0-793000000 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <650000>;
+ required-opps = <&opp2_00>;
+ };
+ opp0-910000000 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <687500>;
+ required-opps = <&opp2_01>;
+ };
+ opp0-1014000000 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <718750>;
+ required-opps = <&opp2_02>;
+ };
+ opp0-1131000000 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <756250>;
+ required-opps = <&opp2_03>;
+ };
+ opp0-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ required-opps = <&opp2_04>;
+ };
+ opp0-1326000000 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <818750>;
+ required-opps = <&opp2_05>;
+ };
+ opp0-1417000000 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ required-opps = <&opp2_06>;
+ };
+ opp0-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <868750>;
+ required-opps = <&opp2_07>;
+ };
+ opp0-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <893750>;
+ required-opps = <&opp2_08>;
+ };
+ opp0-1625000000 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <906250>;
+ required-opps = <&opp2_09>;
+ };
+ opp0-1677000000 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ required-opps = <&opp2_10>;
+ };
+ opp0-1716000000 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <943750>;
+ required-opps = <&opp2_11>;
+ };
+ opp0-1781000000 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ required-opps = <&opp2_12>;
+ };
+ opp0-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ required-opps = <&opp2_13>;
+ };
+ opp0-1924000000 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ required-opps = <&opp2_14>;
+ };
+ opp0-1989000000 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ required-opps = <&opp2_15>;
+ }; };
+
+ cluster1_opp: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp1-793000000 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <700000>;
+ required-opps = <&opp2_00>;
+ };
+ opp1-910000000 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <725000>;
+ required-opps = <&opp2_01>;
+ };
+ opp1-1014000000 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <750000>;
+ required-opps = <&opp2_02>;
+ };
+ opp1-1131000000 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <775000>;
+ required-opps = <&opp2_03>;
+ };
+ opp1-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ required-opps = <&opp2_04>;
+ };
+ opp1-1326000000 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <825000>;
+ required-opps = <&opp2_05>;
+ };
+ opp1-1417000000 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ required-opps = <&opp2_06>;
+ };
+ opp1-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <875000>;
+ required-opps = <&opp2_07>;
+ };
+ opp1-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <900000>;
+ required-opps = <&opp2_08>;
+ };
+ opp1-1625000000 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <912500>;
+ required-opps = <&opp2_09>;
+ };
+ opp1-1677000000 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ required-opps = <&opp2_10>;
+ };
+ opp1-1716000000 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <950000>;
+ required-opps = <&opp2_11>;
+ };
+ opp1-1781000000 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ required-opps = <&opp2_12>;
+ };
+ opp1-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ required-opps = <&opp2_13>;
+ };
+ opp1-1924000000 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ required-opps = <&opp2_14>;
+ };
+ opp1-1989000000 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ required-opps = <&opp2_15>;
+ };
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp2_00: opp-273000000 {
+ opp-hz = /bits/ 64 <273000000>;
+ opp-microvolt = <650000>;
+ };
+ opp2_01: opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ opp-microvolt = <687500>;
+ };
+ opp2_02: opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>;
+ opp-microvolt = <718750>;
+ };
+ opp2_03: opp-463000000 {
+ opp-hz = /bits/ 64 <463000000>;
+ opp-microvolt = <756250>;
+ };
+ opp2_04: opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <800000>;
+ };
+ opp2_05: opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <818750>;
+ };
+ opp2_06: opp-689000000 {
+ opp-hz = /bits/ 64 <689000000>;
+ opp-microvolt = <850000>;
+ };
+ opp2_07: opp-767000000 {
+ opp-hz = /bits/ 64 <767000000>;
+ opp-microvolt = <868750>;
+ };
+ opp2_08: opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ opp-microvolt = <893750>;
+ };
+ opp2_09: opp-871000000 {
+ opp-hz = /bits/ 64 <871000000>;
+ opp-microvolt = <906250>;
+ };
+ opp2_10: opp-923000000 {
+ opp-hz = /bits/ 64 <923000000>;
+ opp-microvolt = <931250>;
+ };
+ opp2_11: opp-962000000 {
+ opp-hz = /bits/ 64 <962000000>;
+ opp-microvolt = <943750>;
+ };
+ opp2_12: opp-1027000000 {
+ opp-hz = /bits/ 64 <1027000000>;
+ opp-microvolt = <975000>;
+ };
+ opp2_13: opp-1092000000 {
+ opp-hz = /bits/ 64 <1092000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp2_14: opp-1144000000 {
+ opp-hz = /bits/ 64 <1144000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp2_15: opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -85,6 +323,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -96,6 +338,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -107,6 +353,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -118,6 +368,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -129,6 +383,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -140,6 +398,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -151,6 +413,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -162,6 +428,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 08/10] arm64: dts: mediatek: Add opp table and clock property for MT8183 cpufreq
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen,
Andrew-sh . Cheng
- Add cpufreq opp table.
- Add MediaTek cci opp table.
- Add property of opp table and clock fro cpufreq.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 32 +++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 270 ++++++++++++++++++++
2 files changed, 302 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index f3fd3cca23e9..8953dbf84f3e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -412,6 +412,38 @@
};
+&cpu0 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu4 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu5 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu6 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu7 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 01e650251928..cecf96b628b7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -42,6 +42,244 @@
rdma1 = &rdma1;
};
+ cluster0_opp: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp0-793000000 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <650000>;
+ required-opps = <&opp2_00>;
+ };
+ opp0-910000000 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <687500>;
+ required-opps = <&opp2_01>;
+ };
+ opp0-1014000000 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <718750>;
+ required-opps = <&opp2_02>;
+ };
+ opp0-1131000000 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <756250>;
+ required-opps = <&opp2_03>;
+ };
+ opp0-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ required-opps = <&opp2_04>;
+ };
+ opp0-1326000000 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <818750>;
+ required-opps = <&opp2_05>;
+ };
+ opp0-1417000000 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ required-opps = <&opp2_06>;
+ };
+ opp0-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <868750>;
+ required-opps = <&opp2_07>;
+ };
+ opp0-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <893750>;
+ required-opps = <&opp2_08>;
+ };
+ opp0-1625000000 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <906250>;
+ required-opps = <&opp2_09>;
+ };
+ opp0-1677000000 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ required-opps = <&opp2_10>;
+ };
+ opp0-1716000000 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <943750>;
+ required-opps = <&opp2_11>;
+ };
+ opp0-1781000000 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ required-opps = <&opp2_12>;
+ };
+ opp0-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ required-opps = <&opp2_13>;
+ };
+ opp0-1924000000 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ required-opps = <&opp2_14>;
+ };
+ opp0-1989000000 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ required-opps = <&opp2_15>;
+ }; };
+
+ cluster1_opp: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp1-793000000 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <700000>;
+ required-opps = <&opp2_00>;
+ };
+ opp1-910000000 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <725000>;
+ required-opps = <&opp2_01>;
+ };
+ opp1-1014000000 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <750000>;
+ required-opps = <&opp2_02>;
+ };
+ opp1-1131000000 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <775000>;
+ required-opps = <&opp2_03>;
+ };
+ opp1-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ required-opps = <&opp2_04>;
+ };
+ opp1-1326000000 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <825000>;
+ required-opps = <&opp2_05>;
+ };
+ opp1-1417000000 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ required-opps = <&opp2_06>;
+ };
+ opp1-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <875000>;
+ required-opps = <&opp2_07>;
+ };
+ opp1-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <900000>;
+ required-opps = <&opp2_08>;
+ };
+ opp1-1625000000 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <912500>;
+ required-opps = <&opp2_09>;
+ };
+ opp1-1677000000 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ required-opps = <&opp2_10>;
+ };
+ opp1-1716000000 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <950000>;
+ required-opps = <&opp2_11>;
+ };
+ opp1-1781000000 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ required-opps = <&opp2_12>;
+ };
+ opp1-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ required-opps = <&opp2_13>;
+ };
+ opp1-1924000000 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ required-opps = <&opp2_14>;
+ };
+ opp1-1989000000 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ required-opps = <&opp2_15>;
+ };
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp2_00: opp-273000000 {
+ opp-hz = /bits/ 64 <273000000>;
+ opp-microvolt = <650000>;
+ };
+ opp2_01: opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ opp-microvolt = <687500>;
+ };
+ opp2_02: opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>;
+ opp-microvolt = <718750>;
+ };
+ opp2_03: opp-463000000 {
+ opp-hz = /bits/ 64 <463000000>;
+ opp-microvolt = <756250>;
+ };
+ opp2_04: opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <800000>;
+ };
+ opp2_05: opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <818750>;
+ };
+ opp2_06: opp-689000000 {
+ opp-hz = /bits/ 64 <689000000>;
+ opp-microvolt = <850000>;
+ };
+ opp2_07: opp-767000000 {
+ opp-hz = /bits/ 64 <767000000>;
+ opp-microvolt = <868750>;
+ };
+ opp2_08: opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ opp-microvolt = <893750>;
+ };
+ opp2_09: opp-871000000 {
+ opp-hz = /bits/ 64 <871000000>;
+ opp-microvolt = <906250>;
+ };
+ opp2_10: opp-923000000 {
+ opp-hz = /bits/ 64 <923000000>;
+ opp-microvolt = <931250>;
+ };
+ opp2_11: opp-962000000 {
+ opp-hz = /bits/ 64 <962000000>;
+ opp-microvolt = <943750>;
+ };
+ opp2_12: opp-1027000000 {
+ opp-hz = /bits/ 64 <1027000000>;
+ opp-microvolt = <975000>;
+ };
+ opp2_13: opp-1092000000 {
+ opp-hz = /bits/ 64 <1092000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp2_14: opp-1144000000 {
+ opp-hz = /bits/ 64 <1144000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp2_15: opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -85,6 +323,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -96,6 +338,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -107,6 +353,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -118,6 +368,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -129,6 +383,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -140,6 +398,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -151,6 +413,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -162,6 +428,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
--
2.18.0
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^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 08/10] arm64: dts: mediatek: Add opp table and clock property for MT8183 cpufreq
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen,
Andrew-sh . Cheng
- Add cpufreq opp table.
- Add MediaTek cci opp table.
- Add property of opp table and clock fro cpufreq.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 32 +++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 270 ++++++++++++++++++++
2 files changed, 302 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index f3fd3cca23e9..8953dbf84f3e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -412,6 +412,38 @@
};
+&cpu0 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
+&cpu4 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu5 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu6 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
+&cpu7 {
+ proc-supply = <&mt6358_vproc11_reg>;
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 01e650251928..cecf96b628b7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -42,6 +42,244 @@
rdma1 = &rdma1;
};
+ cluster0_opp: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp0-793000000 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <650000>;
+ required-opps = <&opp2_00>;
+ };
+ opp0-910000000 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <687500>;
+ required-opps = <&opp2_01>;
+ };
+ opp0-1014000000 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <718750>;
+ required-opps = <&opp2_02>;
+ };
+ opp0-1131000000 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <756250>;
+ required-opps = <&opp2_03>;
+ };
+ opp0-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ required-opps = <&opp2_04>;
+ };
+ opp0-1326000000 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <818750>;
+ required-opps = <&opp2_05>;
+ };
+ opp0-1417000000 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ required-opps = <&opp2_06>;
+ };
+ opp0-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <868750>;
+ required-opps = <&opp2_07>;
+ };
+ opp0-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <893750>;
+ required-opps = <&opp2_08>;
+ };
+ opp0-1625000000 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <906250>;
+ required-opps = <&opp2_09>;
+ };
+ opp0-1677000000 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ required-opps = <&opp2_10>;
+ };
+ opp0-1716000000 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <943750>;
+ required-opps = <&opp2_11>;
+ };
+ opp0-1781000000 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ required-opps = <&opp2_12>;
+ };
+ opp0-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ required-opps = <&opp2_13>;
+ };
+ opp0-1924000000 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ required-opps = <&opp2_14>;
+ };
+ opp0-1989000000 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ required-opps = <&opp2_15>;
+ }; };
+
+ cluster1_opp: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp1-793000000 {
+ opp-hz = /bits/ 64 <793000000>;
+ opp-microvolt = <700000>;
+ required-opps = <&opp2_00>;
+ };
+ opp1-910000000 {
+ opp-hz = /bits/ 64 <910000000>;
+ opp-microvolt = <725000>;
+ required-opps = <&opp2_01>;
+ };
+ opp1-1014000000 {
+ opp-hz = /bits/ 64 <1014000000>;
+ opp-microvolt = <750000>;
+ required-opps = <&opp2_02>;
+ };
+ opp1-1131000000 {
+ opp-hz = /bits/ 64 <1131000000>;
+ opp-microvolt = <775000>;
+ required-opps = <&opp2_03>;
+ };
+ opp1-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-microvolt = <800000>;
+ required-opps = <&opp2_04>;
+ };
+ opp1-1326000000 {
+ opp-hz = /bits/ 64 <1326000000>;
+ opp-microvolt = <825000>;
+ required-opps = <&opp2_05>;
+ };
+ opp1-1417000000 {
+ opp-hz = /bits/ 64 <1417000000>;
+ opp-microvolt = <850000>;
+ required-opps = <&opp2_06>;
+ };
+ opp1-1508000000 {
+ opp-hz = /bits/ 64 <1508000000>;
+ opp-microvolt = <875000>;
+ required-opps = <&opp2_07>;
+ };
+ opp1-1586000000 {
+ opp-hz = /bits/ 64 <1586000000>;
+ opp-microvolt = <900000>;
+ required-opps = <&opp2_08>;
+ };
+ opp1-1625000000 {
+ opp-hz = /bits/ 64 <1625000000>;
+ opp-microvolt = <912500>;
+ required-opps = <&opp2_09>;
+ };
+ opp1-1677000000 {
+ opp-hz = /bits/ 64 <1677000000>;
+ opp-microvolt = <931250>;
+ required-opps = <&opp2_10>;
+ };
+ opp1-1716000000 {
+ opp-hz = /bits/ 64 <1716000000>;
+ opp-microvolt = <950000>;
+ required-opps = <&opp2_11>;
+ };
+ opp1-1781000000 {
+ opp-hz = /bits/ 64 <1781000000>;
+ opp-microvolt = <975000>;
+ required-opps = <&opp2_12>;
+ };
+ opp1-1846000000 {
+ opp-hz = /bits/ 64 <1846000000>;
+ opp-microvolt = <1000000>;
+ required-opps = <&opp2_13>;
+ };
+ opp1-1924000000 {
+ opp-hz = /bits/ 64 <1924000000>;
+ opp-microvolt = <1025000>;
+ required-opps = <&opp2_14>;
+ };
+ opp1-1989000000 {
+ opp-hz = /bits/ 64 <1989000000>;
+ opp-microvolt = <1050000>;
+ required-opps = <&opp2_15>;
+ };
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp2_00: opp-273000000 {
+ opp-hz = /bits/ 64 <273000000>;
+ opp-microvolt = <650000>;
+ };
+ opp2_01: opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ opp-microvolt = <687500>;
+ };
+ opp2_02: opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>;
+ opp-microvolt = <718750>;
+ };
+ opp2_03: opp-463000000 {
+ opp-hz = /bits/ 64 <463000000>;
+ opp-microvolt = <756250>;
+ };
+ opp2_04: opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <800000>;
+ };
+ opp2_05: opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <818750>;
+ };
+ opp2_06: opp-689000000 {
+ opp-hz = /bits/ 64 <689000000>;
+ opp-microvolt = <850000>;
+ };
+ opp2_07: opp-767000000 {
+ opp-hz = /bits/ 64 <767000000>;
+ opp-microvolt = <868750>;
+ };
+ opp2_08: opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ opp-microvolt = <893750>;
+ };
+ opp2_09: opp-871000000 {
+ opp-hz = /bits/ 64 <871000000>;
+ opp-microvolt = <906250>;
+ };
+ opp2_10: opp-923000000 {
+ opp-hz = /bits/ 64 <923000000>;
+ opp-microvolt = <931250>;
+ };
+ opp2_11: opp-962000000 {
+ opp-hz = /bits/ 64 <962000000>;
+ opp-microvolt = <943750>;
+ };
+ opp2_12: opp-1027000000 {
+ opp-hz = /bits/ 64 <1027000000>;
+ opp-microvolt = <975000>;
+ };
+ opp2_13: opp-1092000000 {
+ opp-hz = /bits/ 64 <1092000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp2_14: opp-1144000000 {
+ opp-hz = /bits/ 64 <1144000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp2_15: opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -85,6 +323,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -96,6 +338,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -107,6 +353,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -118,6 +368,10 @@
enable-method = "psci";
capacity-dmips-mhz = <741>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
+ clocks = <&mcucfg CLK_MCU_MP0_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
};
@@ -129,6 +383,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -140,6 +398,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -151,6 +413,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
@@ -162,6 +428,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
+ clocks = <&mcucfg CLK_MCU_MP2_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
};
--
2.18.0
_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread* Re: [PATCH v6 08/10] arm64: dts: mediatek: Add opp table and clock property for MT8183 cpufreq
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-12 6:11 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-12 6:11 UTC (permalink / raw)
To: matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng, rafael,
viresh.kumar, robh+dt, krzk+dt
On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> - Add cpufreq opp table.
> - Add MediaTek cci opp table.
> - Add property of opp table and clock fro cpufreq.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 32 +++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 270
> ++++++++++++++++++++
> 2 files changed, 302 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index f3fd3cca23e9..8953dbf84f3e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -412,6 +412,38 @@
>
> };
>
> +&cpu0 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu1 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu2 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu3 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu4 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu5 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu6 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu7 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> &uart0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 01e650251928..cecf96b628b7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -42,6 +42,244 @@
> rdma1 = &rdma1;
> };
>
> + cluster0_opp: opp-table-cluster0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp0-793000000 {
> + opp-hz = /bits/ 64 <793000000>;
> + opp-microvolt = <650000>;
> + required-opps = <&opp2_00>;
> + };
> + opp0-910000000 {
> + opp-hz = /bits/ 64 <910000000>;
> + opp-microvolt = <687500>;
> + required-opps = <&opp2_01>;
> + };
> + opp0-1014000000 {
> + opp-hz = /bits/ 64 <1014000000>;
> + opp-microvolt = <718750>;
> + required-opps = <&opp2_02>;
> + };
> + opp0-1131000000 {
> + opp-hz = /bits/ 64 <1131000000>;
> + opp-microvolt = <756250>;
> + required-opps = <&opp2_03>;
> + };
> + opp0-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <800000>;
> + required-opps = <&opp2_04>;
> + };
> + opp0-1326000000 {
> + opp-hz = /bits/ 64 <1326000000>;
> + opp-microvolt = <818750>;
> + required-opps = <&opp2_05>;
> + };
> + opp0-1417000000 {
> + opp-hz = /bits/ 64 <1417000000>;
> + opp-microvolt = <850000>;
> + required-opps = <&opp2_06>;
> + };
> + opp0-1508000000 {
> + opp-hz = /bits/ 64 <1508000000>;
> + opp-microvolt = <868750>;
> + required-opps = <&opp2_07>;
> + };
> + opp0-1586000000 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <893750>;
> + required-opps = <&opp2_08>;
> + };
> + opp0-1625000000 {
> + opp-hz = /bits/ 64 <1625000000>;
> + opp-microvolt = <906250>;
> + required-opps = <&opp2_09>;
> + };
> + opp0-1677000000 {
> + opp-hz = /bits/ 64 <1677000000>;
> + opp-microvolt = <931250>;
> + required-opps = <&opp2_10>;
> + };
> + opp0-1716000000 {
> + opp-hz = /bits/ 64 <1716000000>;
> + opp-microvolt = <943750>;
> + required-opps = <&opp2_11>;
> + };
> + opp0-1781000000 {
> + opp-hz = /bits/ 64 <1781000000>;
> + opp-microvolt = <975000>;
> + required-opps = <&opp2_12>;
> + };
> + opp0-1846000000 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <1000000>;
> + required-opps = <&opp2_13>;
> + };
> + opp0-1924000000 {
> + opp-hz = /bits/ 64 <1924000000>;
> + opp-microvolt = <1025000>;
> + required-opps = <&opp2_14>;
> + };
> + opp0-1989000000 {
> + opp-hz = /bits/ 64 <1989000000>;
> + opp-microvolt = <1050000>;
> + required-opps = <&opp2_15>;
> + }; };
> +
> + cluster1_opp: opp-table-cluster1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp1-793000000 {
> + opp-hz = /bits/ 64 <793000000>;
> + opp-microvolt = <700000>;
> + required-opps = <&opp2_00>;
> + };
> + opp1-910000000 {
> + opp-hz = /bits/ 64 <910000000>;
> + opp-microvolt = <725000>;
> + required-opps = <&opp2_01>;
> + };
> + opp1-1014000000 {
> + opp-hz = /bits/ 64 <1014000000>;
> + opp-microvolt = <750000>;
> + required-opps = <&opp2_02>;
> + };
> + opp1-1131000000 {
> + opp-hz = /bits/ 64 <1131000000>;
> + opp-microvolt = <775000>;
> + required-opps = <&opp2_03>;
> + };
> + opp1-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <800000>;
> + required-opps = <&opp2_04>;
> + };
> + opp1-1326000000 {
> + opp-hz = /bits/ 64 <1326000000>;
> + opp-microvolt = <825000>;
> + required-opps = <&opp2_05>;
> + };
> + opp1-1417000000 {
> + opp-hz = /bits/ 64 <1417000000>;
> + opp-microvolt = <850000>;
> + required-opps = <&opp2_06>;
> + };
> + opp1-1508000000 {
> + opp-hz = /bits/ 64 <1508000000>;
> + opp-microvolt = <875000>;
> + required-opps = <&opp2_07>;
> + };
> + opp1-1586000000 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <900000>;
> + required-opps = <&opp2_08>;
> + };
> + opp1-1625000000 {
> + opp-hz = /bits/ 64 <1625000000>;
> + opp-microvolt = <912500>;
> + required-opps = <&opp2_09>;
> + };
> + opp1-1677000000 {
> + opp-hz = /bits/ 64 <1677000000>;
> + opp-microvolt = <931250>;
> + required-opps = <&opp2_10>;
> + };
> + opp1-1716000000 {
> + opp-hz = /bits/ 64 <1716000000>;
> + opp-microvolt = <950000>;
> + required-opps = <&opp2_11>;
> + };
> + opp1-1781000000 {
> + opp-hz = /bits/ 64 <1781000000>;
> + opp-microvolt = <975000>;
> + required-opps = <&opp2_12>;
> + };
> + opp1-1846000000 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <1000000>;
> + required-opps = <&opp2_13>;
> + };
> + opp1-1924000000 {
> + opp-hz = /bits/ 64 <1924000000>;
> + opp-microvolt = <1025000>;
> + required-opps = <&opp2_14>;
> + };
> + opp1-1989000000 {
> + opp-hz = /bits/ 64 <1989000000>;
> + opp-microvolt = <1050000>;
> + required-opps = <&opp2_15>;
> + };
> + };
> +
> + cci_opp: opp-table-cci {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp2_00: opp-273000000 {
> + opp-hz = /bits/ 64 <273000000>;
> + opp-microvolt = <650000>;
> + };
> + opp2_01: opp-338000000 {
> + opp-hz = /bits/ 64 <338000000>;
> + opp-microvolt = <687500>;
> + };
> + opp2_02: opp-403000000 {
> + opp-hz = /bits/ 64 <403000000>;
> + opp-microvolt = <718750>;
> + };
> + opp2_03: opp-463000000 {
> + opp-hz = /bits/ 64 <463000000>;
> + opp-microvolt = <756250>;
> + };
> + opp2_04: opp-546000000 {
> + opp-hz = /bits/ 64 <546000000>;
> + opp-microvolt = <800000>;
> + };
> + opp2_05: opp-624000000 {
> + opp-hz = /bits/ 64 <624000000>;
> + opp-microvolt = <818750>;
> + };
> + opp2_06: opp-689000000 {
> + opp-hz = /bits/ 64 <689000000>;
> + opp-microvolt = <850000>;
> + };
> + opp2_07: opp-767000000 {
> + opp-hz = /bits/ 64 <767000000>;
> + opp-microvolt = <868750>;
> + };
> + opp2_08: opp-845000000 {
> + opp-hz = /bits/ 64 <845000000>;
> + opp-microvolt = <893750>;
> + };
> + opp2_09: opp-871000000 {
> + opp-hz = /bits/ 64 <871000000>;
> + opp-microvolt = <906250>;
> + };
> + opp2_10: opp-923000000 {
> + opp-hz = /bits/ 64 <923000000>;
> + opp-microvolt = <931250>;
> + };
> + opp2_11: opp-962000000 {
> + opp-hz = /bits/ 64 <962000000>;
> + opp-microvolt = <943750>;
> + };
> + opp2_12: opp-1027000000 {
> + opp-hz = /bits/ 64 <1027000000>;
> + opp-microvolt = <975000>;
> + };
> + opp2_13: opp-1092000000 {
> + opp-hz = /bits/ 64 <1092000000>;
> + opp-microvolt = <1000000>;
> + };
> + opp2_14: opp-1144000000 {
> + opp-hz = /bits/ 64 <1144000000>;
> + opp-microvolt = <1025000>;
> + };
> + opp2_15: opp-1196000000 {
> + opp-hz = /bits/ 64 <1196000000>;
> + opp-microvolt = <1050000>;
> + };
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -85,6 +323,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -96,6 +338,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -107,6 +353,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -118,6 +368,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -129,6 +383,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
> @@ -140,6 +398,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
> @@ -151,6 +413,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
> @@ -162,6 +428,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
Hello Matthias,
Could you give us some advice or ack for these patches of mt8183 dts?
The drviers and dt-binding of this series are picked by Viresh, and he
also wants to pick these three dts patches.
Thanks!
Viresh's branch:
https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git/log/?h=cpufreq/arm/linux-next
BRs,
Rex
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 08/10] arm64: dts: mediatek: Add opp table and clock property for MT8183 cpufreq
@ 2022-05-12 6:11 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-12 6:11 UTC (permalink / raw)
To: matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng, rafael,
viresh.kumar, robh+dt, krzk+dt
On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> - Add cpufreq opp table.
> - Add MediaTek cci opp table.
> - Add property of opp table and clock fro cpufreq.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 32 +++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 270
> ++++++++++++++++++++
> 2 files changed, 302 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index f3fd3cca23e9..8953dbf84f3e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -412,6 +412,38 @@
>
> };
>
> +&cpu0 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu1 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu2 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu3 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu4 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu5 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu6 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu7 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> &uart0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 01e650251928..cecf96b628b7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -42,6 +42,244 @@
> rdma1 = &rdma1;
> };
>
> + cluster0_opp: opp-table-cluster0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp0-793000000 {
> + opp-hz = /bits/ 64 <793000000>;
> + opp-microvolt = <650000>;
> + required-opps = <&opp2_00>;
> + };
> + opp0-910000000 {
> + opp-hz = /bits/ 64 <910000000>;
> + opp-microvolt = <687500>;
> + required-opps = <&opp2_01>;
> + };
> + opp0-1014000000 {
> + opp-hz = /bits/ 64 <1014000000>;
> + opp-microvolt = <718750>;
> + required-opps = <&opp2_02>;
> + };
> + opp0-1131000000 {
> + opp-hz = /bits/ 64 <1131000000>;
> + opp-microvolt = <756250>;
> + required-opps = <&opp2_03>;
> + };
> + opp0-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <800000>;
> + required-opps = <&opp2_04>;
> + };
> + opp0-1326000000 {
> + opp-hz = /bits/ 64 <1326000000>;
> + opp-microvolt = <818750>;
> + required-opps = <&opp2_05>;
> + };
> + opp0-1417000000 {
> + opp-hz = /bits/ 64 <1417000000>;
> + opp-microvolt = <850000>;
> + required-opps = <&opp2_06>;
> + };
> + opp0-1508000000 {
> + opp-hz = /bits/ 64 <1508000000>;
> + opp-microvolt = <868750>;
> + required-opps = <&opp2_07>;
> + };
> + opp0-1586000000 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <893750>;
> + required-opps = <&opp2_08>;
> + };
> + opp0-1625000000 {
> + opp-hz = /bits/ 64 <1625000000>;
> + opp-microvolt = <906250>;
> + required-opps = <&opp2_09>;
> + };
> + opp0-1677000000 {
> + opp-hz = /bits/ 64 <1677000000>;
> + opp-microvolt = <931250>;
> + required-opps = <&opp2_10>;
> + };
> + opp0-1716000000 {
> + opp-hz = /bits/ 64 <1716000000>;
> + opp-microvolt = <943750>;
> + required-opps = <&opp2_11>;
> + };
> + opp0-1781000000 {
> + opp-hz = /bits/ 64 <1781000000>;
> + opp-microvolt = <975000>;
> + required-opps = <&opp2_12>;
> + };
> + opp0-1846000000 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <1000000>;
> + required-opps = <&opp2_13>;
> + };
> + opp0-1924000000 {
> + opp-hz = /bits/ 64 <1924000000>;
> + opp-microvolt = <1025000>;
> + required-opps = <&opp2_14>;
> + };
> + opp0-1989000000 {
> + opp-hz = /bits/ 64 <1989000000>;
> + opp-microvolt = <1050000>;
> + required-opps = <&opp2_15>;
> + }; };
> +
> + cluster1_opp: opp-table-cluster1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp1-793000000 {
> + opp-hz = /bits/ 64 <793000000>;
> + opp-microvolt = <700000>;
> + required-opps = <&opp2_00>;
> + };
> + opp1-910000000 {
> + opp-hz = /bits/ 64 <910000000>;
> + opp-microvolt = <725000>;
> + required-opps = <&opp2_01>;
> + };
> + opp1-1014000000 {
> + opp-hz = /bits/ 64 <1014000000>;
> + opp-microvolt = <750000>;
> + required-opps = <&opp2_02>;
> + };
> + opp1-1131000000 {
> + opp-hz = /bits/ 64 <1131000000>;
> + opp-microvolt = <775000>;
> + required-opps = <&opp2_03>;
> + };
> + opp1-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <800000>;
> + required-opps = <&opp2_04>;
> + };
> + opp1-1326000000 {
> + opp-hz = /bits/ 64 <1326000000>;
> + opp-microvolt = <825000>;
> + required-opps = <&opp2_05>;
> + };
> + opp1-1417000000 {
> + opp-hz = /bits/ 64 <1417000000>;
> + opp-microvolt = <850000>;
> + required-opps = <&opp2_06>;
> + };
> + opp1-1508000000 {
> + opp-hz = /bits/ 64 <1508000000>;
> + opp-microvolt = <875000>;
> + required-opps = <&opp2_07>;
> + };
> + opp1-1586000000 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <900000>;
> + required-opps = <&opp2_08>;
> + };
> + opp1-1625000000 {
> + opp-hz = /bits/ 64 <1625000000>;
> + opp-microvolt = <912500>;
> + required-opps = <&opp2_09>;
> + };
> + opp1-1677000000 {
> + opp-hz = /bits/ 64 <1677000000>;
> + opp-microvolt = <931250>;
> + required-opps = <&opp2_10>;
> + };
> + opp1-1716000000 {
> + opp-hz = /bits/ 64 <1716000000>;
> + opp-microvolt = <950000>;
> + required-opps = <&opp2_11>;
> + };
> + opp1-1781000000 {
> + opp-hz = /bits/ 64 <1781000000>;
> + opp-microvolt = <975000>;
> + required-opps = <&opp2_12>;
> + };
> + opp1-1846000000 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <1000000>;
> + required-opps = <&opp2_13>;
> + };
> + opp1-1924000000 {
> + opp-hz = /bits/ 64 <1924000000>;
> + opp-microvolt = <1025000>;
> + required-opps = <&opp2_14>;
> + };
> + opp1-1989000000 {
> + opp-hz = /bits/ 64 <1989000000>;
> + opp-microvolt = <1050000>;
> + required-opps = <&opp2_15>;
> + };
> + };
> +
> + cci_opp: opp-table-cci {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp2_00: opp-273000000 {
> + opp-hz = /bits/ 64 <273000000>;
> + opp-microvolt = <650000>;
> + };
> + opp2_01: opp-338000000 {
> + opp-hz = /bits/ 64 <338000000>;
> + opp-microvolt = <687500>;
> + };
> + opp2_02: opp-403000000 {
> + opp-hz = /bits/ 64 <403000000>;
> + opp-microvolt = <718750>;
> + };
> + opp2_03: opp-463000000 {
> + opp-hz = /bits/ 64 <463000000>;
> + opp-microvolt = <756250>;
> + };
> + opp2_04: opp-546000000 {
> + opp-hz = /bits/ 64 <546000000>;
> + opp-microvolt = <800000>;
> + };
> + opp2_05: opp-624000000 {
> + opp-hz = /bits/ 64 <624000000>;
> + opp-microvolt = <818750>;
> + };
> + opp2_06: opp-689000000 {
> + opp-hz = /bits/ 64 <689000000>;
> + opp-microvolt = <850000>;
> + };
> + opp2_07: opp-767000000 {
> + opp-hz = /bits/ 64 <767000000>;
> + opp-microvolt = <868750>;
> + };
> + opp2_08: opp-845000000 {
> + opp-hz = /bits/ 64 <845000000>;
> + opp-microvolt = <893750>;
> + };
> + opp2_09: opp-871000000 {
> + opp-hz = /bits/ 64 <871000000>;
> + opp-microvolt = <906250>;
> + };
> + opp2_10: opp-923000000 {
> + opp-hz = /bits/ 64 <923000000>;
> + opp-microvolt = <931250>;
> + };
> + opp2_11: opp-962000000 {
> + opp-hz = /bits/ 64 <962000000>;
> + opp-microvolt = <943750>;
> + };
> + opp2_12: opp-1027000000 {
> + opp-hz = /bits/ 64 <1027000000>;
> + opp-microvolt = <975000>;
> + };
> + opp2_13: opp-1092000000 {
> + opp-hz = /bits/ 64 <1092000000>;
> + opp-microvolt = <1000000>;
> + };
> + opp2_14: opp-1144000000 {
> + opp-hz = /bits/ 64 <1144000000>;
> + opp-microvolt = <1025000>;
> + };
> + opp2_15: opp-1196000000 {
> + opp-hz = /bits/ 64 <1196000000>;
> + opp-microvolt = <1050000>;
> + };
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -85,6 +323,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -96,6 +338,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -107,6 +353,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -118,6 +368,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -129,6 +383,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
> @@ -140,6 +398,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
> @@ -151,6 +413,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
> @@ -162,6 +428,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
Hello Matthias,
Could you give us some advice or ack for these patches of mt8183 dts?
The drviers and dt-binding of this series are picked by Viresh, and he
also wants to pick these three dts patches.
Thanks!
Viresh's branch:
https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git/log/?h=cpufreq/arm/linux-next
BRs,
Rex
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^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 08/10] arm64: dts: mediatek: Add opp table and clock property for MT8183 cpufreq
@ 2022-05-12 6:11 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-12 6:11 UTC (permalink / raw)
To: matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng, rafael,
viresh.kumar, robh+dt, krzk+dt
On Thu, 2022-05-05 at 19:52 +0800, Rex-BC Chen wrote:
> - Add cpufreq opp table.
> - Add MediaTek cci opp table.
> - Add property of opp table and clock fro cpufreq.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 32 +++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 270
> ++++++++++++++++++++
> 2 files changed, 302 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index f3fd3cca23e9..8953dbf84f3e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -412,6 +412,38 @@
>
> };
>
> +&cpu0 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu1 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu2 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu3 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu4 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu5 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu6 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu7 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> &uart0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 01e650251928..cecf96b628b7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -42,6 +42,244 @@
> rdma1 = &rdma1;
> };
>
> + cluster0_opp: opp-table-cluster0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp0-793000000 {
> + opp-hz = /bits/ 64 <793000000>;
> + opp-microvolt = <650000>;
> + required-opps = <&opp2_00>;
> + };
> + opp0-910000000 {
> + opp-hz = /bits/ 64 <910000000>;
> + opp-microvolt = <687500>;
> + required-opps = <&opp2_01>;
> + };
> + opp0-1014000000 {
> + opp-hz = /bits/ 64 <1014000000>;
> + opp-microvolt = <718750>;
> + required-opps = <&opp2_02>;
> + };
> + opp0-1131000000 {
> + opp-hz = /bits/ 64 <1131000000>;
> + opp-microvolt = <756250>;
> + required-opps = <&opp2_03>;
> + };
> + opp0-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <800000>;
> + required-opps = <&opp2_04>;
> + };
> + opp0-1326000000 {
> + opp-hz = /bits/ 64 <1326000000>;
> + opp-microvolt = <818750>;
> + required-opps = <&opp2_05>;
> + };
> + opp0-1417000000 {
> + opp-hz = /bits/ 64 <1417000000>;
> + opp-microvolt = <850000>;
> + required-opps = <&opp2_06>;
> + };
> + opp0-1508000000 {
> + opp-hz = /bits/ 64 <1508000000>;
> + opp-microvolt = <868750>;
> + required-opps = <&opp2_07>;
> + };
> + opp0-1586000000 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <893750>;
> + required-opps = <&opp2_08>;
> + };
> + opp0-1625000000 {
> + opp-hz = /bits/ 64 <1625000000>;
> + opp-microvolt = <906250>;
> + required-opps = <&opp2_09>;
> + };
> + opp0-1677000000 {
> + opp-hz = /bits/ 64 <1677000000>;
> + opp-microvolt = <931250>;
> + required-opps = <&opp2_10>;
> + };
> + opp0-1716000000 {
> + opp-hz = /bits/ 64 <1716000000>;
> + opp-microvolt = <943750>;
> + required-opps = <&opp2_11>;
> + };
> + opp0-1781000000 {
> + opp-hz = /bits/ 64 <1781000000>;
> + opp-microvolt = <975000>;
> + required-opps = <&opp2_12>;
> + };
> + opp0-1846000000 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <1000000>;
> + required-opps = <&opp2_13>;
> + };
> + opp0-1924000000 {
> + opp-hz = /bits/ 64 <1924000000>;
> + opp-microvolt = <1025000>;
> + required-opps = <&opp2_14>;
> + };
> + opp0-1989000000 {
> + opp-hz = /bits/ 64 <1989000000>;
> + opp-microvolt = <1050000>;
> + required-opps = <&opp2_15>;
> + }; };
> +
> + cluster1_opp: opp-table-cluster1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp1-793000000 {
> + opp-hz = /bits/ 64 <793000000>;
> + opp-microvolt = <700000>;
> + required-opps = <&opp2_00>;
> + };
> + opp1-910000000 {
> + opp-hz = /bits/ 64 <910000000>;
> + opp-microvolt = <725000>;
> + required-opps = <&opp2_01>;
> + };
> + opp1-1014000000 {
> + opp-hz = /bits/ 64 <1014000000>;
> + opp-microvolt = <750000>;
> + required-opps = <&opp2_02>;
> + };
> + opp1-1131000000 {
> + opp-hz = /bits/ 64 <1131000000>;
> + opp-microvolt = <775000>;
> + required-opps = <&opp2_03>;
> + };
> + opp1-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <800000>;
> + required-opps = <&opp2_04>;
> + };
> + opp1-1326000000 {
> + opp-hz = /bits/ 64 <1326000000>;
> + opp-microvolt = <825000>;
> + required-opps = <&opp2_05>;
> + };
> + opp1-1417000000 {
> + opp-hz = /bits/ 64 <1417000000>;
> + opp-microvolt = <850000>;
> + required-opps = <&opp2_06>;
> + };
> + opp1-1508000000 {
> + opp-hz = /bits/ 64 <1508000000>;
> + opp-microvolt = <875000>;
> + required-opps = <&opp2_07>;
> + };
> + opp1-1586000000 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <900000>;
> + required-opps = <&opp2_08>;
> + };
> + opp1-1625000000 {
> + opp-hz = /bits/ 64 <1625000000>;
> + opp-microvolt = <912500>;
> + required-opps = <&opp2_09>;
> + };
> + opp1-1677000000 {
> + opp-hz = /bits/ 64 <1677000000>;
> + opp-microvolt = <931250>;
> + required-opps = <&opp2_10>;
> + };
> + opp1-1716000000 {
> + opp-hz = /bits/ 64 <1716000000>;
> + opp-microvolt = <950000>;
> + required-opps = <&opp2_11>;
> + };
> + opp1-1781000000 {
> + opp-hz = /bits/ 64 <1781000000>;
> + opp-microvolt = <975000>;
> + required-opps = <&opp2_12>;
> + };
> + opp1-1846000000 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <1000000>;
> + required-opps = <&opp2_13>;
> + };
> + opp1-1924000000 {
> + opp-hz = /bits/ 64 <1924000000>;
> + opp-microvolt = <1025000>;
> + required-opps = <&opp2_14>;
> + };
> + opp1-1989000000 {
> + opp-hz = /bits/ 64 <1989000000>;
> + opp-microvolt = <1050000>;
> + required-opps = <&opp2_15>;
> + };
> + };
> +
> + cci_opp: opp-table-cci {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp2_00: opp-273000000 {
> + opp-hz = /bits/ 64 <273000000>;
> + opp-microvolt = <650000>;
> + };
> + opp2_01: opp-338000000 {
> + opp-hz = /bits/ 64 <338000000>;
> + opp-microvolt = <687500>;
> + };
> + opp2_02: opp-403000000 {
> + opp-hz = /bits/ 64 <403000000>;
> + opp-microvolt = <718750>;
> + };
> + opp2_03: opp-463000000 {
> + opp-hz = /bits/ 64 <463000000>;
> + opp-microvolt = <756250>;
> + };
> + opp2_04: opp-546000000 {
> + opp-hz = /bits/ 64 <546000000>;
> + opp-microvolt = <800000>;
> + };
> + opp2_05: opp-624000000 {
> + opp-hz = /bits/ 64 <624000000>;
> + opp-microvolt = <818750>;
> + };
> + opp2_06: opp-689000000 {
> + opp-hz = /bits/ 64 <689000000>;
> + opp-microvolt = <850000>;
> + };
> + opp2_07: opp-767000000 {
> + opp-hz = /bits/ 64 <767000000>;
> + opp-microvolt = <868750>;
> + };
> + opp2_08: opp-845000000 {
> + opp-hz = /bits/ 64 <845000000>;
> + opp-microvolt = <893750>;
> + };
> + opp2_09: opp-871000000 {
> + opp-hz = /bits/ 64 <871000000>;
> + opp-microvolt = <906250>;
> + };
> + opp2_10: opp-923000000 {
> + opp-hz = /bits/ 64 <923000000>;
> + opp-microvolt = <931250>;
> + };
> + opp2_11: opp-962000000 {
> + opp-hz = /bits/ 64 <962000000>;
> + opp-microvolt = <943750>;
> + };
> + opp2_12: opp-1027000000 {
> + opp-hz = /bits/ 64 <1027000000>;
> + opp-microvolt = <975000>;
> + };
> + opp2_13: opp-1092000000 {
> + opp-hz = /bits/ 64 <1092000000>;
> + opp-microvolt = <1000000>;
> + };
> + opp2_14: opp-1144000000 {
> + opp-hz = /bits/ 64 <1144000000>;
> + opp-microvolt = <1025000>;
> + };
> + opp2_15: opp-1196000000 {
> + opp-hz = /bits/ 64 <1196000000>;
> + opp-microvolt = <1050000>;
> + };
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -85,6 +323,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -96,6 +338,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -107,6 +353,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -118,6 +368,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> dynamic-power-coefficient = <84>;
> #cooling-cells = <2>;
> };
> @@ -129,6 +383,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
> @@ -140,6 +398,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
> @@ -151,6 +413,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
> @@ -162,6 +428,10 @@
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> dynamic-power-coefficient = <211>;
> #cooling-cells = <2>;
> };
Hello Matthias,
Could you give us some advice or ack for these patches of mt8183 dts?
The drviers and dt-binding of this series are picked by Viresh, and he
also wants to pick these three dts patches.
Thanks!
Viresh's branch:
https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git/log/?h=cpufreq/arm/linux-next
BRs,
Rex
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen,
Andrew-sh . Cheng
Add MediaTek CCI devfreq node for MT8183.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
3 files changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 8953dbf84f3e..7ac9864db9de 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -412,6 +412,10 @@
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index 8d5bf73a9099..b035e06840e6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -230,6 +230,10 @@
status = "okay";
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index cecf96b628b7..11caf3dd85cd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -280,6 +280,13 @@
};
};
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
+ clock-names = "cci_clock";
+ operating-points-v2 = <&cci_opp>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen,
Andrew-sh . Cheng
Add MediaTek CCI devfreq node for MT8183.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
3 files changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 8953dbf84f3e..7ac9864db9de 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -412,6 +412,10 @@
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index 8d5bf73a9099..b035e06840e6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -230,6 +230,10 @@
status = "okay";
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index cecf96b628b7..11caf3dd85cd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -280,6 +280,13 @@
};
};
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
+ clock-names = "cci_clock";
+ operating-points-v2 = <&cci_opp>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen,
Andrew-sh . Cheng
Add MediaTek CCI devfreq node for MT8183.
Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
3 files changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 8953dbf84f3e..7ac9864db9de 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -412,6 +412,10 @@
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
index 8d5bf73a9099..b035e06840e6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
@@ -230,6 +230,10 @@
status = "okay";
};
+&cci {
+ proc-supply = <&mt6358_vproc12_reg>;
+};
+
&cpu0 {
proc-supply = <&mt6358_vproc12_reg>;
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index cecf96b628b7..11caf3dd85cd 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -280,6 +280,13 @@
};
};
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
+ clock-names = "cci_clock";
+ operating-points-v2 = <&cci_opp>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread* Re: [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-16 5:35 ` Chen-Yu Tsai
-1 siblings, 0 replies; 96+ messages in thread
From: Chen-Yu Tsai @ 2022-05-16 5:35 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Thu, May 5, 2022 at 8:04 PM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
>
> Add MediaTek CCI devfreq node for MT8183.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> 3 files changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index 8953dbf84f3e..7ac9864db9de 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -412,6 +412,10 @@
>
> };
>
> +&cci {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> &cpu0 {
> proc-supply = <&mt6358_vproc12_reg>;
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> index 8d5bf73a9099..b035e06840e6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> @@ -230,6 +230,10 @@
> status = "okay";
> };
>
> +&cci {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> &cpu0 {
> proc-supply = <&mt6358_vproc12_reg>;
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index cecf96b628b7..11caf3dd85cd 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -280,6 +280,13 @@
> };
> };
>
> + cci: cci {
> + compatible = "mediatek,mt8183-cci";
> + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
> + clock-names = "cci_clock";
Binding says there should be two clocks: the actual clock that drives
CCI, and a stable "intermediate" clock to switch to during clock rate
changes. So I think this should look like:
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cci", "intermediate";
ChenYu
> + operating-points-v2 = <&cci_opp>;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
@ 2022-05-16 5:35 ` Chen-Yu Tsai
0 siblings, 0 replies; 96+ messages in thread
From: Chen-Yu Tsai @ 2022-05-16 5:35 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Thu, May 5, 2022 at 8:04 PM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
>
> Add MediaTek CCI devfreq node for MT8183.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> 3 files changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index 8953dbf84f3e..7ac9864db9de 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -412,6 +412,10 @@
>
> };
>
> +&cci {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> &cpu0 {
> proc-supply = <&mt6358_vproc12_reg>;
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> index 8d5bf73a9099..b035e06840e6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> @@ -230,6 +230,10 @@
> status = "okay";
> };
>
> +&cci {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> &cpu0 {
> proc-supply = <&mt6358_vproc12_reg>;
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index cecf96b628b7..11caf3dd85cd 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -280,6 +280,13 @@
> };
> };
>
> + cci: cci {
> + compatible = "mediatek,mt8183-cci";
> + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
> + clock-names = "cci_clock";
Binding says there should be two clocks: the actual clock that drives
CCI, and a stable "intermediate" clock to switch to during clock rate
changes. So I think this should look like:
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cci", "intermediate";
ChenYu
> + operating-points-v2 = <&cci_opp>;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
@ 2022-05-16 5:35 ` Chen-Yu Tsai
0 siblings, 0 replies; 96+ messages in thread
From: Chen-Yu Tsai @ 2022-05-16 5:35 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Thu, May 5, 2022 at 8:04 PM Rex-BC Chen <rex-bc.chen@mediatek.com> wrote:
>
> Add MediaTek CCI devfreq node for MT8183.
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> 3 files changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index 8953dbf84f3e..7ac9864db9de 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -412,6 +412,10 @@
>
> };
>
> +&cci {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> &cpu0 {
> proc-supply = <&mt6358_vproc12_reg>;
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> index 8d5bf73a9099..b035e06840e6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> @@ -230,6 +230,10 @@
> status = "okay";
> };
>
> +&cci {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> &cpu0 {
> proc-supply = <&mt6358_vproc12_reg>;
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index cecf96b628b7..11caf3dd85cd 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -280,6 +280,13 @@
> };
> };
>
> + cci: cci {
> + compatible = "mediatek,mt8183-cci";
> + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
> + clock-names = "cci_clock";
Binding says there should be two clocks: the actual clock that drives
CCI, and a stable "intermediate" clock to switch to during clock rate
changes. So I think this should look like:
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cci", "intermediate";
ChenYu
> + operating-points-v2 = <&cci_opp>;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
2022-05-16 5:35 ` Chen-Yu Tsai
(?)
@ 2022-05-16 10:41 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-16 10:41 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Mon, 2022-05-16 at 13:35 +0800, Chen-Yu Tsai wrote:
> On Thu, May 5, 2022 at 8:04 PM Rex-BC Chen <rex-bc.chen@mediatek.com>
> wrote:
> >
> > Add MediaTek CCI devfreq node for MT8183.
> >
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
> > arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> > 3 files changed, 15 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > index 8953dbf84f3e..7ac9864db9de 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > @@ -412,6 +412,10 @@
> >
> > };
> >
> > +&cci {
> > + proc-supply = <&mt6358_vproc12_reg>;
> > +};
> > +
> > &cpu0 {
> > proc-supply = <&mt6358_vproc12_reg>;
> > };
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > index 8d5bf73a9099..b035e06840e6 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > @@ -230,6 +230,10 @@
> > status = "okay";
> > };
> >
> > +&cci {
> > + proc-supply = <&mt6358_vproc12_reg>;
> > +};
> > +
> > &cpu0 {
> > proc-supply = <&mt6358_vproc12_reg>;
> > };
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index cecf96b628b7..11caf3dd85cd 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -280,6 +280,13 @@
> > };
> > };
> >
> > + cci: cci {
> > + compatible = "mediatek,mt8183-cci";
> > + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
> > + clock-names = "cci_clock";
>
> Binding says there should be two clocks: the actual clock that drives
> CCI, and a stable "intermediate" clock to switch to during clock rate
> changes. So I think this should look like:
>
> clocks = <&mcucfg CLK_MCU_BUS_SEL>,
> <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> clock-names = "cci", "intermediate";
>
>
> ChenYu
>
Hello Chen-Yu,
Thanks for your reminder.
I will update this and sned next version.
BRs,
Rex
> > + operating-points-v2 = <&cci_opp>;
> > + };
> > +
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
@ 2022-05-16 10:41 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-16 10:41 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Mon, 2022-05-16 at 13:35 +0800, Chen-Yu Tsai wrote:
> On Thu, May 5, 2022 at 8:04 PM Rex-BC Chen <rex-bc.chen@mediatek.com>
> wrote:
> >
> > Add MediaTek CCI devfreq node for MT8183.
> >
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
> > arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> > 3 files changed, 15 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > index 8953dbf84f3e..7ac9864db9de 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > @@ -412,6 +412,10 @@
> >
> > };
> >
> > +&cci {
> > + proc-supply = <&mt6358_vproc12_reg>;
> > +};
> > +
> > &cpu0 {
> > proc-supply = <&mt6358_vproc12_reg>;
> > };
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > index 8d5bf73a9099..b035e06840e6 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > @@ -230,6 +230,10 @@
> > status = "okay";
> > };
> >
> > +&cci {
> > + proc-supply = <&mt6358_vproc12_reg>;
> > +};
> > +
> > &cpu0 {
> > proc-supply = <&mt6358_vproc12_reg>;
> > };
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index cecf96b628b7..11caf3dd85cd 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -280,6 +280,13 @@
> > };
> > };
> >
> > + cci: cci {
> > + compatible = "mediatek,mt8183-cci";
> > + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
> > + clock-names = "cci_clock";
>
> Binding says there should be two clocks: the actual clock that drives
> CCI, and a stable "intermediate" clock to switch to during clock rate
> changes. So I think this should look like:
>
> clocks = <&mcucfg CLK_MCU_BUS_SEL>,
> <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> clock-names = "cci", "intermediate";
>
>
> ChenYu
>
Hello Chen-Yu,
Thanks for your reminder.
I will update this and sned next version.
BRs,
Rex
> > + operating-points-v2 = <&cci_opp>;
> > + };
> > +
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread* Re: [PATCH v6 09/10] arm64: dts: mediatek: Add MediaTek CCI node for MT8183
@ 2022-05-16 10:41 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-16 10:41 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg,
jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Andrew-sh . Cheng
On Mon, 2022-05-16 at 13:35 +0800, Chen-Yu Tsai wrote:
> On Thu, May 5, 2022 at 8:04 PM Rex-BC Chen <rex-bc.chen@mediatek.com>
> wrote:
> >
> > Add MediaTek CCI devfreq node for MT8183.
> >
> > Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4 ++++
> > arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 ++++
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> > 3 files changed, 15 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > index 8953dbf84f3e..7ac9864db9de 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > @@ -412,6 +412,10 @@
> >
> > };
> >
> > +&cci {
> > + proc-supply = <&mt6358_vproc12_reg>;
> > +};
> > +
> > &cpu0 {
> > proc-supply = <&mt6358_vproc12_reg>;
> > };
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > index 8d5bf73a9099..b035e06840e6 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > @@ -230,6 +230,10 @@
> > status = "okay";
> > };
> >
> > +&cci {
> > + proc-supply = <&mt6358_vproc12_reg>;
> > +};
> > +
> > &cpu0 {
> > proc-supply = <&mt6358_vproc12_reg>;
> > };
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index cecf96b628b7..11caf3dd85cd 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -280,6 +280,13 @@
> > };
> > };
> >
> > + cci: cci {
> > + compatible = "mediatek,mt8183-cci";
> > + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
> > + clock-names = "cci_clock";
>
> Binding says there should be two clocks: the actual clock that drives
> CCI, and a stable "intermediate" clock to switch to during clock rate
> changes. So I think this should look like:
>
> clocks = <&mcucfg CLK_MCU_BUS_SEL>,
> <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> clock-names = "cci", "intermediate";
>
>
> ChenYu
>
Hello Chen-Yu,
Thanks for your reminder.
I will update this and sned next version.
BRs,
Rex
> > + operating-points-v2 = <&cci_opp>;
> > + };
> > +
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* [PATCH v6 10/10] arm64: dts: mediatek: Add mediatek,cci property for MT8183 cpufreq
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-05 11:52 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
Add mediatek,cci property to support MediaTek CCI feature.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 11caf3dd85cd..e5d4a8e0c545 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -336,6 +336,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu1: cpu@1 {
@@ -351,6 +352,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu2: cpu@2 {
@@ -366,6 +368,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu3: cpu@3 {
@@ -381,6 +384,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu4: cpu@100 {
@@ -396,6 +400,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu5: cpu@101 {
@@ -411,6 +416,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu6: cpu@102 {
@@ -426,6 +432,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu7: cpu@103 {
@@ -441,6 +448,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
idle-states {
--
2.18.0
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 10/10] arm64: dts: mediatek: Add mediatek, cci property for MT8183 cpufreq
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
Add mediatek,cci property to support MediaTek CCI feature.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 11caf3dd85cd..e5d4a8e0c545 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -336,6 +336,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu1: cpu@1 {
@@ -351,6 +352,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu2: cpu@2 {
@@ -366,6 +368,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu3: cpu@3 {
@@ -381,6 +384,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu4: cpu@100 {
@@ -396,6 +400,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu5: cpu@101 {
@@ -411,6 +416,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu6: cpu@102 {
@@ -426,6 +432,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu7: cpu@103 {
@@ -441,6 +448,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
idle-states {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 96+ messages in thread* [PATCH v6 10/10] arm64: dts: mediatek: Add mediatek, cci property for MT8183 cpufreq
@ 2022-05-05 11:52 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-05 11:52 UTC (permalink / raw)
To: rafael, viresh.kumar, robh+dt, krzk+dt, matthias.bgg
Cc: jia-wei.chang, roger.lu, hsinyi, khilman,
angelogioacchino.delregno, linux-pm, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group, Rex-BC Chen
Add mediatek,cci property to support MediaTek CCI feature.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 11caf3dd85cd..e5d4a8e0c545 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -336,6 +336,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu1: cpu@1 {
@@ -351,6 +352,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu2: cpu@2 {
@@ -366,6 +368,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu3: cpu@3 {
@@ -381,6 +384,7 @@
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu4: cpu@100 {
@@ -396,6 +400,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu5: cpu@101 {
@@ -411,6 +416,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu6: cpu@102 {
@@ -426,6 +432,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu7: cpu@103 {
@@ -441,6 +448,7 @@
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
idle-states {
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
2022-05-05 11:52 ` Rex-BC Chen
(?)
@ 2022-05-06 4:20 ` Viresh Kumar
-1 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:20 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 05-05-22, 19:52, Rex-BC Chen wrote:
> Cpufreq is a DVFS driver used for power saving to scale the clock frequency
> and supply the voltage for CPUs. This series do some cleanup for MediaTek
> cpufreq drivers and add support for MediaTek SVS[2] and MediaTek CCI
> devfreq[3] which are supported in MT8183 and MT8186.
Applied 2-5, rest of them depend on the binding and dts patches to be
Acked.
--
viresh
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-06 4:20 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:20 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 05-05-22, 19:52, Rex-BC Chen wrote:
> Cpufreq is a DVFS driver used for power saving to scale the clock frequency
> and supply the voltage for CPUs. This series do some cleanup for MediaTek
> cpufreq drivers and add support for MediaTek SVS[2] and MediaTek CCI
> devfreq[3] which are supported in MT8183 and MT8186.
Applied 2-5, rest of them depend on the binding and dts patches to be
Acked.
--
viresh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-06 4:20 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-06 4:20 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 05-05-22, 19:52, Rex-BC Chen wrote:
> Cpufreq is a DVFS driver used for power saving to scale the clock frequency
> and supply the voltage for CPUs. This series do some cleanup for MediaTek
> cpufreq drivers and add support for MediaTek SVS[2] and MediaTek CCI
> devfreq[3] which are supported in MT8183 and MT8186.
Applied 2-5, rest of them depend on the binding and dts patches to be
Acked.
--
viresh
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
2022-05-06 4:20 ` Viresh Kumar
(?)
@ 2022-05-06 6:32 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 6:32 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Fri, 2022-05-06 at 09:50 +0530, Viresh Kumar wrote:
> On 05-05-22, 19:52, Rex-BC Chen wrote:
> > Cpufreq is a DVFS driver used for power saving to scale the clock
> > frequency
> > and supply the voltage for CPUs. This series do some cleanup for
> > MediaTek
> > cpufreq drivers and add support for MediaTek SVS[2] and MediaTek
> > CCI
> > devfreq[3] which are supported in MT8183 and MT8186.
>
> Applied 2-5, rest of them depend on the binding and dts patches to be
> Acked.
>
Hello Viresh,
Thanks for accepting our patches.
As for rest patch:
The cci series [1] is still under reviewing and it depends on chanwoo's
series [2].
Therefore, I think it won't be so quick to be acked for these patches
in my series.
[1]: cci:
https://lore.kernel.org/all/20220425125546.4129-1-johnson.wang@mediatek.com/
[2]: chanwoo's passive governor support for devfreq:
https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
BRs,
Rex
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-06 6:32 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 6:32 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Fri, 2022-05-06 at 09:50 +0530, Viresh Kumar wrote:
> On 05-05-22, 19:52, Rex-BC Chen wrote:
> > Cpufreq is a DVFS driver used for power saving to scale the clock
> > frequency
> > and supply the voltage for CPUs. This series do some cleanup for
> > MediaTek
> > cpufreq drivers and add support for MediaTek SVS[2] and MediaTek
> > CCI
> > devfreq[3] which are supported in MT8183 and MT8186.
>
> Applied 2-5, rest of them depend on the binding and dts patches to be
> Acked.
>
Hello Viresh,
Thanks for accepting our patches.
As for rest patch:
The cci series [1] is still under reviewing and it depends on chanwoo's
series [2].
Therefore, I think it won't be so quick to be acked for these patches
in my series.
[1]: cci:
https://lore.kernel.org/all/20220425125546.4129-1-johnson.wang@mediatek.com/
[2]: chanwoo's passive governor support for devfreq:
https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
BRs,
Rex
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-06 6:32 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-06 6:32 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Fri, 2022-05-06 at 09:50 +0530, Viresh Kumar wrote:
> On 05-05-22, 19:52, Rex-BC Chen wrote:
> > Cpufreq is a DVFS driver used for power saving to scale the clock
> > frequency
> > and supply the voltage for CPUs. This series do some cleanup for
> > MediaTek
> > cpufreq drivers and add support for MediaTek SVS[2] and MediaTek
> > CCI
> > devfreq[3] which are supported in MT8183 and MT8186.
>
> Applied 2-5, rest of them depend on the binding and dts patches to be
> Acked.
>
Hello Viresh,
Thanks for accepting our patches.
As for rest patch:
The cci series [1] is still under reviewing and it depends on chanwoo's
series [2].
Therefore, I think it won't be so quick to be acked for these patches
in my series.
[1]: cci:
https://lore.kernel.org/all/20220425125546.4129-1-johnson.wang@mediatek.com/
[2]: chanwoo's passive governor support for devfreq:
https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
BRs,
Rex
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
2022-05-06 6:32 ` Rex-BC Chen
(?)
@ 2022-05-12 5:27 ` Viresh Kumar
-1 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-12 5:27 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 06-05-22, 14:32, Rex-BC Chen wrote:
> As for rest patch:
> The cci series [1] is still under reviewing and it depends on chanwoo's
> series [2].
> Therefore, I think it won't be so quick to be acked for these patches
> in my series.
I have applied 1, 6-7 now. I hope it is safe to apply them ? What about other
three, can you get them acked now ?
--
viresh
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-12 5:27 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-12 5:27 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 06-05-22, 14:32, Rex-BC Chen wrote:
> As for rest patch:
> The cci series [1] is still under reviewing and it depends on chanwoo's
> series [2].
> Therefore, I think it won't be so quick to be acked for these patches
> in my series.
I have applied 1, 6-7 now. I hope it is safe to apply them ? What about other
three, can you get them acked now ?
--
viresh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-12 5:27 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-12 5:27 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 06-05-22, 14:32, Rex-BC Chen wrote:
> As for rest patch:
> The cci series [1] is still under reviewing and it depends on chanwoo's
> series [2].
> Therefore, I think it won't be so quick to be acked for these patches
> in my series.
I have applied 1, 6-7 now. I hope it is safe to apply them ? What about other
three, can you get them acked now ?
--
viresh
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
2022-05-12 5:27 ` Viresh Kumar
(?)
@ 2022-05-12 5:33 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-12 5:33 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-12 at 10:57 +0530, Viresh Kumar wrote:
> On 06-05-22, 14:32, Rex-BC Chen wrote:
> > As for rest patch:
> > The cci series [1] is still under reviewing and it depends on
> > chanwoo's
> > series [2].
> > Therefore, I think it won't be so quick to be acked for these
> > patches
> > in my series.
>
> I have applied 1, 6-7 now. I hope it is safe to apply them ? What
> about other
> three, can you get them acked now ?
>
Hello Viresh,
Thanks for your help!
Matthias is not the member of mediatek, so I think we still need his
feedback for these three patches.
BRs,
Rex
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-12 5:33 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-12 5:33 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-12 at 10:57 +0530, Viresh Kumar wrote:
> On 06-05-22, 14:32, Rex-BC Chen wrote:
> > As for rest patch:
> > The cci series [1] is still under reviewing and it depends on
> > chanwoo's
> > series [2].
> > Therefore, I think it won't be so quick to be acked for these
> > patches
> > in my series.
>
> I have applied 1, 6-7 now. I hope it is safe to apply them ? What
> about other
> three, can you get them acked now ?
>
Hello Viresh,
Thanks for your help!
Matthias is not the member of mediatek, so I think we still need his
feedback for these three patches.
BRs,
Rex
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-12 5:33 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-12 5:33 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-12 at 10:57 +0530, Viresh Kumar wrote:
> On 06-05-22, 14:32, Rex-BC Chen wrote:
> > As for rest patch:
> > The cci series [1] is still under reviewing and it depends on
> > chanwoo's
> > series [2].
> > Therefore, I think it won't be so quick to be acked for these
> > patches
> > in my series.
>
> I have applied 1, 6-7 now. I hope it is safe to apply them ? What
> about other
> three, can you get them acked now ?
>
Hello Viresh,
Thanks for your help!
Matthias is not the member of mediatek, so I think we still need his
feedback for these three patches.
BRs,
Rex
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
2022-05-12 5:33 ` Rex-BC Chen
(?)
@ 2022-05-12 5:48 ` Viresh Kumar
-1 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-12 5:48 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 12-05-22, 13:33, Rex-BC Chen wrote:
> Matthias is not the member of mediatek, so I think we still need his
> feedback for these three patches.
Please ping him and ask for his feedback then.
--
viresh
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-12 5:48 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-12 5:48 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 12-05-22, 13:33, Rex-BC Chen wrote:
> Matthias is not the member of mediatek, so I think we still need his
> feedback for these three patches.
Please ping him and ask for his feedback then.
--
viresh
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-12 5:48 ` Viresh Kumar
0 siblings, 0 replies; 96+ messages in thread
From: Viresh Kumar @ 2022-05-12 5:48 UTC (permalink / raw)
To: Rex-BC Chen
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 12-05-22, 13:33, Rex-BC Chen wrote:
> Matthias is not the member of mediatek, so I think we still need his
> feedback for these three patches.
Please ping him and ask for his feedback then.
--
viresh
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
2022-05-12 5:48 ` Viresh Kumar
(?)
@ 2022-05-12 6:05 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-12 6:05 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-12 at 11:18 +0530, Viresh Kumar wrote:
> On 12-05-22, 13:33, Rex-BC Chen wrote:
> > Matthias is not the member of mediatek, so I think we still need
> > his
> > feedback for these three patches.
>
> Please ping him and ask for his feedback then.
>
ok, I will do this.
Thanks!
BRs,
Rex
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-12 6:05 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-12 6:05 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-12 at 11:18 +0530, Viresh Kumar wrote:
> On 12-05-22, 13:33, Rex-BC Chen wrote:
> > Matthias is not the member of mediatek, so I think we still need
> > his
> > feedback for these three patches.
>
> Please ping him and ask for his feedback then.
>
ok, I will do this.
Thanks!
BRs,
Rex
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-12 6:05 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-12 6:05 UTC (permalink / raw)
To: Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, matthias.bgg, jia-wei.chang, roger.lu,
hsinyi, khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-12 at 11:18 +0530, Viresh Kumar wrote:
> On 12-05-22, 13:33, Rex-BC Chen wrote:
> > Matthias is not the member of mediatek, so I think we still need
> > his
> > feedback for these three patches.
>
> Please ping him and ask for his feedback then.
>
ok, I will do this.
Thanks!
BRs,
Rex
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
2022-05-12 6:05 ` Rex-BC Chen
(?)
@ 2022-05-17 9:57 ` Matthias Brugger
-1 siblings, 0 replies; 96+ messages in thread
From: Matthias Brugger @ 2022-05-17 9:57 UTC (permalink / raw)
To: Rex-BC Chen, Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, jia-wei.chang, roger.lu, hsinyi,
khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 12/05/2022 08:05, Rex-BC Chen wrote:
> On Thu, 2022-05-12 at 11:18 +0530, Viresh Kumar wrote:
>> On 12-05-22, 13:33, Rex-BC Chen wrote:
>>> Matthias is not the member of mediatek, so I think we still need
>>> his
>>> feedback for these three patches.
>>
>> Please ping him and ask for his feedback then.
>>
>
> ok, I will do this.
> Thanks!
>
Sorry for the late reply. I'll take the DTS patches through my tree. As I'm late
to the game this will be for v5.20.
Regards,
Matthias
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-17 9:57 ` Matthias Brugger
0 siblings, 0 replies; 96+ messages in thread
From: Matthias Brugger @ 2022-05-17 9:57 UTC (permalink / raw)
To: Rex-BC Chen, Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, jia-wei.chang, roger.lu, hsinyi,
khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 12/05/2022 08:05, Rex-BC Chen wrote:
> On Thu, 2022-05-12 at 11:18 +0530, Viresh Kumar wrote:
>> On 12-05-22, 13:33, Rex-BC Chen wrote:
>>> Matthias is not the member of mediatek, so I think we still need
>>> his
>>> feedback for these three patches.
>>
>> Please ping him and ask for his feedback then.
>>
>
> ok, I will do this.
> Thanks!
>
Sorry for the late reply. I'll take the DTS patches through my tree. As I'm late
to the game this will be for v5.20.
Regards,
Matthias
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-17 9:57 ` Matthias Brugger
0 siblings, 0 replies; 96+ messages in thread
From: Matthias Brugger @ 2022-05-17 9:57 UTC (permalink / raw)
To: Rex-BC Chen, Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, jia-wei.chang, roger.lu, hsinyi,
khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On 12/05/2022 08:05, Rex-BC Chen wrote:
> On Thu, 2022-05-12 at 11:18 +0530, Viresh Kumar wrote:
>> On 12-05-22, 13:33, Rex-BC Chen wrote:
>>> Matthias is not the member of mediatek, so I think we still need
>>> his
>>> feedback for these three patches.
>>
>> Please ping him and ask for his feedback then.
>>
>
> ok, I will do this.
> Thanks!
>
Sorry for the late reply. I'll take the DTS patches through my tree. As I'm late
to the game this will be for v5.20.
Regards,
Matthias
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
2022-05-17 9:57 ` Matthias Brugger
(?)
@ 2022-05-17 10:02 ` Rex-BC Chen
-1 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-17 10:02 UTC (permalink / raw)
To: Matthias Brugger, Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, jia-wei.chang, roger.lu, hsinyi,
khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Tue, 2022-05-17 at 11:57 +0200, Matthias Brugger wrote:
>
> On 12/05/2022 08:05, Rex-BC Chen wrote:
> > On Thu, 2022-05-12 at 11:18 +0530, Viresh Kumar wrote:
> > > On 12-05-22, 13:33, Rex-BC Chen wrote:
> > > > Matthias is not the member of mediatek, so I think we still
> > > > need
> > > > his
> > > > feedback for these three patches.
> > >
> > > Please ping him and ask for his feedback then.
> > >
> >
> > ok, I will do this.
> > Thanks!
> >
>
> Sorry for the late reply. I'll take the DTS patches through my tree.
> As I'm late
> to the game this will be for v5.20.
>
> Regards,
> Matthias
Hello Matthias,
Thanks for you reply,
I send another version for this series.
Please refer to this:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=641933
BRs,
Rex
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-17 10:02 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-17 10:02 UTC (permalink / raw)
To: Matthias Brugger, Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, jia-wei.chang, roger.lu, hsinyi,
khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Tue, 2022-05-17 at 11:57 +0200, Matthias Brugger wrote:
>
> On 12/05/2022 08:05, Rex-BC Chen wrote:
> > On Thu, 2022-05-12 at 11:18 +0530, Viresh Kumar wrote:
> > > On 12-05-22, 13:33, Rex-BC Chen wrote:
> > > > Matthias is not the member of mediatek, so I think we still
> > > > need
> > > > his
> > > > feedback for these three patches.
> > >
> > > Please ping him and ask for his feedback then.
> > >
> >
> > ok, I will do this.
> > Thanks!
> >
>
> Sorry for the late reply. I'll take the DTS patches through my tree.
> As I'm late
> to the game this will be for v5.20.
>
> Regards,
> Matthias
Hello Matthias,
Thanks for you reply,
I send another version for this series.
Please refer to this:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=641933
BRs,
Rex
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 96+ messages in thread
* Re: [PATCH v6 00/10] cpufreq: mediatek: Cleanup and support MT8183 and MT8186
@ 2022-05-17 10:02 ` Rex-BC Chen
0 siblings, 0 replies; 96+ messages in thread
From: Rex-BC Chen @ 2022-05-17 10:02 UTC (permalink / raw)
To: Matthias Brugger, Viresh Kumar
Cc: rafael, robh+dt, krzk+dt, jia-wei.chang, roger.lu, hsinyi,
khilman, angelogioacchino.delregno, linux-pm, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek,
Project_Global_Chrome_Upstream_Group
On Tue, 2022-05-17 at 11:57 +0200, Matthias Brugger wrote:
>
> On 12/05/2022 08:05, Rex-BC Chen wrote:
> > On Thu, 2022-05-12 at 11:18 +0530, Viresh Kumar wrote:
> > > On 12-05-22, 13:33, Rex-BC Chen wrote:
> > > > Matthias is not the member of mediatek, so I think we still
> > > > need
> > > > his
> > > > feedback for these three patches.
> > >
> > > Please ping him and ask for his feedback then.
> > >
> >
> > ok, I will do this.
> > Thanks!
> >
>
> Sorry for the late reply. I'll take the DTS patches through my tree.
> As I'm late
> to the game this will be for v5.20.
>
> Regards,
> Matthias
Hello Matthias,
Thanks for you reply,
I send another version for this series.
Please refer to this:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=641933
BRs,
Rex
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 96+ messages in thread