From: Christoph Hellwig <hch@lst.de> To: Heiko Stuebner <heiko@sntech.de> Cc: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Wei Wu <lazyparser@gmail.com>, Daniel Lustig <dlustig@nvidia.com>, Bill Huffman <huffman@cadence.com> Subject: Re: [PATCH 09/12] riscv: add RISC-V Svpbmt extension support Date: Mon, 16 May 2022 08:10:57 +0200 [thread overview] Message-ID: <20220516061057.GL12339@lst.de> (raw) In-Reply-To: <20220511192921.2223629-10-heiko@sntech.de> > +config RISCV_ISA_SVPBMT > + bool "SVPBMT extension support" I don't think this prompt is very useful as it doesn't describe what it does. But do we even want people to disable it as it is really essentially for a fully functioning kernel and a pity that it took RISC-V so long to get there? > + depends on 64BIT && MMU > + select RISCV_ALTERNATIVE > + default y > + help > + Adds support to dynamically detect the presence of the SVPBMT extension overly long line here. > index 5f1046e82d9f..dbfcd9b72bd8 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -14,6 +14,9 @@ > #define ERRATA_SIFIVE_NUMBER 2 > #endif > > +#define CPUFEATURE_SVPBMT 0 > +#define CPUFEATURE_NUMBER 1 is errata_list.h really the right place for architectural features? Otherwise looks good: Reviewed-by: Christoph Hellwig <hch@lst.de> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de> To: Heiko Stuebner <heiko@sntech.de> Cc: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Wei Wu <lazyparser@gmail.com>, Daniel Lustig <dlustig@nvidia.com>, Bill Huffman <huffman@cadence.com> Subject: Re: [PATCH 09/12] riscv: add RISC-V Svpbmt extension support Date: Mon, 16 May 2022 08:10:57 +0200 [thread overview] Message-ID: <20220516061057.GL12339@lst.de> (raw) In-Reply-To: <20220511192921.2223629-10-heiko@sntech.de> > +config RISCV_ISA_SVPBMT > + bool "SVPBMT extension support" I don't think this prompt is very useful as it doesn't describe what it does. But do we even want people to disable it as it is really essentially for a fully functioning kernel and a pity that it took RISC-V so long to get there? > + depends on 64BIT && MMU > + select RISCV_ALTERNATIVE > + default y > + help > + Adds support to dynamically detect the presence of the SVPBMT extension overly long line here. > index 5f1046e82d9f..dbfcd9b72bd8 100644 > --- a/arch/riscv/include/asm/errata_list.h > +++ b/arch/riscv/include/asm/errata_list.h > @@ -14,6 +14,9 @@ > #define ERRATA_SIFIVE_NUMBER 2 > #endif > > +#define CPUFEATURE_SVPBMT 0 > +#define CPUFEATURE_NUMBER 1 is errata_list.h really the right place for architectural features? Otherwise looks good: Reviewed-by: Christoph Hellwig <hch@lst.de>
next prev parent reply other threads:[~2022-05-16 6:11 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-11 19:29 [PATCH v10 00/12] riscv: support for Svpbmt and D1 memory types Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-11 19:29 ` [PATCH 01/12] riscv: integrate alternatives better into the main architecture Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:01 ` Christoph Hellwig 2022-05-16 6:01 ` Christoph Hellwig 2022-05-16 6:45 ` Guo Ren 2022-05-16 6:45 ` Guo Ren 2022-05-11 19:29 ` [PATCH 02/12] riscv: allow different stages with alternatives Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:01 ` Christoph Hellwig 2022-05-16 6:01 ` Christoph Hellwig 2022-05-16 6:51 ` Guo Ren 2022-05-16 6:51 ` Guo Ren 2022-05-11 19:29 ` [PATCH 03/12] riscv: implement module alternatives Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:02 ` Christoph Hellwig 2022-05-16 6:02 ` Christoph Hellwig 2022-05-16 6:54 ` Guo Ren 2022-05-16 6:54 ` Guo Ren 2022-05-11 19:29 ` [PATCH 04/12] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:03 ` Christoph Hellwig 2022-05-16 6:03 ` Christoph Hellwig 2022-05-16 6:54 ` Guo Ren 2022-05-16 6:54 ` Guo Ren 2022-05-11 19:29 ` [PATCH 05/12] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:03 ` Christoph Hellwig 2022-05-16 6:03 ` Christoph Hellwig 2022-05-16 6:55 ` Guo Ren 2022-05-16 6:55 ` Guo Ren 2022-05-11 19:29 ` [PATCH 06/12] riscv: prevent compressed instructions in alternatives Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:04 ` Christoph Hellwig 2022-05-16 6:04 ` Christoph Hellwig 2022-05-16 6:55 ` Guo Ren 2022-05-16 6:55 ` Guo Ren 2022-05-11 19:29 ` [PATCH 07/12] riscv: move boot alternatives to after fill_hwcap Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-11 19:29 ` [PATCH 08/12] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:04 ` Christoph Hellwig 2022-05-16 6:04 ` Christoph Hellwig 2022-05-16 6:55 ` Guo Ren 2022-05-16 6:55 ` Guo Ren 2022-05-23 14:03 ` Alexandre Ghiti 2022-05-23 14:03 ` Alexandre Ghiti 2022-05-25 15:22 ` Heiko Stübner 2022-05-25 15:22 ` Heiko Stübner 2022-05-28 8:15 ` Alexandre Ghiti 2022-05-28 8:15 ` Alexandre Ghiti 2022-05-11 19:29 ` [PATCH 09/12] riscv: add RISC-V Svpbmt extension support Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:10 ` Christoph Hellwig [this message] 2022-05-16 6:10 ` Christoph Hellwig 2022-05-16 9:09 ` Philipp Tomsich 2022-05-16 9:09 ` Philipp Tomsich 2022-05-16 10:30 ` Heiko Stübner 2022-05-16 10:30 ` Heiko Stübner 2022-05-11 19:29 ` [PATCH 10/12] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-11 19:29 ` [PATCH 11/12] riscv: don't use global static vars to store alternative data Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-16 6:15 ` Christoph Hellwig 2022-05-16 6:15 ` Christoph Hellwig 2022-05-11 19:29 ` [PATCH 12/12] riscv: add memory-type errata for T-Head Heiko Stuebner 2022-05-11 19:29 ` Heiko Stuebner 2022-05-13 13:37 ` Guo Ren 2022-05-13 13:37 ` Guo Ren 2022-05-13 3:32 ` [PATCH v10 00/12] riscv: support for Svpbmt and D1 memory types Palmer Dabbelt 2022-05-13 3:32 ` Palmer Dabbelt 2022-05-13 21:41 ` Heiko Stuebner 2022-05-13 21:41 ` Heiko Stuebner
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