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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: linux-serial@vger.kernel.org,
	Greg KH <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Alexandre Torgue <alexandre.torgue@foss.st.com>,
	Erwan Le Ray <erwan.leray@st.com>,
	linux-stm32@st-md-mailman.stormreply.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: [PATCH 8/9] serial: stm32-usart: Correct CSIZE, bits, and parity
Date: Tue, 17 May 2022 14:07:36 +0300	[thread overview]
Message-ID: <20220517110737.37148-9-ilpo.jarvinen@linux.intel.com> (raw)
In-Reply-To: <20220517110737.37148-1-ilpo.jarvinen@linux.intel.com>

Add CSIZE sanitization for unsupported CSIZE configurations. In
addition, if parity is asked for but CSx was unsupported, the sensible
result is CS8+parity which requires setting USART_CR1_M0 like with 9
bits.

Incorrect CSIZE results in miscalculation of the frame bits in
tty_get_char_size() or in its predecessor where the roughly the same
code is directly within uart_update_timeout().

Cc: Erwan Le Ray <erwan.leray@st.com>
Fixes: c8a9d043947b (serial: stm32: fix word length configuration)
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
 drivers/tty/serial/stm32-usart.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index 87b5cd4c9743..3c551fd4f3ff 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -1037,13 +1037,22 @@ static void stm32_usart_set_termios(struct uart_port *port,
 	 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
 	 * M0 and M1 already cleared by cr1 initialization.
 	 */
-	if (bits == 9)
+	if (bits == 9) {
 		cr1 |= USART_CR1_M0;
-	else if ((bits == 7) && cfg->has_7bits_data)
+	} else if ((bits == 7) && cfg->has_7bits_data) {
 		cr1 |= USART_CR1_M1;
-	else if (bits != 8)
+	} else if (bits != 8) {
 		dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
 			, bits);
+		cflag &= ~CSIZE;
+		cflag |= CS8;
+		termios->c_cflag = cflag;
+		bits = 8;
+		if (cflag & PARENB) {
+			bits++;
+			cr1 |= USART_CR1_M0;
+		}
+	}
 
 	if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
 				       (stm32_port->fifoen &&
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: linux-serial@vger.kernel.org,
	Greg KH <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Alexandre Torgue <alexandre.torgue@foss.st.com>,
	Erwan Le Ray <erwan.leray@st.com>,
	linux-stm32@st-md-mailman.stormreply.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: [PATCH 8/9] serial: stm32-usart: Correct CSIZE, bits, and parity
Date: Tue, 17 May 2022 14:07:36 +0300	[thread overview]
Message-ID: <20220517110737.37148-9-ilpo.jarvinen@linux.intel.com> (raw)
In-Reply-To: <20220517110737.37148-1-ilpo.jarvinen@linux.intel.com>

Add CSIZE sanitization for unsupported CSIZE configurations. In
addition, if parity is asked for but CSx was unsupported, the sensible
result is CS8+parity which requires setting USART_CR1_M0 like with 9
bits.

Incorrect CSIZE results in miscalculation of the frame bits in
tty_get_char_size() or in its predecessor where the roughly the same
code is directly within uart_update_timeout().

Cc: Erwan Le Ray <erwan.leray@st.com>
Fixes: c8a9d043947b (serial: stm32: fix word length configuration)
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
 drivers/tty/serial/stm32-usart.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index 87b5cd4c9743..3c551fd4f3ff 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -1037,13 +1037,22 @@ static void stm32_usart_set_termios(struct uart_port *port,
 	 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
 	 * M0 and M1 already cleared by cr1 initialization.
 	 */
-	if (bits == 9)
+	if (bits == 9) {
 		cr1 |= USART_CR1_M0;
-	else if ((bits == 7) && cfg->has_7bits_data)
+	} else if ((bits == 7) && cfg->has_7bits_data) {
 		cr1 |= USART_CR1_M1;
-	else if (bits != 8)
+	} else if (bits != 8) {
 		dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
 			, bits);
+		cflag &= ~CSIZE;
+		cflag |= CS8;
+		termios->c_cflag = cflag;
+		bits = 8;
+		if (cflag & PARENB) {
+			bits++;
+			cr1 |= USART_CR1_M0;
+		}
+	}
 
 	if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
 				       (stm32_port->fifoen &&
-- 
2.30.2


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  parent reply	other threads:[~2022-05-17 11:09 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-17 11:07 [PATCH 0/9] tty/serial: Termios flag fixes Ilpo Järvinen
2022-05-17 11:07 ` Ilpo Järvinen
2022-05-17 11:07 ` [PATCH 1/9] serial: uartline: Fix BRKINT clearing Ilpo Järvinen
2022-05-17 14:33   ` Sean Anderson
2022-05-18 12:18   ` Shubhrajyoti Datta
2022-05-18 12:25     ` Ilpo Järvinen
2022-05-17 11:07 ` [PATCH 2/9] serial: digicolor-usart: Don't allow CS5-6 Ilpo Järvinen
2022-05-17 11:07   ` Ilpo Järvinen
2022-05-18  4:16   ` Baruch Siach
2022-05-18  4:16     ` Baruch Siach
2022-05-17 11:07 ` [PATCH 3/9] serial: rda-uart: " Ilpo Järvinen
2022-05-17 11:07   ` Ilpo Järvinen
2022-05-17 11:07 ` [PATCH 4/9] serial: txx9: " Ilpo Järvinen
2022-05-17 11:07 ` [PATCH 5/9] serial: sh-sci: " Ilpo Järvinen
2022-05-17 11:07 ` [PATCH 6/9] serial: sifive: Sanitize CSIZE and c_iflag Ilpo Järvinen
2022-05-17 11:07   ` Ilpo Järvinen
2022-05-17 11:07 ` [PATCH 7/9] serial: st-asc: Sanitize CSIZE and correct PARENB for CS7 Ilpo Järvinen
2022-05-17 11:07   ` Ilpo Järvinen
2022-05-17 11:07 ` Ilpo Järvinen [this message]
2022-05-17 11:07   ` [PATCH 8/9] serial: stm32-usart: Correct CSIZE, bits, and parity Ilpo Järvinen
2022-05-17 11:07 ` [PATCH 9/9] pcmcia: synclink_cs: Don't allow CS5-6 Ilpo Järvinen

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