* [PATCH 00/14] Canaan devicetree fixes
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
Hey all,
This series should rid us of dtbs_check errors for the RISC-V Canaan k210
based boards (well, unless you enable W=1 but that's another days work).
I *DO NOT* have any Canaan hardware so I have not tested any of this in
anger. I based the series on next-20220617.
For the bindings, I am never sure about which of {unevaluated,additional}
Properties is correct to use, but the if statements in the binding didn't
work with additional so I used unevaluated...
@Mark, for your two bindings I was not sure about the properties that I
made depend on the compatible, but I looked in tree and was not able to
find other users to contradict what's in the Canaan devicetrees nor did
I get that much help from their docs.
@Rob, yesterday's removal of ilitek,ili9341.txt is moved to ths series
since I was editing the dt-schema binding here anyway.
Finally, @Palmer:
This + Atul's stuff + the sifive dts watchdog patch will get us sorted
in terms of dtbs_check errors. To make keeping it that way a little
easier, I changed the Canaan devicetree Makefile so that it would build
all of the devicetrees in the directory if SOC_CANAAN. Hopefully someone
with a device can test it - but my build log *looked* fine but that's
not exactly sufficient.
Thanks,
Conor.
Conor Dooley (14):
dt-bindings: display: convert ilitek,ili9341.txt to dt-schema
dt-bindings: display: panel: allow ilitek,ili9341 in isolation
ASoC: dt-bindings: convert designware-i2s to dt-schema
dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
riscv: dts: canaan: fix the k210's memory node
riscv: dts: canaan: add a specific compatible for k210's dma
riscv: dts: canaan: add a specific compatible for k210's timers
riscv: dts: canaan: fix mmc node names
riscv: dts: canaan: fix kd233 display spi frequency
riscv: dts: canaan: use custom compatible for k210 i2s
riscv: dts: canaan: remove spi-max-frequency from controllers
riscv: dts: canaan: build all devicetress if SOC_CANAAN
.../bindings/display/ilitek,ili9341.txt | 27 ------
.../display/panel/ilitek,ili9341.yaml | 60 ++++++++----
.../bindings/dma/snps,dw-axi-dmac.yaml | 35 +++++--
.../bindings/sound/designware-i2s.txt | 35 -------
.../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 +++++++---
.../bindings/timer/snps,dw-apb-timer.yaml | 28 ++++--
arch/riscv/boot/dts/canaan/Makefile | 10 +-
arch/riscv/boot/dts/canaan/canaan_kd233.dts | 4 +-
arch/riscv/boot/dts/canaan/k210.dtsi | 25 ++---
.../riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +-
.../boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +-
.../boot/dts/canaan/sipeed_maixduino.dts | 2 +-
14 files changed, 239 insertions(+), 134 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt
create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
base-commit: 07dc787be2316e243a16a33d0a9b734cd9365bd3
--
2.36.1
^ permalink raw reply [flat|nested] 159+ messages in thread* [PATCH 00/14] Canaan devicetree fixes
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
Hey all,
This series should rid us of dtbs_check errors for the RISC-V Canaan k210
based boards (well, unless you enable W=1 but that's another days work).
I *DO NOT* have any Canaan hardware so I have not tested any of this in
anger. I based the series on next-20220617.
For the bindings, I am never sure about which of {unevaluated,additional}
Properties is correct to use, but the if statements in the binding didn't
work with additional so I used unevaluated...
@Mark, for your two bindings I was not sure about the properties that I
made depend on the compatible, but I looked in tree and was not able to
find other users to contradict what's in the Canaan devicetrees nor did
I get that much help from their docs.
@Rob, yesterday's removal of ilitek,ili9341.txt is moved to ths series
since I was editing the dt-schema binding here anyway.
Finally, @Palmer:
This + Atul's stuff + the sifive dts watchdog patch will get us sorted
in terms of dtbs_check errors. To make keeping it that way a little
easier, I changed the Canaan devicetree Makefile so that it would build
all of the devicetrees in the directory if SOC_CANAAN. Hopefully someone
with a device can test it - but my build log *looked* fine but that's
not exactly sufficient.
Thanks,
Conor.
Conor Dooley (14):
dt-bindings: display: convert ilitek,ili9341.txt to dt-schema
dt-bindings: display: panel: allow ilitek,ili9341 in isolation
ASoC: dt-bindings: convert designware-i2s to dt-schema
dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
riscv: dts: canaan: fix the k210's memory node
riscv: dts: canaan: add a specific compatible for k210's dma
riscv: dts: canaan: add a specific compatible for k210's timers
riscv: dts: canaan: fix mmc node names
riscv: dts: canaan: fix kd233 display spi frequency
riscv: dts: canaan: use custom compatible for k210 i2s
riscv: dts: canaan: remove spi-max-frequency from controllers
riscv: dts: canaan: build all devicetress if SOC_CANAAN
.../bindings/display/ilitek,ili9341.txt | 27 ------
.../display/panel/ilitek,ili9341.yaml | 60 ++++++++----
.../bindings/dma/snps,dw-axi-dmac.yaml | 35 +++++--
.../bindings/sound/designware-i2s.txt | 35 -------
.../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 +++++++---
.../bindings/timer/snps,dw-apb-timer.yaml | 28 ++++--
arch/riscv/boot/dts/canaan/Makefile | 10 +-
arch/riscv/boot/dts/canaan/canaan_kd233.dts | 4 +-
arch/riscv/boot/dts/canaan/k210.dtsi | 25 ++---
.../riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +-
.../boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +-
.../boot/dts/canaan/sipeed_maixduino.dts | 2 +-
14 files changed, 239 insertions(+), 134 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt
create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
base-commit: 07dc787be2316e243a16a33d0a9b734cd9365bd3
--
2.36.1
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linux-riscv@lists.infradead.org
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^ permalink raw reply [flat|nested] 159+ messages in thread* [PATCH 01/14] dt-bindings: display: convert ilitek,ili9341.txt to dt-schema
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
A dt-schema binding for the Ilitek ili9341 was created as
panel/ilitek,ili9341.yaml but the txt binding was ignored in the
process. Move the remaining items in the txt binding to the yaml one &
delete it.
The example in the txt binding has a spi-max-frequency which disagrees
with the yaml replacement (and its own documentation) so change that to
conform with the binding. There are no users in tree of the Adafruit
yx240qv29 to check against.
Link: https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240QV29-T_Rev.A__1_.pdf
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/display/ilitek,ili9341.txt | 27 -----------
.../display/panel/ilitek,ili9341.yaml | 48 +++++++++++++------
2 files changed, 34 insertions(+), 41 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt b/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
deleted file mode 100644
index 169b32e4ee4e..000000000000
--- a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-Ilitek ILI9341 display panels
-
-This binding is for display panels using an Ilitek ILI9341 controller in SPI
-mode.
-
-Required properties:
-- compatible: "adafruit,yx240qv29", "ilitek,ili9341"
-- dc-gpios: D/C pin
-- reset-gpios: Reset pin
-
-The node for this driver must be a child node of a SPI controller, hence
-all mandatory properties described in ../spi/spi-bus.txt must be specified.
-
-Optional properties:
-- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
-- backlight: phandle of the backlight device attached to the panel
-
-Example:
- display@0{
- compatible = "adafruit,yx240qv29", "ilitek,ili9341";
- reg = <0>;
- spi-max-frequency = <32000000>;
- dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
- rotation = <270>;
- backlight = <&backlight>;
- };
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
index 6058948a9764..94ca92878434 100644
--- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
@@ -23,6 +23,7 @@ properties:
- enum:
# ili9341 240*320 Color on stm32f429-disco board
- st,sf-tc240t-9370-t
+ - adafruit,yx240qv29
- const: ilitek,ili9341
reg: true
@@ -47,31 +48,50 @@ properties:
vddi-led-supply:
description: Voltage supply for the LED driver (1.65 .. 3.3 V)
-additionalProperties: false
+unevaluatedProperties: false
required:
- compatible
- reg
- dc-gpios
- - port
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,sf-tc240t-9370-t
+then:
+ required:
+ - port
examples:
- |+
+ #include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
panel: display@0 {
- compatible = "st,sf-tc240t-9370-t",
- "ilitek,ili9341";
- reg = <0>;
- spi-3wire;
- spi-max-frequency = <10000000>;
- dc-gpios = <&gpiod 13 0>;
- port {
- panel_in: endpoint {
- remote-endpoint = <&display_out>;
- };
- };
- };
+ compatible = "st,sf-tc240t-9370-t",
+ "ilitek,ili9341";
+ reg = <0>;
+ spi-3wire;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpiod 13 0>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+ display@1{
+ compatible = "adafruit,yx240qv29", "ilitek,ili9341";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ rotation = <270>;
+ backlight = <&backlight>;
};
+ };
...
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 01/14] dt-bindings: display: convert ilitek, ili9341.txt to dt-schema
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
A dt-schema binding for the Ilitek ili9341 was created as
panel/ilitek,ili9341.yaml but the txt binding was ignored in the
process. Move the remaining items in the txt binding to the yaml one &
delete it.
The example in the txt binding has a spi-max-frequency which disagrees
with the yaml replacement (and its own documentation) so change that to
conform with the binding. There are no users in tree of the Adafruit
yx240qv29 to check against.
Link: https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240QV29-T_Rev.A__1_.pdf
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/display/ilitek,ili9341.txt | 27 -----------
.../display/panel/ilitek,ili9341.yaml | 48 +++++++++++++------
2 files changed, 34 insertions(+), 41 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt b/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
deleted file mode 100644
index 169b32e4ee4e..000000000000
--- a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-Ilitek ILI9341 display panels
-
-This binding is for display panels using an Ilitek ILI9341 controller in SPI
-mode.
-
-Required properties:
-- compatible: "adafruit,yx240qv29", "ilitek,ili9341"
-- dc-gpios: D/C pin
-- reset-gpios: Reset pin
-
-The node for this driver must be a child node of a SPI controller, hence
-all mandatory properties described in ../spi/spi-bus.txt must be specified.
-
-Optional properties:
-- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
-- backlight: phandle of the backlight device attached to the panel
-
-Example:
- display@0{
- compatible = "adafruit,yx240qv29", "ilitek,ili9341";
- reg = <0>;
- spi-max-frequency = <32000000>;
- dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
- rotation = <270>;
- backlight = <&backlight>;
- };
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
index 6058948a9764..94ca92878434 100644
--- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
@@ -23,6 +23,7 @@ properties:
- enum:
# ili9341 240*320 Color on stm32f429-disco board
- st,sf-tc240t-9370-t
+ - adafruit,yx240qv29
- const: ilitek,ili9341
reg: true
@@ -47,31 +48,50 @@ properties:
vddi-led-supply:
description: Voltage supply for the LED driver (1.65 .. 3.3 V)
-additionalProperties: false
+unevaluatedProperties: false
required:
- compatible
- reg
- dc-gpios
- - port
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,sf-tc240t-9370-t
+then:
+ required:
+ - port
examples:
- |+
+ #include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
panel: display@0 {
- compatible = "st,sf-tc240t-9370-t",
- "ilitek,ili9341";
- reg = <0>;
- spi-3wire;
- spi-max-frequency = <10000000>;
- dc-gpios = <&gpiod 13 0>;
- port {
- panel_in: endpoint {
- remote-endpoint = <&display_out>;
- };
- };
- };
+ compatible = "st,sf-tc240t-9370-t",
+ "ilitek,ili9341";
+ reg = <0>;
+ spi-3wire;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpiod 13 0>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+ display@1{
+ compatible = "adafruit,yx240qv29", "ilitek,ili9341";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ rotation = <270>;
+ backlight = <&backlight>;
};
+ };
...
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 01/14] dt-bindings: display: convert ilitek,ili9341.txt to dt-schema
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
A dt-schema binding for the Ilitek ili9341 was created as
panel/ilitek,ili9341.yaml but the txt binding was ignored in the
process. Move the remaining items in the txt binding to the yaml one &
delete it.
The example in the txt binding has a spi-max-frequency which disagrees
with the yaml replacement (and its own documentation) so change that to
conform with the binding. There are no users in tree of the Adafruit
yx240qv29 to check against.
Link: https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240QV29-T_Rev.A__1_.pdf
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/display/ilitek,ili9341.txt | 27 -----------
.../display/panel/ilitek,ili9341.yaml | 48 +++++++++++++------
2 files changed, 34 insertions(+), 41 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt b/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
deleted file mode 100644
index 169b32e4ee4e..000000000000
--- a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-Ilitek ILI9341 display panels
-
-This binding is for display panels using an Ilitek ILI9341 controller in SPI
-mode.
-
-Required properties:
-- compatible: "adafruit,yx240qv29", "ilitek,ili9341"
-- dc-gpios: D/C pin
-- reset-gpios: Reset pin
-
-The node for this driver must be a child node of a SPI controller, hence
-all mandatory properties described in ../spi/spi-bus.txt must be specified.
-
-Optional properties:
-- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
-- backlight: phandle of the backlight device attached to the panel
-
-Example:
- display@0{
- compatible = "adafruit,yx240qv29", "ilitek,ili9341";
- reg = <0>;
- spi-max-frequency = <32000000>;
- dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
- rotation = <270>;
- backlight = <&backlight>;
- };
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
index 6058948a9764..94ca92878434 100644
--- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
@@ -23,6 +23,7 @@ properties:
- enum:
# ili9341 240*320 Color on stm32f429-disco board
- st,sf-tc240t-9370-t
+ - adafruit,yx240qv29
- const: ilitek,ili9341
reg: true
@@ -47,31 +48,50 @@ properties:
vddi-led-supply:
description: Voltage supply for the LED driver (1.65 .. 3.3 V)
-additionalProperties: false
+unevaluatedProperties: false
required:
- compatible
- reg
- dc-gpios
- - port
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - st,sf-tc240t-9370-t
+then:
+ required:
+ - port
examples:
- |+
+ #include <dt-bindings/gpio/gpio.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
panel: display@0 {
- compatible = "st,sf-tc240t-9370-t",
- "ilitek,ili9341";
- reg = <0>;
- spi-3wire;
- spi-max-frequency = <10000000>;
- dc-gpios = <&gpiod 13 0>;
- port {
- panel_in: endpoint {
- remote-endpoint = <&display_out>;
- };
- };
- };
+ compatible = "st,sf-tc240t-9370-t",
+ "ilitek,ili9341";
+ reg = <0>;
+ spi-3wire;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpiod 13 0>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+ display@1{
+ compatible = "adafruit,yx240qv29", "ilitek,ili9341";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ rotation = <270>;
+ backlight = <&backlight>;
};
+ };
...
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread* Re: [PATCH 01/14] dt-bindings: display: convert ilitek,ili9341.txt to dt-schema
2022-06-18 12:30 ` [PATCH 01/14] dt-bindings: display: convert ilitek,ili9341.txt " Conor Dooley
(?)
@ 2022-06-27 23:20 ` Rob Herring
-1 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:20 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, alsa-devel, David Airlie, dri-devel, linux-kernel,
Conor Dooley, Thierry Reding, Heng Sia, Krzysztof Kozlowski,
linux-riscv, Sam Ravnborg, Masahiro Yamada, Daniel Lezcano,
Jose Abreu, Geert Uytterhoeven, Eugeniy Paltsev, devicetree,
Albert Ou, Rob Herring, Palmer Dabbelt, Paul Walmsley,
Thomas Gleixner, Dillon Min, Liam Girdwood, Serge Semin,
linux-spi, Vinod Koul, Mark Brown, Palmer Dabbelt, dmaengine,
Damien Le Moal
On Sat, 18 Jun 2022 13:30:23 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> A dt-schema binding for the Ilitek ili9341 was created as
> panel/ilitek,ili9341.yaml but the txt binding was ignored in the
> process. Move the remaining items in the txt binding to the yaml one &
> delete it.
>
> The example in the txt binding has a spi-max-frequency which disagrees
> with the yaml replacement (and its own documentation) so change that to
> conform with the binding. There are no users in tree of the Adafruit
> yx240qv29 to check against.
>
> Link: https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240QV29-T_Rev.A__1_.pdf
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/display/ilitek,ili9341.txt | 27 -----------
> .../display/panel/ilitek,ili9341.yaml | 48 +++++++++++++------
> 2 files changed, 34 insertions(+), 41 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 01/14] dt-bindings: display: convert ilitek,ili9341.txt to dt-schema
@ 2022-06-27 23:20 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:20 UTC (permalink / raw)
To: Conor Dooley
Cc: Masahiro Yamada, Geert Uytterhoeven, Jose Abreu, devicetree,
Vinod Koul, Liam Girdwood, Thomas Gleixner, alsa-devel,
linux-riscv, Rob Herring, linux-kernel, Serge Semin,
Daniel Lezcano, Damien Le Moal, dri-devel, Sam Ravnborg,
Paul Walmsley, Palmer Dabbelt, Daniel Vetter,
Krzysztof Kozlowski, Thierry Reding, Albert Ou, Niklas Cassel,
Mark Brown, Conor Dooley, Heng Sia, dmaengine, linux-spi,
David Airlie, Eugeniy Paltsev, Dillon Min, Palmer Dabbelt
On Sat, 18 Jun 2022 13:30:23 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> A dt-schema binding for the Ilitek ili9341 was created as
> panel/ilitek,ili9341.yaml but the txt binding was ignored in the
> process. Move the remaining items in the txt binding to the yaml one &
> delete it.
>
> The example in the txt binding has a spi-max-frequency which disagrees
> with the yaml replacement (and its own documentation) so change that to
> conform with the binding. There are no users in tree of the Adafruit
> yx240qv29 to check against.
>
> Link: https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240QV29-T_Rev.A__1_.pdf
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/display/ilitek,ili9341.txt | 27 -----------
> .../display/panel/ilitek,ili9341.yaml | 48 +++++++++++++------
> 2 files changed, 34 insertions(+), 41 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 01/14] dt-bindings: display: convert ilitek,ili9341.txt to dt-schema
@ 2022-06-27 23:20 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:20 UTC (permalink / raw)
To: Conor Dooley
Cc: Masahiro Yamada, Geert Uytterhoeven, Jose Abreu, devicetree,
Vinod Koul, Liam Girdwood, Thomas Gleixner, alsa-devel,
linux-riscv, Rob Herring, linux-kernel, Serge Semin,
Daniel Lezcano, Damien Le Moal, dri-devel, Sam Ravnborg,
Paul Walmsley, Palmer Dabbelt, Daniel Vetter,
Krzysztof Kozlowski, Thierry Reding, Albert Ou, Niklas Cassel,
Mark Brown, Conor Dooley, Heng Sia, dmaengine, linux-spi,
David Airlie, Eugeniy Paltsev, Dillon Min, Palmer Dabbelt
On Sat, 18 Jun 2022 13:30:23 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> A dt-schema binding for the Ilitek ili9341 was created as
> panel/ilitek,ili9341.yaml but the txt binding was ignored in the
> process. Move the remaining items in the txt binding to the yaml one &
> delete it.
>
> The example in the txt binding has a spi-max-frequency which disagrees
> with the yaml replacement (and its own documentation) so change that to
> conform with the binding. There are no users in tree of the Adafruit
> yx240qv29 to check against.
>
> Link: https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240QV29-T_Rev.A__1_.pdf
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/display/ilitek,ili9341.txt | 27 -----------
> .../display/panel/ilitek,ili9341.yaml | 48 +++++++++++++------
> 2 files changed, 34 insertions(+), 41 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 159+ messages in thread
* [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 in isolation
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The dt-binding for the ilitek,ili9341 does not allow it to be used as a
compatible in isolation. This generates a warning for the Canaan kd233
devicetree:
arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t']
From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short
From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
Allow ilitek,ili9341 to be selected in isolation.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/display/panel/ilitek,ili9341.yaml | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
index 94ca92878434..c402bedaa37a 100644
--- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
@@ -19,12 +19,14 @@ allOf:
properties:
compatible:
- items:
- - enum:
- # ili9341 240*320 Color on stm32f429-disco board
- - st,sf-tc240t-9370-t
- - adafruit,yx240qv29
- - const: ilitek,ili9341
+ oneOf:
+ - items:
+ - const: ilitek,ili9341
+ - items:
+ - enum:
+ - st,sf-tc240t-9370-t
+ - adafruit,yx240qv29
+ - const: ilitek,ili9341
reg: true
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 02/14] dt-bindings: display: panel: allow ilitek, ili9341 in isolation
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
The dt-binding for the ilitek,ili9341 does not allow it to be used as a
compatible in isolation. This generates a warning for the Canaan kd233
devicetree:
arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t']
From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short
From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
Allow ilitek,ili9341 to be selected in isolation.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/display/panel/ilitek,ili9341.yaml | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
index 94ca92878434..c402bedaa37a 100644
--- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
@@ -19,12 +19,14 @@ allOf:
properties:
compatible:
- items:
- - enum:
- # ili9341 240*320 Color on stm32f429-disco board
- - st,sf-tc240t-9370-t
- - adafruit,yx240qv29
- - const: ilitek,ili9341
+ oneOf:
+ - items:
+ - const: ilitek,ili9341
+ - items:
+ - enum:
+ - st,sf-tc240t-9370-t
+ - adafruit,yx240qv29
+ - const: ilitek,ili9341
reg: true
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 in isolation
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The dt-binding for the ilitek,ili9341 does not allow it to be used as a
compatible in isolation. This generates a warning for the Canaan kd233
devicetree:
arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t']
From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short
From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
Allow ilitek,ili9341 to be selected in isolation.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/display/panel/ilitek,ili9341.yaml | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
index 94ca92878434..c402bedaa37a 100644
--- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
@@ -19,12 +19,14 @@ allOf:
properties:
compatible:
- items:
- - enum:
- # ili9341 240*320 Color on stm32f429-disco board
- - st,sf-tc240t-9370-t
- - adafruit,yx240qv29
- - const: ilitek,ili9341
+ oneOf:
+ - items:
+ - const: ilitek,ili9341
+ - items:
+ - enum:
+ - st,sf-tc240t-9370-t
+ - adafruit,yx240qv29
+ - const: ilitek,ili9341
reg: true
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread* Re: [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 in isolation
2022-06-18 12:30 ` [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 " Conor Dooley
(?)
@ 2022-06-27 23:17 ` Rob Herring
-1 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:17 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Krzysztof Kozlowski, Thierry Reding,
Sam Ravnborg, Eugeniy Paltsev, Vinod Koul, Liam Girdwood,
Mark Brown, Serge Semin, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:24PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The dt-binding for the ilitek,ili9341 does not allow it to be used as a
> compatible in isolation. This generates a warning for the Canaan kd233
> devicetree:
> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t']
> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short
> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
> Allow ilitek,ili9341 to be selected in isolation.
Just because you get a warning doesn't mean it is right. ili9341 is a
panel driver IC, not a complete panel. It needs a more specific
compatible.
Rob
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 in isolation
@ 2022-06-27 23:17 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:17 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Krzysztof Kozlowski, Thierry Reding,
Sam Ravnborg, Eugeniy Paltsev, Vinod Koul, Liam Girdwood,
Mark Brown, Serge Semin, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:24PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The dt-binding for the ilitek,ili9341 does not allow it to be used as a
> compatible in isolation. This generates a warning for the Canaan kd233
> devicetree:
> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t']
> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short
> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
> Allow ilitek,ili9341 to be selected in isolation.
Just because you get a warning doesn't mean it is right. ili9341 is a
panel driver IC, not a complete panel. It needs a more specific
compatible.
Rob
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 in isolation
@ 2022-06-27 23:17 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:17 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, alsa-devel, David Airlie, Palmer Dabbelt,
linux-kernel, Conor Dooley, Thierry Reding, Heng Sia,
Krzysztof Kozlowski, linux-riscv, Sam Ravnborg, Damien Le Moal,
Daniel Lezcano, Jose Abreu, Geert Uytterhoeven, Eugeniy Paltsev,
devicetree, Albert Ou, Mark Brown, dri-devel, Paul Walmsley,
Thomas Gleixner, Dillon Min, Liam Girdwood, Serge Semin,
linux-spi, Vinod Koul, Palmer Dabbelt, dmaengine,
Masahiro Yamada
On Sat, Jun 18, 2022 at 01:30:24PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The dt-binding for the ilitek,ili9341 does not allow it to be used as a
> compatible in isolation. This generates a warning for the Canaan kd233
> devicetree:
> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t']
> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short
> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
> Allow ilitek,ili9341 to be selected in isolation.
Just because you get a warning doesn't mean it is right. ili9341 is a
panel driver IC, not a complete panel. It needs a more specific
compatible.
Rob
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 in isolation
2022-06-27 23:17 ` Rob Herring
(?)
@ 2022-06-28 6:26 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-28 6:26 UTC (permalink / raw)
To: robh, mail
Cc: airlied, daniel, krzysztof.kozlowski+dt, thierry.reding, sam,
Eugeniy.Paltsev, vkoul, lgirdwood, broonie, fancer.lancer,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, damien.lemoal, geert, niklas.cassel, dillon.minfei,
jee.heng.sia, joabreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On 28/06/2022 00:17, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:24PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The dt-binding for the ilitek,ili9341 does not allow it to be used as a
>> compatible in isolation. This generates a warning for the Canaan kd233
>> devicetree:
>> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t']
>> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
>> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short
>> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
>> Allow ilitek,ili9341 to be selected in isolation.
>
> Just because you get a warning doesn't mean it is right. ili9341 is a
> panel driver IC, not a complete panel. It needs a more specific
> compatible.
pff, makes sense. I'll conjure one up.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 in isolation
@ 2022-06-28 6:26 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-28 6:26 UTC (permalink / raw)
To: robh, mail
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, jee.heng.sia, krzysztof.kozlowski+dt,
linux-riscv, sam, damien.lemoal, daniel.lezcano, joabreu, geert,
Eugeniy.Paltsev, devicetree, aou, broonie, dri-devel,
paul.walmsley, tglx, dillon.minfei, lgirdwood, fancer.lancer,
linux-spi, vkoul, palmer, dmaengine, masahiroy
On 28/06/2022 00:17, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:24PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The dt-binding for the ilitek,ili9341 does not allow it to be used as a
>> compatible in isolation. This generates a warning for the Canaan kd233
>> devicetree:
>> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t']
>> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
>> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short
>> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
>> Allow ilitek,ili9341 to be selected in isolation.
>
> Just because you get a warning doesn't mean it is right. ili9341 is a
> panel driver IC, not a complete panel. It needs a more specific
> compatible.
pff, makes sense. I'll conjure one up.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 in isolation
@ 2022-06-28 6:26 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-28 6:26 UTC (permalink / raw)
To: robh, mail
Cc: airlied, daniel, krzysztof.kozlowski+dt, thierry.reding, sam,
Eugeniy.Paltsev, vkoul, lgirdwood, broonie, fancer.lancer,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, damien.lemoal, geert, niklas.cassel, dillon.minfei,
jee.heng.sia, joabreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On 28/06/2022 00:17, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:24PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The dt-binding for the ilitek,ili9341 does not allow it to be used as a
>> compatible in isolation. This generates a warning for the Canaan kd233
>> devicetree:
>> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t']
>> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
>> arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short
>> From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
>> Allow ilitek,ili9341 to be selected in isolation.
>
> Just because you get a warning doesn't mean it is right. ili9341 is a
> panel driver IC, not a complete panel. It needs a more specific
> compatible.
pff, makes sense. I'll conjure one up.
Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread
* [PATCH 03/14] ASoC: dt-bindings: convert designware-i2s to dt-schema
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
Convert the Synopsys DesignWare I2S controller binding to dt-schema.
There was no listed maintainer but Jose Abreu was the last editor of the
txt binding so add him as maintainer.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/sound/designware-i2s.txt | 35 -------
.../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++
2 files changed, 93 insertions(+), 35 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt
create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt
deleted file mode 100644
index 6a536d570e29..000000000000
--- a/Documentation/devicetree/bindings/sound/designware-i2s.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-DesignWare I2S controller
-
-Required properties:
- - compatible : Must be "snps,designware-i2s"
- - reg : Must contain the I2S core's registers location and length
- - clocks : Pairs of phandle and specifier referencing the controller's
- clocks. The controller expects one clock: the clock used as the sampling
- rate reference clock sample.
- - clock-names : "i2sclk" for the sample rate reference clock.
- - dmas: Pairs of phandle and specifier for the DMA channels that are used by
- the core. The core expects one or two dma channels: one for transmit and
- one for receive.
- - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
-
-Optional properties:
- - interrupts: The interrupt line number for the I2S controller. Add this
- parameter if the I2S controller that you are using does not support DMA.
-
-For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
-properties please check:
- * resource-names.txt
- * clock/clock-bindings.txt
- * dma/dma.txt
-
-Example:
-
- soc_i2s: i2s@7ff90000 {
- compatible = "snps,designware-i2s";
- reg = <0x0 0x7ff90000 0x0 0x1000>;
- clocks = <&scpi_i2sclk 0>;
- clock-names = "i2sclk";
- #sound-dai-cells = <0>;
- dmas = <&dma0 5>;
- dma-names = "tx";
- };
diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
new file mode 100644
index 000000000000..5ac9c00157bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare I2S controller
+
+maintainers:
+ - Jose Abreu <joabreu@synopsys.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: canaan,k210-i2s
+ - const: snps,designware-i2s
+ - enum:
+ - snps,designware-i2s
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ The interrupt line number for the I2S controller. Add this
+ parameter if the I2S controller that you are using does not
+ support DMA.
+ maxItems: 1
+
+ clocks:
+ description: Sampling rate reference clock
+
+ clock-names:
+ const: i2sclk
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel
+ minItems: 1
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+ minItems: 1
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: canaan,k210-i2s
+
+then:
+ properties:
+ "#sound-dai-cells":
+ const: 1
+
+else:
+ properties:
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+oneOf:
+ - required:
+ - dmas
+ - dma-names
+ - required:
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc_i2s: i2s@7ff90000 {
+ compatible = "snps,designware-i2s";
+ reg = <0x7ff90000 0x1000>;
+ clocks = <&scpi_i2sclk 0>;
+ clock-names = "i2sclk";
+ #sound-dai-cells = <0>;
+ dmas = <&dma0 5>;
+ dma-names = "tx";
+ };
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 03/14] ASoC: dt-bindings: convert designware-i2s to dt-schema
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
Convert the Synopsys DesignWare I2S controller binding to dt-schema.
There was no listed maintainer but Jose Abreu was the last editor of the
txt binding so add him as maintainer.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/sound/designware-i2s.txt | 35 -------
.../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++
2 files changed, 93 insertions(+), 35 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt
create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt
deleted file mode 100644
index 6a536d570e29..000000000000
--- a/Documentation/devicetree/bindings/sound/designware-i2s.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-DesignWare I2S controller
-
-Required properties:
- - compatible : Must be "snps,designware-i2s"
- - reg : Must contain the I2S core's registers location and length
- - clocks : Pairs of phandle and specifier referencing the controller's
- clocks. The controller expects one clock: the clock used as the sampling
- rate reference clock sample.
- - clock-names : "i2sclk" for the sample rate reference clock.
- - dmas: Pairs of phandle and specifier for the DMA channels that are used by
- the core. The core expects one or two dma channels: one for transmit and
- one for receive.
- - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
-
-Optional properties:
- - interrupts: The interrupt line number for the I2S controller. Add this
- parameter if the I2S controller that you are using does not support DMA.
-
-For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
-properties please check:
- * resource-names.txt
- * clock/clock-bindings.txt
- * dma/dma.txt
-
-Example:
-
- soc_i2s: i2s@7ff90000 {
- compatible = "snps,designware-i2s";
- reg = <0x0 0x7ff90000 0x0 0x1000>;
- clocks = <&scpi_i2sclk 0>;
- clock-names = "i2sclk";
- #sound-dai-cells = <0>;
- dmas = <&dma0 5>;
- dma-names = "tx";
- };
diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
new file mode 100644
index 000000000000..5ac9c00157bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare I2S controller
+
+maintainers:
+ - Jose Abreu <joabreu@synopsys.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: canaan,k210-i2s
+ - const: snps,designware-i2s
+ - enum:
+ - snps,designware-i2s
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ The interrupt line number for the I2S controller. Add this
+ parameter if the I2S controller that you are using does not
+ support DMA.
+ maxItems: 1
+
+ clocks:
+ description: Sampling rate reference clock
+
+ clock-names:
+ const: i2sclk
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel
+ minItems: 1
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+ minItems: 1
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: canaan,k210-i2s
+
+then:
+ properties:
+ "#sound-dai-cells":
+ const: 1
+
+else:
+ properties:
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+oneOf:
+ - required:
+ - dmas
+ - dma-names
+ - required:
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc_i2s: i2s@7ff90000 {
+ compatible = "snps,designware-i2s";
+ reg = <0x7ff90000 0x1000>;
+ clocks = <&scpi_i2sclk 0>;
+ clock-names = "i2sclk";
+ #sound-dai-cells = <0>;
+ dmas = <&dma0 5>;
+ dma-names = "tx";
+ };
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 03/14] ASoC: dt-bindings: convert designware-i2s to dt-schema
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
Convert the Synopsys DesignWare I2S controller binding to dt-schema.
There was no listed maintainer but Jose Abreu was the last editor of the
txt binding so add him as maintainer.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/sound/designware-i2s.txt | 35 -------
.../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++
2 files changed, 93 insertions(+), 35 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt
create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt
deleted file mode 100644
index 6a536d570e29..000000000000
--- a/Documentation/devicetree/bindings/sound/designware-i2s.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-DesignWare I2S controller
-
-Required properties:
- - compatible : Must be "snps,designware-i2s"
- - reg : Must contain the I2S core's registers location and length
- - clocks : Pairs of phandle and specifier referencing the controller's
- clocks. The controller expects one clock: the clock used as the sampling
- rate reference clock sample.
- - clock-names : "i2sclk" for the sample rate reference clock.
- - dmas: Pairs of phandle and specifier for the DMA channels that are used by
- the core. The core expects one or two dma channels: one for transmit and
- one for receive.
- - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
-
-Optional properties:
- - interrupts: The interrupt line number for the I2S controller. Add this
- parameter if the I2S controller that you are using does not support DMA.
-
-For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
-properties please check:
- * resource-names.txt
- * clock/clock-bindings.txt
- * dma/dma.txt
-
-Example:
-
- soc_i2s: i2s@7ff90000 {
- compatible = "snps,designware-i2s";
- reg = <0x0 0x7ff90000 0x0 0x1000>;
- clocks = <&scpi_i2sclk 0>;
- clock-names = "i2sclk";
- #sound-dai-cells = <0>;
- dmas = <&dma0 5>;
- dma-names = "tx";
- };
diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
new file mode 100644
index 000000000000..5ac9c00157bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DesignWare I2S controller
+
+maintainers:
+ - Jose Abreu <joabreu@synopsys.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: canaan,k210-i2s
+ - const: snps,designware-i2s
+ - enum:
+ - snps,designware-i2s
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ The interrupt line number for the I2S controller. Add this
+ parameter if the I2S controller that you are using does not
+ support DMA.
+ maxItems: 1
+
+ clocks:
+ description: Sampling rate reference clock
+
+ clock-names:
+ const: i2sclk
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel
+ minItems: 1
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+ minItems: 1
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: canaan,k210-i2s
+
+then:
+ properties:
+ "#sound-dai-cells":
+ const: 1
+
+else:
+ properties:
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+oneOf:
+ - required:
+ - dmas
+ - dma-names
+ - required:
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ soc_i2s: i2s@7ff90000 {
+ compatible = "snps,designware-i2s";
+ reg = <0x7ff90000 0x1000>;
+ clocks = <&scpi_i2sclk 0>;
+ clock-names = "i2sclk";
+ #sound-dai-cells = <0>;
+ dmas = <&dma0 5>;
+ dma-names = "tx";
+ };
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread* Re: [PATCH 03/14] ASoC: dt-bindings: convert designware-i2s to dt-schema
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-27 23:22 ` Rob Herring
-1 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:22 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Krzysztof Kozlowski, Thierry Reding,
Sam Ravnborg, Eugeniy Paltsev, Vinod Koul, Liam Girdwood,
Mark Brown, Serge Semin, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:25PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Convert the Synopsys DesignWare I2S controller binding to dt-schema.
> There was no listed maintainer but Jose Abreu was the last editor of the
> txt binding so add him as maintainer.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/sound/designware-i2s.txt | 35 -------
> .../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++
> 2 files changed, 93 insertions(+), 35 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt
> create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt
> deleted file mode 100644
> index 6a536d570e29..000000000000
> --- a/Documentation/devicetree/bindings/sound/designware-i2s.txt
> +++ /dev/null
> @@ -1,35 +0,0 @@
> -DesignWare I2S controller
> -
> -Required properties:
> - - compatible : Must be "snps,designware-i2s"
> - - reg : Must contain the I2S core's registers location and length
> - - clocks : Pairs of phandle and specifier referencing the controller's
> - clocks. The controller expects one clock: the clock used as the sampling
> - rate reference clock sample.
> - - clock-names : "i2sclk" for the sample rate reference clock.
> - - dmas: Pairs of phandle and specifier for the DMA channels that are used by
> - the core. The core expects one or two dma channels: one for transmit and
> - one for receive.
> - - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
> -
> -Optional properties:
> - - interrupts: The interrupt line number for the I2S controller. Add this
> - parameter if the I2S controller that you are using does not support DMA.
> -
> -For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
> -properties please check:
> - * resource-names.txt
> - * clock/clock-bindings.txt
> - * dma/dma.txt
> -
> -Example:
> -
> - soc_i2s: i2s@7ff90000 {
> - compatible = "snps,designware-i2s";
> - reg = <0x0 0x7ff90000 0x0 0x1000>;
> - clocks = <&scpi_i2sclk 0>;
> - clock-names = "i2sclk";
> - #sound-dai-cells = <0>;
> - dmas = <&dma0 5>;
> - dma-names = "tx";
> - };
> diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
> new file mode 100644
> index 000000000000..5ac9c00157bf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
> @@ -0,0 +1,93 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: DesignWare I2S controller
> +
> +maintainers:
> + - Jose Abreu <joabreu@synopsys.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: canaan,k210-i2s
> + - const: snps,designware-i2s
> + - enum:
> + - snps,designware-i2s
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description: |
> + The interrupt line number for the I2S controller. Add this
> + parameter if the I2S controller that you are using does not
> + support DMA.
> + maxItems: 1
> +
> + clocks:
> + description: Sampling rate reference clock
How many?
> +
> + clock-names:
> + const: i2sclk
> +
> + resets:
> + maxItems: 1
> +
> + dmas:
> + items:
> + - description: TX DMA Channel
> + - description: RX DMA Channel
> + minItems: 1
> +
> + dma-names:
> + items:
> + - const: tx
> + - const: rx
> + minItems: 1
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: canaan,k210-i2s
> +
> +then:
> + properties:
> + "#sound-dai-cells":
> + const: 1
> +
> +else:
> + properties:
> + "#sound-dai-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +oneOf:
> + - required:
> + - dmas
> + - dma-names
> + - required:
> + - interrupts
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + soc_i2s: i2s@7ff90000 {
> + compatible = "snps,designware-i2s";
> + reg = <0x7ff90000 0x1000>;
> + clocks = <&scpi_i2sclk 0>;
> + clock-names = "i2sclk";
> + #sound-dai-cells = <0>;
> + dmas = <&dma0 5>;
> + dma-names = "tx";
> + };
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 03/14] ASoC: dt-bindings: convert designware-i2s to dt-schema
@ 2022-06-27 23:22 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:22 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Krzysztof Kozlowski, Thierry Reding,
Sam Ravnborg, Eugeniy Paltsev, Vinod Koul, Liam Girdwood,
Mark Brown, Serge Semin, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:25PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Convert the Synopsys DesignWare I2S controller binding to dt-schema.
> There was no listed maintainer but Jose Abreu was the last editor of the
> txt binding so add him as maintainer.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/sound/designware-i2s.txt | 35 -------
> .../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++
> 2 files changed, 93 insertions(+), 35 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt
> create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt
> deleted file mode 100644
> index 6a536d570e29..000000000000
> --- a/Documentation/devicetree/bindings/sound/designware-i2s.txt
> +++ /dev/null
> @@ -1,35 +0,0 @@
> -DesignWare I2S controller
> -
> -Required properties:
> - - compatible : Must be "snps,designware-i2s"
> - - reg : Must contain the I2S core's registers location and length
> - - clocks : Pairs of phandle and specifier referencing the controller's
> - clocks. The controller expects one clock: the clock used as the sampling
> - rate reference clock sample.
> - - clock-names : "i2sclk" for the sample rate reference clock.
> - - dmas: Pairs of phandle and specifier for the DMA channels that are used by
> - the core. The core expects one or two dma channels: one for transmit and
> - one for receive.
> - - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
> -
> -Optional properties:
> - - interrupts: The interrupt line number for the I2S controller. Add this
> - parameter if the I2S controller that you are using does not support DMA.
> -
> -For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
> -properties please check:
> - * resource-names.txt
> - * clock/clock-bindings.txt
> - * dma/dma.txt
> -
> -Example:
> -
> - soc_i2s: i2s@7ff90000 {
> - compatible = "snps,designware-i2s";
> - reg = <0x0 0x7ff90000 0x0 0x1000>;
> - clocks = <&scpi_i2sclk 0>;
> - clock-names = "i2sclk";
> - #sound-dai-cells = <0>;
> - dmas = <&dma0 5>;
> - dma-names = "tx";
> - };
> diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
> new file mode 100644
> index 000000000000..5ac9c00157bf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
> @@ -0,0 +1,93 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: DesignWare I2S controller
> +
> +maintainers:
> + - Jose Abreu <joabreu@synopsys.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: canaan,k210-i2s
> + - const: snps,designware-i2s
> + - enum:
> + - snps,designware-i2s
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description: |
> + The interrupt line number for the I2S controller. Add this
> + parameter if the I2S controller that you are using does not
> + support DMA.
> + maxItems: 1
> +
> + clocks:
> + description: Sampling rate reference clock
How many?
> +
> + clock-names:
> + const: i2sclk
> +
> + resets:
> + maxItems: 1
> +
> + dmas:
> + items:
> + - description: TX DMA Channel
> + - description: RX DMA Channel
> + minItems: 1
> +
> + dma-names:
> + items:
> + - const: tx
> + - const: rx
> + minItems: 1
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: canaan,k210-i2s
> +
> +then:
> + properties:
> + "#sound-dai-cells":
> + const: 1
> +
> +else:
> + properties:
> + "#sound-dai-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +oneOf:
> + - required:
> + - dmas
> + - dma-names
> + - required:
> + - interrupts
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + soc_i2s: i2s@7ff90000 {
> + compatible = "snps,designware-i2s";
> + reg = <0x7ff90000 0x1000>;
> + clocks = <&scpi_i2sclk 0>;
> + clock-names = "i2sclk";
> + #sound-dai-cells = <0>;
> + dmas = <&dma0 5>;
> + dma-names = "tx";
> + };
> --
> 2.36.1
>
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 03/14] ASoC: dt-bindings: convert designware-i2s to dt-schema
@ 2022-06-27 23:22 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:22 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, alsa-devel, David Airlie, Palmer Dabbelt,
linux-kernel, Conor Dooley, Thierry Reding, Heng Sia,
Krzysztof Kozlowski, linux-riscv, Sam Ravnborg, Damien Le Moal,
Daniel Lezcano, Jose Abreu, Geert Uytterhoeven, Eugeniy Paltsev,
devicetree, Albert Ou, Mark Brown, dri-devel, Paul Walmsley,
Thomas Gleixner, Dillon Min, Liam Girdwood, Serge Semin,
linux-spi, Vinod Koul, Palmer Dabbelt, dmaengine,
Masahiro Yamada
On Sat, Jun 18, 2022 at 01:30:25PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Convert the Synopsys DesignWare I2S controller binding to dt-schema.
> There was no listed maintainer but Jose Abreu was the last editor of the
> txt binding so add him as maintainer.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/sound/designware-i2s.txt | 35 -------
> .../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++
> 2 files changed, 93 insertions(+), 35 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt
> create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt
> deleted file mode 100644
> index 6a536d570e29..000000000000
> --- a/Documentation/devicetree/bindings/sound/designware-i2s.txt
> +++ /dev/null
> @@ -1,35 +0,0 @@
> -DesignWare I2S controller
> -
> -Required properties:
> - - compatible : Must be "snps,designware-i2s"
> - - reg : Must contain the I2S core's registers location and length
> - - clocks : Pairs of phandle and specifier referencing the controller's
> - clocks. The controller expects one clock: the clock used as the sampling
> - rate reference clock sample.
> - - clock-names : "i2sclk" for the sample rate reference clock.
> - - dmas: Pairs of phandle and specifier for the DMA channels that are used by
> - the core. The core expects one or two dma channels: one for transmit and
> - one for receive.
> - - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
> -
> -Optional properties:
> - - interrupts: The interrupt line number for the I2S controller. Add this
> - parameter if the I2S controller that you are using does not support DMA.
> -
> -For more details on the 'dma', 'dma-names', 'clock' and 'clock-names'
> -properties please check:
> - * resource-names.txt
> - * clock/clock-bindings.txt
> - * dma/dma.txt
> -
> -Example:
> -
> - soc_i2s: i2s@7ff90000 {
> - compatible = "snps,designware-i2s";
> - reg = <0x0 0x7ff90000 0x0 0x1000>;
> - clocks = <&scpi_i2sclk 0>;
> - clock-names = "i2sclk";
> - #sound-dai-cells = <0>;
> - dmas = <&dma0 5>;
> - dma-names = "tx";
> - };
> diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
> new file mode 100644
> index 000000000000..5ac9c00157bf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
> @@ -0,0 +1,93 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: DesignWare I2S controller
> +
> +maintainers:
> + - Jose Abreu <joabreu@synopsys.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: canaan,k210-i2s
> + - const: snps,designware-i2s
> + - enum:
> + - snps,designware-i2s
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description: |
> + The interrupt line number for the I2S controller. Add this
> + parameter if the I2S controller that you are using does not
> + support DMA.
> + maxItems: 1
> +
> + clocks:
> + description: Sampling rate reference clock
How many?
> +
> + clock-names:
> + const: i2sclk
> +
> + resets:
> + maxItems: 1
> +
> + dmas:
> + items:
> + - description: TX DMA Channel
> + - description: RX DMA Channel
> + minItems: 1
> +
> + dma-names:
> + items:
> + - const: tx
> + - const: rx
> + minItems: 1
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: canaan,k210-i2s
> +
> +then:
> + properties:
> + "#sound-dai-cells":
> + const: 1
> +
> +else:
> + properties:
> + "#sound-dai-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +oneOf:
> + - required:
> + - dmas
> + - dma-names
> + - required:
> + - interrupts
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + soc_i2s: i2s@7ff90000 {
> + compatible = "snps,designware-i2s";
> + reg = <0x7ff90000 0x1000>;
> + clocks = <&scpi_i2sclk 0>;
> + clock-names = "i2sclk";
> + #sound-dai-cells = <0>;
> + dmas = <&dma0 5>;
> + dma-names = "tx";
> + };
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 159+ messages in thread
* [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
controller, but according to the documentation & devicetree it has 6
interrupts rather than the standard one. Add a custom compatible that
supports the 6 interrupt configuration which falls back to the standard
binding which is currently the one in use in the devicetree entry.
Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++-----
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 4324a94b26b2..bc85598151ef 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -18,9 +18,13 @@ allOf:
properties:
compatible:
- enum:
- - snps,axi-dma-1.01a
- - intel,kmb-axi-dma
+ oneOf:
+ - items:
+ - const: canaan,k210-axi-dma
+ - const: snps,axi-dma-1.01a
+ - enum:
+ - snps,axi-dma-1.01a
+ - intel,kmb-axi-dma
reg:
minItems: 1
@@ -33,9 +37,6 @@ properties:
- const: axidma_ctrl_regs
- const: axidma_apb_regs
- interrupts:
- maxItems: 1
-
clocks:
items:
- description: Bus Clock
@@ -92,6 +93,22 @@ properties:
minimum: 1
maximum: 256
+if:
+ properties:
+ compatible:
+ contains:
+ const: canaan,k210-axi-dma
+
+then:
+ properties:
+ interrupts:
+ maxItems: 6
+
+else:
+ properties:
+ interrupts:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -105,7 +122,7 @@ required:
- snps,priority
- snps,block-size
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
@@ -113,12 +130,12 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
/* example with snps,dw-axi-dmac */
dmac: dma-controller@80000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
reg = <0x80000 0x400>;
clocks = <&core_clk>, <&cfgr_clk>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
- interrupts = <27>;
+ interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <2>;
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
controller, but according to the documentation & devicetree it has 6
interrupts rather than the standard one. Add a custom compatible that
supports the 6 interrupt configuration which falls back to the standard
binding which is currently the one in use in the devicetree entry.
Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++-----
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 4324a94b26b2..bc85598151ef 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -18,9 +18,13 @@ allOf:
properties:
compatible:
- enum:
- - snps,axi-dma-1.01a
- - intel,kmb-axi-dma
+ oneOf:
+ - items:
+ - const: canaan,k210-axi-dma
+ - const: snps,axi-dma-1.01a
+ - enum:
+ - snps,axi-dma-1.01a
+ - intel,kmb-axi-dma
reg:
minItems: 1
@@ -33,9 +37,6 @@ properties:
- const: axidma_ctrl_regs
- const: axidma_apb_regs
- interrupts:
- maxItems: 1
-
clocks:
items:
- description: Bus Clock
@@ -92,6 +93,22 @@ properties:
minimum: 1
maximum: 256
+if:
+ properties:
+ compatible:
+ contains:
+ const: canaan,k210-axi-dma
+
+then:
+ properties:
+ interrupts:
+ maxItems: 6
+
+else:
+ properties:
+ interrupts:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -105,7 +122,7 @@ required:
- snps,priority
- snps,block-size
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
@@ -113,12 +130,12 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
/* example with snps,dw-axi-dmac */
dmac: dma-controller@80000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
reg = <0x80000 0x400>;
clocks = <&core_clk>, <&cfgr_clk>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
- interrupts = <27>;
+ interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <2>;
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
controller, but according to the documentation & devicetree it has 6
interrupts rather than the standard one. Add a custom compatible that
supports the 6 interrupt configuration which falls back to the standard
binding which is currently the one in use in the devicetree entry.
Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++-----
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 4324a94b26b2..bc85598151ef 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -18,9 +18,13 @@ allOf:
properties:
compatible:
- enum:
- - snps,axi-dma-1.01a
- - intel,kmb-axi-dma
+ oneOf:
+ - items:
+ - const: canaan,k210-axi-dma
+ - const: snps,axi-dma-1.01a
+ - enum:
+ - snps,axi-dma-1.01a
+ - intel,kmb-axi-dma
reg:
minItems: 1
@@ -33,9 +37,6 @@ properties:
- const: axidma_ctrl_regs
- const: axidma_apb_regs
- interrupts:
- maxItems: 1
-
clocks:
items:
- description: Bus Clock
@@ -92,6 +93,22 @@ properties:
minimum: 1
maximum: 256
+if:
+ properties:
+ compatible:
+ contains:
+ const: canaan,k210-axi-dma
+
+then:
+ properties:
+ interrupts:
+ maxItems: 6
+
+else:
+ properties:
+ interrupts:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -105,7 +122,7 @@ required:
- snps,priority
- snps,block-size
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
@@ -113,12 +130,12 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
/* example with snps,dw-axi-dmac */
dmac: dma-controller@80000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
reg = <0x80000 0x400>;
clocks = <&core_clk>, <&cfgr_clk>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
- interrupts = <27>;
+ interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
dma-channels = <4>;
snps,dma-masters = <2>;
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-27 23:29 ` Rob Herring
-1 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:29 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Krzysztof Kozlowski, Thierry Reding,
Sam Ravnborg, Eugeniy Paltsev, Vinod Koul, Liam Girdwood,
Mark Brown, Serge Semin, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> controller, but according to the documentation & devicetree it has 6
> interrupts rather than the standard one. Add a custom compatible that
> supports the 6 interrupt configuration which falls back to the standard
> binding which is currently the one in use in the devicetree entry.
But it works with only 1 interrupt?
>
> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++-----
> 1 file changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 4324a94b26b2..bc85598151ef 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -18,9 +18,13 @@ allOf:
>
> properties:
> compatible:
> - enum:
> - - snps,axi-dma-1.01a
> - - intel,kmb-axi-dma
> + oneOf:
> + - items:
> + - const: canaan,k210-axi-dma
> + - const: snps,axi-dma-1.01a
I would drop this depending on your need for compatibility. Are you sure
on the IP version? It's not really compatible if the number of
interrupts is different.
> + - enum:
> + - snps,axi-dma-1.01a
> + - intel,kmb-axi-dma
>
> reg:
> minItems: 1
> @@ -33,9 +37,6 @@ properties:
> - const: axidma_ctrl_regs
> - const: axidma_apb_regs
>
> - interrupts:
> - maxItems: 1
> -
> clocks:
> items:
> - description: Bus Clock
> @@ -92,6 +93,22 @@ properties:
> minimum: 1
> maximum: 256
>
> +if:
> + properties:
> + compatible:
> + contains:
> + const: canaan,k210-axi-dma
> +
> +then:
> + properties:
> + interrupts:
> + maxItems: 6
> +
> +else:
> + properties:
> + interrupts:
> + maxItems: 1
> +
> required:
> - compatible
> - reg
> @@ -105,7 +122,7 @@ required:
> - snps,priority
> - snps,block-size
>
> -additionalProperties: false
> +unevaluatedProperties: false
>
> examples:
> - |
> @@ -113,12 +130,12 @@ examples:
> #include <dt-bindings/interrupt-controller/irq.h>
> /* example with snps,dw-axi-dmac */
> dmac: dma-controller@80000 {
> - compatible = "snps,axi-dma-1.01a";
> + compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
> reg = <0x80000 0x400>;
> clocks = <&core_clk>, <&cfgr_clk>;
> clock-names = "core-clk", "cfgr-clk";
> interrupt-parent = <&intc>;
> - interrupts = <27>;
> + interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
Does the example really need changing? The old one was correct, right?
> #dma-cells = <1>;
> dma-channels = <4>;
> snps,dma-masters = <2>;
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-27 23:29 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:29 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, alsa-devel, David Airlie, Palmer Dabbelt,
linux-kernel, Conor Dooley, Thierry Reding, Heng Sia,
Krzysztof Kozlowski, linux-riscv, Sam Ravnborg, Damien Le Moal,
Daniel Lezcano, Jose Abreu, Geert Uytterhoeven, Eugeniy Paltsev,
devicetree, Albert Ou, Mark Brown, dri-devel, Paul Walmsley,
Thomas Gleixner, Dillon Min, Liam Girdwood, Serge Semin,
linux-spi, Vinod Koul, Palmer Dabbelt, dmaengine,
Masahiro Yamada
On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> controller, but according to the documentation & devicetree it has 6
> interrupts rather than the standard one. Add a custom compatible that
> supports the 6 interrupt configuration which falls back to the standard
> binding which is currently the one in use in the devicetree entry.
But it works with only 1 interrupt?
>
> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++-----
> 1 file changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 4324a94b26b2..bc85598151ef 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -18,9 +18,13 @@ allOf:
>
> properties:
> compatible:
> - enum:
> - - snps,axi-dma-1.01a
> - - intel,kmb-axi-dma
> + oneOf:
> + - items:
> + - const: canaan,k210-axi-dma
> + - const: snps,axi-dma-1.01a
I would drop this depending on your need for compatibility. Are you sure
on the IP version? It's not really compatible if the number of
interrupts is different.
> + - enum:
> + - snps,axi-dma-1.01a
> + - intel,kmb-axi-dma
>
> reg:
> minItems: 1
> @@ -33,9 +37,6 @@ properties:
> - const: axidma_ctrl_regs
> - const: axidma_apb_regs
>
> - interrupts:
> - maxItems: 1
> -
> clocks:
> items:
> - description: Bus Clock
> @@ -92,6 +93,22 @@ properties:
> minimum: 1
> maximum: 256
>
> +if:
> + properties:
> + compatible:
> + contains:
> + const: canaan,k210-axi-dma
> +
> +then:
> + properties:
> + interrupts:
> + maxItems: 6
> +
> +else:
> + properties:
> + interrupts:
> + maxItems: 1
> +
> required:
> - compatible
> - reg
> @@ -105,7 +122,7 @@ required:
> - snps,priority
> - snps,block-size
>
> -additionalProperties: false
> +unevaluatedProperties: false
>
> examples:
> - |
> @@ -113,12 +130,12 @@ examples:
> #include <dt-bindings/interrupt-controller/irq.h>
> /* example with snps,dw-axi-dmac */
> dmac: dma-controller@80000 {
> - compatible = "snps,axi-dma-1.01a";
> + compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
> reg = <0x80000 0x400>;
> clocks = <&core_clk>, <&cfgr_clk>;
> clock-names = "core-clk", "cfgr-clk";
> interrupt-parent = <&intc>;
> - interrupts = <27>;
> + interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
Does the example really need changing? The old one was correct, right?
> #dma-cells = <1>;
> dma-channels = <4>;
> snps,dma-masters = <2>;
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-27 23:29 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:29 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Krzysztof Kozlowski, Thierry Reding,
Sam Ravnborg, Eugeniy Paltsev, Vinod Koul, Liam Girdwood,
Mark Brown, Serge Semin, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> controller, but according to the documentation & devicetree it has 6
> interrupts rather than the standard one. Add a custom compatible that
> supports the 6 interrupt configuration which falls back to the standard
> binding which is currently the one in use in the devicetree entry.
But it works with only 1 interrupt?
>
> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++-----
> 1 file changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 4324a94b26b2..bc85598151ef 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -18,9 +18,13 @@ allOf:
>
> properties:
> compatible:
> - enum:
> - - snps,axi-dma-1.01a
> - - intel,kmb-axi-dma
> + oneOf:
> + - items:
> + - const: canaan,k210-axi-dma
> + - const: snps,axi-dma-1.01a
I would drop this depending on your need for compatibility. Are you sure
on the IP version? It's not really compatible if the number of
interrupts is different.
> + - enum:
> + - snps,axi-dma-1.01a
> + - intel,kmb-axi-dma
>
> reg:
> minItems: 1
> @@ -33,9 +37,6 @@ properties:
> - const: axidma_ctrl_regs
> - const: axidma_apb_regs
>
> - interrupts:
> - maxItems: 1
> -
> clocks:
> items:
> - description: Bus Clock
> @@ -92,6 +93,22 @@ properties:
> minimum: 1
> maximum: 256
>
> +if:
> + properties:
> + compatible:
> + contains:
> + const: canaan,k210-axi-dma
> +
> +then:
> + properties:
> + interrupts:
> + maxItems: 6
> +
> +else:
> + properties:
> + interrupts:
> + maxItems: 1
> +
> required:
> - compatible
> - reg
> @@ -105,7 +122,7 @@ required:
> - snps,priority
> - snps,block-size
>
> -additionalProperties: false
> +unevaluatedProperties: false
>
> examples:
> - |
> @@ -113,12 +130,12 @@ examples:
> #include <dt-bindings/interrupt-controller/irq.h>
> /* example with snps,dw-axi-dmac */
> dmac: dma-controller@80000 {
> - compatible = "snps,axi-dma-1.01a";
> + compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
> reg = <0x80000 0x400>;
> clocks = <&core_clk>, <&cfgr_clk>;
> clock-names = "core-clk", "cfgr-clk";
> interrupt-parent = <&intc>;
> - interrupts = <27>;
> + interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
Does the example really need changing? The old one was correct, right?
> #dma-cells = <1>;
> dma-channels = <4>;
> snps,dma-masters = <2>;
> --
> 2.36.1
>
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
2022-06-27 23:29 ` Rob Herring
(?)
@ 2022-06-28 6:30 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-28 6:30 UTC (permalink / raw)
To: robh, mail
Cc: airlied, daniel, krzysztof.kozlowski+dt, thierry.reding, sam,
Eugeniy.Paltsev, vkoul, lgirdwood, broonie, fancer.lancer,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, damien.lemoal, geert, niklas.cassel, dillon.minfei,
jee.heng.sia, joabreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On 28/06/2022 00:29, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
>> controller, but according to the documentation & devicetree it has 6
>> interrupts rather than the standard one. Add a custom compatible that
>> supports the 6 interrupt configuration which falls back to the standard
>> binding which is currently the one in use in the devicetree entry.
>
> But it works with only 1 interrupt?
Seemingly...
>
>>
>> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++-----
>> 1 file changed, 26 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> index 4324a94b26b2..bc85598151ef 100644
>> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> @@ -18,9 +18,13 @@ allOf:
>>
>> properties:
>> compatible:
>> - enum:
>> - - snps,axi-dma-1.01a
>> - - intel,kmb-axi-dma
>> + oneOf:
>> + - items:
>> + - const: canaan,k210-axi-dma
>> + - const: snps,axi-dma-1.01a
>
> I would drop this depending on your need for compatibility. Are you sure
> on the IP version? It's not really compatible if the number of
> interrupts is different.
That's what it has been using until now. Am I sure? No.
Do I have docs to go check against? Unfortunately, also no.
Does it not qualify as a fallback compatible if it supports
a subset of what the hardware does?
>
>> + - enum:
>> + - snps,axi-dma-1.01a
>> + - intel,kmb-axi-dma
>>
>> reg:
>> minItems: 1
>> @@ -33,9 +37,6 @@ properties:
>> - const: axidma_ctrl_regs
>> - const: axidma_apb_regs
>>
>> - interrupts:
>> - maxItems: 1
>> -
>> clocks:
>> items:
>> - description: Bus Clock
>> @@ -92,6 +93,22 @@ properties:
>> minimum: 1
>> maximum: 256
>>
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: canaan,k210-axi-dma
>> +
>> +then:
>> + properties:
>> + interrupts:
>> + maxItems: 6
>> +
>> +else:
>> + properties:
>> + interrupts:
>> + maxItems: 1
>> +
>> required:
>> - compatible
>> - reg
>> @@ -105,7 +122,7 @@ required:
>> - snps,priority
>> - snps,block-size
>>
>> -additionalProperties: false
>> +unevaluatedProperties: false
>>
>> examples:
>> - |
>> @@ -113,12 +130,12 @@ examples:
>> #include <dt-bindings/interrupt-controller/irq.h>
>> /* example with snps,dw-axi-dmac */
>> dmac: dma-controller@80000 {
>> - compatible = "snps,axi-dma-1.01a";
>> + compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
>> reg = <0x80000 0x400>;
>> clocks = <&core_clk>, <&cfgr_clk>;
>> clock-names = "core-clk", "cfgr-clk";
>> interrupt-parent = <&intc>;
>> - interrupts = <27>;
>> + interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
>
> Does the example really need changing? The old one was correct, right?
:facepalm:, committed my dt_binding_check test
Thanks Rob,
Conor.
>
>> #dma-cells = <1>;
>> dma-channels = <4>;
>> snps,dma-masters = <2>;
>> --
>> 2.36.1
>>
>>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-28 6:30 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-28 6:30 UTC (permalink / raw)
To: robh, mail
Cc: airlied, daniel, krzysztof.kozlowski+dt, thierry.reding, sam,
Eugeniy.Paltsev, vkoul, lgirdwood, broonie, fancer.lancer,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, damien.lemoal, geert, niklas.cassel, dillon.minfei,
jee.heng.sia, joabreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On 28/06/2022 00:29, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
>> controller, but according to the documentation & devicetree it has 6
>> interrupts rather than the standard one. Add a custom compatible that
>> supports the 6 interrupt configuration which falls back to the standard
>> binding which is currently the one in use in the devicetree entry.
>
> But it works with only 1 interrupt?
Seemingly...
>
>>
>> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++-----
>> 1 file changed, 26 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> index 4324a94b26b2..bc85598151ef 100644
>> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> @@ -18,9 +18,13 @@ allOf:
>>
>> properties:
>> compatible:
>> - enum:
>> - - snps,axi-dma-1.01a
>> - - intel,kmb-axi-dma
>> + oneOf:
>> + - items:
>> + - const: canaan,k210-axi-dma
>> + - const: snps,axi-dma-1.01a
>
> I would drop this depending on your need for compatibility. Are you sure
> on the IP version? It's not really compatible if the number of
> interrupts is different.
That's what it has been using until now. Am I sure? No.
Do I have docs to go check against? Unfortunately, also no.
Does it not qualify as a fallback compatible if it supports
a subset of what the hardware does?
>
>> + - enum:
>> + - snps,axi-dma-1.01a
>> + - intel,kmb-axi-dma
>>
>> reg:
>> minItems: 1
>> @@ -33,9 +37,6 @@ properties:
>> - const: axidma_ctrl_regs
>> - const: axidma_apb_regs
>>
>> - interrupts:
>> - maxItems: 1
>> -
>> clocks:
>> items:
>> - description: Bus Clock
>> @@ -92,6 +93,22 @@ properties:
>> minimum: 1
>> maximum: 256
>>
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: canaan,k210-axi-dma
>> +
>> +then:
>> + properties:
>> + interrupts:
>> + maxItems: 6
>> +
>> +else:
>> + properties:
>> + interrupts:
>> + maxItems: 1
>> +
>> required:
>> - compatible
>> - reg
>> @@ -105,7 +122,7 @@ required:
>> - snps,priority
>> - snps,block-size
>>
>> -additionalProperties: false
>> +unevaluatedProperties: false
>>
>> examples:
>> - |
>> @@ -113,12 +130,12 @@ examples:
>> #include <dt-bindings/interrupt-controller/irq.h>
>> /* example with snps,dw-axi-dmac */
>> dmac: dma-controller@80000 {
>> - compatible = "snps,axi-dma-1.01a";
>> + compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
>> reg = <0x80000 0x400>;
>> clocks = <&core_clk>, <&cfgr_clk>;
>> clock-names = "core-clk", "cfgr-clk";
>> interrupt-parent = <&intc>;
>> - interrupts = <27>;
>> + interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
>
> Does the example really need changing? The old one was correct, right?
:facepalm:, committed my dt_binding_check test
Thanks Rob,
Conor.
>
>> #dma-cells = <1>;
>> dma-channels = <4>;
>> snps,dma-masters = <2>;
>> --
>> 2.36.1
>>
>>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-28 6:30 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-28 6:30 UTC (permalink / raw)
To: robh, mail
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, jee.heng.sia, krzysztof.kozlowski+dt,
linux-riscv, sam, damien.lemoal, daniel.lezcano, joabreu, geert,
Eugeniy.Paltsev, devicetree, aou, broonie, dri-devel,
paul.walmsley, tglx, dillon.minfei, lgirdwood, fancer.lancer,
linux-spi, vkoul, palmer, dmaengine, masahiroy
On 28/06/2022 00:29, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
>> controller, but according to the documentation & devicetree it has 6
>> interrupts rather than the standard one. Add a custom compatible that
>> supports the 6 interrupt configuration which falls back to the standard
>> binding which is currently the one in use in the devicetree entry.
>
> But it works with only 1 interrupt?
Seemingly...
>
>>
>> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++-----
>> 1 file changed, 26 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> index 4324a94b26b2..bc85598151ef 100644
>> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>> @@ -18,9 +18,13 @@ allOf:
>>
>> properties:
>> compatible:
>> - enum:
>> - - snps,axi-dma-1.01a
>> - - intel,kmb-axi-dma
>> + oneOf:
>> + - items:
>> + - const: canaan,k210-axi-dma
>> + - const: snps,axi-dma-1.01a
>
> I would drop this depending on your need for compatibility. Are you sure
> on the IP version? It's not really compatible if the number of
> interrupts is different.
That's what it has been using until now. Am I sure? No.
Do I have docs to go check against? Unfortunately, also no.
Does it not qualify as a fallback compatible if it supports
a subset of what the hardware does?
>
>> + - enum:
>> + - snps,axi-dma-1.01a
>> + - intel,kmb-axi-dma
>>
>> reg:
>> minItems: 1
>> @@ -33,9 +37,6 @@ properties:
>> - const: axidma_ctrl_regs
>> - const: axidma_apb_regs
>>
>> - interrupts:
>> - maxItems: 1
>> -
>> clocks:
>> items:
>> - description: Bus Clock
>> @@ -92,6 +93,22 @@ properties:
>> minimum: 1
>> maximum: 256
>>
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: canaan,k210-axi-dma
>> +
>> +then:
>> + properties:
>> + interrupts:
>> + maxItems: 6
>> +
>> +else:
>> + properties:
>> + interrupts:
>> + maxItems: 1
>> +
>> required:
>> - compatible
>> - reg
>> @@ -105,7 +122,7 @@ required:
>> - snps,priority
>> - snps,block-size
>>
>> -additionalProperties: false
>> +unevaluatedProperties: false
>>
>> examples:
>> - |
>> @@ -113,12 +130,12 @@ examples:
>> #include <dt-bindings/interrupt-controller/irq.h>
>> /* example with snps,dw-axi-dmac */
>> dmac: dma-controller@80000 {
>> - compatible = "snps,axi-dma-1.01a";
>> + compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
>> reg = <0x80000 0x400>;
>> clocks = <&core_clk>, <&cfgr_clk>;
>> clock-names = "core-clk", "cfgr-clk";
>> interrupt-parent = <&intc>;
>> - interrupts = <27>;
>> + interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
>
> Does the example really need changing? The old one was correct, right?
:facepalm:, committed my dt_binding_check test
Thanks Rob,
Conor.
>
>> #dma-cells = <1>;
>> dma-channels = <4>;
>> snps,dma-masters = <2>;
>> --
>> 2.36.1
>>
>>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
2022-06-28 6:30 ` Conor.Dooley
(?)
@ 2022-06-28 7:08 ` Geert Uytterhoeven
-1 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-28 7:08 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Conor Dooley, David Airlie, Daniel Vetter,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod, Liam Girdwood, Mark Brown, Serge Semin,
Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner,
Paul Walmsley, Albert Ou, Masahiro Yamada, Damien Le Moal,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, dmaengine,
ALSA Development Mailing List, linux-spi, linux-riscv
Hi Conor,
On Tue, Jun 28, 2022 at 8:30 AM <Conor.Dooley@microchip.com> wrote:
> On 28/06/2022 00:29, Rob Herring wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> >> controller, but according to the documentation & devicetree it has 6
> >> interrupts rather than the standard one. Add a custom compatible that
> >> supports the 6 interrupt configuration which falls back to the standard
> >> binding which is currently the one in use in the devicetree entry.
> >
> > But it works with only 1 interrupt?
>
> Seemingly...
The Linux driver uses the only first interrupt.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-28 7:08 ` Geert Uytterhoeven
0 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-28 7:08 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Conor Dooley, David Airlie, Daniel Vetter,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod, Liam Girdwood, Mark Brown, Serge Semin,
Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner,
Paul Walmsley, Albert Ou, Masahiro Yamada, Damien Le Moal,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, dmaengine,
ALSA Development Mailing List, linux-spi, linux-riscv
Hi Conor,
On Tue, Jun 28, 2022 at 8:30 AM <Conor.Dooley@microchip.com> wrote:
> On 28/06/2022 00:29, Rob Herring wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> >> controller, but according to the documentation & devicetree it has 6
> >> interrupts rather than the standard one. Add a custom compatible that
> >> supports the 6 interrupt configuration which falls back to the standard
> >> binding which is currently the one in use in the devicetree entry.
> >
> > But it works with only 1 interrupt?
>
> Seemingly...
The Linux driver uses the only first interrupt.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-28 7:08 ` Geert Uytterhoeven
0 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-28 7:08 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, ALSA Development Mailing List, David Airlie,
Palmer Dabbelt, Linux Kernel Mailing List, Thierry Reding,
Heng Sia, Krzysztof Kozlowski, linux-riscv, Sam Ravnborg,
Damien Le Moal, Daniel Lezcano, Jose Abreu, Eugeniy Paltsev,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Albert Ou, Mark Brown, DRI Development, Paul Walmsley,
Conor Dooley, Thomas Gleixner, Dillon Min, Liam Girdwood,
Serge Semin, linux-spi, Vinod, Palmer Dabbelt, dmaengine,
Masahiro Yamada
Hi Conor,
On Tue, Jun 28, 2022 at 8:30 AM <Conor.Dooley@microchip.com> wrote:
> On 28/06/2022 00:29, Rob Herring wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> >> controller, but according to the documentation & devicetree it has 6
> >> interrupts rather than the standard one. Add a custom compatible that
> >> supports the 6 interrupt configuration which falls back to the standard
> >> binding which is currently the one in use in the devicetree entry.
> >
> > But it works with only 1 interrupt?
>
> Seemingly...
The Linux driver uses the only first interrupt.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
2022-06-28 7:08 ` Geert Uytterhoeven
(?)
@ 2022-06-28 7:13 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-28 7:13 UTC (permalink / raw)
To: geert
Cc: robh, mail, airlied, daniel, krzysztof.kozlowski+dt,
thierry.reding, sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie,
fancer.lancer, daniel.lezcano, palmer, palmer, tglx,
paul.walmsley, aou, masahiroy, damien.lemoal, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On 28/06/2022 08:08, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Tue, Jun 28, 2022 at 8:30 AM <Conor.Dooley@microchip.com> wrote:
>> On 28/06/2022 00:29, Rob Herring wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
>>>> controller, but according to the documentation & devicetree it has 6
>>>> interrupts rather than the standard one. Add a custom compatible that
>>>> supports the 6 interrupt configuration which falls back to the standard
>>>> binding which is currently the one in use in the devicetree entry.
>>>
>>> But it works with only 1 interrupt?
>>
>> Seemingly...
>
> The Linux driver uses the only first interrupt.
Aye, that was my basis for the seemingly ;)
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-28 7:13 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-28 7:13 UTC (permalink / raw)
To: geert
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, jee.heng.sia, krzysztof.kozlowski+dt,
linux-riscv, sam, damien.lemoal, daniel.lezcano, joabreu,
Eugeniy.Paltsev, devicetree, aou, broonie, dri-devel,
paul.walmsley, mail, tglx, dillon.minfei, lgirdwood,
fancer.lancer, linux-spi, vkoul, palmer, dmaengine, masahiroy
On 28/06/2022 08:08, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Tue, Jun 28, 2022 at 8:30 AM <Conor.Dooley@microchip.com> wrote:
>> On 28/06/2022 00:29, Rob Herring wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
>>>> controller, but according to the documentation & devicetree it has 6
>>>> interrupts rather than the standard one. Add a custom compatible that
>>>> supports the 6 interrupt configuration which falls back to the standard
>>>> binding which is currently the one in use in the devicetree entry.
>>>
>>> But it works with only 1 interrupt?
>>
>> Seemingly...
>
> The Linux driver uses the only first interrupt.
Aye, that was my basis for the seemingly ;)
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-28 7:13 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-28 7:13 UTC (permalink / raw)
To: geert
Cc: robh, mail, airlied, daniel, krzysztof.kozlowski+dt,
thierry.reding, sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie,
fancer.lancer, daniel.lezcano, palmer, palmer, tglx,
paul.walmsley, aou, masahiroy, damien.lemoal, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On 28/06/2022 08:08, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Tue, Jun 28, 2022 at 8:30 AM <Conor.Dooley@microchip.com> wrote:
>> On 28/06/2022 00:29, Rob Herring wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
>>>> controller, but according to the documentation & devicetree it has 6
>>>> interrupts rather than the standard one. Add a custom compatible that
>>>> supports the 6 interrupt configuration which falls back to the standard
>>>> binding which is currently the one in use in the devicetree entry.
>>>
>>> But it works with only 1 interrupt?
>>
>> Seemingly...
>
> The Linux driver uses the only first interrupt.
Aye, that was my basis for the seemingly ;)
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
2022-06-28 7:08 ` Geert Uytterhoeven
(?)
@ 2022-06-28 11:04 ` Serge Semin
-1 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-28 11:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring
Cc: Conor Dooley, Conor Dooley, David Airlie, Daniel Vetter,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod, Liam Girdwood, Mark Brown,
Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner,
Paul Walmsley, Albert Ou, Masahiro Yamada, Damien Le Moal,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, dmaengine,
ALSA Development Mailing List, linux-spi, linux-riscv
On Tue, Jun 28, 2022 at 09:08:32AM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Tue, Jun 28, 2022 at 8:30 AM <Conor.Dooley@microchip.com> wrote:
> > On 28/06/2022 00:29, Rob Herring wrote:
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > >
> > > On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
> > >> From: Conor Dooley <conor.dooley@microchip.com>
> > >>
> > >> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> > >> controller, but according to the documentation & devicetree it has 6
> > >> interrupts rather than the standard one. Add a custom compatible that
> > >> supports the 6 interrupt configuration which falls back to the standard
> > >> binding which is currently the one in use in the devicetree entry.
> > >
> > > But it works with only 1 interrupt?
> >
> > Seemingly...
>
> The Linux driver uses the only first interrupt.
Folks, there v2 of this series. A more suitable and justified solution has
been given there:
Link: https://lore.kernel.org/lkml/20220627213450.ukqai4bsjzcwhnlp@mobilestation/
-Sergey
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-28 11:04 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-28 11:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring
Cc: Niklas Cassel, ALSA Development Mailing List, David Airlie,
Palmer Dabbelt, Linux Kernel Mailing List, Conor Dooley,
Thierry Reding, Krzysztof Kozlowski, linux-riscv, Sam Ravnborg,
Damien Le Moal, Daniel Lezcano, Jose Abreu, Eugeniy Paltsev,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Albert Ou, Mark Brown, DRI Development, Paul Walmsley,
Conor Dooley, Thomas Gleixner, Dillon Min, Liam Girdwood,
Heng Sia, linux-spi, Vinod, Palmer Dabbelt, dmaengine,
Masahiro Yamada
On Tue, Jun 28, 2022 at 09:08:32AM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Tue, Jun 28, 2022 at 8:30 AM <Conor.Dooley@microchip.com> wrote:
> > On 28/06/2022 00:29, Rob Herring wrote:
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > >
> > > On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
> > >> From: Conor Dooley <conor.dooley@microchip.com>
> > >>
> > >> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> > >> controller, but according to the documentation & devicetree it has 6
> > >> interrupts rather than the standard one. Add a custom compatible that
> > >> supports the 6 interrupt configuration which falls back to the standard
> > >> binding which is currently the one in use in the devicetree entry.
> > >
> > > But it works with only 1 interrupt?
> >
> > Seemingly...
>
> The Linux driver uses the only first interrupt.
Folks, there v2 of this series. A more suitable and justified solution has
been given there:
Link: https://lore.kernel.org/lkml/20220627213450.ukqai4bsjzcwhnlp@mobilestation/
-Sergey
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA
@ 2022-06-28 11:04 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-28 11:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring
Cc: Conor Dooley, Conor Dooley, David Airlie, Daniel Vetter,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod, Liam Girdwood, Mark Brown,
Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner,
Paul Walmsley, Albert Ou, Masahiro Yamada, Damien Le Moal,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, dmaengine,
ALSA Development Mailing List, linux-spi, linux-riscv
On Tue, Jun 28, 2022 at 09:08:32AM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Tue, Jun 28, 2022 at 8:30 AM <Conor.Dooley@microchip.com> wrote:
> > On 28/06/2022 00:29, Rob Herring wrote:
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > >
> > > On Sat, Jun 18, 2022 at 01:30:26PM +0100, Conor Dooley wrote:
> > >> From: Conor Dooley <conor.dooley@microchip.com>
> > >>
> > >> The Canaan k210 apparently has a Sysnopsys Designware AXI DMA
> > >> controller, but according to the documentation & devicetree it has 6
> > >> interrupts rather than the standard one. Add a custom compatible that
> > >> supports the 6 interrupt configuration which falls back to the standard
> > >> binding which is currently the one in use in the devicetree entry.
> > >
> > > But it works with only 1 interrupt?
> >
> > Seemingly...
>
> The Linux driver uses the only first interrupt.
Folks, there v2 of this series. A more suitable and justified solution has
been given there:
Link: https://lore.kernel.org/lkml/20220627213450.ukqai4bsjzcwhnlp@mobilestation/
-Sergey
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread
* [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The Canaan k210 apparently has a Sysnopsys Designware timer but
according to the documentation & devicetree it has 2 interrupts rather
than the standard one. Add a custom compatible that supports the 2
interrupt configuration and falls back to the standard binding (which
is currently the one in use in the devicetree entry).
Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++----
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
index d33c9205a909..9a76acc7a66f 100644
--- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
@@ -12,6 +12,9 @@ maintainers:
properties:
compatible:
oneOf:
+ - items:
+ - const: canaan,k210-apb-timer
+ - const: snps,dw-apb-timer
- const: snps,dw-apb-timer
- enum:
- snps,dw-apb-timer-sp
@@ -21,9 +24,6 @@ properties:
reg:
maxItems: 1
- interrupts:
- maxItems: 1
-
resets:
maxItems: 1
@@ -41,7 +41,23 @@ properties:
clock-frequency: true
-additionalProperties: false
+unevaluatedProperties: false
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: canaan,k210-apb-timer
+
+then:
+ properties:
+ interrupts:
+ maxItems: 2
+
+else:
+ properties:
+ interrupts:
+ maxItems: 1
required:
- compatible
@@ -60,8 +76,8 @@ oneOf:
examples:
- |
timer@ffe00000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 170 4>;
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
+ interrupts = <0 170 4>, <0 170 4>;
reg = <0xffe00000 0x1000>;
clocks = <&timer_clk>, <&timer_pclk>;
clock-names = "timer", "pclk";
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
The Canaan k210 apparently has a Sysnopsys Designware timer but
according to the documentation & devicetree it has 2 interrupts rather
than the standard one. Add a custom compatible that supports the 2
interrupt configuration and falls back to the standard binding (which
is currently the one in use in the devicetree entry).
Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++----
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
index d33c9205a909..9a76acc7a66f 100644
--- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
@@ -12,6 +12,9 @@ maintainers:
properties:
compatible:
oneOf:
+ - items:
+ - const: canaan,k210-apb-timer
+ - const: snps,dw-apb-timer
- const: snps,dw-apb-timer
- enum:
- snps,dw-apb-timer-sp
@@ -21,9 +24,6 @@ properties:
reg:
maxItems: 1
- interrupts:
- maxItems: 1
-
resets:
maxItems: 1
@@ -41,7 +41,23 @@ properties:
clock-frequency: true
-additionalProperties: false
+unevaluatedProperties: false
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: canaan,k210-apb-timer
+
+then:
+ properties:
+ interrupts:
+ maxItems: 2
+
+else:
+ properties:
+ interrupts:
+ maxItems: 1
required:
- compatible
@@ -60,8 +76,8 @@ oneOf:
examples:
- |
timer@ffe00000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 170 4>;
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
+ interrupts = <0 170 4>, <0 170 4>;
reg = <0xffe00000 0x1000>;
clocks = <&timer_clk>, <&timer_pclk>;
clock-names = "timer", "pclk";
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The Canaan k210 apparently has a Sysnopsys Designware timer but
according to the documentation & devicetree it has 2 interrupts rather
than the standard one. Add a custom compatible that supports the 2
interrupt configuration and falls back to the standard binding (which
is currently the one in use in the devicetree entry).
Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++----
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
index d33c9205a909..9a76acc7a66f 100644
--- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
@@ -12,6 +12,9 @@ maintainers:
properties:
compatible:
oneOf:
+ - items:
+ - const: canaan,k210-apb-timer
+ - const: snps,dw-apb-timer
- const: snps,dw-apb-timer
- enum:
- snps,dw-apb-timer-sp
@@ -21,9 +24,6 @@ properties:
reg:
maxItems: 1
- interrupts:
- maxItems: 1
-
resets:
maxItems: 1
@@ -41,7 +41,23 @@ properties:
clock-frequency: true
-additionalProperties: false
+unevaluatedProperties: false
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: canaan,k210-apb-timer
+
+then:
+ properties:
+ interrupts:
+ maxItems: 2
+
+else:
+ properties:
+ interrupts:
+ maxItems: 1
required:
- compatible
@@ -60,8 +76,8 @@ oneOf:
examples:
- |
timer@ffe00000 {
- compatible = "snps,dw-apb-timer";
- interrupts = <0 170 4>;
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
+ interrupts = <0 170 4>, <0 170 4>;
reg = <0xffe00000 0x1000>;
clocks = <&timer_clk>, <&timer_pclk>;
clock-names = "timer", "pclk";
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread* Re: [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-27 23:30 ` Rob Herring
-1 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:30 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Krzysztof Kozlowski, Thierry Reding,
Sam Ravnborg, Eugeniy Paltsev, Vinod Koul, Liam Girdwood,
Mark Brown, Serge Semin, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:27PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The Canaan k210 apparently has a Sysnopsys Designware timer but
> according to the documentation & devicetree it has 2 interrupts rather
> than the standard one. Add a custom compatible that supports the 2
> interrupt configuration and falls back to the standard binding (which
> is currently the one in use in the devicetree entry).
>
> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++----
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> index d33c9205a909..9a76acc7a66f 100644
> --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> @@ -12,6 +12,9 @@ maintainers:
> properties:
> compatible:
> oneOf:
> + - items:
> + - const: canaan,k210-apb-timer
> + - const: snps,dw-apb-timer
> - const: snps,dw-apb-timer
> - enum:
> - snps,dw-apb-timer-sp
> @@ -21,9 +24,6 @@ properties:
> reg:
> maxItems: 1
>
> - interrupts:
> - maxItems: 1
> -
> resets:
> maxItems: 1
>
> @@ -41,7 +41,23 @@ properties:
>
> clock-frequency: true
>
> -additionalProperties: false
> +unevaluatedProperties: false
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: canaan,k210-apb-timer
> +
> +then:
> + properties:
> + interrupts:
> + maxItems: 2
When more than 1, you need to define what they are and the order.
> +
> +else:
> + properties:
> + interrupts:
> + maxItems: 1
>
> required:
> - compatible
> @@ -60,8 +76,8 @@ oneOf:
> examples:
> - |
> timer@ffe00000 {
> - compatible = "snps,dw-apb-timer";
> - interrupts = <0 170 4>;
> + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
> + interrupts = <0 170 4>, <0 170 4>;
> reg = <0xffe00000 0x1000>;
> clocks = <&timer_clk>, <&timer_pclk>;
> clock-names = "timer", "pclk";
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
@ 2022-06-27 23:30 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:30 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, alsa-devel, David Airlie, Palmer Dabbelt,
linux-kernel, Conor Dooley, Thierry Reding, Heng Sia,
Krzysztof Kozlowski, linux-riscv, Sam Ravnborg, Damien Le Moal,
Daniel Lezcano, Jose Abreu, Geert Uytterhoeven, Eugeniy Paltsev,
devicetree, Albert Ou, Mark Brown, dri-devel, Paul Walmsley,
Thomas Gleixner, Dillon Min, Liam Girdwood, Serge Semin,
linux-spi, Vinod Koul, Palmer Dabbelt, dmaengine,
Masahiro Yamada
On Sat, Jun 18, 2022 at 01:30:27PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The Canaan k210 apparently has a Sysnopsys Designware timer but
> according to the documentation & devicetree it has 2 interrupts rather
> than the standard one. Add a custom compatible that supports the 2
> interrupt configuration and falls back to the standard binding (which
> is currently the one in use in the devicetree entry).
>
> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++----
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> index d33c9205a909..9a76acc7a66f 100644
> --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> @@ -12,6 +12,9 @@ maintainers:
> properties:
> compatible:
> oneOf:
> + - items:
> + - const: canaan,k210-apb-timer
> + - const: snps,dw-apb-timer
> - const: snps,dw-apb-timer
> - enum:
> - snps,dw-apb-timer-sp
> @@ -21,9 +24,6 @@ properties:
> reg:
> maxItems: 1
>
> - interrupts:
> - maxItems: 1
> -
> resets:
> maxItems: 1
>
> @@ -41,7 +41,23 @@ properties:
>
> clock-frequency: true
>
> -additionalProperties: false
> +unevaluatedProperties: false
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: canaan,k210-apb-timer
> +
> +then:
> + properties:
> + interrupts:
> + maxItems: 2
When more than 1, you need to define what they are and the order.
> +
> +else:
> + properties:
> + interrupts:
> + maxItems: 1
>
> required:
> - compatible
> @@ -60,8 +76,8 @@ oneOf:
> examples:
> - |
> timer@ffe00000 {
> - compatible = "snps,dw-apb-timer";
> - interrupts = <0 170 4>;
> + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
> + interrupts = <0 170 4>, <0 170 4>;
> reg = <0xffe00000 0x1000>;
> clocks = <&timer_clk>, <&timer_pclk>;
> clock-names = "timer", "pclk";
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
@ 2022-06-27 23:30 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 23:30 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Krzysztof Kozlowski, Thierry Reding,
Sam Ravnborg, Eugeniy Paltsev, Vinod Koul, Liam Girdwood,
Mark Brown, Serge Semin, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:27PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The Canaan k210 apparently has a Sysnopsys Designware timer but
> according to the documentation & devicetree it has 2 interrupts rather
> than the standard one. Add a custom compatible that supports the 2
> interrupt configuration and falls back to the standard binding (which
> is currently the one in use in the devicetree entry).
>
> Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++----
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> index d33c9205a909..9a76acc7a66f 100644
> --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> @@ -12,6 +12,9 @@ maintainers:
> properties:
> compatible:
> oneOf:
> + - items:
> + - const: canaan,k210-apb-timer
> + - const: snps,dw-apb-timer
> - const: snps,dw-apb-timer
> - enum:
> - snps,dw-apb-timer-sp
> @@ -21,9 +24,6 @@ properties:
> reg:
> maxItems: 1
>
> - interrupts:
> - maxItems: 1
> -
> resets:
> maxItems: 1
>
> @@ -41,7 +41,23 @@ properties:
>
> clock-frequency: true
>
> -additionalProperties: false
> +unevaluatedProperties: false
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + const: canaan,k210-apb-timer
> +
> +then:
> + properties:
> + interrupts:
> + maxItems: 2
When more than 1, you need to define what they are and the order.
> +
> +else:
> + properties:
> + interrupts:
> + maxItems: 1
>
> required:
> - compatible
> @@ -60,8 +76,8 @@ oneOf:
> examples:
> - |
> timer@ffe00000 {
> - compatible = "snps,dw-apb-timer";
> - interrupts = <0 170 4>;
> + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
> + interrupts = <0 170 4>, <0 170 4>;
> reg = <0xffe00000 0x1000>;
> clocks = <&timer_clk>, <&timer_pclk>;
> clock-names = "timer", "pclk";
> --
> 2.36.1
>
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
2022-06-27 23:30 ` Rob Herring
(?)
@ 2022-06-28 11:06 ` Serge Semin
-1 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-28 11:06 UTC (permalink / raw)
To: Rob Herring
Cc: Conor Dooley, David Airlie, Daniel Vetter, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
Hi Rob,
On Mon, Jun 27, 2022 at 05:30:25PM -0600, Rob Herring wrote:
> On Sat, Jun 18, 2022 at 01:30:27PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > The Canaan k210 apparently has a Sysnopsys Designware timer but
> > according to the documentation & devicetree it has 2 interrupts rather
> > than the standard one. Add a custom compatible that supports the 2
> > interrupt configuration and falls back to the standard binding (which
> > is currently the one in use in the devicetree entry).
> >
> > Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > .../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++----
> > 1 file changed, 22 insertions(+), 6 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> > index d33c9205a909..9a76acc7a66f 100644
> > --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> > +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> > @@ -12,6 +12,9 @@ maintainers:
> > properties:
> > compatible:
> > oneOf:
> > + - items:
> > + - const: canaan,k210-apb-timer
> > + - const: snps,dw-apb-timer
> > - const: snps,dw-apb-timer
> > - enum:
> > - snps,dw-apb-timer-sp
> > @@ -21,9 +24,6 @@ properties:
> > reg:
> > maxItems: 1
> >
> > - interrupts:
> > - maxItems: 1
> > -
> > resets:
> > maxItems: 1
> >
> > @@ -41,7 +41,23 @@ properties:
> >
> > clock-frequency: true
> >
> > -additionalProperties: false
> > +unevaluatedProperties: false
> > +
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: canaan,k210-apb-timer
> > +
> > +then:
> > + properties:
> > + interrupts:
> > + maxItems: 2
>
> When more than 1, you need to define what they are and the order.
Please see my note to v2 of this patch:
Link: https://lore.kernel.org/lkml/20220627211314.dc2hempelyl5ayjg@mobilestation/
-Sergey
>
> > +
> > +else:
> > + properties:
> > + interrupts:
> > + maxItems: 1
> >
> > required:
> > - compatible
> > @@ -60,8 +76,8 @@ oneOf:
> > examples:
> > - |
> > timer@ffe00000 {
> > - compatible = "snps,dw-apb-timer";
> > - interrupts = <0 170 4>;
> > + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
> > + interrupts = <0 170 4>, <0 170 4>;
> > reg = <0xffe00000 0x1000>;
> > clocks = <&timer_clk>, <&timer_pclk>;
> > clock-names = "timer", "pclk";
> > --
> > 2.36.1
> >
> >
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
@ 2022-06-28 11:06 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-28 11:06 UTC (permalink / raw)
To: Rob Herring
Cc: Niklas Cassel, alsa-devel, David Airlie, Palmer Dabbelt,
linux-kernel, Conor Dooley, Thierry Reding, Krzysztof Kozlowski,
linux-riscv, Sam Ravnborg, Damien Le Moal, Daniel Lezcano,
Jose Abreu, Geert Uytterhoeven, Eugeniy Paltsev, devicetree,
Albert Ou, Mark Brown, dri-devel, Paul Walmsley, Conor Dooley,
Thomas Gleixner, Dillon Min, Liam Girdwood, Heng Sia, linux-spi,
Vinod Koul, Palmer Dabbelt, dmaengine, Masahiro Yamada
Hi Rob,
On Mon, Jun 27, 2022 at 05:30:25PM -0600, Rob Herring wrote:
> On Sat, Jun 18, 2022 at 01:30:27PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > The Canaan k210 apparently has a Sysnopsys Designware timer but
> > according to the documentation & devicetree it has 2 interrupts rather
> > than the standard one. Add a custom compatible that supports the 2
> > interrupt configuration and falls back to the standard binding (which
> > is currently the one in use in the devicetree entry).
> >
> > Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > .../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++----
> > 1 file changed, 22 insertions(+), 6 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> > index d33c9205a909..9a76acc7a66f 100644
> > --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> > +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> > @@ -12,6 +12,9 @@ maintainers:
> > properties:
> > compatible:
> > oneOf:
> > + - items:
> > + - const: canaan,k210-apb-timer
> > + - const: snps,dw-apb-timer
> > - const: snps,dw-apb-timer
> > - enum:
> > - snps,dw-apb-timer-sp
> > @@ -21,9 +24,6 @@ properties:
> > reg:
> > maxItems: 1
> >
> > - interrupts:
> > - maxItems: 1
> > -
> > resets:
> > maxItems: 1
> >
> > @@ -41,7 +41,23 @@ properties:
> >
> > clock-frequency: true
> >
> > -additionalProperties: false
> > +unevaluatedProperties: false
> > +
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: canaan,k210-apb-timer
> > +
> > +then:
> > + properties:
> > + interrupts:
> > + maxItems: 2
>
> When more than 1, you need to define what they are and the order.
Please see my note to v2 of this patch:
Link: https://lore.kernel.org/lkml/20220627211314.dc2hempelyl5ayjg@mobilestation/
-Sergey
>
> > +
> > +else:
> > + properties:
> > + interrupts:
> > + maxItems: 1
> >
> > required:
> > - compatible
> > @@ -60,8 +76,8 @@ oneOf:
> > examples:
> > - |
> > timer@ffe00000 {
> > - compatible = "snps,dw-apb-timer";
> > - interrupts = <0 170 4>;
> > + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
> > + interrupts = <0 170 4>, <0 170 4>;
> > reg = <0xffe00000 0x1000>;
> > clocks = <&timer_clk>, <&timer_pclk>;
> > clock-names = "timer", "pclk";
> > --
> > 2.36.1
> >
> >
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer
@ 2022-06-28 11:06 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-28 11:06 UTC (permalink / raw)
To: Rob Herring
Cc: Conor Dooley, David Airlie, Daniel Vetter, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
Hi Rob,
On Mon, Jun 27, 2022 at 05:30:25PM -0600, Rob Herring wrote:
> On Sat, Jun 18, 2022 at 01:30:27PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > The Canaan k210 apparently has a Sysnopsys Designware timer but
> > according to the documentation & devicetree it has 2 interrupts rather
> > than the standard one. Add a custom compatible that supports the 2
> > interrupt configuration and falls back to the standard binding (which
> > is currently the one in use in the devicetree entry).
> >
> > Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_programming_guide_20190311144158_en.pdf #Page 58
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > .../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++----
> > 1 file changed, 22 insertions(+), 6 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> > index d33c9205a909..9a76acc7a66f 100644
> > --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> > +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
> > @@ -12,6 +12,9 @@ maintainers:
> > properties:
> > compatible:
> > oneOf:
> > + - items:
> > + - const: canaan,k210-apb-timer
> > + - const: snps,dw-apb-timer
> > - const: snps,dw-apb-timer
> > - enum:
> > - snps,dw-apb-timer-sp
> > @@ -21,9 +24,6 @@ properties:
> > reg:
> > maxItems: 1
> >
> > - interrupts:
> > - maxItems: 1
> > -
> > resets:
> > maxItems: 1
> >
> > @@ -41,7 +41,23 @@ properties:
> >
> > clock-frequency: true
> >
> > -additionalProperties: false
> > +unevaluatedProperties: false
> > +
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: canaan,k210-apb-timer
> > +
> > +then:
> > + properties:
> > + interrupts:
> > + maxItems: 2
>
> When more than 1, you need to define what they are and the order.
Please see my note to v2 of this patch:
Link: https://lore.kernel.org/lkml/20220627211314.dc2hempelyl5ayjg@mobilestation/
-Sergey
>
> > +
> > +else:
> > + properties:
> > + interrupts:
> > + maxItems: 1
> >
> > required:
> > - compatible
> > @@ -60,8 +76,8 @@ oneOf:
> > examples:
> > - |
> > timer@ffe00000 {
> > - compatible = "snps,dw-apb-timer";
> > - interrupts = <0 170 4>;
> > + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
> > + interrupts = <0 170 4>, <0 170 4>;
> > reg = <0xffe00000 0x1000>;
> > clocks = <&timer_clk>, <&timer_pclk>;
> > clock-names = "timer", "pclk";
> > --
> > 2.36.1
> >
> >
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread
* [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
this.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index e25d44c218f2..f2b9e3f062cd 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -135,19 +135,41 @@ properties:
of the designware controller, and the upper limit is also subject to
controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
- reg:
- minimum: 0
- maximum: 3
-
- spi-rx-bus-width:
- const: 1
-
- spi-tx-bus-width:
- const: 1
+if:
+ properties:
+ compatible:
+ contains:
+ const: snps,dwc-ssi-1.01a
+
+then:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ spi-rx-bus-width:
+ const: 4
+
+ spi-tx-bus-width:
+ const: 4
+
+else:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ spi-rx-bus-width:
+ const: 1
+
+ spi-tx-bus-width:
+ const: 1
unevaluatedProperties: false
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r, t}x-bus-width for dwc-ssi
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
this.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index e25d44c218f2..f2b9e3f062cd 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -135,19 +135,41 @@ properties:
of the designware controller, and the upper limit is also subject to
controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
- reg:
- minimum: 0
- maximum: 3
-
- spi-rx-bus-width:
- const: 1
-
- spi-tx-bus-width:
- const: 1
+if:
+ properties:
+ compatible:
+ contains:
+ const: snps,dwc-ssi-1.01a
+
+then:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ spi-rx-bus-width:
+ const: 4
+
+ spi-tx-bus-width:
+ const: 4
+
+else:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ spi-rx-bus-width:
+ const: 1
+
+ spi-tx-bus-width:
+ const: 1
unevaluatedProperties: false
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
this.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index e25d44c218f2..f2b9e3f062cd 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -135,19 +135,41 @@ properties:
of the designware controller, and the upper limit is also subject to
controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
- reg:
- minimum: 0
- maximum: 3
-
- spi-rx-bus-width:
- const: 1
-
- spi-tx-bus-width:
- const: 1
+if:
+ properties:
+ compatible:
+ contains:
+ const: snps,dwc-ssi-1.01a
+
+then:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ spi-rx-bus-width:
+ const: 4
+
+ spi-tx-bus-width:
+ const: 4
+
+else:
+ patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 3
+
+ spi-rx-bus-width:
+ const: 1
+
+ spi-tx-bus-width:
+ const: 1
unevaluatedProperties: false
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-18 12:30 ` [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width " Conor Dooley
(?)
(?)
@ 2022-06-20 8:02 ` Geert Uytterhoeven
-1 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-20 8:02 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner, Paul Walmsley,
Albert Ou, Conor Dooley, Masahiro Yamada, Damien Le Moal,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
Hi Conor,
On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley <mail@conchuod.ie> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
> of the designware controller, and the upper limit is also subject to
> controller configuration.
>
> -patternProperties:
> - "^.*@[0-9a-f]+$":
> - type: object
> - properties:
> - reg:
> - minimum: 0
> - maximum: 3
> -
> - spi-rx-bus-width:
> - const: 1
> -
> - spi-tx-bus-width:
> - const: 1
> +if:
> + properties:
> + compatible:
> + contains:
> + const: snps,dwc-ssi-1.01a
> +
> +then:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 4
> +
> + spi-tx-bus-width:
> + const: 4
These two also depend on the board (SPI device + wiring).
So all of [1, 2, 4] are valid values.
> +
> +else:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 1
> +
> + spi-tx-bus-width:
> + const: 1
>
> unevaluatedProperties: false
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 8:02 ` Geert Uytterhoeven
0 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-20 8:02 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, alsa-devel, David Airlie, Palmer Dabbelt,
linux-kernel, Conor Dooley, Thierry Reding, Heng Sia,
Krzysztof Kozlowski, linux-riscv, Sam Ravnborg, Damien Le Moal,
Daniel Lezcano, Jose Abreu, Eugeniy Paltsev, devicetree,
Albert Ou, Mark Brown, dri-devel, Paul Walmsley, Thomas Gleixner,
Dillon Min, Liam Girdwood, Serge Semin, linux-spi, Vinod Koul,
Rob Herring, Palmer Dabbelt, Daniel Vetter, dmaengine,
Masahiro Yamada
Hi Conor,
On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley <mail@conchuod.ie> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
> of the designware controller, and the upper limit is also subject to
> controller configuration.
>
> -patternProperties:
> - "^.*@[0-9a-f]+$":
> - type: object
> - properties:
> - reg:
> - minimum: 0
> - maximum: 3
> -
> - spi-rx-bus-width:
> - const: 1
> -
> - spi-tx-bus-width:
> - const: 1
> +if:
> + properties:
> + compatible:
> + contains:
> + const: snps,dwc-ssi-1.01a
> +
> +then:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 4
> +
> + spi-tx-bus-width:
> + const: 4
These two also depend on the board (SPI device + wiring).
So all of [1, 2, 4] are valid values.
> +
> +else:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 1
> +
> + spi-tx-bus-width:
> + const: 1
>
> unevaluatedProperties: false
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 8:02 ` Geert Uytterhoeven
0 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-20 8:02 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, alsa-devel, David Airlie, Palmer Dabbelt,
linux-kernel, Conor Dooley, Thierry Reding, Heng Sia,
Krzysztof Kozlowski, linux-riscv, Sam Ravnborg, Damien Le Moal,
Daniel Lezcano, Jose Abreu, Eugeniy Paltsev, devicetree,
Albert Ou, Mark Brown, dri-devel, Paul Walmsley, Thomas Gleixner,
Dillon Min, Liam Girdwood, Serge Semin, linux-spi, Vinod Koul,
Rob Herring, Palmer Dabbelt, dmaengine, Masahiro Yamada
Hi Conor,
On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley <mail@conchuod.ie> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
> of the designware controller, and the upper limit is also subject to
> controller configuration.
>
> -patternProperties:
> - "^.*@[0-9a-f]+$":
> - type: object
> - properties:
> - reg:
> - minimum: 0
> - maximum: 3
> -
> - spi-rx-bus-width:
> - const: 1
> -
> - spi-tx-bus-width:
> - const: 1
> +if:
> + properties:
> + compatible:
> + contains:
> + const: snps,dwc-ssi-1.01a
> +
> +then:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 4
> +
> + spi-tx-bus-width:
> + const: 4
These two also depend on the board (SPI device + wiring).
So all of [1, 2, 4] are valid values.
> +
> +else:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 1
> +
> + spi-tx-bus-width:
> + const: 1
>
> unevaluatedProperties: false
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 8:02 ` Geert Uytterhoeven
0 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-20 8:02 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner, Paul Walmsley,
Albert Ou, Conor Dooley, Masahiro Yamada, Damien Le Moal,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
Hi Conor,
On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley <mail@conchuod.ie> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
> of the designware controller, and the upper limit is also subject to
> controller configuration.
>
> -patternProperties:
> - "^.*@[0-9a-f]+$":
> - type: object
> - properties:
> - reg:
> - minimum: 0
> - maximum: 3
> -
> - spi-rx-bus-width:
> - const: 1
> -
> - spi-tx-bus-width:
> - const: 1
> +if:
> + properties:
> + compatible:
> + contains:
> + const: snps,dwc-ssi-1.01a
> +
> +then:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 4
> +
> + spi-tx-bus-width:
> + const: 4
These two also depend on the board (SPI device + wiring).
So all of [1, 2, 4] are valid values.
> +
> +else:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 1
> +
> + spi-tx-bus-width:
> + const: 1
>
> unevaluatedProperties: false
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-20 8:02 ` Geert Uytterhoeven
(?)
(?)
@ 2022-06-20 8:47 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-20 8:47 UTC (permalink / raw)
To: geert
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, fancer.lancer,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
Conor.Dooley, masahiroy, damien.lemoal, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On 20/06/2022 09:02, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley <mail@conchuod.ie> wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>> this.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks for your patch!
>
>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> @@ -135,19 +135,41 @@ properties:
>> of the designware controller, and the upper limit is also subject to
>> controller configuration.
>>
>> -patternProperties:
>> - "^.*@[0-9a-f]+$":
>> - type: object
>> - properties:
>> - reg:
>> - minimum: 0
>> - maximum: 3
>> -
>> - spi-rx-bus-width:
>> - const: 1
>> -
>> - spi-tx-bus-width:
>> - const: 1
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,dwc-ssi-1.01a
>> +
>> +then:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 4
>> +
>> + spi-tx-bus-width:
>> + const: 4
>
> These two also depend on the board (SPI device + wiring).
> So all of [1, 2, 4] are valid values.
Yeah, I wasn't sure about this one as I was writing it.
enum: [1, 2, 4] I guess.
As always, thanks Geert!
Conor.
>
>> +
>> +else:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 1
>> +
>> + spi-tx-bus-width:
>> + const: 1
>>
>> unevaluatedProperties: false
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 8:47 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-20 8:47 UTC (permalink / raw)
To: geert
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
Conor.Dooley, thierry.reding, jee.heng.sia,
krzysztof.kozlowski+dt, linux-riscv, sam, damien.lemoal,
daniel.lezcano, joabreu, Eugeniy.Paltsev, devicetree, aou,
broonie, dri-devel, paul.walmsley, tglx, dillon.minfei,
lgirdwood, fancer.lancer, linux-spi, vkoul, robh+dt, palmer,
daniel, dmaengine, masahiroy
On 20/06/2022 09:02, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley <mail@conchuod.ie> wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>> this.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks for your patch!
>
>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> @@ -135,19 +135,41 @@ properties:
>> of the designware controller, and the upper limit is also subject to
>> controller configuration.
>>
>> -patternProperties:
>> - "^.*@[0-9a-f]+$":
>> - type: object
>> - properties:
>> - reg:
>> - minimum: 0
>> - maximum: 3
>> -
>> - spi-rx-bus-width:
>> - const: 1
>> -
>> - spi-tx-bus-width:
>> - const: 1
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,dwc-ssi-1.01a
>> +
>> +then:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 4
>> +
>> + spi-tx-bus-width:
>> + const: 4
>
> These two also depend on the board (SPI device + wiring).
> So all of [1, 2, 4] are valid values.
Yeah, I wasn't sure about this one as I was writing it.
enum: [1, 2, 4] I guess.
As always, thanks Geert!
Conor.
>
>> +
>> +else:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 1
>> +
>> + spi-tx-bus-width:
>> + const: 1
>>
>> unevaluatedProperties: false
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 8:47 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-20 8:47 UTC (permalink / raw)
To: geert
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
Conor.Dooley, thierry.reding, jee.heng.sia,
krzysztof.kozlowski+dt, linux-riscv, sam, damien.lemoal,
daniel.lezcano, joabreu, Eugeniy.Paltsev, devicetree, aou,
broonie, dri-devel, paul.walmsley, tglx, dillon.minfei,
lgirdwood, fancer.lancer, linux-spi, vkoul, robh+dt, palmer,
dmaengine, masahiroy
On 20/06/2022 09:02, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley <mail@conchuod.ie> wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>> this.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks for your patch!
>
>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> @@ -135,19 +135,41 @@ properties:
>> of the designware controller, and the upper limit is also subject to
>> controller configuration.
>>
>> -patternProperties:
>> - "^.*@[0-9a-f]+$":
>> - type: object
>> - properties:
>> - reg:
>> - minimum: 0
>> - maximum: 3
>> -
>> - spi-rx-bus-width:
>> - const: 1
>> -
>> - spi-tx-bus-width:
>> - const: 1
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,dwc-ssi-1.01a
>> +
>> +then:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 4
>> +
>> + spi-tx-bus-width:
>> + const: 4
>
> These two also depend on the board (SPI device + wiring).
> So all of [1, 2, 4] are valid values.
Yeah, I wasn't sure about this one as I was writing it.
enum: [1, 2, 4] I guess.
As always, thanks Geert!
Conor.
>
>> +
>> +else:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 1
>> +
>> + spi-tx-bus-width:
>> + const: 1
>>
>> unevaluatedProperties: false
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 8:47 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-20 8:47 UTC (permalink / raw)
To: geert
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, fancer.lancer,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
Conor.Dooley, masahiroy, damien.lemoal, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On 20/06/2022 09:02, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley <mail@conchuod.ie> wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>> this.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> Thanks for your patch!
>
>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> @@ -135,19 +135,41 @@ properties:
>> of the designware controller, and the upper limit is also subject to
>> controller configuration.
>>
>> -patternProperties:
>> - "^.*@[0-9a-f]+$":
>> - type: object
>> - properties:
>> - reg:
>> - minimum: 0
>> - maximum: 3
>> -
>> - spi-rx-bus-width:
>> - const: 1
>> -
>> - spi-tx-bus-width:
>> - const: 1
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,dwc-ssi-1.01a
>> +
>> +then:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 4
>> +
>> + spi-tx-bus-width:
>> + const: 4
>
> These two also depend on the board (SPI device + wiring).
> So all of [1, 2, 4] are valid values.
Yeah, I wasn't sure about this one as I was writing it.
enum: [1, 2, 4] I guess.
As always, thanks Geert!
Conor.
>
>> +
>> +else:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 1
>> +
>> + spi-tx-bus-width:
>> + const: 1
>>
>> unevaluatedProperties: false
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-18 12:30 ` [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width " Conor Dooley
(?)
(?)
@ 2022-06-20 20:56 ` Serge Semin
-1 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-20 20:56 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> 1 file changed, 35 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index e25d44c218f2..f2b9e3f062cd 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
> of the designware controller, and the upper limit is also subject to
> controller configuration.
>
> -patternProperties:
> - "^.*@[0-9a-f]+$":
> - type: object
> - properties:
> - reg:
> - minimum: 0
> - maximum: 3
> -
> - spi-rx-bus-width:
> - const: 1
> -
> - spi-tx-bus-width:
> - const: 1
> +if:
> + properties:
> + compatible:
> + contains:
> + const: snps,dwc-ssi-1.01a
> +
> +then:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 4
> +
> + spi-tx-bus-width:
> + const: 4
> +
> +else:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 1
> +
> + spi-tx-bus-width:
> + const: 1
You can just use a more relaxed constraint "enum: [1 2 4 8]" here
irrespective from the compatible string. The modern DW APB SSI
controllers of v.4.* and newer also support the enhanced SPI Modes too
(Dual, Quad and Octal). Since the IP-core version is auto-detected at
run-time there is no way to create a DT-schema correctly constraining
the Rx/Tx SPI bus widths. So let's keep the
compatible-string-independent "patternProperties" here but just extend
the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
properties values.
Note the DW APB SSI/AHB SSI driver currently doesn't support the
enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
activated by means of the corresponding CSR. So most likely the DW AHB
SSI controllers need some specific setups too.
-Sergey
>
> unevaluatedProperties: false
>
> --
> 2.36.1
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 20:56 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-20 20:56 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, alsa-devel, David Airlie, Palmer Dabbelt,
linux-kernel, Conor Dooley, Thierry Reding, Krzysztof Kozlowski,
linux-riscv, Sam Ravnborg, Damien Le Moal, Daniel Lezcano,
Jose Abreu, Geert Uytterhoeven, Eugeniy Paltsev, devicetree,
Albert Ou, Mark Brown, dri-devel, Paul Walmsley, Thomas Gleixner,
Dillon Min, Liam Girdwood, Heng Sia, linux-spi, Vinod Koul,
Rob Herring, Palmer Dabbelt, Daniel Vetter, dmaengine,
Masahiro Yamada
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> 1 file changed, 35 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index e25d44c218f2..f2b9e3f062cd 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
> of the designware controller, and the upper limit is also subject to
> controller configuration.
>
> -patternProperties:
> - "^.*@[0-9a-f]+$":
> - type: object
> - properties:
> - reg:
> - minimum: 0
> - maximum: 3
> -
> - spi-rx-bus-width:
> - const: 1
> -
> - spi-tx-bus-width:
> - const: 1
> +if:
> + properties:
> + compatible:
> + contains:
> + const: snps,dwc-ssi-1.01a
> +
> +then:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 4
> +
> + spi-tx-bus-width:
> + const: 4
> +
> +else:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 1
> +
> + spi-tx-bus-width:
> + const: 1
You can just use a more relaxed constraint "enum: [1 2 4 8]" here
irrespective from the compatible string. The modern DW APB SSI
controllers of v.4.* and newer also support the enhanced SPI Modes too
(Dual, Quad and Octal). Since the IP-core version is auto-detected at
run-time there is no way to create a DT-schema correctly constraining
the Rx/Tx SPI bus widths. So let's keep the
compatible-string-independent "patternProperties" here but just extend
the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
properties values.
Note the DW APB SSI/AHB SSI driver currently doesn't support the
enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
activated by means of the corresponding CSR. So most likely the DW AHB
SSI controllers need some specific setups too.
-Sergey
>
> unevaluatedProperties: false
>
> --
> 2.36.1
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 20:56 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-20 20:56 UTC (permalink / raw)
To: Conor Dooley
Cc: Niklas Cassel, alsa-devel, David Airlie, Palmer Dabbelt,
linux-kernel, Conor Dooley, Thierry Reding, Krzysztof Kozlowski,
linux-riscv, Sam Ravnborg, Damien Le Moal, Daniel Lezcano,
Jose Abreu, Geert Uytterhoeven, Eugeniy Paltsev, devicetree,
Albert Ou, Mark Brown, dri-devel, Paul Walmsley, Thomas Gleixner,
Dillon Min, Liam Girdwood, Heng Sia, linux-spi, Vinod Koul,
Rob Herring, Palmer Dabbelt, dmaengine, Masahiro Yamada
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> 1 file changed, 35 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index e25d44c218f2..f2b9e3f062cd 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
> of the designware controller, and the upper limit is also subject to
> controller configuration.
>
> -patternProperties:
> - "^.*@[0-9a-f]+$":
> - type: object
> - properties:
> - reg:
> - minimum: 0
> - maximum: 3
> -
> - spi-rx-bus-width:
> - const: 1
> -
> - spi-tx-bus-width:
> - const: 1
> +if:
> + properties:
> + compatible:
> + contains:
> + const: snps,dwc-ssi-1.01a
> +
> +then:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 4
> +
> + spi-tx-bus-width:
> + const: 4
> +
> +else:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 1
> +
> + spi-tx-bus-width:
> + const: 1
You can just use a more relaxed constraint "enum: [1 2 4 8]" here
irrespective from the compatible string. The modern DW APB SSI
controllers of v.4.* and newer also support the enhanced SPI Modes too
(Dual, Quad and Octal). Since the IP-core version is auto-detected at
run-time there is no way to create a DT-schema correctly constraining
the Rx/Tx SPI bus widths. So let's keep the
compatible-string-independent "patternProperties" here but just extend
the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
properties values.
Note the DW APB SSI/AHB SSI driver currently doesn't support the
enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
activated by means of the corresponding CSR. So most likely the DW AHB
SSI controllers need some specific setups too.
-Sergey
>
> unevaluatedProperties: false
>
> --
> 2.36.1
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 20:56 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-20 20:56 UTC (permalink / raw)
To: Conor Dooley
Cc: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Daniel Lezcano, Palmer Dabbelt,
Palmer Dabbelt, Thomas Gleixner, Paul Walmsley, Albert Ou,
Conor Dooley, Masahiro Yamada, Damien Le Moal,
Geert Uytterhoeven, Niklas Cassel, Dillon Min, Heng Sia,
Jose Abreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> 1 file changed, 35 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index e25d44c218f2..f2b9e3f062cd 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
> of the designware controller, and the upper limit is also subject to
> controller configuration.
>
> -patternProperties:
> - "^.*@[0-9a-f]+$":
> - type: object
> - properties:
> - reg:
> - minimum: 0
> - maximum: 3
> -
> - spi-rx-bus-width:
> - const: 1
> -
> - spi-tx-bus-width:
> - const: 1
> +if:
> + properties:
> + compatible:
> + contains:
> + const: snps,dwc-ssi-1.01a
> +
> +then:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 4
> +
> + spi-tx-bus-width:
> + const: 4
> +
> +else:
> + patternProperties:
> + "^.*@[0-9a-f]+$":
> + type: object
> + properties:
> + reg:
> + minimum: 0
> + maximum: 3
> +
> + spi-rx-bus-width:
> + const: 1
> +
> + spi-tx-bus-width:
> + const: 1
You can just use a more relaxed constraint "enum: [1 2 4 8]" here
irrespective from the compatible string. The modern DW APB SSI
controllers of v.4.* and newer also support the enhanced SPI Modes too
(Dual, Quad and Octal). Since the IP-core version is auto-detected at
run-time there is no way to create a DT-schema correctly constraining
the Rx/Tx SPI bus widths. So let's keep the
compatible-string-independent "patternProperties" here but just extend
the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
properties values.
Note the DW APB SSI/AHB SSI driver currently doesn't support the
enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
activated by means of the corresponding CSR. So most likely the DW AHB
SSI controllers need some specific setups too.
-Sergey
>
> unevaluatedProperties: false
>
> --
> 2.36.1
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-20 20:56 ` Serge Semin
(?)
(?)
@ 2022-06-20 21:06 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-20 21:06 UTC (permalink / raw)
To: fancer.lancer, mail
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy,
damien.lemoal, geert, niklas.cassel, dillon.minfei, jee.heng.sia,
joabreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On 20/06/2022 21:56, Serge Semin wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>> this.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> index e25d44c218f2..f2b9e3f062cd 100644
>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> @@ -135,19 +135,41 @@ properties:
>> of the designware controller, and the upper limit is also subject to
>> controller configuration.
>>
>> -patternProperties:
>> - "^.*@[0-9a-f]+$":
>> - type: object
>> - properties:
>> - reg:
>> - minimum: 0
>> - maximum: 3
>> -
>> - spi-rx-bus-width:
>> - const: 1
>> -
>> - spi-tx-bus-width:
>> - const: 1
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,dwc-ssi-1.01a
>> +
>> +then:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 4
>> +
>> + spi-tx-bus-width:
>> + const: 4
>> +
>> +else:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 1
>> +
>> + spi-tx-bus-width:
>> + const: 1
>
> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
8 too? sure.
> irrespective from the compatible string. The modern DW APB SSI
> controllers of v.4.* and newer also support the enhanced SPI Modes too
> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> run-time there is no way to create a DT-schema correctly constraining
> the Rx/Tx SPI bus widths. So let's keep the
> compatible-string-independent "patternProperties" here but just extend
> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> properties values.
SGTM!
>
> Note the DW APB SSI/AHB SSI driver currently doesn't support the
> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> activated by means of the corresponding CSR. So most likely the DW AHB
> SSI controllers need some specific setups too.
hmm, well I'll leave that up to people that have Canaan hardware!
Thanks,
Conor.
>
> -Sergey
>
>>
>> unevaluatedProperties: false
>>
>> --
>> 2.36.1
>>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 21:06 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-20 21:06 UTC (permalink / raw)
To: fancer.lancer, mail
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
damien.lemoal, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, daniel, dmaengine, masahiroy
On 20/06/2022 21:56, Serge Semin wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>> this.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> index e25d44c218f2..f2b9e3f062cd 100644
>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> @@ -135,19 +135,41 @@ properties:
>> of the designware controller, and the upper limit is also subject to
>> controller configuration.
>>
>> -patternProperties:
>> - "^.*@[0-9a-f]+$":
>> - type: object
>> - properties:
>> - reg:
>> - minimum: 0
>> - maximum: 3
>> -
>> - spi-rx-bus-width:
>> - const: 1
>> -
>> - spi-tx-bus-width:
>> - const: 1
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,dwc-ssi-1.01a
>> +
>> +then:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 4
>> +
>> + spi-tx-bus-width:
>> + const: 4
>> +
>> +else:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 1
>> +
>> + spi-tx-bus-width:
>> + const: 1
>
> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
8 too? sure.
> irrespective from the compatible string. The modern DW APB SSI
> controllers of v.4.* and newer also support the enhanced SPI Modes too
> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> run-time there is no way to create a DT-schema correctly constraining
> the Rx/Tx SPI bus widths. So let's keep the
> compatible-string-independent "patternProperties" here but just extend
> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> properties values.
SGTM!
>
> Note the DW APB SSI/AHB SSI driver currently doesn't support the
> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> activated by means of the corresponding CSR. So most likely the DW AHB
> SSI controllers need some specific setups too.
hmm, well I'll leave that up to people that have Canaan hardware!
Thanks,
Conor.
>
> -Sergey
>
>>
>> unevaluatedProperties: false
>>
>> --
>> 2.36.1
>>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 21:06 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-20 21:06 UTC (permalink / raw)
To: fancer.lancer, mail
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy,
damien.lemoal, geert, niklas.cassel, dillon.minfei, jee.heng.sia,
joabreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On 20/06/2022 21:56, Serge Semin wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>> this.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> index e25d44c218f2..f2b9e3f062cd 100644
>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> @@ -135,19 +135,41 @@ properties:
>> of the designware controller, and the upper limit is also subject to
>> controller configuration.
>>
>> -patternProperties:
>> - "^.*@[0-9a-f]+$":
>> - type: object
>> - properties:
>> - reg:
>> - minimum: 0
>> - maximum: 3
>> -
>> - spi-rx-bus-width:
>> - const: 1
>> -
>> - spi-tx-bus-width:
>> - const: 1
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,dwc-ssi-1.01a
>> +
>> +then:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 4
>> +
>> + spi-tx-bus-width:
>> + const: 4
>> +
>> +else:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 1
>> +
>> + spi-tx-bus-width:
>> + const: 1
>
> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
8 too? sure.
> irrespective from the compatible string. The modern DW APB SSI
> controllers of v.4.* and newer also support the enhanced SPI Modes too
> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> run-time there is no way to create a DT-schema correctly constraining
> the Rx/Tx SPI bus widths. So let's keep the
> compatible-string-independent "patternProperties" here but just extend
> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> properties values.
SGTM!
>
> Note the DW APB SSI/AHB SSI driver currently doesn't support the
> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> activated by means of the corresponding CSR. So most likely the DW AHB
> SSI controllers need some specific setups too.
hmm, well I'll leave that up to people that have Canaan hardware!
Thanks,
Conor.
>
> -Sergey
>
>>
>> unevaluatedProperties: false
>>
>> --
>> 2.36.1
>>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 21:06 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-20 21:06 UTC (permalink / raw)
To: fancer.lancer, mail
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
damien.lemoal, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, dmaengine, masahiroy
On 20/06/2022 21:56, Serge Semin wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>> this.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> index e25d44c218f2..f2b9e3f062cd 100644
>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>> @@ -135,19 +135,41 @@ properties:
>> of the designware controller, and the upper limit is also subject to
>> controller configuration.
>>
>> -patternProperties:
>> - "^.*@[0-9a-f]+$":
>> - type: object
>> - properties:
>> - reg:
>> - minimum: 0
>> - maximum: 3
>> -
>> - spi-rx-bus-width:
>> - const: 1
>> -
>> - spi-tx-bus-width:
>> - const: 1
>> +if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: snps,dwc-ssi-1.01a
>> +
>> +then:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 4
>> +
>> + spi-tx-bus-width:
>> + const: 4
>> +
>> +else:
>> + patternProperties:
>> + "^.*@[0-9a-f]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 3
>> +
>> + spi-rx-bus-width:
>> + const: 1
>> +
>> + spi-tx-bus-width:
>> + const: 1
>
> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
8 too? sure.
> irrespective from the compatible string. The modern DW APB SSI
> controllers of v.4.* and newer also support the enhanced SPI Modes too
> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> run-time there is no way to create a DT-schema correctly constraining
> the Rx/Tx SPI bus widths. So let's keep the
> compatible-string-independent "patternProperties" here but just extend
> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> properties values.
SGTM!
>
> Note the DW APB SSI/AHB SSI driver currently doesn't support the
> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> activated by means of the corresponding CSR. So most likely the DW AHB
> SSI controllers need some specific setups too.
hmm, well I'll leave that up to people that have Canaan hardware!
Thanks,
Conor.
>
> -Sergey
>
>>
>> unevaluatedProperties: false
>>
>> --
>> 2.36.1
>>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-20 21:06 ` Conor.Dooley
(?)
(?)
@ 2022-06-20 22:46 ` Damien Le Moal
-1 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 22:46 UTC (permalink / raw)
To: Conor.Dooley, fancer.lancer, mail
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy, geert,
niklas.cassel, dillon.minfei, jee.heng.sia, joabreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 21:56, Serge Semin wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>> this.
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> index e25d44c218f2..f2b9e3f062cd 100644
>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> @@ -135,19 +135,41 @@ properties:
>>> of the designware controller, and the upper limit is also subject to
>>> controller configuration.
>>>
>>> -patternProperties:
>>> - "^.*@[0-9a-f]+$":
>>> - type: object
>>> - properties:
>>> - reg:
>>> - minimum: 0
>>> - maximum: 3
>>> -
>>> - spi-rx-bus-width:
>>> - const: 1
>>> -
>>> - spi-tx-bus-width:
>>> - const: 1
>>> +if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: snps,dwc-ssi-1.01a
>>> +
>>> +then:
>>> + patternProperties:
>>> + "^.*@[0-9a-f]+$":
>>> + type: object
>>> + properties:
>>> + reg:
>>> + minimum: 0
>>> + maximum: 3
>>> +
>>> + spi-rx-bus-width:
>>> + const: 4
>>> +
>>> + spi-tx-bus-width:
>>> + const: 4
>>> +
>>> +else:
>>> + patternProperties:
>>> + "^.*@[0-9a-f]+$":
>>> + type: object
>>> + properties:
>>> + reg:
>>> + minimum: 0
>>> + maximum: 3
>>> +
>>> + spi-rx-bus-width:
>>> + const: 1
>>> +
>>> + spi-tx-bus-width:
>>> + const: 1
>>
>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>
> 8 too? sure.
>
>> irrespective from the compatible string. The modern DW APB SSI
>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>> run-time there is no way to create a DT-schema correctly constraining
>> the Rx/Tx SPI bus widths. So let's keep the
>> compatible-string-independent "patternProperties" here but just extend
>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>> properties values.
>
> SGTM!
>
>>
>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>> activated by means of the corresponding CSR. So most likely the DW AHB
>> SSI controllers need some specific setups too.
>
> hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
> Thanks,
> Conor.
>
>>
>> -Sergey
>>
>>>
>>> unevaluatedProperties: false
>>>
>>> --
>>> 2.36.1
>>>
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 22:46 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 22:46 UTC (permalink / raw)
To: Conor.Dooley, fancer.lancer, mail
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
masahiroy, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, daniel, dmaengine
On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 21:56, Serge Semin wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>> this.
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> index e25d44c218f2..f2b9e3f062cd 100644
>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> @@ -135,19 +135,41 @@ properties:
>>> of the designware controller, and the upper limit is also subject to
>>> controller configuration.
>>>
>>> -patternProperties:
>>> - "^.*@[0-9a-f]+$":
>>> - type: object
>>> - properties:
>>> - reg:
>>> - minimum: 0
>>> - maximum: 3
>>> -
>>> - spi-rx-bus-width:
>>> - const: 1
>>> -
>>> - spi-tx-bus-width:
>>> - const: 1
>>> +if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: snps,dwc-ssi-1.01a
>>> +
>>> +then:
>>> + patternProperties:
>>> + "^.*@[0-9a-f]+$":
>>> + type: object
>>> + properties:
>>> + reg:
>>> + minimum: 0
>>> + maximum: 3
>>> +
>>> + spi-rx-bus-width:
>>> + const: 4
>>> +
>>> + spi-tx-bus-width:
>>> + const: 4
>>> +
>>> +else:
>>> + patternProperties:
>>> + "^.*@[0-9a-f]+$":
>>> + type: object
>>> + properties:
>>> + reg:
>>> + minimum: 0
>>> + maximum: 3
>>> +
>>> + spi-rx-bus-width:
>>> + const: 1
>>> +
>>> + spi-tx-bus-width:
>>> + const: 1
>>
>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>
> 8 too? sure.
>
>> irrespective from the compatible string. The modern DW APB SSI
>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>> run-time there is no way to create a DT-schema correctly constraining
>> the Rx/Tx SPI bus widths. So let's keep the
>> compatible-string-independent "patternProperties" here but just extend
>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>> properties values.
>
> SGTM!
>
>>
>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>> activated by means of the corresponding CSR. So most likely the DW AHB
>> SSI controllers need some specific setups too.
>
> hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
> Thanks,
> Conor.
>
>>
>> -Sergey
>>
>>>
>>> unevaluatedProperties: false
>>>
>>> --
>>> 2.36.1
>>>
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 22:46 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 22:46 UTC (permalink / raw)
To: Conor.Dooley, fancer.lancer, mail
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
masahiroy, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, dmaengine
On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 21:56, Serge Semin wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>> this.
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> index e25d44c218f2..f2b9e3f062cd 100644
>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> @@ -135,19 +135,41 @@ properties:
>>> of the designware controller, and the upper limit is also subject to
>>> controller configuration.
>>>
>>> -patternProperties:
>>> - "^.*@[0-9a-f]+$":
>>> - type: object
>>> - properties:
>>> - reg:
>>> - minimum: 0
>>> - maximum: 3
>>> -
>>> - spi-rx-bus-width:
>>> - const: 1
>>> -
>>> - spi-tx-bus-width:
>>> - const: 1
>>> +if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: snps,dwc-ssi-1.01a
>>> +
>>> +then:
>>> + patternProperties:
>>> + "^.*@[0-9a-f]+$":
>>> + type: object
>>> + properties:
>>> + reg:
>>> + minimum: 0
>>> + maximum: 3
>>> +
>>> + spi-rx-bus-width:
>>> + const: 4
>>> +
>>> + spi-tx-bus-width:
>>> + const: 4
>>> +
>>> +else:
>>> + patternProperties:
>>> + "^.*@[0-9a-f]+$":
>>> + type: object
>>> + properties:
>>> + reg:
>>> + minimum: 0
>>> + maximum: 3
>>> +
>>> + spi-rx-bus-width:
>>> + const: 1
>>> +
>>> + spi-tx-bus-width:
>>> + const: 1
>>
>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>
> 8 too? sure.
>
>> irrespective from the compatible string. The modern DW APB SSI
>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>> run-time there is no way to create a DT-schema correctly constraining
>> the Rx/Tx SPI bus widths. So let's keep the
>> compatible-string-independent "patternProperties" here but just extend
>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>> properties values.
>
> SGTM!
>
>>
>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>> activated by means of the corresponding CSR. So most likely the DW AHB
>> SSI controllers need some specific setups too.
>
> hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
> Thanks,
> Conor.
>
>>
>> -Sergey
>>
>>>
>>> unevaluatedProperties: false
>>>
>>> --
>>> 2.36.1
>>>
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 22:46 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 22:46 UTC (permalink / raw)
To: Conor.Dooley, fancer.lancer, mail
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy, geert,
niklas.cassel, dillon.minfei, jee.heng.sia, joabreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 21:56, Serge Semin wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>> this.
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> index e25d44c218f2..f2b9e3f062cd 100644
>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>> @@ -135,19 +135,41 @@ properties:
>>> of the designware controller, and the upper limit is also subject to
>>> controller configuration.
>>>
>>> -patternProperties:
>>> - "^.*@[0-9a-f]+$":
>>> - type: object
>>> - properties:
>>> - reg:
>>> - minimum: 0
>>> - maximum: 3
>>> -
>>> - spi-rx-bus-width:
>>> - const: 1
>>> -
>>> - spi-tx-bus-width:
>>> - const: 1
>>> +if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: snps,dwc-ssi-1.01a
>>> +
>>> +then:
>>> + patternProperties:
>>> + "^.*@[0-9a-f]+$":
>>> + type: object
>>> + properties:
>>> + reg:
>>> + minimum: 0
>>> + maximum: 3
>>> +
>>> + spi-rx-bus-width:
>>> + const: 4
>>> +
>>> + spi-tx-bus-width:
>>> + const: 4
>>> +
>>> +else:
>>> + patternProperties:
>>> + "^.*@[0-9a-f]+$":
>>> + type: object
>>> + properties:
>>> + reg:
>>> + minimum: 0
>>> + maximum: 3
>>> +
>>> + spi-rx-bus-width:
>>> + const: 1
>>> +
>>> + spi-tx-bus-width:
>>> + const: 1
>>
>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>
> 8 too? sure.
>
>> irrespective from the compatible string. The modern DW APB SSI
>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>> run-time there is no way to create a DT-schema correctly constraining
>> the Rx/Tx SPI bus widths. So let's keep the
>> compatible-string-independent "patternProperties" here but just extend
>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>> properties values.
>
> SGTM!
>
>>
>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>> activated by means of the corresponding CSR. So most likely the DW AHB
>> SSI controllers need some specific setups too.
>
> hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
> Thanks,
> Conor.
>
>>
>> -Sergey
>>
>>>
>>> unevaluatedProperties: false
>>>
>>> --
>>> 2.36.1
>>>
>
--
Damien Le Moal
Western Digital Research
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-20 22:46 ` Damien Le Moal
(?)
(?)
@ 2022-06-20 22:49 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-20 22:49 UTC (permalink / raw)
To: Damien Le Moal, Conor.Dooley, fancer.lancer
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy, geert,
niklas.cassel, dillon.minfei, jee.heng.sia, joabreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
On 20/06/2022 23:46, Damien Le Moal wrote:
> On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 21:56, Serge Semin wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>> this.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> @@ -135,19 +135,41 @@ properties:
>>>> of the designware controller, and the upper limit is also subject to
>>>> controller configuration.
>>>>
>>>> -patternProperties:
>>>> - "^.*@[0-9a-f]+$":
>>>> - type: object
>>>> - properties:
>>>> - reg:
>>>> - minimum: 0
>>>> - maximum: 3
>>>> -
>>>> - spi-rx-bus-width:
>>>> - const: 1
>>>> -
>>>> - spi-tx-bus-width:
>>>> - const: 1
>>>> +if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: snps,dwc-ssi-1.01a
>>>> +
>>>> +then:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 4
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 4
>>>> +
>>>> +else:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 1
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 1
>>>
>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>
>> 8 too? sure.
>>
>>> irrespective from the compatible string. The modern DW APB SSI
>>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>>> run-time there is no way to create a DT-schema correctly constraining
>>> the Rx/Tx SPI bus widths. So let's keep the
>>> compatible-string-independent "patternProperties" here but just extend
>>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>>> properties values.
>>
>> SGTM!
>>
>>>
>>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>>> activated by means of the corresponding CSR. So most likely the DW AHB
>>> SSI controllers need some specific setups too.
>>
>> hmm, well I'll leave that up to people that have Canaan hardware!
>
> I will test this series.
>
Cool, thanks.
I'll try to get a respin out tomorrow w/ the memory node "unfixed".
Conor.
>> Thanks,
>> Conor.
>>
>>>
>>> -Sergey
>>>
>>>>
>>>> unevaluatedProperties: false
>>>>
>>>> --
>>>> 2.36.1
>>>>
>>
>
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 22:49 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-20 22:49 UTC (permalink / raw)
To: Damien Le Moal, Conor.Dooley, fancer.lancer
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
masahiroy, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, daniel, dmaengine
On 20/06/2022 23:46, Damien Le Moal wrote:
> On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 21:56, Serge Semin wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>> this.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> @@ -135,19 +135,41 @@ properties:
>>>> of the designware controller, and the upper limit is also subject to
>>>> controller configuration.
>>>>
>>>> -patternProperties:
>>>> - "^.*@[0-9a-f]+$":
>>>> - type: object
>>>> - properties:
>>>> - reg:
>>>> - minimum: 0
>>>> - maximum: 3
>>>> -
>>>> - spi-rx-bus-width:
>>>> - const: 1
>>>> -
>>>> - spi-tx-bus-width:
>>>> - const: 1
>>>> +if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: snps,dwc-ssi-1.01a
>>>> +
>>>> +then:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 4
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 4
>>>> +
>>>> +else:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 1
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 1
>>>
>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>
>> 8 too? sure.
>>
>>> irrespective from the compatible string. The modern DW APB SSI
>>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>>> run-time there is no way to create a DT-schema correctly constraining
>>> the Rx/Tx SPI bus widths. So let's keep the
>>> compatible-string-independent "patternProperties" here but just extend
>>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>>> properties values.
>>
>> SGTM!
>>
>>>
>>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>>> activated by means of the corresponding CSR. So most likely the DW AHB
>>> SSI controllers need some specific setups too.
>>
>> hmm, well I'll leave that up to people that have Canaan hardware!
>
> I will test this series.
>
Cool, thanks.
I'll try to get a respin out tomorrow w/ the memory node "unfixed".
Conor.
>> Thanks,
>> Conor.
>>
>>>
>>> -Sergey
>>>
>>>>
>>>> unevaluatedProperties: false
>>>>
>>>> --
>>>> 2.36.1
>>>>
>>
>
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 22:49 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-20 22:49 UTC (permalink / raw)
To: Damien Le Moal, Conor.Dooley, fancer.lancer
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
masahiroy, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, dmaengine
On 20/06/2022 23:46, Damien Le Moal wrote:
> On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 21:56, Serge Semin wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>> this.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> @@ -135,19 +135,41 @@ properties:
>>>> of the designware controller, and the upper limit is also subject to
>>>> controller configuration.
>>>>
>>>> -patternProperties:
>>>> - "^.*@[0-9a-f]+$":
>>>> - type: object
>>>> - properties:
>>>> - reg:
>>>> - minimum: 0
>>>> - maximum: 3
>>>> -
>>>> - spi-rx-bus-width:
>>>> - const: 1
>>>> -
>>>> - spi-tx-bus-width:
>>>> - const: 1
>>>> +if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: snps,dwc-ssi-1.01a
>>>> +
>>>> +then:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 4
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 4
>>>> +
>>>> +else:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 1
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 1
>>>
>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>
>> 8 too? sure.
>>
>>> irrespective from the compatible string. The modern DW APB SSI
>>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>>> run-time there is no way to create a DT-schema correctly constraining
>>> the Rx/Tx SPI bus widths. So let's keep the
>>> compatible-string-independent "patternProperties" here but just extend
>>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>>> properties values.
>>
>> SGTM!
>>
>>>
>>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>>> activated by means of the corresponding CSR. So most likely the DW AHB
>>> SSI controllers need some specific setups too.
>>
>> hmm, well I'll leave that up to people that have Canaan hardware!
>
> I will test this series.
>
Cool, thanks.
I'll try to get a respin out tomorrow w/ the memory node "unfixed".
Conor.
>> Thanks,
>> Conor.
>>
>>>
>>> -Sergey
>>>
>>>>
>>>> unevaluatedProperties: false
>>>>
>>>> --
>>>> 2.36.1
>>>>
>>
>
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 22:49 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-20 22:49 UTC (permalink / raw)
To: Damien Le Moal, Conor.Dooley, fancer.lancer
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy, geert,
niklas.cassel, dillon.minfei, jee.heng.sia, joabreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
On 20/06/2022 23:46, Damien Le Moal wrote:
> On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 21:56, Serge Semin wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>> this.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> @@ -135,19 +135,41 @@ properties:
>>>> of the designware controller, and the upper limit is also subject to
>>>> controller configuration.
>>>>
>>>> -patternProperties:
>>>> - "^.*@[0-9a-f]+$":
>>>> - type: object
>>>> - properties:
>>>> - reg:
>>>> - minimum: 0
>>>> - maximum: 3
>>>> -
>>>> - spi-rx-bus-width:
>>>> - const: 1
>>>> -
>>>> - spi-tx-bus-width:
>>>> - const: 1
>>>> +if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: snps,dwc-ssi-1.01a
>>>> +
>>>> +then:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 4
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 4
>>>> +
>>>> +else:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 1
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 1
>>>
>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>
>> 8 too? sure.
>>
>>> irrespective from the compatible string. The modern DW APB SSI
>>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>>> run-time there is no way to create a DT-schema correctly constraining
>>> the Rx/Tx SPI bus widths. So let's keep the
>>> compatible-string-independent "patternProperties" here but just extend
>>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>>> properties values.
>>
>> SGTM!
>>
>>>
>>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>>> activated by means of the corresponding CSR. So most likely the DW AHB
>>> SSI controllers need some specific setups too.
>>
>> hmm, well I'll leave that up to people that have Canaan hardware!
>
> I will test this series.
>
Cool, thanks.
I'll try to get a respin out tomorrow w/ the memory node "unfixed".
Conor.
>> Thanks,
>> Conor.
>>
>>>
>>> -Sergey
>>>
>>>>
>>>> unevaluatedProperties: false
>>>>
>>>> --
>>>> 2.36.1
>>>>
>>
>
>
_______________________________________________
linux-riscv mailing list
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^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-20 22:49 ` Conor Dooley
(?)
(?)
@ 2022-06-20 23:17 ` Damien Le Moal
-1 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 23:17 UTC (permalink / raw)
To: Conor Dooley, Conor.Dooley, fancer.lancer
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy, geert,
niklas.cassel, dillon.minfei, jee.heng.sia, joabreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
On 6/21/22 07:49, Conor Dooley wrote:
>
>
> On 20/06/2022 23:46, Damien Le Moal wrote:
>> On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 21:56, Serge Semin wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>>> this.
>>>>>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>> ---
>>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> @@ -135,19 +135,41 @@ properties:
>>>>> of the designware controller, and the upper limit is also subject to
>>>>> controller configuration.
>>>>>
>>>>> -patternProperties:
>>>>> - "^.*@[0-9a-f]+$":
>>>>> - type: object
>>>>> - properties:
>>>>> - reg:
>>>>> - minimum: 0
>>>>> - maximum: 3
>>>>> -
>>>>> - spi-rx-bus-width:
>>>>> - const: 1
>>>>> -
>>>>> - spi-tx-bus-width:
>>>>> - const: 1
>>>>> +if:
>>>>> + properties:
>>>>> + compatible:
>>>>> + contains:
>>>>> + const: snps,dwc-ssi-1.01a
>>>>> +
>>>>> +then:
>>>>> + patternProperties:
>>>>> + "^.*@[0-9a-f]+$":
>>>>> + type: object
>>>>> + properties:
>>>>> + reg:
>>>>> + minimum: 0
>>>>> + maximum: 3
>>>>> +
>>>>> + spi-rx-bus-width:
>>>>> + const: 4
>>>>> +
>>>>> + spi-tx-bus-width:
>>>>> + const: 4
>>>>> +
>>>>> +else:
>>>>> + patternProperties:
>>>>> + "^.*@[0-9a-f]+$":
>>>>> + type: object
>>>>> + properties:
>>>>> + reg:
>>>>> + minimum: 0
>>>>> + maximum: 3
>>>>> +
>>>>> + spi-rx-bus-width:
>>>>> + const: 1
>>>>> +
>>>>> + spi-tx-bus-width:
>>>>> + const: 1
>>>>
>>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>>
>>> 8 too? sure.
>>>
>>>> irrespective from the compatible string. The modern DW APB SSI
>>>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>>>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>>>> run-time there is no way to create a DT-schema correctly constraining
>>>> the Rx/Tx SPI bus widths. So let's keep the
>>>> compatible-string-independent "patternProperties" here but just extend
>>>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>>>> properties values.
>>>
>>> SGTM!
>>>
>>>>
>>>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>>>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>>>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>>>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>>>> activated by means of the corresponding CSR. So most likely the DW AHB
>>>> SSI controllers need some specific setups too.
>>>
>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>
>> I will test this series.
>>
>
> Cool, thanks.
> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
OK. I will test that then :)
> Conor.
>
>>> Thanks,
>>> Conor.
>>>
>>>>
>>>> -Sergey
>>>>
>>>>>
>>>>> unevaluatedProperties: false
>>>>>
>>>>> --
>>>>> 2.36.1
>>>>>
>>>
>>
>>
--
Damien Le Moal
Western Digital Research
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^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 23:17 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 23:17 UTC (permalink / raw)
To: Conor Dooley, Conor.Dooley, fancer.lancer
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
masahiroy, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, daniel, dmaengine
On 6/21/22 07:49, Conor Dooley wrote:
>
>
> On 20/06/2022 23:46, Damien Le Moal wrote:
>> On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 21:56, Serge Semin wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>>> this.
>>>>>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>> ---
>>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> @@ -135,19 +135,41 @@ properties:
>>>>> of the designware controller, and the upper limit is also subject to
>>>>> controller configuration.
>>>>>
>>>>> -patternProperties:
>>>>> - "^.*@[0-9a-f]+$":
>>>>> - type: object
>>>>> - properties:
>>>>> - reg:
>>>>> - minimum: 0
>>>>> - maximum: 3
>>>>> -
>>>>> - spi-rx-bus-width:
>>>>> - const: 1
>>>>> -
>>>>> - spi-tx-bus-width:
>>>>> - const: 1
>>>>> +if:
>>>>> + properties:
>>>>> + compatible:
>>>>> + contains:
>>>>> + const: snps,dwc-ssi-1.01a
>>>>> +
>>>>> +then:
>>>>> + patternProperties:
>>>>> + "^.*@[0-9a-f]+$":
>>>>> + type: object
>>>>> + properties:
>>>>> + reg:
>>>>> + minimum: 0
>>>>> + maximum: 3
>>>>> +
>>>>> + spi-rx-bus-width:
>>>>> + const: 4
>>>>> +
>>>>> + spi-tx-bus-width:
>>>>> + const: 4
>>>>> +
>>>>> +else:
>>>>> + patternProperties:
>>>>> + "^.*@[0-9a-f]+$":
>>>>> + type: object
>>>>> + properties:
>>>>> + reg:
>>>>> + minimum: 0
>>>>> + maximum: 3
>>>>> +
>>>>> + spi-rx-bus-width:
>>>>> + const: 1
>>>>> +
>>>>> + spi-tx-bus-width:
>>>>> + const: 1
>>>>
>>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>>
>>> 8 too? sure.
>>>
>>>> irrespective from the compatible string. The modern DW APB SSI
>>>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>>>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>>>> run-time there is no way to create a DT-schema correctly constraining
>>>> the Rx/Tx SPI bus widths. So let's keep the
>>>> compatible-string-independent "patternProperties" here but just extend
>>>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>>>> properties values.
>>>
>>> SGTM!
>>>
>>>>
>>>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>>>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>>>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>>>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>>>> activated by means of the corresponding CSR. So most likely the DW AHB
>>>> SSI controllers need some specific setups too.
>>>
>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>
>> I will test this series.
>>
>
> Cool, thanks.
> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
OK. I will test that then :)
> Conor.
>
>>> Thanks,
>>> Conor.
>>>
>>>>
>>>> -Sergey
>>>>
>>>>>
>>>>> unevaluatedProperties: false
>>>>>
>>>>> --
>>>>> 2.36.1
>>>>>
>>>
>>
>>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 23:17 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 23:17 UTC (permalink / raw)
To: Conor Dooley, Conor.Dooley, fancer.lancer
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
masahiroy, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, dmaengine
On 6/21/22 07:49, Conor Dooley wrote:
>
>
> On 20/06/2022 23:46, Damien Le Moal wrote:
>> On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 21:56, Serge Semin wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>>> this.
>>>>>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>> ---
>>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> @@ -135,19 +135,41 @@ properties:
>>>>> of the designware controller, and the upper limit is also subject to
>>>>> controller configuration.
>>>>>
>>>>> -patternProperties:
>>>>> - "^.*@[0-9a-f]+$":
>>>>> - type: object
>>>>> - properties:
>>>>> - reg:
>>>>> - minimum: 0
>>>>> - maximum: 3
>>>>> -
>>>>> - spi-rx-bus-width:
>>>>> - const: 1
>>>>> -
>>>>> - spi-tx-bus-width:
>>>>> - const: 1
>>>>> +if:
>>>>> + properties:
>>>>> + compatible:
>>>>> + contains:
>>>>> + const: snps,dwc-ssi-1.01a
>>>>> +
>>>>> +then:
>>>>> + patternProperties:
>>>>> + "^.*@[0-9a-f]+$":
>>>>> + type: object
>>>>> + properties:
>>>>> + reg:
>>>>> + minimum: 0
>>>>> + maximum: 3
>>>>> +
>>>>> + spi-rx-bus-width:
>>>>> + const: 4
>>>>> +
>>>>> + spi-tx-bus-width:
>>>>> + const: 4
>>>>> +
>>>>> +else:
>>>>> + patternProperties:
>>>>> + "^.*@[0-9a-f]+$":
>>>>> + type: object
>>>>> + properties:
>>>>> + reg:
>>>>> + minimum: 0
>>>>> + maximum: 3
>>>>> +
>>>>> + spi-rx-bus-width:
>>>>> + const: 1
>>>>> +
>>>>> + spi-tx-bus-width:
>>>>> + const: 1
>>>>
>>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>>
>>> 8 too? sure.
>>>
>>>> irrespective from the compatible string. The modern DW APB SSI
>>>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>>>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>>>> run-time there is no way to create a DT-schema correctly constraining
>>>> the Rx/Tx SPI bus widths. So let's keep the
>>>> compatible-string-independent "patternProperties" here but just extend
>>>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>>>> properties values.
>>>
>>> SGTM!
>>>
>>>>
>>>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>>>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>>>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>>>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>>>> activated by means of the corresponding CSR. So most likely the DW AHB
>>>> SSI controllers need some specific setups too.
>>>
>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>
>> I will test this series.
>>
>
> Cool, thanks.
> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
OK. I will test that then :)
> Conor.
>
>>> Thanks,
>>> Conor.
>>>
>>>>
>>>> -Sergey
>>>>
>>>>>
>>>>> unevaluatedProperties: false
>>>>>
>>>>> --
>>>>> 2.36.1
>>>>>
>>>
>>
>>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-20 23:17 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 23:17 UTC (permalink / raw)
To: Conor Dooley, Conor.Dooley, fancer.lancer
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy, geert,
niklas.cassel, dillon.minfei, jee.heng.sia, joabreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
On 6/21/22 07:49, Conor Dooley wrote:
>
>
> On 20/06/2022 23:46, Damien Le Moal wrote:
>> On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 21:56, Serge Semin wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>>> this.
>>>>>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>> ---
>>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>>> @@ -135,19 +135,41 @@ properties:
>>>>> of the designware controller, and the upper limit is also subject to
>>>>> controller configuration.
>>>>>
>>>>> -patternProperties:
>>>>> - "^.*@[0-9a-f]+$":
>>>>> - type: object
>>>>> - properties:
>>>>> - reg:
>>>>> - minimum: 0
>>>>> - maximum: 3
>>>>> -
>>>>> - spi-rx-bus-width:
>>>>> - const: 1
>>>>> -
>>>>> - spi-tx-bus-width:
>>>>> - const: 1
>>>>> +if:
>>>>> + properties:
>>>>> + compatible:
>>>>> + contains:
>>>>> + const: snps,dwc-ssi-1.01a
>>>>> +
>>>>> +then:
>>>>> + patternProperties:
>>>>> + "^.*@[0-9a-f]+$":
>>>>> + type: object
>>>>> + properties:
>>>>> + reg:
>>>>> + minimum: 0
>>>>> + maximum: 3
>>>>> +
>>>>> + spi-rx-bus-width:
>>>>> + const: 4
>>>>> +
>>>>> + spi-tx-bus-width:
>>>>> + const: 4
>>>>> +
>>>>> +else:
>>>>> + patternProperties:
>>>>> + "^.*@[0-9a-f]+$":
>>>>> + type: object
>>>>> + properties:
>>>>> + reg:
>>>>> + minimum: 0
>>>>> + maximum: 3
>>>>> +
>>>>> + spi-rx-bus-width:
>>>>> + const: 1
>>>>> +
>>>>> + spi-tx-bus-width:
>>>>> + const: 1
>>>>
>>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>>
>>> 8 too? sure.
>>>
>>>> irrespective from the compatible string. The modern DW APB SSI
>>>> controllers of v.4.* and newer also support the enhanced SPI Modes too
>>>> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
>>>> run-time there is no way to create a DT-schema correctly constraining
>>>> the Rx/Tx SPI bus widths. So let's keep the
>>>> compatible-string-independent "patternProperties" here but just extend
>>>> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
>>>> properties values.
>>>
>>> SGTM!
>>>
>>>>
>>>> Note the DW APB SSI/AHB SSI driver currently doesn't support the
>>>> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
>>>> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
>>>> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
>>>> activated by means of the corresponding CSR. So most likely the DW AHB
>>>> SSI controllers need some specific setups too.
>>>
>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>
>> I will test this series.
>>
>
> Cool, thanks.
> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
OK. I will test that then :)
> Conor.
>
>>> Thanks,
>>> Conor.
>>>
>>>>
>>>> -Sergey
>>>>
>>>>>
>>>>> unevaluatedProperties: false
>>>>>
>>>>> --
>>>>> 2.36.1
>>>>>
>>>
>>
>>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-20 23:17 ` Damien Le Moal
(?)
(?)
@ 2022-06-21 16:06 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-21 16:06 UTC (permalink / raw)
To: damien.lemoal, mail, fancer.lancer
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy, geert,
niklas.cassel, dillon.minfei, jee.heng.sia, joabreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
On 21/06/2022 00:17, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/21/22 07:49, Conor Dooley wrote:
>>
---8<---
>>>>
>>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>>
>>> I will test this series.
>>>
>>
>> Cool, thanks.
>> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
>
> OK. I will test that then :)
Since the memory node hit that dt-schema snag, I have not sent a v2.
Going to be AFK for a few days, so I dropped the memory node change,
changed the spi binding & put the series on:
git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
If you get a chance to look at it great, if not I'll send a v2 once
the memory node is figured out.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-21 16:06 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-21 16:06 UTC (permalink / raw)
To: damien.lemoal, mail, fancer.lancer
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
masahiroy, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, daniel, dmaengine
On 21/06/2022 00:17, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/21/22 07:49, Conor Dooley wrote:
>>
---8<---
>>>>
>>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>>
>>> I will test this series.
>>>
>>
>> Cool, thanks.
>> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
>
> OK. I will test that then :)
Since the memory node hit that dt-schema snag, I have not sent a v2.
Going to be AFK for a few days, so I dropped the memory node change,
changed the spi binding & put the series on:
git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
If you get a chance to look at it great, if not I'll send a v2 once
the memory node is figured out.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-21 16:06 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-21 16:06 UTC (permalink / raw)
To: damien.lemoal, mail, fancer.lancer
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
masahiroy, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, broonie, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
robh+dt, palmer, dmaengine
On 21/06/2022 00:17, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/21/22 07:49, Conor Dooley wrote:
>>
---8<---
>>>>
>>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>>
>>> I will test this series.
>>>
>>
>> Cool, thanks.
>> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
>
> OK. I will test that then :)
Since the memory node hit that dt-schema snag, I have not sent a v2.
Going to be AFK for a few days, so I dropped the memory node change,
changed the spi binding & put the series on:
git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
If you get a chance to look at it great, if not I'll send a v2 once
the memory node is figured out.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-21 16:06 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-21 16:06 UTC (permalink / raw)
To: damien.lemoal, mail, fancer.lancer
Cc: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, daniel.lezcano,
palmer, palmer, tglx, paul.walmsley, aou, masahiroy, geert,
niklas.cassel, dillon.minfei, jee.heng.sia, joabreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
On 21/06/2022 00:17, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/21/22 07:49, Conor Dooley wrote:
>>
---8<---
>>>>
>>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>>
>>> I will test this series.
>>>
>>
>> Cool, thanks.
>> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
>
> OK. I will test that then :)
Since the memory node hit that dt-schema snag, I have not sent a v2.
Going to be AFK for a few days, so I dropped the memory node change,
changed the spi binding & put the series on:
git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
If you get a chance to look at it great, if not I'll send a v2 once
the memory node is figured out.
Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-21 16:06 ` Conor.Dooley
(?)
(?)
@ 2022-06-23 10:25 ` Serge Semin
-1 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-23 10:25 UTC (permalink / raw)
To: Conor.Dooley
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
damien.lemoal, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, robh+dt, dri-devel, paul.walmsley, mail, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
broonie, palmer, dmaengine, masahiroy
On Tue, Jun 21, 2022 at 04:06:21PM +0000, Conor.Dooley@microchip.com wrote:
> On 21/06/2022 00:17, Damien Le Moal wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 6/21/22 07:49, Conor Dooley wrote:
> >>
> ---8<---
> >>>>
> >>>> hmm, well I'll leave that up to people that have Canaan hardware!
> >>>
> >>> I will test this series.
> >>>
> >>
> >> Cool, thanks.
> >> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
> >
> > OK. I will test that then :)
>
> Since the memory node hit that dt-schema snag, I have not sent a v2.
> Going to be AFK for a few days, so I dropped the memory node change,
> changed the spi binding & put the series on:
> git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
>
> If you get a chance to look at it great, if not I'll send a v2 once
> the memory node is figured out.
commit 84df6ca0f277 ("spi: dt-bindings: dw-apb-ssi: update
spi-{r,t}x-bus-width") looks good to me. Feel free to add my ack tag
to v2 of that patch.
-Sergey
>
> Thanks,
> Conor.
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-23 10:25 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-23 10:25 UTC (permalink / raw)
To: Conor.Dooley
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
damien.lemoal, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, robh+dt, dri-devel, paul.walmsley, mail, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
broonie, palmer, daniel, dmaengine, masahiroy
On Tue, Jun 21, 2022 at 04:06:21PM +0000, Conor.Dooley@microchip.com wrote:
> On 21/06/2022 00:17, Damien Le Moal wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 6/21/22 07:49, Conor Dooley wrote:
> >>
> ---8<---
> >>>>
> >>>> hmm, well I'll leave that up to people that have Canaan hardware!
> >>>
> >>> I will test this series.
> >>>
> >>
> >> Cool, thanks.
> >> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
> >
> > OK. I will test that then :)
>
> Since the memory node hit that dt-schema snag, I have not sent a v2.
> Going to be AFK for a few days, so I dropped the memory node change,
> changed the spi binding & put the series on:
> git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
>
> If you get a chance to look at it great, if not I'll send a v2 once
> the memory node is figured out.
commit 84df6ca0f277 ("spi: dt-bindings: dw-apb-ssi: update
spi-{r,t}x-bus-width") looks good to me. Feel free to add my ack tag
to v2 of that patch.
-Sergey
>
> Thanks,
> Conor.
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-23 10:25 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-23 10:25 UTC (permalink / raw)
To: Conor.Dooley
Cc: damien.lemoal, mail, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, thierry.reding, sam, Eugeniy.Paltsev,
vkoul, lgirdwood, broonie, daniel.lezcano, palmer, palmer, tglx,
paul.walmsley, aou, masahiroy, geert, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On Tue, Jun 21, 2022 at 04:06:21PM +0000, Conor.Dooley@microchip.com wrote:
> On 21/06/2022 00:17, Damien Le Moal wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 6/21/22 07:49, Conor Dooley wrote:
> >>
> ---8<---
> >>>>
> >>>> hmm, well I'll leave that up to people that have Canaan hardware!
> >>>
> >>> I will test this series.
> >>>
> >>
> >> Cool, thanks.
> >> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
> >
> > OK. I will test that then :)
>
> Since the memory node hit that dt-schema snag, I have not sent a v2.
> Going to be AFK for a few days, so I dropped the memory node change,
> changed the spi binding & put the series on:
> git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
>
> If you get a chance to look at it great, if not I'll send a v2 once
> the memory node is figured out.
commit 84df6ca0f277 ("spi: dt-bindings: dw-apb-ssi: update
spi-{r,t}x-bus-width") looks good to me. Feel free to add my ack tag
to v2 of that patch.
-Sergey
>
> Thanks,
> Conor.
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-23 10:25 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-23 10:25 UTC (permalink / raw)
To: Conor.Dooley
Cc: damien.lemoal, mail, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, thierry.reding, sam, Eugeniy.Paltsev,
vkoul, lgirdwood, broonie, daniel.lezcano, palmer, palmer, tglx,
paul.walmsley, aou, masahiroy, geert, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On Tue, Jun 21, 2022 at 04:06:21PM +0000, Conor.Dooley@microchip.com wrote:
> On 21/06/2022 00:17, Damien Le Moal wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On 6/21/22 07:49, Conor Dooley wrote:
> >>
> ---8<---
> >>>>
> >>>> hmm, well I'll leave that up to people that have Canaan hardware!
> >>>
> >>> I will test this series.
> >>>
> >>
> >> Cool, thanks.
> >> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
> >
> > OK. I will test that then :)
>
> Since the memory node hit that dt-schema snag, I have not sent a v2.
> Going to be AFK for a few days, so I dropped the memory node change,
> changed the spi binding & put the series on:
> git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
>
> If you get a chance to look at it great, if not I'll send a v2 once
> the memory node is figured out.
commit 84df6ca0f277 ("spi: dt-bindings: dw-apb-ssi: update
spi-{r,t}x-bus-width") looks good to me. Feel free to add my ack tag
to v2 of that patch.
-Sergey
>
> Thanks,
> Conor.
>
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-23 10:25 ` Serge Semin
(?)
@ 2022-06-23 12:41 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-23 12:41 UTC (permalink / raw)
To: Serge Semin, Conor.Dooley
Cc: damien.lemoal, airlied, daniel, robh+dt, krzysztof.kozlowski+dt,
thierry.reding, sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, geert, niklas.cassel, dillon.minfei, jee.heng.sia,
joabreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On 23/06/2022 11:25, Serge Semin wrote:
> On Tue, Jun 21, 2022 at 04:06:21PM +0000, Conor.Dooley@microchip.com wrote:
>> On 21/06/2022 00:17, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/21/22 07:49, Conor Dooley wrote:
>>>>
>> ---8<---
>>>>>>
>>>>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>>>>
>>>>> I will test this series.
>>>>>
>>>>
>>>> Cool, thanks.
>>>> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
>>>
>>> OK. I will test that then :)
>>
>> Since the memory node hit that dt-schema snag, I have not sent a v2.
>> Going to be AFK for a few days, so I dropped the memory node change,
>> changed the spi binding & put the series on:
>> git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
>>
>
>> If you get a chance to look at it great, if not I'll send a v2 once
>> the memory node is figured out.
>
> commit 84df6ca0f277 ("spi: dt-bindings: dw-apb-ssi: update
> spi-{r,t}x-bus-width") looks good to me. Feel free to add my ack tag
> to v2 of that patch.
Sure, thanks!
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-23 12:41 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-23 12:41 UTC (permalink / raw)
To: Serge Semin, Conor.Dooley
Cc: damien.lemoal, airlied, daniel, robh+dt, krzysztof.kozlowski+dt,
thierry.reding, sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, geert, niklas.cassel, dillon.minfei, jee.heng.sia,
joabreu, dri-devel, devicetree, linux-kernel, dmaengine,
alsa-devel, linux-spi, linux-riscv
On 23/06/2022 11:25, Serge Semin wrote:
> On Tue, Jun 21, 2022 at 04:06:21PM +0000, Conor.Dooley@microchip.com wrote:
>> On 21/06/2022 00:17, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/21/22 07:49, Conor Dooley wrote:
>>>>
>> ---8<---
>>>>>>
>>>>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>>>>
>>>>> I will test this series.
>>>>>
>>>>
>>>> Cool, thanks.
>>>> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
>>>
>>> OK. I will test that then :)
>>
>> Since the memory node hit that dt-schema snag, I have not sent a v2.
>> Going to be AFK for a few days, so I dropped the memory node change,
>> changed the spi binding & put the series on:
>> git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
>>
>
>> If you get a chance to look at it great, if not I'll send a v2 once
>> the memory node is figured out.
>
> commit 84df6ca0f277 ("spi: dt-bindings: dw-apb-ssi: update
> spi-{r,t}x-bus-width") looks good to me. Feel free to add my ack tag
> to v2 of that patch.
Sure, thanks!
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-23 12:41 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-23 12:41 UTC (permalink / raw)
To: Serge Semin, Conor.Dooley
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, krzysztof.kozlowski+dt, linux-riscv, sam,
damien.lemoal, daniel.lezcano, joabreu, geert, Eugeniy.Paltsev,
devicetree, aou, robh+dt, dri-devel, paul.walmsley, tglx,
dillon.minfei, lgirdwood, jee.heng.sia, linux-spi, vkoul,
broonie, palmer, dmaengine, masahiroy
On 23/06/2022 11:25, Serge Semin wrote:
> On Tue, Jun 21, 2022 at 04:06:21PM +0000, Conor.Dooley@microchip.com wrote:
>> On 21/06/2022 00:17, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/21/22 07:49, Conor Dooley wrote:
>>>>
>> ---8<---
>>>>>>
>>>>>> hmm, well I'll leave that up to people that have Canaan hardware!
>>>>>
>>>>> I will test this series.
>>>>>
>>>>
>>>> Cool, thanks.
>>>> I'll try to get a respin out tomorrow w/ the memory node "unfixed".
>>>
>>> OK. I will test that then :)
>>
>> Since the memory node hit that dt-schema snag, I have not sent a v2.
>> Going to be AFK for a few days, so I dropped the memory node change,
>> changed the spi binding & put the series on:
>> git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
>>
>
>> If you get a chance to look at it great, if not I'll send a v2 once
>> the memory node is figured out.
>
> commit 84df6ca0f277 ("spi: dt-bindings: dw-apb-ssi: update
> spi-{r,t}x-bus-width") looks good to me. Feel free to add my ack tag
> to v2 of that patch.
Sure, thanks!
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-20 21:06 ` Conor.Dooley
(?)
@ 2022-06-27 17:15 ` Rob Herring
-1 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 17:15 UTC (permalink / raw)
To: Conor.Dooley
Cc: fancer.lancer, mail, airlied, daniel, krzysztof.kozlowski+dt,
thierry.reding, sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, damien.lemoal, geert, niklas.cassel, dillon.minfei,
jee.heng.sia, joabreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On Mon, Jun 20, 2022 at 09:06:34PM +0000, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 21:56, Serge Semin wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> >> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> >> this.
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> >> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> >> 1 file changed, 35 insertions(+), 13 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> >> index e25d44c218f2..f2b9e3f062cd 100644
> >> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> >> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> >> @@ -135,19 +135,41 @@ properties:
> >> of the designware controller, and the upper limit is also subject to
> >> controller configuration.
> >>
> >> -patternProperties:
> >> - "^.*@[0-9a-f]+$":
> >> - type: object
> >> - properties:
> >> - reg:
> >> - minimum: 0
> >> - maximum: 3
> >> -
> >> - spi-rx-bus-width:
> >> - const: 1
> >> -
> >> - spi-tx-bus-width:
> >> - const: 1
> >> +if:
> >> + properties:
> >> + compatible:
> >> + contains:
> >> + const: snps,dwc-ssi-1.01a
> >> +
> >> +then:
> >> + patternProperties:
> >> + "^.*@[0-9a-f]+$":
> >> + type: object
> >> + properties:
> >> + reg:
> >> + minimum: 0
> >> + maximum: 3
> >> +
> >> + spi-rx-bus-width:
> >> + const: 4
> >> +
> >> + spi-tx-bus-width:
> >> + const: 4
> >> +
> >> +else:
> >> + patternProperties:
> >> + "^.*@[0-9a-f]+$":
> >> + type: object
> >> + properties:
> >> + reg:
> >> + minimum: 0
> >> + maximum: 3
> >> +
> >> + spi-rx-bus-width:
> >> + const: 1
> >> +
> >> + spi-tx-bus-width:
> >> + const: 1
> >
> > You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>
> 8 too? sure.
Then no constraints needed because the common definition already has
this presumably.
Rob
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-27 17:15 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 17:15 UTC (permalink / raw)
To: Conor.Dooley
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, jee.heng.sia, krzysztof.kozlowski+dt,
linux-riscv, sam, damien.lemoal, daniel.lezcano, joabreu, geert,
Eugeniy.Paltsev, devicetree, aou, broonie, dri-devel,
paul.walmsley, mail, tglx, dillon.minfei, lgirdwood,
fancer.lancer, linux-spi, vkoul, palmer, dmaengine, masahiroy
On Mon, Jun 20, 2022 at 09:06:34PM +0000, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 21:56, Serge Semin wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> >> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> >> this.
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> >> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> >> 1 file changed, 35 insertions(+), 13 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> >> index e25d44c218f2..f2b9e3f062cd 100644
> >> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> >> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> >> @@ -135,19 +135,41 @@ properties:
> >> of the designware controller, and the upper limit is also subject to
> >> controller configuration.
> >>
> >> -patternProperties:
> >> - "^.*@[0-9a-f]+$":
> >> - type: object
> >> - properties:
> >> - reg:
> >> - minimum: 0
> >> - maximum: 3
> >> -
> >> - spi-rx-bus-width:
> >> - const: 1
> >> -
> >> - spi-tx-bus-width:
> >> - const: 1
> >> +if:
> >> + properties:
> >> + compatible:
> >> + contains:
> >> + const: snps,dwc-ssi-1.01a
> >> +
> >> +then:
> >> + patternProperties:
> >> + "^.*@[0-9a-f]+$":
> >> + type: object
> >> + properties:
> >> + reg:
> >> + minimum: 0
> >> + maximum: 3
> >> +
> >> + spi-rx-bus-width:
> >> + const: 4
> >> +
> >> + spi-tx-bus-width:
> >> + const: 4
> >> +
> >> +else:
> >> + patternProperties:
> >> + "^.*@[0-9a-f]+$":
> >> + type: object
> >> + properties:
> >> + reg:
> >> + minimum: 0
> >> + maximum: 3
> >> +
> >> + spi-rx-bus-width:
> >> + const: 1
> >> +
> >> + spi-tx-bus-width:
> >> + const: 1
> >
> > You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>
> 8 too? sure.
Then no constraints needed because the common definition already has
this presumably.
Rob
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-27 17:15 ` Rob Herring
0 siblings, 0 replies; 159+ messages in thread
From: Rob Herring @ 2022-06-27 17:15 UTC (permalink / raw)
To: Conor.Dooley
Cc: fancer.lancer, mail, airlied, daniel, krzysztof.kozlowski+dt,
thierry.reding, sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, damien.lemoal, geert, niklas.cassel, dillon.minfei,
jee.heng.sia, joabreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On Mon, Jun 20, 2022 at 09:06:34PM +0000, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 21:56, Serge Semin wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> >> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> >> this.
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> >> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> >> 1 file changed, 35 insertions(+), 13 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> >> index e25d44c218f2..f2b9e3f062cd 100644
> >> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> >> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> >> @@ -135,19 +135,41 @@ properties:
> >> of the designware controller, and the upper limit is also subject to
> >> controller configuration.
> >>
> >> -patternProperties:
> >> - "^.*@[0-9a-f]+$":
> >> - type: object
> >> - properties:
> >> - reg:
> >> - minimum: 0
> >> - maximum: 3
> >> -
> >> - spi-rx-bus-width:
> >> - const: 1
> >> -
> >> - spi-tx-bus-width:
> >> - const: 1
> >> +if:
> >> + properties:
> >> + compatible:
> >> + contains:
> >> + const: snps,dwc-ssi-1.01a
> >> +
> >> +then:
> >> + patternProperties:
> >> + "^.*@[0-9a-f]+$":
> >> + type: object
> >> + properties:
> >> + reg:
> >> + minimum: 0
> >> + maximum: 3
> >> +
> >> + spi-rx-bus-width:
> >> + const: 4
> >> +
> >> + spi-tx-bus-width:
> >> + const: 4
> >> +
> >> +else:
> >> + patternProperties:
> >> + "^.*@[0-9a-f]+$":
> >> + type: object
> >> + properties:
> >> + reg:
> >> + minimum: 0
> >> + maximum: 3
> >> +
> >> + spi-rx-bus-width:
> >> + const: 1
> >> +
> >> + spi-tx-bus-width:
> >> + const: 1
> >
> > You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>
> 8 too? sure.
Then no constraints needed because the common definition already has
this presumably.
Rob
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-27 17:15 ` Rob Herring
(?)
@ 2022-06-27 18:05 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-27 18:05 UTC (permalink / raw)
To: robh
Cc: mail, airlied, daniel, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, fancer.lancer, vkoul, lgirdwood, broonie,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, damien.lemoal, geert, niklas.cassel, dillon.minfei,
jee.heng.sia, joabreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On 27/06/2022 18:15, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, Jun 20, 2022 at 09:06:34PM +0000, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 21:56, Serge Semin wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>> this.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> @@ -135,19 +135,41 @@ properties:
>>>> of the designware controller, and the upper limit is also subject to
>>>> controller configuration.
>>>>
>>>> -patternProperties:
>>>> - "^.*@[0-9a-f]+$":
>>>> - type: object
>>>> - properties:
>>>> - reg:
>>>> - minimum: 0
>>>> - maximum: 3
>>>> -
>>>> - spi-rx-bus-width:
>>>> - const: 1
>>>> -
>>>> - spi-tx-bus-width:
>>>> - const: 1
>>>> +if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: snps,dwc-ssi-1.01a
>>>> +
>>>> +then:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 4
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 4
>>>> +
>>>> +else:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 1
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 1
>>>
>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>
>> 8 too? sure.
>
> Then no constraints needed because the common definition already has
> this presumably.
Almost, the default has 0 in the enum too.
I'll go with that - thanks!
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-27 18:05 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-27 18:05 UTC (permalink / raw)
To: robh
Cc: mail, airlied, daniel, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, fancer.lancer, vkoul, lgirdwood, broonie,
daniel.lezcano, palmer, palmer, tglx, paul.walmsley, aou,
masahiroy, damien.lemoal, geert, niklas.cassel, dillon.minfei,
jee.heng.sia, joabreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On 27/06/2022 18:15, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, Jun 20, 2022 at 09:06:34PM +0000, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 21:56, Serge Semin wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>> this.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> @@ -135,19 +135,41 @@ properties:
>>>> of the designware controller, and the upper limit is also subject to
>>>> controller configuration.
>>>>
>>>> -patternProperties:
>>>> - "^.*@[0-9a-f]+$":
>>>> - type: object
>>>> - properties:
>>>> - reg:
>>>> - minimum: 0
>>>> - maximum: 3
>>>> -
>>>> - spi-rx-bus-width:
>>>> - const: 1
>>>> -
>>>> - spi-tx-bus-width:
>>>> - const: 1
>>>> +if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: snps,dwc-ssi-1.01a
>>>> +
>>>> +then:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 4
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 4
>>>> +
>>>> +else:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 1
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 1
>>>
>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>
>> 8 too? sure.
>
> Then no constraints needed because the common definition already has
> this presumably.
Almost, the default has 0 in the enum too.
I'll go with that - thanks!
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-27 18:05 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-27 18:05 UTC (permalink / raw)
To: robh
Cc: niklas.cassel, alsa-devel, airlied, palmer, linux-kernel,
thierry.reding, jee.heng.sia, krzysztof.kozlowski+dt,
linux-riscv, sam, damien.lemoal, daniel.lezcano, joabreu, geert,
Eugeniy.Paltsev, devicetree, aou, broonie, dri-devel,
paul.walmsley, mail, tglx, dillon.minfei, lgirdwood,
fancer.lancer, linux-spi, vkoul, palmer, dmaengine, masahiroy
On 27/06/2022 18:15, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, Jun 20, 2022 at 09:06:34PM +0000, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 21:56, Serge Semin wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
>>>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
>>>> this.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
>>>> 1 file changed, 35 insertions(+), 13 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> index e25d44c218f2..f2b9e3f062cd 100644
>>>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
>>>> @@ -135,19 +135,41 @@ properties:
>>>> of the designware controller, and the upper limit is also subject to
>>>> controller configuration.
>>>>
>>>> -patternProperties:
>>>> - "^.*@[0-9a-f]+$":
>>>> - type: object
>>>> - properties:
>>>> - reg:
>>>> - minimum: 0
>>>> - maximum: 3
>>>> -
>>>> - spi-rx-bus-width:
>>>> - const: 1
>>>> -
>>>> - spi-tx-bus-width:
>>>> - const: 1
>>>> +if:
>>>> + properties:
>>>> + compatible:
>>>> + contains:
>>>> + const: snps,dwc-ssi-1.01a
>>>> +
>>>> +then:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 4
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 4
>>>> +
>>>> +else:
>>>> + patternProperties:
>>>> + "^.*@[0-9a-f]+$":
>>>> + type: object
>>>> + properties:
>>>> + reg:
>>>> + minimum: 0
>>>> + maximum: 3
>>>> +
>>>> + spi-rx-bus-width:
>>>> + const: 1
>>>> +
>>>> + spi-tx-bus-width:
>>>> + const: 1
>>>
>>> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
>>
>> 8 too? sure.
>
> Then no constraints needed because the common definition already has
> this presumably.
Almost, the default has 0 in the enum too.
I'll go with that - thanks!
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-20 20:56 ` Serge Semin
(?)
(?)
@ 2022-06-21 7:03 ` Geert Uytterhoeven
-1 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-21 7:03 UTC (permalink / raw)
To: Serge Semin
Cc: Conor Dooley, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod Koul, Liam Girdwood, Mark Brown,
Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner,
Paul Walmsley, Albert Ou, Conor Dooley, Masahiro Yamada,
Damien Le Moal, Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu,
DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, dmaengine,
ALSA Development Mailing List, linux-spi, linux-riscv
Hi Serge,
On Mon, Jun 20, 2022 at 10:56 PM Serge Semin <fancer.lancer@gmail.com> wrote:
> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> > width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> > this.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> > 1 file changed, 35 insertions(+), 13 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > index e25d44c218f2..f2b9e3f062cd 100644
> > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > @@ -135,19 +135,41 @@ properties:
> > of the designware controller, and the upper limit is also subject to
> > controller configuration.
> >
> > -patternProperties:
> > - "^.*@[0-9a-f]+$":
> > - type: object
> > - properties:
> > - reg:
> > - minimum: 0
> > - maximum: 3
> > -
> > - spi-rx-bus-width:
> > - const: 1
> > -
> > - spi-tx-bus-width:
> > - const: 1
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: snps,dwc-ssi-1.01a
> > +
> > +then:
> > + patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 4
> > +
> > + spi-tx-bus-width:
> > + const: 4
> > +
> > +else:
> > + patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 1
> > +
> > + spi-tx-bus-width:
> > + const: 1
>
> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
> irrespective from the compatible string. The modern DW APB SSI
> controllers of v.4.* and newer also support the enhanced SPI Modes too
> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> run-time there is no way to create a DT-schema correctly constraining
> the Rx/Tx SPI bus widths. So let's keep the
> compatible-string-independent "patternProperties" here but just extend
> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> properties values.
>
> Note the DW APB SSI/AHB SSI driver currently doesn't support the
> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> activated by means of the corresponding CSR. So most likely the DW AHB
> SSI controllers need some specific setups too.
That doesn't matter here, as DT describes hardware, not software
limitations.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-21 7:03 ` Geert Uytterhoeven
0 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-21 7:03 UTC (permalink / raw)
To: Serge Semin
Cc: Niklas Cassel, ALSA Development Mailing List, David Airlie,
Palmer Dabbelt, Linux Kernel Mailing List, Conor Dooley,
Thierry Reding, Krzysztof Kozlowski, linux-riscv, Sam Ravnborg,
Damien Le Moal, Daniel Lezcano, Jose Abreu, Eugeniy Paltsev,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Albert Ou, Mark Brown, DRI Development, Paul Walmsley,
Conor Dooley, Thomas Gleixner, Dillon Min, Liam Girdwood,
Heng Sia, linux-spi, Vinod Koul, Rob Herring, Palmer Dabbelt,
Daniel Vetter, dmaengine, Masahiro Yamada
Hi Serge,
On Mon, Jun 20, 2022 at 10:56 PM Serge Semin <fancer.lancer@gmail.com> wrote:
> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> > width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> > this.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> > 1 file changed, 35 insertions(+), 13 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > index e25d44c218f2..f2b9e3f062cd 100644
> > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > @@ -135,19 +135,41 @@ properties:
> > of the designware controller, and the upper limit is also subject to
> > controller configuration.
> >
> > -patternProperties:
> > - "^.*@[0-9a-f]+$":
> > - type: object
> > - properties:
> > - reg:
> > - minimum: 0
> > - maximum: 3
> > -
> > - spi-rx-bus-width:
> > - const: 1
> > -
> > - spi-tx-bus-width:
> > - const: 1
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: snps,dwc-ssi-1.01a
> > +
> > +then:
> > + patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 4
> > +
> > + spi-tx-bus-width:
> > + const: 4
> > +
> > +else:
> > + patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 1
> > +
> > + spi-tx-bus-width:
> > + const: 1
>
> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
> irrespective from the compatible string. The modern DW APB SSI
> controllers of v.4.* and newer also support the enhanced SPI Modes too
> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> run-time there is no way to create a DT-schema correctly constraining
> the Rx/Tx SPI bus widths. So let's keep the
> compatible-string-independent "patternProperties" here but just extend
> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> properties values.
>
> Note the DW APB SSI/AHB SSI driver currently doesn't support the
> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> activated by means of the corresponding CSR. So most likely the DW AHB
> SSI controllers need some specific setups too.
That doesn't matter here, as DT describes hardware, not software
limitations.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-21 7:03 ` Geert Uytterhoeven
0 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-21 7:03 UTC (permalink / raw)
To: Serge Semin
Cc: Conor Dooley, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod Koul, Liam Girdwood, Mark Brown,
Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner,
Paul Walmsley, Albert Ou, Conor Dooley, Masahiro Yamada,
Damien Le Moal, Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu,
DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, dmaengine,
ALSA Development Mailing List, linux-spi, linux-riscv
Hi Serge,
On Mon, Jun 20, 2022 at 10:56 PM Serge Semin <fancer.lancer@gmail.com> wrote:
> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> > width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> > this.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> > 1 file changed, 35 insertions(+), 13 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > index e25d44c218f2..f2b9e3f062cd 100644
> > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > @@ -135,19 +135,41 @@ properties:
> > of the designware controller, and the upper limit is also subject to
> > controller configuration.
> >
> > -patternProperties:
> > - "^.*@[0-9a-f]+$":
> > - type: object
> > - properties:
> > - reg:
> > - minimum: 0
> > - maximum: 3
> > -
> > - spi-rx-bus-width:
> > - const: 1
> > -
> > - spi-tx-bus-width:
> > - const: 1
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: snps,dwc-ssi-1.01a
> > +
> > +then:
> > + patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 4
> > +
> > + spi-tx-bus-width:
> > + const: 4
> > +
> > +else:
> > + patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 1
> > +
> > + spi-tx-bus-width:
> > + const: 1
>
> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
> irrespective from the compatible string. The modern DW APB SSI
> controllers of v.4.* and newer also support the enhanced SPI Modes too
> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> run-time there is no way to create a DT-schema correctly constraining
> the Rx/Tx SPI bus widths. So let's keep the
> compatible-string-independent "patternProperties" here but just extend
> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> properties values.
>
> Note the DW APB SSI/AHB SSI driver currently doesn't support the
> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> activated by means of the corresponding CSR. So most likely the DW AHB
> SSI controllers need some specific setups too.
That doesn't matter here, as DT describes hardware, not software
limitations.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-21 7:03 ` Geert Uytterhoeven
0 siblings, 0 replies; 159+ messages in thread
From: Geert Uytterhoeven @ 2022-06-21 7:03 UTC (permalink / raw)
To: Serge Semin
Cc: Niklas Cassel, ALSA Development Mailing List, David Airlie,
Palmer Dabbelt, Linux Kernel Mailing List, Conor Dooley,
Thierry Reding, Krzysztof Kozlowski, linux-riscv, Sam Ravnborg,
Damien Le Moal, Daniel Lezcano, Jose Abreu, Eugeniy Paltsev,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Albert Ou, Mark Brown, DRI Development, Paul Walmsley,
Conor Dooley, Thomas Gleixner, Dillon Min, Liam Girdwood,
Heng Sia, linux-spi, Vinod Koul, Rob Herring, Palmer Dabbelt,
dmaengine, Masahiro Yamada
Hi Serge,
On Mon, Jun 20, 2022 at 10:56 PM Serge Semin <fancer.lancer@gmail.com> wrote:
> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> > width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> > this.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++-----
> > 1 file changed, 35 insertions(+), 13 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > index e25d44c218f2..f2b9e3f062cd 100644
> > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > @@ -135,19 +135,41 @@ properties:
> > of the designware controller, and the upper limit is also subject to
> > controller configuration.
> >
> > -patternProperties:
> > - "^.*@[0-9a-f]+$":
> > - type: object
> > - properties:
> > - reg:
> > - minimum: 0
> > - maximum: 3
> > -
> > - spi-rx-bus-width:
> > - const: 1
> > -
> > - spi-tx-bus-width:
> > - const: 1
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: snps,dwc-ssi-1.01a
> > +
> > +then:
> > + patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 4
> > +
> > + spi-tx-bus-width:
> > + const: 4
> > +
> > +else:
> > + patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 1
> > +
> > + spi-tx-bus-width:
> > + const: 1
>
> You can just use a more relaxed constraint "enum: [1 2 4 8]" here
> irrespective from the compatible string. The modern DW APB SSI
> controllers of v.4.* and newer also support the enhanced SPI Modes too
> (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> run-time there is no way to create a DT-schema correctly constraining
> the Rx/Tx SPI bus widths. So let's keep the
> compatible-string-independent "patternProperties" here but just extend
> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> properties values.
>
> Note the DW APB SSI/AHB SSI driver currently doesn't support the
> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> activated by means of the corresponding CSR. So most likely the DW AHB
> SSI controllers need some specific setups too.
That doesn't matter here, as DT describes hardware, not software
limitations.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
2022-06-21 7:03 ` Geert Uytterhoeven
(?)
(?)
@ 2022-06-21 9:32 ` Serge Semin
-1 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-21 9:32 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Conor Dooley, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod Koul, Liam Girdwood, Mark Brown,
Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner,
Paul Walmsley, Albert Ou, Conor Dooley, Masahiro Yamada,
Damien Le Moal, Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu,
DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, dmaengine,
ALSA Development Mailing List, linux-spi, linux-riscv
Hi Geert
On Tue, Jun 21, 2022 at 09:03:25AM +0200, Geert Uytterhoeven wrote:
> Hi Serge,
>
> On Mon, Jun 20, 2022 at 10:56 PM Serge Semin <fancer.lancer@gmail.com> wrote:
> > On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > > From: Conor Dooley <conor.dooley@microchip.com>
> > >
[...]
> > > +
> > > + spi-rx-bus-width:
> > > + const: 1
> > > +
> > > + spi-tx-bus-width:
> > > + const: 1
> >
> > You can just use a more relaxed constraint "enum: [1 2 4 8]" here
> > irrespective from the compatible string. The modern DW APB SSI
> > controllers of v.4.* and newer also support the enhanced SPI Modes too
> > (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> > run-time there is no way to create a DT-schema correctly constraining
> > the Rx/Tx SPI bus widths. So let's keep the
> > compatible-string-independent "patternProperties" here but just extend
> > the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> > properties values.
> >
> > Note the DW APB SSI/AHB SSI driver currently doesn't support the
> > enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> > bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> > DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> > activated by means of the corresponding CSR. So most likely the DW AHB
> > SSI controllers need some specific setups too.
>
> That doesn't matter here, as DT describes hardware, not software
> limitations.
Can't argue with that.) My note regarding the current DW APB SSI
driver was mainly addressed for the Canaan K210 users, since
should the SoC-based board really have the Quad Tx/Rx SPI bus
most likely the interface won't work with the full bandwidth.
So it is a good reason to perform the platform research and if
possible alter the driver accordingly.
-Sergey
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-21 9:32 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-21 9:32 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Niklas Cassel, ALSA Development Mailing List, David Airlie,
Palmer Dabbelt, Linux Kernel Mailing List, Conor Dooley,
Thierry Reding, Krzysztof Kozlowski, linux-riscv, Sam Ravnborg,
Damien Le Moal, Daniel Lezcano, Jose Abreu, Eugeniy Paltsev,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Albert Ou, Mark Brown, DRI Development, Paul Walmsley,
Conor Dooley, Thomas Gleixner, Dillon Min, Liam Girdwood,
Heng Sia, linux-spi, Vinod Koul, Rob Herring, Palmer Dabbelt,
Daniel Vetter, dmaengine, Masahiro Yamada
Hi Geert
On Tue, Jun 21, 2022 at 09:03:25AM +0200, Geert Uytterhoeven wrote:
> Hi Serge,
>
> On Mon, Jun 20, 2022 at 10:56 PM Serge Semin <fancer.lancer@gmail.com> wrote:
> > On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > > From: Conor Dooley <conor.dooley@microchip.com>
> > >
[...]
> > > +
> > > + spi-rx-bus-width:
> > > + const: 1
> > > +
> > > + spi-tx-bus-width:
> > > + const: 1
> >
> > You can just use a more relaxed constraint "enum: [1 2 4 8]" here
> > irrespective from the compatible string. The modern DW APB SSI
> > controllers of v.4.* and newer also support the enhanced SPI Modes too
> > (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> > run-time there is no way to create a DT-schema correctly constraining
> > the Rx/Tx SPI bus widths. So let's keep the
> > compatible-string-independent "patternProperties" here but just extend
> > the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> > properties values.
> >
> > Note the DW APB SSI/AHB SSI driver currently doesn't support the
> > enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> > bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> > DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> > activated by means of the corresponding CSR. So most likely the DW AHB
> > SSI controllers need some specific setups too.
>
> That doesn't matter here, as DT describes hardware, not software
> limitations.
Can't argue with that.) My note regarding the current DW APB SSI
driver was mainly addressed for the Canaan K210 users, since
should the SoC-based board really have the Quad Tx/Rx SPI bus
most likely the interface won't work with the full bandwidth.
So it is a good reason to perform the platform research and if
possible alter the driver accordingly.
-Sergey
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-21 9:32 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-21 9:32 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Niklas Cassel, ALSA Development Mailing List, David Airlie,
Palmer Dabbelt, Linux Kernel Mailing List, Conor Dooley,
Thierry Reding, Krzysztof Kozlowski, linux-riscv, Sam Ravnborg,
Damien Le Moal, Daniel Lezcano, Jose Abreu, Eugeniy Paltsev,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Albert Ou, Mark Brown, DRI Development, Paul Walmsley,
Conor Dooley, Thomas Gleixner, Dillon Min, Liam Girdwood,
Heng Sia, linux-spi, Vinod Koul, Rob Herring, Palmer Dabbelt,
dmaengine, Masahiro Yamada
Hi Geert
On Tue, Jun 21, 2022 at 09:03:25AM +0200, Geert Uytterhoeven wrote:
> Hi Serge,
>
> On Mon, Jun 20, 2022 at 10:56 PM Serge Semin <fancer.lancer@gmail.com> wrote:
> > On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > > From: Conor Dooley <conor.dooley@microchip.com>
> > >
[...]
> > > +
> > > + spi-rx-bus-width:
> > > + const: 1
> > > +
> > > + spi-tx-bus-width:
> > > + const: 1
> >
> > You can just use a more relaxed constraint "enum: [1 2 4 8]" here
> > irrespective from the compatible string. The modern DW APB SSI
> > controllers of v.4.* and newer also support the enhanced SPI Modes too
> > (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> > run-time there is no way to create a DT-schema correctly constraining
> > the Rx/Tx SPI bus widths. So let's keep the
> > compatible-string-independent "patternProperties" here but just extend
> > the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> > properties values.
> >
> > Note the DW APB SSI/AHB SSI driver currently doesn't support the
> > enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> > bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> > DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> > activated by means of the corresponding CSR. So most likely the DW AHB
> > SSI controllers need some specific setups too.
>
> That doesn't matter here, as DT describes hardware, not software
> limitations.
Can't argue with that.) My note regarding the current DW APB SSI
driver was mainly addressed for the Canaan K210 users, since
should the SoC-based board really have the Quad Tx/Rx SPI bus
most likely the interface won't work with the full bandwidth.
So it is a good reason to perform the platform research and if
possible alter the driver accordingly.
-Sergey
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
@ 2022-06-21 9:32 ` Serge Semin
0 siblings, 0 replies; 159+ messages in thread
From: Serge Semin @ 2022-06-21 9:32 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Conor Dooley, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod Koul, Liam Girdwood, Mark Brown,
Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt, Thomas Gleixner,
Paul Walmsley, Albert Ou, Conor Dooley, Masahiro Yamada,
Damien Le Moal, Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu,
DRI Development,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, dmaengine,
ALSA Development Mailing List, linux-spi, linux-riscv
Hi Geert
On Tue, Jun 21, 2022 at 09:03:25AM +0200, Geert Uytterhoeven wrote:
> Hi Serge,
>
> On Mon, Jun 20, 2022 at 10:56 PM Serge Semin <fancer.lancer@gmail.com> wrote:
> > On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> > > From: Conor Dooley <conor.dooley@microchip.com>
> > >
[...]
> > > +
> > > + spi-rx-bus-width:
> > > + const: 1
> > > +
> > > + spi-tx-bus-width:
> > > + const: 1
> >
> > You can just use a more relaxed constraint "enum: [1 2 4 8]" here
> > irrespective from the compatible string. The modern DW APB SSI
> > controllers of v.4.* and newer also support the enhanced SPI Modes too
> > (Dual, Quad and Octal). Since the IP-core version is auto-detected at
> > run-time there is no way to create a DT-schema correctly constraining
> > the Rx/Tx SPI bus widths. So let's keep the
> > compatible-string-independent "patternProperties" here but just extend
> > the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
> > properties values.
> >
> > Note the DW APB SSI/AHB SSI driver currently doesn't support the
> > enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
> > bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
> > DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
> > activated by means of the corresponding CSR. So most likely the DW AHB
> > SSI controllers need some specific setups too.
>
> That doesn't matter here, as DT describes hardware, not software
> limitations.
Can't argue with that.) My note regarding the current DW APB SSI
driver was mainly addressed for the Canaan K210 users, since
should the SoC-based board really have the Quad Tx/Rx SPI bus
most likely the interface won't work with the full bandwidth.
So it is a good reason to perform the platform research and if
possible alter the driver accordingly.
-Sergey
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread
* [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The k210 memory node has a compatible string that does not match with
any driver or dt-binding & has several non standard properties.
Replace the reg names with a comment and delete the rest.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
---
arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
1 file changed, 6 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 44d338514761..287ea6eebe47 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
sram: memory@80000000 {
device_type = "memory";
- compatible = "canaan,k210-sram";
reg = <0x80000000 0x400000>,
<0x80400000 0x200000>,
<0x80600000 0x200000>;
- reg-names = "sram0", "sram1", "aisram";
- clocks = <&sysclk K210_CLK_SRAM0>,
- <&sysclk K210_CLK_SRAM1>,
- <&sysclk K210_CLK_AI>;
- clock-names = "sram0", "sram1", "aisram";
};
clocks {
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
The k210 memory node has a compatible string that does not match with
any driver or dt-binding & has several non standard properties.
Replace the reg names with a comment and delete the rest.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
---
arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
1 file changed, 6 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 44d338514761..287ea6eebe47 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
sram: memory@80000000 {
device_type = "memory";
- compatible = "canaan,k210-sram";
reg = <0x80000000 0x400000>,
<0x80400000 0x200000>,
<0x80600000 0x200000>;
- reg-names = "sram0", "sram1", "aisram";
- clocks = <&sysclk K210_CLK_SRAM0>,
- <&sysclk K210_CLK_SRAM1>,
- <&sysclk K210_CLK_AI>;
- clock-names = "sram0", "sram1", "aisram";
};
clocks {
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The k210 memory node has a compatible string that does not match with
any driver or dt-binding & has several non standard properties.
Replace the reg names with a comment and delete the rest.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
---
arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
1 file changed, 6 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 44d338514761..287ea6eebe47 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
sram: memory@80000000 {
device_type = "memory";
- compatible = "canaan,k210-sram";
reg = <0x80000000 0x400000>,
<0x80400000 0x200000>,
<0x80600000 0x200000>;
- reg-names = "sram0", "sram1", "aisram";
- clocks = <&sysclk K210_CLK_SRAM0>,
- <&sysclk K210_CLK_SRAM1>,
- <&sysclk K210_CLK_AI>;
- clock-names = "sram0", "sram1", "aisram";
};
clocks {
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:35 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-18 12:35 UTC (permalink / raw)
To: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, fancer.lancer,
daniel.lezcano, palmer, palmer
Cc: tglx, paul.walmsley, aou, Conor.Dooley, masahiroy, damien.lemoal,
geert, niklas.cassel, dillon.minfei, jee.heng.sia, joabreu,
dri-devel, devicetree, linux-kernel, dmaengine, alsa-devel,
linux-spi, linux-riscv
On 18/06/2022 13:30, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The k210 memory node has a compatible string that does not match with
> any driver or dt-binding & has several non standard properties.
> Replace the reg names with a comment and delete the rest.
Gah, should've fixed that during rebase.
I'm sure there'll need to be (at least) a v2 & I'll wait rather
than resend.
Thanks,
Conor.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> ---
> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
> index 44d338514761..287ea6eebe47 100644
> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>
> sram: memory@80000000 {
> device_type = "memory";
> - compatible = "canaan,k210-sram";
> reg = <0x80000000 0x400000>,
> <0x80400000 0x200000>,
> <0x80600000 0x200000>;
> - reg-names = "sram0", "sram1", "aisram";
> - clocks = <&sysclk K210_CLK_SRAM0>,
> - <&sysclk K210_CLK_SRAM1>,
> - <&sysclk K210_CLK_AI>;
> - clock-names = "sram0", "sram1", "aisram";
> };
>
> clocks {
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-18 12:35 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-18 12:35 UTC (permalink / raw)
To: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, fancer.lancer,
daniel.lezcano, palmer, palmer
Cc: tglx, paul.walmsley, aou, Conor.Dooley, masahiroy, damien.lemoal,
geert, niklas.cassel, dillon.minfei, jee.heng.sia, joabreu,
dri-devel, devicetree, linux-kernel, dmaengine, alsa-devel,
linux-spi, linux-riscv
On 18/06/2022 13:30, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The k210 memory node has a compatible string that does not match with
> any driver or dt-binding & has several non standard properties.
> Replace the reg names with a comment and delete the rest.
Gah, should've fixed that during rebase.
I'm sure there'll need to be (at least) a v2 & I'll wait rather
than resend.
Thanks,
Conor.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> ---
> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
> index 44d338514761..287ea6eebe47 100644
> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>
> sram: memory@80000000 {
> device_type = "memory";
> - compatible = "canaan,k210-sram";
> reg = <0x80000000 0x400000>,
> <0x80400000 0x200000>,
> <0x80600000 0x200000>;
> - reg-names = "sram0", "sram1", "aisram";
> - clocks = <&sysclk K210_CLK_SRAM0>,
> - <&sysclk K210_CLK_SRAM1>,
> - <&sysclk K210_CLK_AI>;
> - clock-names = "sram0", "sram1", "aisram";
> };
>
> clocks {
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-18 12:35 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-18 12:35 UTC (permalink / raw)
To: airlied, daniel, robh+dt, krzysztof.kozlowski+dt, thierry.reding,
sam, Eugeniy.Paltsev, vkoul, lgirdwood, broonie, fancer.lancer,
daniel.lezcano, palmer, palmer
Cc: linux-riscv, niklas.cassel, alsa-devel, aou, devicetree,
damien.lemoal, linux-kernel, jee.heng.sia, linux-spi,
Conor.Dooley, joabreu, geert, dri-devel, paul.walmsley,
dmaengine, tglx, dillon.minfei, masahiroy
On 18/06/2022 13:30, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The k210 memory node has a compatible string that does not match with
> any driver or dt-binding & has several non standard properties.
> Replace the reg names with a comment and delete the rest.
Gah, should've fixed that during rebase.
I'm sure there'll need to be (at least) a v2 & I'll wait rather
than resend.
Thanks,
Conor.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> ---
> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
> index 44d338514761..287ea6eebe47 100644
> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>
> sram: memory@80000000 {
> device_type = "memory";
> - compatible = "canaan,k210-sram";
> reg = <0x80000000 0x400000>,
> <0x80400000 0x200000>,
> <0x80600000 0x200000>;
> - reg-names = "sram0", "sram1", "aisram";
> - clocks = <&sysclk K210_CLK_SRAM0>,
> - <&sysclk K210_CLK_SRAM1>,
> - <&sysclk K210_CLK_AI>;
> - clock-names = "sram0", "sram1", "aisram";
> };
>
> clocks {
^ permalink raw reply [flat|nested] 159+ messages in thread
* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-19 23:38 ` Damien Le Moal
-1 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-19 23:38 UTC (permalink / raw)
To: Conor Dooley, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod Koul, Liam Girdwood, Mark Brown,
Serge Semin, Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Geert Uytterhoeven, Niklas Cassel, Dillon Min,
Heng Sia, Jose Abreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On 6/18/22 21:30, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The k210 memory node has a compatible string that does not match with
> any driver or dt-binding & has several non standard properties.
> Replace the reg names with a comment and delete the rest.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> ---
> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
> index 44d338514761..287ea6eebe47 100644
> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>
> sram: memory@80000000 {
> device_type = "memory";
> - compatible = "canaan,k210-sram";
> reg = <0x80000000 0x400000>,
> <0x80400000 0x200000>,
> <0x80600000 0x200000>;
> - reg-names = "sram0", "sram1", "aisram";
> - clocks = <&sysclk K210_CLK_SRAM0>,
> - <&sysclk K210_CLK_SRAM1>,
> - <&sysclk K210_CLK_AI>;
> - clock-names = "sram0", "sram1", "aisram";
> };
These are used by u-boot to setup the memory clocks and initialize the
aisram. Sure the kernel actually does not use this, but to be in sync with
u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
kernel work fine with both u-boot internal DT and the kernel DT.
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-19 23:38 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-19 23:38 UTC (permalink / raw)
To: Conor Dooley, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod Koul, Liam Girdwood, Mark Brown,
Serge Semin, Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt
Cc: Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Masahiro Yamada, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, linux-riscv
On 6/18/22 21:30, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The k210 memory node has a compatible string that does not match with
> any driver or dt-binding & has several non standard properties.
> Replace the reg names with a comment and delete the rest.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> ---
> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
> index 44d338514761..287ea6eebe47 100644
> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>
> sram: memory@80000000 {
> device_type = "memory";
> - compatible = "canaan,k210-sram";
> reg = <0x80000000 0x400000>,
> <0x80400000 0x200000>,
> <0x80600000 0x200000>;
> - reg-names = "sram0", "sram1", "aisram";
> - clocks = <&sysclk K210_CLK_SRAM0>,
> - <&sysclk K210_CLK_SRAM1>,
> - <&sysclk K210_CLK_AI>;
> - clock-names = "sram0", "sram1", "aisram";
> };
These are used by u-boot to setup the memory clocks and initialize the
aisram. Sure the kernel actually does not use this, but to be in sync with
u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
kernel work fine with both u-boot internal DT and the kernel DT.
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-19 23:38 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-19 23:38 UTC (permalink / raw)
To: Conor Dooley, David Airlie, Daniel Vetter, Rob Herring,
Krzysztof Kozlowski, Thierry Reding, Sam Ravnborg,
Eugeniy Paltsev, Vinod Koul, Liam Girdwood, Mark Brown,
Serge Semin, Daniel Lezcano, Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Geert Uytterhoeven, Niklas Cassel, Dillon Min,
Heng Sia, Jose Abreu, dri-devel, devicetree, linux-kernel,
dmaengine, alsa-devel, linux-spi, linux-riscv
On 6/18/22 21:30, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The k210 memory node has a compatible string that does not match with
> any driver or dt-binding & has several non standard properties.
> Replace the reg names with a comment and delete the rest.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> ---
> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
> index 44d338514761..287ea6eebe47 100644
> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>
> sram: memory@80000000 {
> device_type = "memory";
> - compatible = "canaan,k210-sram";
> reg = <0x80000000 0x400000>,
> <0x80400000 0x200000>,
> <0x80600000 0x200000>;
> - reg-names = "sram0", "sram1", "aisram";
> - clocks = <&sysclk K210_CLK_SRAM0>,
> - <&sysclk K210_CLK_SRAM1>,
> - <&sysclk K210_CLK_AI>;
> - clock-names = "sram0", "sram1", "aisram";
> };
These are used by u-boot to setup the memory clocks and initialize the
aisram. Sure the kernel actually does not use this, but to be in sync with
u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
kernel work fine with both u-boot internal DT and the kernel DT.
--
Damien Le Moal
Western Digital Research
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-19 23:38 ` Damien Le Moal
(?)
@ 2022-06-19 23:54 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-19 23:54 UTC (permalink / raw)
To: damien.lemoal, mail, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, thierry.reding, sam, Eugeniy.Paltsev,
vkoul, lgirdwood, broonie, fancer.lancer, daniel.lezcano, palmer,
palmer
Cc: tglx, paul.walmsley, aou, masahiroy, geert, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On 20/06/2022 00:38, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/18/22 21:30, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The k210 memory node has a compatible string that does not match with
>> any driver or dt-binding & has several non standard properties.
>> Replace the reg names with a comment and delete the rest.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> ---
>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>> 1 file changed, 6 deletions(-)
>>
>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>> index 44d338514761..287ea6eebe47 100644
>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>
>> sram: memory@80000000 {
>> device_type = "memory";
>> - compatible = "canaan,k210-sram";
>> reg = <0x80000000 0x400000>,
>> <0x80400000 0x200000>,
>> <0x80600000 0x200000>;
>> - reg-names = "sram0", "sram1", "aisram";
>> - clocks = <&sysclk K210_CLK_SRAM0>,
>> - <&sysclk K210_CLK_SRAM1>,
>> - <&sysclk K210_CLK_AI>;
>> - clock-names = "sram0", "sram1", "aisram";
>> };
>
> These are used by u-boot to setup the memory clocks and initialize the
> aisram. Sure the kernel actually does not use this, but to be in sync with
> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
> kernel work fine with both u-boot internal DT and the kernel DT.
Right, but unfortunately that desire alone doesn't do anything about
the dtbs_check complaints.
I guess the alternative approach of actually documenting the compatible
would be more palatable?
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-19 23:54 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-19 23:54 UTC (permalink / raw)
To: damien.lemoal, mail, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, thierry.reding, sam, Eugeniy.Paltsev,
vkoul, lgirdwood, broonie, fancer.lancer, daniel.lezcano, palmer,
palmer
Cc: niklas.cassel, alsa-devel, aou, devicetree, masahiroy,
linux-kernel, jee.heng.sia, linux-spi, joabreu, geert, dri-devel,
paul.walmsley, dmaengine, tglx, dillon.minfei, linux-riscv
On 20/06/2022 00:38, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/18/22 21:30, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The k210 memory node has a compatible string that does not match with
>> any driver or dt-binding & has several non standard properties.
>> Replace the reg names with a comment and delete the rest.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> ---
>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>> 1 file changed, 6 deletions(-)
>>
>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>> index 44d338514761..287ea6eebe47 100644
>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>
>> sram: memory@80000000 {
>> device_type = "memory";
>> - compatible = "canaan,k210-sram";
>> reg = <0x80000000 0x400000>,
>> <0x80400000 0x200000>,
>> <0x80600000 0x200000>;
>> - reg-names = "sram0", "sram1", "aisram";
>> - clocks = <&sysclk K210_CLK_SRAM0>,
>> - <&sysclk K210_CLK_SRAM1>,
>> - <&sysclk K210_CLK_AI>;
>> - clock-names = "sram0", "sram1", "aisram";
>> };
>
> These are used by u-boot to setup the memory clocks and initialize the
> aisram. Sure the kernel actually does not use this, but to be in sync with
> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
> kernel work fine with both u-boot internal DT and the kernel DT.
Right, but unfortunately that desire alone doesn't do anything about
the dtbs_check complaints.
I guess the alternative approach of actually documenting the compatible
would be more palatable?
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-19 23:54 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-19 23:54 UTC (permalink / raw)
To: damien.lemoal, mail, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, thierry.reding, sam, Eugeniy.Paltsev,
vkoul, lgirdwood, broonie, fancer.lancer, daniel.lezcano, palmer,
palmer
Cc: tglx, paul.walmsley, aou, masahiroy, geert, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On 20/06/2022 00:38, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/18/22 21:30, Conor Dooley wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> The k210 memory node has a compatible string that does not match with
>> any driver or dt-binding & has several non standard properties.
>> Replace the reg names with a comment and delete the rest.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> ---
>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>> 1 file changed, 6 deletions(-)
>>
>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>> index 44d338514761..287ea6eebe47 100644
>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>
>> sram: memory@80000000 {
>> device_type = "memory";
>> - compatible = "canaan,k210-sram";
>> reg = <0x80000000 0x400000>,
>> <0x80400000 0x200000>,
>> <0x80600000 0x200000>;
>> - reg-names = "sram0", "sram1", "aisram";
>> - clocks = <&sysclk K210_CLK_SRAM0>,
>> - <&sysclk K210_CLK_SRAM1>,
>> - <&sysclk K210_CLK_AI>;
>> - clock-names = "sram0", "sram1", "aisram";
>> };
>
> These are used by u-boot to setup the memory clocks and initialize the
> aisram. Sure the kernel actually does not use this, but to be in sync with
> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
> kernel work fine with both u-boot internal DT and the kernel DT.
Right, but unfortunately that desire alone doesn't do anything about
the dtbs_check complaints.
I guess the alternative approach of actually documenting the compatible
would be more palatable?
Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-19 23:54 ` Conor.Dooley
(?)
@ 2022-06-20 0:25 ` Damien Le Moal
-1 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 0:25 UTC (permalink / raw)
To: Conor.Dooley, mail, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, thierry.reding, sam, Eugeniy.Paltsev,
vkoul, lgirdwood, broonie, fancer.lancer, daniel.lezcano, palmer,
palmer
Cc: tglx, paul.walmsley, aou, masahiroy, geert, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 00:38, Damien Le Moal wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 6/18/22 21:30, Conor Dooley wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> The k210 memory node has a compatible string that does not match with
>>> any driver or dt-binding & has several non standard properties.
>>> Replace the reg names with a comment and delete the rest.
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> ---
>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>> 1 file changed, 6 deletions(-)
>>>
>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>> index 44d338514761..287ea6eebe47 100644
>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>
>>> sram: memory@80000000 {
>>> device_type = "memory";
>>> - compatible = "canaan,k210-sram";
>>> reg = <0x80000000 0x400000>,
>>> <0x80400000 0x200000>,
>>> <0x80600000 0x200000>;
>>> - reg-names = "sram0", "sram1", "aisram";
>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>> - <&sysclk K210_CLK_SRAM1>,
>>> - <&sysclk K210_CLK_AI>;
>>> - clock-names = "sram0", "sram1", "aisram";
>>> };
>>
>> These are used by u-boot to setup the memory clocks and initialize the
>> aisram. Sure the kernel actually does not use this, but to be in sync with
>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>> kernel work fine with both u-boot internal DT and the kernel DT.
>
> Right, but unfortunately that desire alone doesn't do anything about
> the dtbs_check complaints.
>
> I guess the alternative approach of actually documenting the compatible
> would be more palatable?
Yes, I think so. That would allow keeping the fields without the DTB build
warnings.
>
> Thanks,
> Conor.
>
>
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-20 0:25 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 0:25 UTC (permalink / raw)
To: Conor.Dooley, mail, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, thierry.reding, sam, Eugeniy.Paltsev,
vkoul, lgirdwood, broonie, fancer.lancer, daniel.lezcano, palmer,
palmer
Cc: niklas.cassel, alsa-devel, aou, devicetree, masahiroy,
linux-kernel, jee.heng.sia, linux-spi, joabreu, geert, dri-devel,
paul.walmsley, dmaengine, tglx, dillon.minfei, linux-riscv
On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 00:38, Damien Le Moal wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 6/18/22 21:30, Conor Dooley wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> The k210 memory node has a compatible string that does not match with
>>> any driver or dt-binding & has several non standard properties.
>>> Replace the reg names with a comment and delete the rest.
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> ---
>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>> 1 file changed, 6 deletions(-)
>>>
>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>> index 44d338514761..287ea6eebe47 100644
>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>
>>> sram: memory@80000000 {
>>> device_type = "memory";
>>> - compatible = "canaan,k210-sram";
>>> reg = <0x80000000 0x400000>,
>>> <0x80400000 0x200000>,
>>> <0x80600000 0x200000>;
>>> - reg-names = "sram0", "sram1", "aisram";
>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>> - <&sysclk K210_CLK_SRAM1>,
>>> - <&sysclk K210_CLK_AI>;
>>> - clock-names = "sram0", "sram1", "aisram";
>>> };
>>
>> These are used by u-boot to setup the memory clocks and initialize the
>> aisram. Sure the kernel actually does not use this, but to be in sync with
>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>> kernel work fine with both u-boot internal DT and the kernel DT.
>
> Right, but unfortunately that desire alone doesn't do anything about
> the dtbs_check complaints.
>
> I guess the alternative approach of actually documenting the compatible
> would be more palatable?
Yes, I think so. That would allow keeping the fields without the DTB build
warnings.
>
> Thanks,
> Conor.
>
>
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-20 0:25 ` Damien Le Moal
0 siblings, 0 replies; 159+ messages in thread
From: Damien Le Moal @ 2022-06-20 0:25 UTC (permalink / raw)
To: Conor.Dooley, mail, airlied, daniel, robh+dt,
krzysztof.kozlowski+dt, thierry.reding, sam, Eugeniy.Paltsev,
vkoul, lgirdwood, broonie, fancer.lancer, daniel.lezcano, palmer,
palmer
Cc: tglx, paul.walmsley, aou, masahiroy, geert, niklas.cassel,
dillon.minfei, jee.heng.sia, joabreu, dri-devel, devicetree,
linux-kernel, dmaengine, alsa-devel, linux-spi, linux-riscv
On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 00:38, Damien Le Moal wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 6/18/22 21:30, Conor Dooley wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> The k210 memory node has a compatible string that does not match with
>>> any driver or dt-binding & has several non standard properties.
>>> Replace the reg names with a comment and delete the rest.
>>>
>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> ---
>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>> 1 file changed, 6 deletions(-)
>>>
>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>> index 44d338514761..287ea6eebe47 100644
>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>
>>> sram: memory@80000000 {
>>> device_type = "memory";
>>> - compatible = "canaan,k210-sram";
>>> reg = <0x80000000 0x400000>,
>>> <0x80400000 0x200000>,
>>> <0x80600000 0x200000>;
>>> - reg-names = "sram0", "sram1", "aisram";
>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>> - <&sysclk K210_CLK_SRAM1>,
>>> - <&sysclk K210_CLK_AI>;
>>> - clock-names = "sram0", "sram1", "aisram";
>>> };
>>
>> These are used by u-boot to setup the memory clocks and initialize the
>> aisram. Sure the kernel actually does not use this, but to be in sync with
>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>> kernel work fine with both u-boot internal DT and the kernel DT.
>
> Right, but unfortunately that desire alone doesn't do anything about
> the dtbs_check complaints.
>
> I guess the alternative approach of actually documenting the compatible
> would be more palatable?
Yes, I think so. That would allow keeping the fields without the DTB build
warnings.
>
> Thanks,
> Conor.
>
>
>
--
Damien Le Moal
Western Digital Research
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-20 0:25 ` Damien Le Moal
(?)
(?)
@ 2022-06-21 9:49 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-21 9:49 UTC (permalink / raw)
To: damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, mail, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 20/06/2022 01:25, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> The k210 memory node has a compatible string that does not match with
>>>> any driver or dt-binding & has several non standard properties.
>>>> Replace the reg names with a comment and delete the rest.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> ---
>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>> 1 file changed, 6 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> index 44d338514761..287ea6eebe47 100644
>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>
>>>> sram: memory@80000000 {
>>>> device_type = "memory";
>>>> - compatible = "canaan,k210-sram";
>>>> reg = <0x80000000 0x400000>,
>>>> <0x80400000 0x200000>,
>>>> <0x80600000 0x200000>;
>>>> - reg-names = "sram0", "sram1", "aisram";
>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>> - <&sysclk K210_CLK_SRAM1>,
>>>> - <&sysclk K210_CLK_AI>;
>>>> - clock-names = "sram0", "sram1", "aisram";
>>>> };
>>>
>>> These are used by u-boot to setup the memory clocks and initialize the
>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>
>> Right, but unfortunately that desire alone doesn't do anything about
>> the dtbs_check complaints.
>>
>> I guess the alternative approach of actually documenting the compatible
>> would be more palatable?
>
> Yes, I think so. That would allow keeping the fields without the DTB build
> warnings.
Hmm looks like that approach contradicts the dt-schema;
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
@Rob,Krzysztof what is one meant to do here?
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-21 9:49 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-21 9:49 UTC (permalink / raw)
To: damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: niklas.cassel, alsa-devel, airlied, dri-devel, linux-kernel,
thierry.reding, jee.heng.sia, linux-riscv, sam, masahiroy,
daniel.lezcano, joabreu, geert, Eugeniy.Paltsev, devicetree, aou,
broonie, palmer, paul.walmsley, mail, tglx, dillon.minfei,
lgirdwood, fancer.lancer, linux-spi, vkoul, palmer, daniel,
dmaengine
On 20/06/2022 01:25, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> The k210 memory node has a compatible string that does not match with
>>>> any driver or dt-binding & has several non standard properties.
>>>> Replace the reg names with a comment and delete the rest.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> ---
>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>> 1 file changed, 6 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> index 44d338514761..287ea6eebe47 100644
>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>
>>>> sram: memory@80000000 {
>>>> device_type = "memory";
>>>> - compatible = "canaan,k210-sram";
>>>> reg = <0x80000000 0x400000>,
>>>> <0x80400000 0x200000>,
>>>> <0x80600000 0x200000>;
>>>> - reg-names = "sram0", "sram1", "aisram";
>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>> - <&sysclk K210_CLK_SRAM1>,
>>>> - <&sysclk K210_CLK_AI>;
>>>> - clock-names = "sram0", "sram1", "aisram";
>>>> };
>>>
>>> These are used by u-boot to setup the memory clocks and initialize the
>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>
>> Right, but unfortunately that desire alone doesn't do anything about
>> the dtbs_check complaints.
>>
>> I guess the alternative approach of actually documenting the compatible
>> would be more palatable?
>
> Yes, I think so. That would allow keeping the fields without the DTB build
> warnings.
Hmm looks like that approach contradicts the dt-schema;
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
@Rob,Krzysztof what is one meant to do here?
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-21 9:49 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-21 9:49 UTC (permalink / raw)
To: damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: niklas.cassel, alsa-devel, airlied, dri-devel, linux-kernel,
thierry.reding, jee.heng.sia, linux-riscv, sam, masahiroy,
daniel.lezcano, joabreu, geert, Eugeniy.Paltsev, devicetree, aou,
broonie, palmer, paul.walmsley, mail, tglx, dillon.minfei,
lgirdwood, fancer.lancer, linux-spi, vkoul, palmer, dmaengine
On 20/06/2022 01:25, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> The k210 memory node has a compatible string that does not match with
>>>> any driver or dt-binding & has several non standard properties.
>>>> Replace the reg names with a comment and delete the rest.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> ---
>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>> 1 file changed, 6 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> index 44d338514761..287ea6eebe47 100644
>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>
>>>> sram: memory@80000000 {
>>>> device_type = "memory";
>>>> - compatible = "canaan,k210-sram";
>>>> reg = <0x80000000 0x400000>,
>>>> <0x80400000 0x200000>,
>>>> <0x80600000 0x200000>;
>>>> - reg-names = "sram0", "sram1", "aisram";
>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>> - <&sysclk K210_CLK_SRAM1>,
>>>> - <&sysclk K210_CLK_AI>;
>>>> - clock-names = "sram0", "sram1", "aisram";
>>>> };
>>>
>>> These are used by u-boot to setup the memory clocks and initialize the
>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>
>> Right, but unfortunately that desire alone doesn't do anything about
>> the dtbs_check complaints.
>>
>> I guess the alternative approach of actually documenting the compatible
>> would be more palatable?
>
> Yes, I think so. That would allow keeping the fields without the DTB build
> warnings.
Hmm looks like that approach contradicts the dt-schema;
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
@Rob,Krzysztof what is one meant to do here?
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-21 9:49 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-21 9:49 UTC (permalink / raw)
To: damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, mail, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 20/06/2022 01:25, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>
>>>> The k210 memory node has a compatible string that does not match with
>>>> any driver or dt-binding & has several non standard properties.
>>>> Replace the reg names with a comment and delete the rest.
>>>>
>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>> ---
>>>> ---
>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>> 1 file changed, 6 deletions(-)
>>>>
>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> index 44d338514761..287ea6eebe47 100644
>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>
>>>> sram: memory@80000000 {
>>>> device_type = "memory";
>>>> - compatible = "canaan,k210-sram";
>>>> reg = <0x80000000 0x400000>,
>>>> <0x80400000 0x200000>,
>>>> <0x80600000 0x200000>;
>>>> - reg-names = "sram0", "sram1", "aisram";
>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>> - <&sysclk K210_CLK_SRAM1>,
>>>> - <&sysclk K210_CLK_AI>;
>>>> - clock-names = "sram0", "sram1", "aisram";
>>>> };
>>>
>>> These are used by u-boot to setup the memory clocks and initialize the
>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>
>> Right, but unfortunately that desire alone doesn't do anything about
>> the dtbs_check complaints.
>>
>> I guess the alternative approach of actually documenting the compatible
>> would be more palatable?
>
> Yes, I think so. That would allow keeping the fields without the DTB build
> warnings.
Hmm looks like that approach contradicts the dt-schema;
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
@Rob,Krzysztof what is one meant to do here?
Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-21 9:49 ` Conor.Dooley
(?)
@ 2022-06-27 6:55 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 159+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-27 6:55 UTC (permalink / raw)
To: Conor.Dooley, damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, mail, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 01:25, Damien Le Moal wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> The k210 memory node has a compatible string that does not match with
>>>>> any driver or dt-binding & has several non standard properties.
>>>>> Replace the reg names with a comment and delete the rest.
>>>>>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>> ---
>>>>> ---
>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>> 1 file changed, 6 deletions(-)
>>>>>
>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>> index 44d338514761..287ea6eebe47 100644
>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>
>>>>> sram: memory@80000000 {
>>>>> device_type = "memory";
>>>>> - compatible = "canaan,k210-sram";
>>>>> reg = <0x80000000 0x400000>,
>>>>> <0x80400000 0x200000>,
>>>>> <0x80600000 0x200000>;
>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>> - <&sysclk K210_CLK_AI>;
>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>> };
>>>>
>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>
>>> Right, but unfortunately that desire alone doesn't do anything about
>>> the dtbs_check complaints.
>>>
>>> I guess the alternative approach of actually documenting the compatible
>>> would be more palatable?
>>
>> Yes, I think so. That would allow keeping the fields without the DTB build
>> warnings.
>
> Hmm looks like that approach contradicts the dt-schema;
> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>
> @Rob,Krzysztof what is one meant to do here?
Why do you think it contradict bindings? Bindings for memory allow
additional properties, so you just need to create binding for this one.
And make it a correct binding, IOW, be sure that these clocks are real etc.
Although usually we had separate bindings (and device drivers) for
memory controllers, instead of including them in the "memory" node.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-27 6:55 ` Krzysztof Kozlowski
0 siblings, 0 replies; 159+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-27 6:55 UTC (permalink / raw)
To: Conor.Dooley, damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, mail, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 01:25, Damien Le Moal wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> The k210 memory node has a compatible string that does not match with
>>>>> any driver or dt-binding & has several non standard properties.
>>>>> Replace the reg names with a comment and delete the rest.
>>>>>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>> ---
>>>>> ---
>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>> 1 file changed, 6 deletions(-)
>>>>>
>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>> index 44d338514761..287ea6eebe47 100644
>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>
>>>>> sram: memory@80000000 {
>>>>> device_type = "memory";
>>>>> - compatible = "canaan,k210-sram";
>>>>> reg = <0x80000000 0x400000>,
>>>>> <0x80400000 0x200000>,
>>>>> <0x80600000 0x200000>;
>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>> - <&sysclk K210_CLK_AI>;
>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>> };
>>>>
>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>
>>> Right, but unfortunately that desire alone doesn't do anything about
>>> the dtbs_check complaints.
>>>
>>> I guess the alternative approach of actually documenting the compatible
>>> would be more palatable?
>>
>> Yes, I think so. That would allow keeping the fields without the DTB build
>> warnings.
>
> Hmm looks like that approach contradicts the dt-schema;
> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>
> @Rob,Krzysztof what is one meant to do here?
Why do you think it contradict bindings? Bindings for memory allow
additional properties, so you just need to create binding for this one.
And make it a correct binding, IOW, be sure that these clocks are real etc.
Although usually we had separate bindings (and device drivers) for
memory controllers, instead of including them in the "memory" node.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-27 6:55 ` Krzysztof Kozlowski
0 siblings, 0 replies; 159+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-27 6:55 UTC (permalink / raw)
To: Conor.Dooley, damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: niklas.cassel, alsa-devel, airlied, dri-devel, linux-kernel,
thierry.reding, jee.heng.sia, linux-riscv, sam, masahiroy,
daniel.lezcano, joabreu, geert, Eugeniy.Paltsev, devicetree, aou,
broonie, palmer, paul.walmsley, mail, tglx, dillon.minfei,
lgirdwood, fancer.lancer, linux-spi, vkoul, palmer, dmaengine
On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
> On 20/06/2022 01:25, Damien Le Moal wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>
>>>>> The k210 memory node has a compatible string that does not match with
>>>>> any driver or dt-binding & has several non standard properties.
>>>>> Replace the reg names with a comment and delete the rest.
>>>>>
>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>> ---
>>>>> ---
>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>> 1 file changed, 6 deletions(-)
>>>>>
>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>> index 44d338514761..287ea6eebe47 100644
>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>
>>>>> sram: memory@80000000 {
>>>>> device_type = "memory";
>>>>> - compatible = "canaan,k210-sram";
>>>>> reg = <0x80000000 0x400000>,
>>>>> <0x80400000 0x200000>,
>>>>> <0x80600000 0x200000>;
>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>> - <&sysclk K210_CLK_AI>;
>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>> };
>>>>
>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>
>>> Right, but unfortunately that desire alone doesn't do anything about
>>> the dtbs_check complaints.
>>>
>>> I guess the alternative approach of actually documenting the compatible
>>> would be more palatable?
>>
>> Yes, I think so. That would allow keeping the fields without the DTB build
>> warnings.
>
> Hmm looks like that approach contradicts the dt-schema;
> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>
> @Rob,Krzysztof what is one meant to do here?
Why do you think it contradict bindings? Bindings for memory allow
additional properties, so you just need to create binding for this one.
And make it a correct binding, IOW, be sure that these clocks are real etc.
Although usually we had separate bindings (and device drivers) for
memory controllers, instead of including them in the "memory" node.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-27 6:55 ` Krzysztof Kozlowski
(?)
@ 2022-06-27 7:06 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-27 7:06 UTC (permalink / raw)
To: krzysztof.kozlowski, Conor.Dooley, damien.lemoal, robh+dt,
krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>
>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>
>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>> ---
>>>>>> ---
>>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>> 1 file changed, 6 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>
>>>>>> sram: memory@80000000 {
>>>>>> device_type = "memory";
>>>>>> - compatible = "canaan,k210-sram";
>>>>>> reg = <0x80000000 0x400000>,
>>>>>> <0x80400000 0x200000>,
>>>>>> <0x80600000 0x200000>;
>>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>>> - <&sysclk K210_CLK_AI>;
>>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>>> };
>>>>>
>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>
>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>> the dtbs_check complaints.
>>>>
>>>> I guess the alternative approach of actually documenting the compatible
>>>> would be more palatable?
>>>
>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>> warnings.
>>
>> Hmm looks like that approach contradicts the dt-schema;
>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>
>> @Rob,Krzysztof what is one meant to do here?
>
> Why do you think it contradict bindings? Bindings for memory allow
Because when I tried to write the binding, the memory node complained
about the clock properties etc and referenced the dt-schema (which
for memory@foo nodes has additionalProperties: false.
> additional properties, so you just need to create binding for this one.
> And make it a correct binding, IOW, be sure that these clocks are real etc.
>
> Although usually we had separate bindings (and device drivers) for
> memory controllers, instead of including them in the "memory" node.
I guess changing to that format would probably require some changes on
the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
looks like the clocks etc go in a controller node, which seems like a
"better" way of doing it - but would break existing dts in U-Boot
without changes to handle both methods there.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-27 7:06 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-27 7:06 UTC (permalink / raw)
To: krzysztof.kozlowski, Conor.Dooley, damien.lemoal, robh+dt,
krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>
>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>
>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>> ---
>>>>>> ---
>>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>> 1 file changed, 6 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>
>>>>>> sram: memory@80000000 {
>>>>>> device_type = "memory";
>>>>>> - compatible = "canaan,k210-sram";
>>>>>> reg = <0x80000000 0x400000>,
>>>>>> <0x80400000 0x200000>,
>>>>>> <0x80600000 0x200000>;
>>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>>> - <&sysclk K210_CLK_AI>;
>>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>>> };
>>>>>
>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>
>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>> the dtbs_check complaints.
>>>>
>>>> I guess the alternative approach of actually documenting the compatible
>>>> would be more palatable?
>>>
>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>> warnings.
>>
>> Hmm looks like that approach contradicts the dt-schema;
>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>
>> @Rob,Krzysztof what is one meant to do here?
>
> Why do you think it contradict bindings? Bindings for memory allow
Because when I tried to write the binding, the memory node complained
about the clock properties etc and referenced the dt-schema (which
for memory@foo nodes has additionalProperties: false.
> additional properties, so you just need to create binding for this one.
> And make it a correct binding, IOW, be sure that these clocks are real etc.
>
> Although usually we had separate bindings (and device drivers) for
> memory controllers, instead of including them in the "memory" node.
I guess changing to that format would probably require some changes on
the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
looks like the clocks etc go in a controller node, which seems like a
"better" way of doing it - but would break existing dts in U-Boot
without changes to handle both methods there.
Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-27 7:06 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-27 7:06 UTC (permalink / raw)
To: krzysztof.kozlowski, Conor.Dooley, damien.lemoal, robh+dt,
krzysztof.kozlowski+dt
Cc: niklas.cassel, alsa-devel, airlied, dri-devel, linux-kernel,
thierry.reding, jee.heng.sia, linux-riscv, sam, masahiroy,
daniel.lezcano, joabreu, geert, Eugeniy.Paltsev, devicetree, aou,
broonie, palmer, paul.walmsley, tglx, dillon.minfei, lgirdwood,
fancer.lancer, linux-spi, vkoul, palmer, dmaengine
On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>
>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>
>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>> ---
>>>>>> ---
>>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>> 1 file changed, 6 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>
>>>>>> sram: memory@80000000 {
>>>>>> device_type = "memory";
>>>>>> - compatible = "canaan,k210-sram";
>>>>>> reg = <0x80000000 0x400000>,
>>>>>> <0x80400000 0x200000>,
>>>>>> <0x80600000 0x200000>;
>>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>>> - <&sysclk K210_CLK_AI>;
>>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>>> };
>>>>>
>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>
>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>> the dtbs_check complaints.
>>>>
>>>> I guess the alternative approach of actually documenting the compatible
>>>> would be more palatable?
>>>
>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>> warnings.
>>
>> Hmm looks like that approach contradicts the dt-schema;
>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>
>> @Rob,Krzysztof what is one meant to do here?
>
> Why do you think it contradict bindings? Bindings for memory allow
Because when I tried to write the binding, the memory node complained
about the clock properties etc and referenced the dt-schema (which
for memory@foo nodes has additionalProperties: false.
> additional properties, so you just need to create binding for this one.
> And make it a correct binding, IOW, be sure that these clocks are real etc.
>
> Although usually we had separate bindings (and device drivers) for
> memory controllers, instead of including them in the "memory" node.
I guess changing to that format would probably require some changes on
the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
looks like the clocks etc go in a controller node, which seems like a
"better" way of doing it - but would break existing dts in U-Boot
without changes to handle both methods there.
Thanks,
Conor.
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-27 7:06 ` Conor.Dooley
(?)
@ 2022-06-27 9:24 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 159+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-27 9:24 UTC (permalink / raw)
To: Conor.Dooley, damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 27/06/2022 09:06, Conor.Dooley@microchip.com wrote:
>
>
> On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
>> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>
>>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>
>>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>>
>>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>>> ---
>>>>>>> ---
>>>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>>> 1 file changed, 6 deletions(-)
>>>>>>>
>>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>>
>>>>>>> sram: memory@80000000 {
>>>>>>> device_type = "memory";
>>>>>>> - compatible = "canaan,k210-sram";
>>>>>>> reg = <0x80000000 0x400000>,
>>>>>>> <0x80400000 0x200000>,
>>>>>>> <0x80600000 0x200000>;
>>>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>>>> - <&sysclk K210_CLK_AI>;
>>>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>>>> };
>>>>>>
>>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>>
>>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>>> the dtbs_check complaints.
>>>>>
>>>>> I guess the alternative approach of actually documenting the compatible
>>>>> would be more palatable?
>>>>
>>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>>> warnings.
>>>
>>> Hmm looks like that approach contradicts the dt-schema;
>>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>>
>>> @Rob,Krzysztof what is one meant to do here?
>>
>> Why do you think it contradict bindings? Bindings for memory allow
>
> Because when I tried to write the binding, the memory node complained
> about the clock properties etc and referenced the dt-schema (which
> for memory@foo nodes has additionalProperties: false.
Ah, I see, I looked at wrong level. Indeed memory node cannot have
anything else.
>
>> additional properties, so you just need to create binding for this one.
>> And make it a correct binding, IOW, be sure that these clocks are real etc.
>>
>> Although usually we had separate bindings (and device drivers) for
>> memory controllers, instead of including them in the "memory" node.
>
> I guess changing to that format would probably require some changes on
> the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
> looks like the clocks etc go in a controller node, which seems like a
> "better" way of doing it -
Yes, because I think memory node is kind of special. It describes the
physical memory layout for the system, not the memory controller or
memory characteristics (like timings).
What U-Boot needs is indeed memory controller node. It's not only
calxeda but also few others using JEDEC LPDDR bindings.
> but would break existing dts in U-Boot
> without changes to handle both methods there.
Yes, that's a bit inconvenient but also a price someone has to pay for
introducing DTS properties without bindings.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-27 9:24 ` Krzysztof Kozlowski
0 siblings, 0 replies; 159+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-27 9:24 UTC (permalink / raw)
To: Conor.Dooley, damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 27/06/2022 09:06, Conor.Dooley@microchip.com wrote:
>
>
> On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
>> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>
>>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>
>>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>>
>>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>>> ---
>>>>>>> ---
>>>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>>> 1 file changed, 6 deletions(-)
>>>>>>>
>>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>>
>>>>>>> sram: memory@80000000 {
>>>>>>> device_type = "memory";
>>>>>>> - compatible = "canaan,k210-sram";
>>>>>>> reg = <0x80000000 0x400000>,
>>>>>>> <0x80400000 0x200000>,
>>>>>>> <0x80600000 0x200000>;
>>>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>>>> - <&sysclk K210_CLK_AI>;
>>>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>>>> };
>>>>>>
>>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>>
>>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>>> the dtbs_check complaints.
>>>>>
>>>>> I guess the alternative approach of actually documenting the compatible
>>>>> would be more palatable?
>>>>
>>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>>> warnings.
>>>
>>> Hmm looks like that approach contradicts the dt-schema;
>>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>>
>>> @Rob,Krzysztof what is one meant to do here?
>>
>> Why do you think it contradict bindings? Bindings for memory allow
>
> Because when I tried to write the binding, the memory node complained
> about the clock properties etc and referenced the dt-schema (which
> for memory@foo nodes has additionalProperties: false.
Ah, I see, I looked at wrong level. Indeed memory node cannot have
anything else.
>
>> additional properties, so you just need to create binding for this one.
>> And make it a correct binding, IOW, be sure that these clocks are real etc.
>>
>> Although usually we had separate bindings (and device drivers) for
>> memory controllers, instead of including them in the "memory" node.
>
> I guess changing to that format would probably require some changes on
> the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
> looks like the clocks etc go in a controller node, which seems like a
> "better" way of doing it -
Yes, because I think memory node is kind of special. It describes the
physical memory layout for the system, not the memory controller or
memory characteristics (like timings).
What U-Boot needs is indeed memory controller node. It's not only
calxeda but also few others using JEDEC LPDDR bindings.
> but would break existing dts in U-Boot
> without changes to handle both methods there.
Yes, that's a bit inconvenient but also a price someone has to pay for
introducing DTS properties without bindings.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-27 9:24 ` Krzysztof Kozlowski
0 siblings, 0 replies; 159+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-27 9:24 UTC (permalink / raw)
To: Conor.Dooley, damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: niklas.cassel, alsa-devel, airlied, dri-devel, linux-kernel,
thierry.reding, jee.heng.sia, linux-riscv, sam, masahiroy,
daniel.lezcano, joabreu, geert, Eugeniy.Paltsev, devicetree, aou,
broonie, palmer, paul.walmsley, tglx, dillon.minfei, lgirdwood,
fancer.lancer, linux-spi, vkoul, palmer, dmaengine
On 27/06/2022 09:06, Conor.Dooley@microchip.com wrote:
>
>
> On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
>> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>
>>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>
>>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>>
>>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>>> ---
>>>>>>> ---
>>>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>>> 1 file changed, 6 deletions(-)
>>>>>>>
>>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>>
>>>>>>> sram: memory@80000000 {
>>>>>>> device_type = "memory";
>>>>>>> - compatible = "canaan,k210-sram";
>>>>>>> reg = <0x80000000 0x400000>,
>>>>>>> <0x80400000 0x200000>,
>>>>>>> <0x80600000 0x200000>;
>>>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>>>> - <&sysclk K210_CLK_AI>;
>>>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>>>> };
>>>>>>
>>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>>
>>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>>> the dtbs_check complaints.
>>>>>
>>>>> I guess the alternative approach of actually documenting the compatible
>>>>> would be more palatable?
>>>>
>>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>>> warnings.
>>>
>>> Hmm looks like that approach contradicts the dt-schema;
>>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>>
>>> @Rob,Krzysztof what is one meant to do here?
>>
>> Why do you think it contradict bindings? Bindings for memory allow
>
> Because when I tried to write the binding, the memory node complained
> about the clock properties etc and referenced the dt-schema (which
> for memory@foo nodes has additionalProperties: false.
Ah, I see, I looked at wrong level. Indeed memory node cannot have
anything else.
>
>> additional properties, so you just need to create binding for this one.
>> And make it a correct binding, IOW, be sure that these clocks are real etc.
>>
>> Although usually we had separate bindings (and device drivers) for
>> memory controllers, instead of including them in the "memory" node.
>
> I guess changing to that format would probably require some changes on
> the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
> looks like the clocks etc go in a controller node, which seems like a
> "better" way of doing it -
Yes, because I think memory node is kind of special. It describes the
physical memory layout for the system, not the memory controller or
memory characteristics (like timings).
What U-Boot needs is indeed memory controller node. It's not only
calxeda but also few others using JEDEC LPDDR bindings.
> but would break existing dts in U-Boot
> without changes to handle both methods there.
Yes, that's a bit inconvenient but also a price someone has to pay for
introducing DTS properties without bindings.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
2022-06-27 9:24 ` Krzysztof Kozlowski
(?)
@ 2022-06-27 11:03 ` Conor.Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-27 11:03 UTC (permalink / raw)
To: krzysztof.kozlowski, damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 27/06/2022 10:24, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 27/06/2022 09:06, Conor.Dooley@microchip.com wrote:
>>
>>
>> On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
>>> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>>>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>>
>>>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>>
>>>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>>>
>>>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>> ---
>>>>>>>> ---
>>>>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>>>> 1 file changed, 6 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>>>
>>>>>>>> sram: memory@80000000 {
>>>>>>>> device_type = "memory";
>>>>>>>> - compatible = "canaan,k210-sram";
>>>>>>>> reg = <0x80000000 0x400000>,
>>>>>>>> <0x80400000 0x200000>,
>>>>>>>> <0x80600000 0x200000>;
>>>>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>>>>> - <&sysclk K210_CLK_AI>;
>>>>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>>>>> };
>>>>>>>
>>>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>>>
>>>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>>>> the dtbs_check complaints.
>>>>>>
>>>>>> I guess the alternative approach of actually documenting the compatible
>>>>>> would be more palatable?
>>>>>
>>>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>>>> warnings.
>>>>
>>>> Hmm looks like that approach contradicts the dt-schema;
>>>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>>>
>>>> @Rob,Krzysztof what is one meant to do here?
>>>
>>> Why do you think it contradict bindings? Bindings for memory allow
>>
>> Because when I tried to write the binding, the memory node complained
>> about the clock properties etc and referenced the dt-schema (which
>> for memory@foo nodes has additionalProperties: false.
>
> Ah, I see, I looked at wrong level. Indeed memory node cannot have
> anything else.
>
>>
>>> additional properties, so you just need to create binding for this one.
>>> And make it a correct binding, IOW, be sure that these clocks are real etc.
>>>
>>> Although usually we had separate bindings (and device drivers) for
>>> memory controllers, instead of including them in the "memory" node.
>>
>> I guess changing to that format would probably require some changes on
>> the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
>> looks like the clocks etc go in a controller node, which seems like a
>> "better" way of doing it -
>
> Yes, because I think memory node is kind of special. It describes the
> physical memory layout for the system, not the memory controller or
> memory characteristics (like timings).
>
> What U-Boot needs is indeed memory controller node. It's not only
> calxeda but also few others using JEDEC LPDDR bindings.
>
>> but would break existing dts in U-Boot
>> without changes to handle both methods there.
>
> Yes, that's a bit inconvenient but also a price someone has to pay for
> introducing DTS properties without bindings.
>
Alright so, I'll make it a memory controller and conjure up a v2.
As always, thanks for your help Krzysztof!
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-27 11:03 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-27 11:03 UTC (permalink / raw)
To: krzysztof.kozlowski, damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: niklas.cassel, alsa-devel, airlied, dri-devel, linux-kernel,
thierry.reding, jee.heng.sia, linux-riscv, sam, masahiroy,
daniel.lezcano, joabreu, geert, Eugeniy.Paltsev, devicetree, aou,
broonie, palmer, paul.walmsley, tglx, dillon.minfei, lgirdwood,
fancer.lancer, linux-spi, vkoul, palmer, dmaengine
On 27/06/2022 10:24, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 27/06/2022 09:06, Conor.Dooley@microchip.com wrote:
>>
>>
>> On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
>>> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>>>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>>
>>>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>>
>>>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>>>
>>>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>> ---
>>>>>>>> ---
>>>>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>>>> 1 file changed, 6 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>>>
>>>>>>>> sram: memory@80000000 {
>>>>>>>> device_type = "memory";
>>>>>>>> - compatible = "canaan,k210-sram";
>>>>>>>> reg = <0x80000000 0x400000>,
>>>>>>>> <0x80400000 0x200000>,
>>>>>>>> <0x80600000 0x200000>;
>>>>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>>>>> - <&sysclk K210_CLK_AI>;
>>>>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>>>>> };
>>>>>>>
>>>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>>>
>>>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>>>> the dtbs_check complaints.
>>>>>>
>>>>>> I guess the alternative approach of actually documenting the compatible
>>>>>> would be more palatable?
>>>>>
>>>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>>>> warnings.
>>>>
>>>> Hmm looks like that approach contradicts the dt-schema;
>>>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>>>
>>>> @Rob,Krzysztof what is one meant to do here?
>>>
>>> Why do you think it contradict bindings? Bindings for memory allow
>>
>> Because when I tried to write the binding, the memory node complained
>> about the clock properties etc and referenced the dt-schema (which
>> for memory@foo nodes has additionalProperties: false.
>
> Ah, I see, I looked at wrong level. Indeed memory node cannot have
> anything else.
>
>>
>>> additional properties, so you just need to create binding for this one.
>>> And make it a correct binding, IOW, be sure that these clocks are real etc.
>>>
>>> Although usually we had separate bindings (and device drivers) for
>>> memory controllers, instead of including them in the "memory" node.
>>
>> I guess changing to that format would probably require some changes on
>> the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
>> looks like the clocks etc go in a controller node, which seems like a
>> "better" way of doing it -
>
> Yes, because I think memory node is kind of special. It describes the
> physical memory layout for the system, not the memory controller or
> memory characteristics (like timings).
>
> What U-Boot needs is indeed memory controller node. It's not only
> calxeda but also few others using JEDEC LPDDR bindings.
>
>> but would break existing dts in U-Boot
>> without changes to handle both methods there.
>
> Yes, that's a bit inconvenient but also a price someone has to pay for
> introducing DTS properties without bindings.
>
Alright so, I'll make it a memory controller and conjure up a v2.
As always, thanks for your help Krzysztof!
^ permalink raw reply [flat|nested] 159+ messages in thread* Re: [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node
@ 2022-06-27 11:03 ` Conor.Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor.Dooley @ 2022-06-27 11:03 UTC (permalink / raw)
To: krzysztof.kozlowski, damien.lemoal, robh+dt, krzysztof.kozlowski+dt
Cc: fancer.lancer, tglx, sam, Eugeniy.Paltsev, daniel.lezcano,
paul.walmsley, aou, masahiroy, geert, lgirdwood, niklas.cassel,
dillon.minfei, jee.heng.sia, thierry.reding, joabreu, dri-devel,
devicetree, airlied, linux-kernel, vkoul, palmer, broonie,
dmaengine, alsa-devel, linux-spi, linux-riscv, palmer, daniel
On 27/06/2022 10:24, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 27/06/2022 09:06, Conor.Dooley@microchip.com wrote:
>>
>>
>> On 27/06/2022 07:55, Krzysztof Kozlowski wrote:
>>> On 21/06/2022 11:49, Conor.Dooley@microchip.com wrote:
>>>> On 20/06/2022 01:25, Damien Le Moal wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>
>>>>> On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
>>>>>> On 20/06/2022 00:38, Damien Le Moal wrote:
>>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>>>>
>>>>>>> On 6/18/22 21:30, Conor Dooley wrote:
>>>>>>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>>
>>>>>>>> The k210 memory node has a compatible string that does not match with
>>>>>>>> any driver or dt-binding & has several non standard properties.
>>>>>>>> Replace the reg names with a comment and delete the rest.
>>>>>>>>
>>>>>>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>>>>>>>> ---
>>>>>>>> ---
>>>>>>>> arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------
>>>>>>>> 1 file changed, 6 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>>> index 44d338514761..287ea6eebe47 100644
>>>>>>>> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>>> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
>>>>>>>> @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
>>>>>>>>
>>>>>>>> sram: memory@80000000 {
>>>>>>>> device_type = "memory";
>>>>>>>> - compatible = "canaan,k210-sram";
>>>>>>>> reg = <0x80000000 0x400000>,
>>>>>>>> <0x80400000 0x200000>,
>>>>>>>> <0x80600000 0x200000>;
>>>>>>>> - reg-names = "sram0", "sram1", "aisram";
>>>>>>>> - clocks = <&sysclk K210_CLK_SRAM0>,
>>>>>>>> - <&sysclk K210_CLK_SRAM1>,
>>>>>>>> - <&sysclk K210_CLK_AI>;
>>>>>>>> - clock-names = "sram0", "sram1", "aisram";
>>>>>>>> };
>>>>>>>
>>>>>>> These are used by u-boot to setup the memory clocks and initialize the
>>>>>>> aisram. Sure the kernel actually does not use this, but to be in sync with
>>>>>>> u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the
>>>>>>> kernel work fine with both u-boot internal DT and the kernel DT.
>>>>>>
>>>>>> Right, but unfortunately that desire alone doesn't do anything about
>>>>>> the dtbs_check complaints.
>>>>>>
>>>>>> I guess the alternative approach of actually documenting the compatible
>>>>>> would be more palatable?
>>>>>
>>>>> Yes, I think so. That would allow keeping the fields without the DTB build
>>>>> warnings.
>>>>
>>>> Hmm looks like that approach contradicts the dt-schema;
>>>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memory.yaml
>>>>
>>>> @Rob,Krzysztof what is one meant to do here?
>>>
>>> Why do you think it contradict bindings? Bindings for memory allow
>>
>> Because when I tried to write the binding, the memory node complained
>> about the clock properties etc and referenced the dt-schema (which
>> for memory@foo nodes has additionalProperties: false.
>
> Ah, I see, I looked at wrong level. Indeed memory node cannot have
> anything else.
>
>>
>>> additional properties, so you just need to create binding for this one.
>>> And make it a correct binding, IOW, be sure that these clocks are real etc.
>>>
>>> Although usually we had separate bindings (and device drivers) for
>>> memory controllers, instead of including them in the "memory" node.
>>
>> I guess changing to that format would probably require some changes on
>> the U-Boot side of things. Taking "calxeda,hb-ddr-ctrl" as an example,
>> looks like the clocks etc go in a controller node, which seems like a
>> "better" way of doing it -
>
> Yes, because I think memory node is kind of special. It describes the
> physical memory layout for the system, not the memory controller or
> memory characteristics (like timings).
>
> What U-Boot needs is indeed memory controller node. It's not only
> calxeda but also few others using JEDEC LPDDR bindings.
>
>> but would break existing dts in U-Boot
>> without changes to handle both methods there.
>
> Yes, that's a bit inconvenient but also a price someone has to pay for
> introducing DTS properties without bindings.
>
Alright so, I'll make it a memory controller and conjure up a v2.
As always, thanks for your help Krzysztof!
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 159+ messages in thread
* [PATCH 08/14] riscv: dts: canaan: add a specific compatible for k210's dma
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The DMAC on the k210 has a non standard interrupt configuration, which
leads to dtbs_check warnings:
k210_generic.dtb: dma-controller@50000000: interrupts: [[27], [28], [29], [30], [31], [32]] is too long
From schema: linux/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
Update the binding to use a custom compatible to avoid the warning.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 287ea6eebe47..314f6da5d7f6 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -135,7 +135,7 @@ gpio0: gpio-controller@38001000 {
};
dmac0: dma-controller@50000000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 08/14] riscv: dts: canaan: add a specific compatible for k210's dma
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
The DMAC on the k210 has a non standard interrupt configuration, which
leads to dtbs_check warnings:
k210_generic.dtb: dma-controller@50000000: interrupts: [[27], [28], [29], [30], [31], [32]] is too long
From schema: linux/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
Update the binding to use a custom compatible to avoid the warning.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 287ea6eebe47..314f6da5d7f6 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -135,7 +135,7 @@ gpio0: gpio-controller@38001000 {
};
dmac0: dma-controller@50000000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 08/14] riscv: dts: canaan: add a specific compatible for k210's dma
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The DMAC on the k210 has a non standard interrupt configuration, which
leads to dtbs_check warnings:
k210_generic.dtb: dma-controller@50000000: interrupts: [[27], [28], [29], [30], [31], [32]] is too long
From schema: linux/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
Update the binding to use a custom compatible to avoid the warning.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 287ea6eebe47..314f6da5d7f6 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -135,7 +135,7 @@ gpio0: gpio-controller@38001000 {
};
dmac0: dma-controller@50000000 {
- compatible = "snps,axi-dma-1.01a";
+ compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread
* [PATCH 09/14] riscv: dts: canaan: add a specific compatible for k210's timers
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The timers on the k210 have non standard interrupt configurations,
which leads to dtbs_check warnings:
k210_generic.dtb: timer@502d0000: interrupts: [[14], [15]] is too long
From schema: Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
Change to using the newly added canaan k210 specific binding to avoid
the warning.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 314f6da5d7f6..ef46ddf3c00c 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -310,7 +310,7 @@ fpioa: pinmux@502b0000 {
};
timer0: timer@502d0000 {
- compatible = "snps,dw-apb-timer";
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
interrupts = <14>, <15>;
clocks = <&sysclk K210_CLK_TIMER0>,
@@ -320,7 +320,7 @@ timer0: timer@502d0000 {
};
timer1: timer@502e0000 {
- compatible = "snps,dw-apb-timer";
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
interrupts = <16>, <17>;
clocks = <&sysclk K210_CLK_TIMER1>,
@@ -330,7 +330,7 @@ timer1: timer@502e0000 {
};
timer2: timer@502f0000 {
- compatible = "snps,dw-apb-timer";
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
interrupts = <18>, <19>;
clocks = <&sysclk K210_CLK_TIMER2>,
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 09/14] riscv: dts: canaan: add a specific compatible for k210's timers
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
The timers on the k210 have non standard interrupt configurations,
which leads to dtbs_check warnings:
k210_generic.dtb: timer@502d0000: interrupts: [[14], [15]] is too long
From schema: Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
Change to using the newly added canaan k210 specific binding to avoid
the warning.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 314f6da5d7f6..ef46ddf3c00c 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -310,7 +310,7 @@ fpioa: pinmux@502b0000 {
};
timer0: timer@502d0000 {
- compatible = "snps,dw-apb-timer";
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
interrupts = <14>, <15>;
clocks = <&sysclk K210_CLK_TIMER0>,
@@ -320,7 +320,7 @@ timer0: timer@502d0000 {
};
timer1: timer@502e0000 {
- compatible = "snps,dw-apb-timer";
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
interrupts = <16>, <17>;
clocks = <&sysclk K210_CLK_TIMER1>,
@@ -330,7 +330,7 @@ timer1: timer@502e0000 {
};
timer2: timer@502f0000 {
- compatible = "snps,dw-apb-timer";
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
interrupts = <18>, <19>;
clocks = <&sysclk K210_CLK_TIMER2>,
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 09/14] riscv: dts: canaan: add a specific compatible for k210's timers
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The timers on the k210 have non standard interrupt configurations,
which leads to dtbs_check warnings:
k210_generic.dtb: timer@502d0000: interrupts: [[14], [15]] is too long
From schema: Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
Change to using the newly added canaan k210 specific binding to avoid
the warning.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 314f6da5d7f6..ef46ddf3c00c 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -310,7 +310,7 @@ fpioa: pinmux@502b0000 {
};
timer0: timer@502d0000 {
- compatible = "snps,dw-apb-timer";
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
interrupts = <14>, <15>;
clocks = <&sysclk K210_CLK_TIMER0>,
@@ -320,7 +320,7 @@ timer0: timer@502d0000 {
};
timer1: timer@502e0000 {
- compatible = "snps,dw-apb-timer";
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
interrupts = <16>, <17>;
clocks = <&sysclk K210_CLK_TIMER1>,
@@ -330,7 +330,7 @@ timer1: timer@502e0000 {
};
timer2: timer@502f0000 {
- compatible = "snps,dw-apb-timer";
+ compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
interrupts = <18>, <19>;
clocks = <&sysclk K210_CLK_TIMER2>,
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread
* [PATCH 10/14] riscv: dts: canaan: fix mmc node names
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The newly-converted-to-dt-schema binding expects the mmc node name to be
'^mmc(@.*)?$' so align the devicetree with the schema.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
index 039b92abf046..40992d495aa8 100644
--- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts
+++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
@@ -142,7 +142,7 @@ &spi1 {
cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
index b9e30df127fe..5e809d0e11fb 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
@@ -189,7 +189,7 @@ &spi1 {
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
index 8d23401b0bbb..4be5ffac6b4a 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
@@ -191,7 +191,7 @@ &spi1 {
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
index 24fd83b43d9d..5c63f79b18ec 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
@@ -199,7 +199,7 @@ &spi1 {
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
index 25341f38292a..59f7eaf74655 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
@@ -164,7 +164,7 @@ &spi1 {
cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 10/14] riscv: dts: canaan: fix mmc node names
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
The newly-converted-to-dt-schema binding expects the mmc node name to be
'^mmc(@.*)?$' so align the devicetree with the schema.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
index 039b92abf046..40992d495aa8 100644
--- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts
+++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
@@ -142,7 +142,7 @@ &spi1 {
cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
index b9e30df127fe..5e809d0e11fb 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
@@ -189,7 +189,7 @@ &spi1 {
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
index 8d23401b0bbb..4be5ffac6b4a 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
@@ -191,7 +191,7 @@ &spi1 {
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
index 24fd83b43d9d..5c63f79b18ec 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
@@ -199,7 +199,7 @@ &spi1 {
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
index 25341f38292a..59f7eaf74655 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
@@ -164,7 +164,7 @@ &spi1 {
cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 10/14] riscv: dts: canaan: fix mmc node names
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The newly-converted-to-dt-schema binding expects the mmc node name to be
'^mmc(@.*)?$' so align the devicetree with the schema.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
index 039b92abf046..40992d495aa8 100644
--- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts
+++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
@@ -142,7 +142,7 @@ &spi1 {
cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
index b9e30df127fe..5e809d0e11fb 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
@@ -189,7 +189,7 @@ &spi1 {
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
index 8d23401b0bbb..4be5ffac6b4a 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
@@ -191,7 +191,7 @@ &spi1 {
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
index 24fd83b43d9d..5c63f79b18ec 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
@@ -199,7 +199,7 @@ &spi1 {
cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
index 25341f38292a..59f7eaf74655 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
@@ -164,7 +164,7 @@ &spi1 {
cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>;
status = "okay";
- slot@0 {
+ mmc@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread
* [PATCH 11/14] riscv: dts: canaan: fix kd233 display spi frequency
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The binding for the ili9341 specifies a const spi-max-frequency of 10
MHz but the kd233 devicetree entry has it listed at 15 Mhz.
Align the devicetree with the value in the binding.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
index 40992d495aa8..4a540158f287 100644
--- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts
+++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
@@ -130,7 +130,7 @@ panel@0 {
compatible = "ilitek,ili9341";
reg = <0>;
dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
- spi-max-frequency = <15000000>;
+ spi-max-frequency = <10000000>;
status = "disabled";
};
};
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 11/14] riscv: dts: canaan: fix kd233 display spi frequency
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
The binding for the ili9341 specifies a const spi-max-frequency of 10
MHz but the kd233 devicetree entry has it listed at 15 Mhz.
Align the devicetree with the value in the binding.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
index 40992d495aa8..4a540158f287 100644
--- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts
+++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
@@ -130,7 +130,7 @@ panel@0 {
compatible = "ilitek,ili9341";
reg = <0>;
dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
- spi-max-frequency = <15000000>;
+ spi-max-frequency = <10000000>;
status = "disabled";
};
};
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 11/14] riscv: dts: canaan: fix kd233 display spi frequency
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The binding for the ili9341 specifies a const spi-max-frequency of 10
MHz but the kd233 devicetree entry has it listed at 15 Mhz.
Align the devicetree with the value in the binding.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
index 40992d495aa8..4a540158f287 100644
--- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts
+++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts
@@ -130,7 +130,7 @@ panel@0 {
compatible = "ilitek,ili9341";
reg = <0>;
dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
- spi-max-frequency = <15000000>;
+ spi-max-frequency = <10000000>;
status = "disabled";
};
};
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread
* [PATCH 12/14] riscv: dts: canaan: use custom compatible for k210 i2s
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The devicetrees using the Canaan k210 all have a sound-dai-cells value
of 1, whereas the standard binding example for the DesignWare i2s and
other use cases suggest 0. Use a k210 specific compatible which
supports this difference.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index ef46ddf3c00c..5eb6b69c1170 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -243,7 +243,7 @@ spi2: spi@50240000 {
};
i2s0: i2s@50250000 {
- compatible = "snps,designware-i2s";
+ compatible = "canaan,k210-i2s", "snps,designware-i2s";
reg = <0x50250000 0x200>;
interrupts = <5>;
clocks = <&sysclk K210_CLK_I2S0>;
@@ -252,7 +252,7 @@ i2s0: i2s@50250000 {
};
i2s1: i2s@50260000 {
- compatible = "snps,designware-i2s";
+ compatible = "canaan,k210-i2s", "snps,designware-i2s";
reg = <0x50260000 0x200>;
interrupts = <6>;
clocks = <&sysclk K210_CLK_I2S1>;
@@ -261,7 +261,7 @@ i2s1: i2s@50260000 {
};
i2s2: i2s@50270000 {
- compatible = "snps,designware-i2s";
+ compatible = "canaan,k210-i2s", "snps,designware-i2s";
reg = <0x50270000 0x200>;
interrupts = <7>;
clocks = <&sysclk K210_CLK_I2S2>;
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 12/14] riscv: dts: canaan: use custom compatible for k210 i2s
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
The devicetrees using the Canaan k210 all have a sound-dai-cells value
of 1, whereas the standard binding example for the DesignWare i2s and
other use cases suggest 0. Use a k210 specific compatible which
supports this difference.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index ef46ddf3c00c..5eb6b69c1170 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -243,7 +243,7 @@ spi2: spi@50240000 {
};
i2s0: i2s@50250000 {
- compatible = "snps,designware-i2s";
+ compatible = "canaan,k210-i2s", "snps,designware-i2s";
reg = <0x50250000 0x200>;
interrupts = <5>;
clocks = <&sysclk K210_CLK_I2S0>;
@@ -252,7 +252,7 @@ i2s0: i2s@50250000 {
};
i2s1: i2s@50260000 {
- compatible = "snps,designware-i2s";
+ compatible = "canaan,k210-i2s", "snps,designware-i2s";
reg = <0x50260000 0x200>;
interrupts = <6>;
clocks = <&sysclk K210_CLK_I2S1>;
@@ -261,7 +261,7 @@ i2s1: i2s@50260000 {
};
i2s2: i2s@50270000 {
- compatible = "snps,designware-i2s";
+ compatible = "canaan,k210-i2s", "snps,designware-i2s";
reg = <0x50270000 0x200>;
interrupts = <7>;
clocks = <&sysclk K210_CLK_I2S2>;
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 12/14] riscv: dts: canaan: use custom compatible for k210 i2s
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
The devicetrees using the Canaan k210 all have a sound-dai-cells value
of 1, whereas the standard binding example for the DesignWare i2s and
other use cases suggest 0. Use a k210 specific compatible which
supports this difference.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index ef46ddf3c00c..5eb6b69c1170 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -243,7 +243,7 @@ spi2: spi@50240000 {
};
i2s0: i2s@50250000 {
- compatible = "snps,designware-i2s";
+ compatible = "canaan,k210-i2s", "snps,designware-i2s";
reg = <0x50250000 0x200>;
interrupts = <5>;
clocks = <&sysclk K210_CLK_I2S0>;
@@ -252,7 +252,7 @@ i2s0: i2s@50250000 {
};
i2s1: i2s@50260000 {
- compatible = "snps,designware-i2s";
+ compatible = "canaan,k210-i2s", "snps,designware-i2s";
reg = <0x50260000 0x200>;
interrupts = <6>;
clocks = <&sysclk K210_CLK_I2S1>;
@@ -261,7 +261,7 @@ i2s1: i2s@50260000 {
};
i2s2: i2s@50270000 {
- compatible = "snps,designware-i2s";
+ compatible = "canaan,k210-i2s", "snps,designware-i2s";
reg = <0x50270000 0x200>;
interrupts = <7>;
clocks = <&sysclk K210_CLK_I2S2>;
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread
* [PATCH 13/14] riscv: dts: canaan: remove spi-max-frequency from controllers
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
spi-max-frequency is a device, not a controller property and should be
removed.
Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 5eb6b69c1170..ec290db4705c 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -413,7 +413,6 @@ spi0: spi@52000000 {
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI0>;
reset-names = "spi";
- spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
};
@@ -429,7 +428,6 @@ spi1: spi@53000000 {
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI1>;
reset-names = "spi";
- spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
};
@@ -445,8 +443,7 @@ spi3: spi@54000000 {
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI3>;
reset-names = "spi";
- /* Could possibly go up to 200 MHz */
- spi-max-frequency = <100000000>;
+
num-cs = <4>;
reg-io-width = <4>;
};
--
2.36.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 13/14] riscv: dts: canaan: remove spi-max-frequency from controllers
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
spi-max-frequency is a device, not a controller property and should be
removed.
Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 5eb6b69c1170..ec290db4705c 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -413,7 +413,6 @@ spi0: spi@52000000 {
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI0>;
reset-names = "spi";
- spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
};
@@ -429,7 +428,6 @@ spi1: spi@53000000 {
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI1>;
reset-names = "spi";
- spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
};
@@ -445,8 +443,7 @@ spi3: spi@54000000 {
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI3>;
reset-names = "spi";
- /* Could possibly go up to 200 MHz */
- spi-max-frequency = <100000000>;
+
num-cs = <4>;
reg-io-width = <4>;
};
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread* [PATCH 13/14] riscv: dts: canaan: remove spi-max-frequency from controllers
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
spi-max-frequency is a device, not a controller property and should be
removed.
Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 5eb6b69c1170..ec290db4705c 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -413,7 +413,6 @@ spi0: spi@52000000 {
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI0>;
reset-names = "spi";
- spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
};
@@ -429,7 +428,6 @@ spi1: spi@53000000 {
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI1>;
reset-names = "spi";
- spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
};
@@ -445,8 +443,7 @@ spi3: spi@54000000 {
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI3>;
reset-names = "spi";
- /* Could possibly go up to 200 MHz */
- spi-max-frequency = <100000000>;
+
num-cs = <4>;
reg-io-width = <4>;
};
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread
* [PATCH 14/14] riscv: dts: canaan: build all devicetress if SOC_CANAAN
2022-06-18 12:30 ` Conor Dooley
(?)
@ 2022-06-18 12:30 ` Conor Dooley
-1 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
Testing & checking the Canaan devicetrees is inconvenient as only the
devicetree corresponding to SOC_CANAAN_K210_DTB_BUILTIN will be built.
Change the Makefile so that all devicetrees are built by default if
SOC_CANAAN but only the one specified by SOC_CANAAN_K210_DTB_BUILTIN
gets built as an object.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
I don't have any Canaan hardware, but I build tested it and the log
looked correct with arch/riscv/boot/dts/canaan/k210_generic.dtb.o
getting successfully built.
---
arch/riscv/boot/dts/canaan/Makefile | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile
index c61b08ac8554..befe4eb7527b 100644
--- a/arch/riscv/boot/dts/canaan/Makefile
+++ b/arch/riscv/boot/dts/canaan/Makefile
@@ -1,3 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))
-obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .o, $(dtb-y))
+dtb-$(CONFIG_SOC_CANAAN) += canaan_kd233.dtb
+dtb-$(CONFIG_SOC_CANAAN) += k210_generic.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_bit.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_dock.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_go.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maixduino.dtb
+
+obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))
--
2.36.1
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^ permalink raw reply related [flat|nested] 159+ messages in thread
* [PATCH 14/14] riscv: dts: canaan: build all devicetress if SOC_CANAAN
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: Thomas Gleixner, Paul Walmsley, Albert Ou, Conor Dooley,
Masahiro Yamada, Damien Le Moal, Geert Uytterhoeven,
Niklas Cassel, Dillon Min, Heng Sia, Jose Abreu, dri-devel,
devicetree, linux-kernel, dmaengine, alsa-devel, linux-spi,
linux-riscv
From: Conor Dooley <conor.dooley@microchip.com>
Testing & checking the Canaan devicetrees is inconvenient as only the
devicetree corresponding to SOC_CANAAN_K210_DTB_BUILTIN will be built.
Change the Makefile so that all devicetrees are built by default if
SOC_CANAAN but only the one specified by SOC_CANAAN_K210_DTB_BUILTIN
gets built as an object.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
I don't have any Canaan hardware, but I build tested it and the log
looked correct with arch/riscv/boot/dts/canaan/k210_generic.dtb.o
getting successfully built.
---
arch/riscv/boot/dts/canaan/Makefile | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile
index c61b08ac8554..befe4eb7527b 100644
--- a/arch/riscv/boot/dts/canaan/Makefile
+++ b/arch/riscv/boot/dts/canaan/Makefile
@@ -1,3 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))
-obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .o, $(dtb-y))
+dtb-$(CONFIG_SOC_CANAAN) += canaan_kd233.dtb
+dtb-$(CONFIG_SOC_CANAAN) += k210_generic.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_bit.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_dock.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_go.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maixduino.dtb
+
+obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread
* [PATCH 14/14] riscv: dts: canaan: build all devicetress if SOC_CANAAN
@ 2022-06-18 12:30 ` Conor Dooley
0 siblings, 0 replies; 159+ messages in thread
From: Conor Dooley @ 2022-06-18 12:30 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Thierry Reding, Sam Ravnborg, Eugeniy Paltsev, Vinod Koul,
Liam Girdwood, Mark Brown, Serge Semin, Daniel Lezcano,
Palmer Dabbelt, Palmer Dabbelt
Cc: linux-riscv, Niklas Cassel, alsa-devel, Albert Ou, devicetree,
Damien Le Moal, linux-kernel, Heng Sia, linux-spi, Conor Dooley,
Jose Abreu, Geert Uytterhoeven, dri-devel, Paul Walmsley,
dmaengine, Thomas Gleixner, Dillon Min, Masahiro Yamada
From: Conor Dooley <conor.dooley@microchip.com>
Testing & checking the Canaan devicetrees is inconvenient as only the
devicetree corresponding to SOC_CANAAN_K210_DTB_BUILTIN will be built.
Change the Makefile so that all devicetrees are built by default if
SOC_CANAAN but only the one specified by SOC_CANAAN_K210_DTB_BUILTIN
gets built as an object.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
I don't have any Canaan hardware, but I build tested it and the log
looked correct with arch/riscv/boot/dts/canaan/k210_generic.dtb.o
getting successfully built.
---
arch/riscv/boot/dts/canaan/Makefile | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile
index c61b08ac8554..befe4eb7527b 100644
--- a/arch/riscv/boot/dts/canaan/Makefile
+++ b/arch/riscv/boot/dts/canaan/Makefile
@@ -1,3 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))
-obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .o, $(dtb-y))
+dtb-$(CONFIG_SOC_CANAAN) += canaan_kd233.dtb
+dtb-$(CONFIG_SOC_CANAAN) += k210_generic.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_bit.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_dock.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_go.dtb
+dtb-$(CONFIG_SOC_CANAAN) += sipeed_maixduino.dtb
+
+obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))
--
2.36.1
^ permalink raw reply related [flat|nested] 159+ messages in thread