* [PATCH V2 00/49] imx: support i.MX93
@ 2022-06-27 3:24 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE Peng Fan (OSS)
` (49 more replies)
0 siblings, 50 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
V2:
Fix issue reported by CI build
- Enlarge SPL_MAX_SIZE for i.MX8MM
- Fix i.MX8ULP break
This patchset is to support i.MX93, during the development, there are some
code cleanup and restructure to make i.MX93 code porting cleaner.
i.MX9 is a new i.MX family and i.MX93 is the first one that we would support
in upstream. It features two Cortex-A55 core, one NPU, one M33 and others.
There are some driver changes that also included to make i.MX93 function well,
lpuart/mmc/network.
mkimage also included, but I have not enable BINMAN which is under development,
will post a follow patchset to switch to binman.
Alice Guo (3):
misc: imx8ulp: move fuse.c from imx8ulp to sentinel
misc: fuse: support to access fuse on i.MX93
misc: fuse: update the code for accessing fuse of i.MX93
Jian Li (1):
imx: imx9: Add function to initialize timer
Peng Fan (31):
spl: imx8mm: enlarge SPL_MAX_SIZE
arm: makefile: cleanup mach-imx usage
imx: simplify dependency with SPL_BOOTROM_SUPPORT
imx: move get_boot_device to common header
imx: move get_boot_device to common file
imx: add USB2_BOOT type
imx: add basic i.MX9 support
fsl_lpuart: add i.MX9 support
gpio: pca953x: support pcal6524
imx: pinctrl: add pinctrl and pinfunc file for i.MX93
imx: imx9: Add CCM and clock API support
mmc: fsl_esdhc_imx: Support i.MX9
spl: Use SPL_FIT_IMAGE_TINY for iMX9
imx: imx9: support romapi
misc: s4mu: Support iMX93 with Sentinel MU
misc: S400_API: New API for FW status and chip info
misc: s400_api: introduce ahab_release_m33_trout
imx: imx9: Get the chip revision through S400 API
imx: imx9: Add MIX power init
imx: imx9: Add M33 release prepare function
imx: imx9: Support booting m33 from Acore
arm: dts: Add i.MX93 SoC DTSi file
imx: imx93_evk: Add basic board support
imx: imx93_evk: Set ARM clock to 1.7Ghz
net: fec_mxc: support i.MX93
net: dwc_eth_qos: fix build break when CLK not enabled
net: dwc_eth_qos: public some functions
net: dwc_eth_qos: move i.MX code out
net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr
board: freescale: imx93_evk: support ethernet
tools: image: support i.MX93
Ye Li (14):
imx: Change USB boot device type
imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device
imx: imx9: disable watchdog
misc: imx: S400_API: Move S400 MU and API to a common place
misc: S400_API: Update release RDC API
imx: imx9: Add TRDC driver for TRDC init
imx: imx9: Add AHAB boot support
misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
imx: imx9: Add gpio registers structure
imx: imx9: Support multiple env storages at runtime
imx: imx9: clock: Add DDR clock support
ddr: imx: Add i.MX9 DDR controller driver
ddr: imx9: enable Performance monitor counter
net: eqos: add function to get phy node and address
arch/arm/Kconfig | 16 +
arch/arm/Makefile | 12 +-
arch/arm/dts/Makefile | 3 +
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 ++
arch/arm/dts/imx93-11x11-evk.dts | 527 ++++++
arch/arm/dts/imx93-pinfunc.h | 625 +++++++
arch/arm/dts/imx93.dtsi | 688 ++++++++
arch/arm/include/asm/arch-imx/cpu.h | 2 +
arch/arm/include/asm/arch-imx8/sys_proto.h | 1 -
arch/arm/include/asm/arch-imx8m/ddr.h | 6 +-
arch/arm/include/asm/arch-imx8m/sys_proto.h | 2 +-
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 5 -
arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 +++
arch/arm/include/asm/arch-imx9/clock.h | 244 +++
arch/arm/include/asm/arch-imx9/ddr.h | 126 ++
arch/arm/include/asm/arch-imx9/gpio.h | 20 +
arch/arm/include/asm/arch-imx9/imx-regs.h | 234 +++
arch/arm/include/asm/arch-imx9/imx93_pins.h | 729 ++++++++
arch/arm/include/asm/arch-imx9/sys_proto.h | 14 +
arch/arm/include/asm/arch-imx9/trdc.h | 19 +
arch/arm/include/asm/arch-mx7/sys_proto.h | 1 -
arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 1 -
arch/arm/include/asm/global_data.h | 5 +-
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
arch/arm/include/asm/mach-imx/iomux-v3.h | 11 +-
.../asm/{arch-imx8ulp => mach-imx}/mu_hal.h | 4 +-
.../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 18 +-
arch/arm/include/asm/mach-imx/sys_proto.h | 11 +-
arch/arm/mach-imx/Kconfig | 3 +-
arch/arm/mach-imx/Makefile | 10 +-
arch/arm/mach-imx/imx8m/soc.c | 47 -
arch/arm/mach-imx/imx8ulp/ahab.c | 345 ++++
arch/arm/mach-imx/imx8ulp/rdc.c | 6 +-
arch/arm/mach-imx/imx8ulp/soc.c | 48 +-
arch/arm/mach-imx/imx9/Kconfig | 34 +
arch/arm/mach-imx/imx9/Makefile | 11 +
arch/arm/mach-imx/imx9/ahab.c | 346 ++++
arch/arm/mach-imx/imx9/clock.c | 844 ++++++++++
arch/arm/mach-imx/imx9/clock_root.c | 438 +++++
arch/arm/mach-imx/imx9/imx_bootaux.c | 133 ++
arch/arm/mach-imx/imx9/lowlevel_init.S | 26 +
arch/arm/mach-imx/imx9/soc.c | 473 ++++++
arch/arm/mach-imx/imx9/trdc.c | 581 +++++++
arch/arm/mach-imx/imx_romapi.c | 60 +
arch/arm/mach-imx/spl.c | 82 +-
board/freescale/common/Makefile | 2 +-
board/freescale/imx8ulp_evk/spl.c | 2 +-
board/freescale/imx93_evk/Kconfig | 21 +
board/freescale/imx93_evk/MAINTAINERS | 6 +
board/freescale/imx93_evk/Makefile | 12 +
board/freescale/imx93_evk/imx93_evk.c | 90 +
board/freescale/imx93_evk/lpddr4x_timing.c | 1486 +++++++++++++++++
board/freescale/imx93_evk/spl.c | 129 ++
common/spl/Kconfig | 3 +-
configs/imx8mm-cl-iot-gate-optee_defconfig | 1 -
configs/imx8mm-cl-iot-gate_defconfig | 1 -
configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
configs/imx8mm-mx8menlo_defconfig | 1 -
configs/imx8mm_beacon_defconfig | 1 -
configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
configs/imx8mm_evk_defconfig | 1 -
configs/imx8mm_venice_defconfig | 1 -
configs/imx93_11x11_evk_defconfig | 117 ++
configs/phycore-imx8mm_defconfig | 1 -
configs/verdin-imx8mm_defconfig | 1 -
drivers/Makefile | 1 +
drivers/ddr/imx/Kconfig | 2 +
drivers/ddr/imx/imx8m/Kconfig | 1 +
drivers/ddr/imx/imx8m/Makefile | 3 +-
drivers/ddr/imx/imx8m/ddr_init.c | 219 +++
drivers/ddr/imx/imx9/Kconfig | 27 +
drivers/ddr/imx/imx9/Makefile | 10 +
drivers/ddr/imx/imx9/ddr_init.c | 489 ++++++
drivers/ddr/imx/phy/Kconfig | 4 +
drivers/ddr/imx/phy/Makefile | 9 +
drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c | 0
drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c | 1 -
drivers/ddr/imx/phy/ddrphy_utils.c | 169 ++
drivers/ddr/imx/{imx8m => phy}/helper.c | 45 +-
drivers/gpio/pca953x_gpio.c | 4 +
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 2 +-
drivers/misc/{imx8ulp => sentinel}/Makefile | 2 +-
drivers/misc/{imx8ulp => sentinel}/fuse.c | 96 +-
drivers/misc/{imx8ulp => sentinel}/s400_api.c | 149 +-
.../{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} | 11 +-
drivers/mmc/Kconfig | 2 +-
drivers/net/Kconfig | 2 +-
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 406 +----
drivers/net/dwc_eth_qos.h | 284 ++++
drivers/net/dwc_eth_qos_imx.c | 131 ++
drivers/net/fec_mxc.c | 4 +-
drivers/pinctrl/nxp/Kconfig | 13 +
drivers/pinctrl/nxp/Makefile | 1 +
drivers/pinctrl/nxp/pinctrl-imx93.c | 37 +
include/configs/imx93_evk.h | 149 ++
include/dt-bindings/clock/imx93-clock.h | 203 +++
include/dt-bindings/power/imx93-power.h | 12 +
include/fsl_lpuart.h | 2 +-
include/imx8image.h | 15 +-
include/imx_sip.h | 1 +
tools/imx8image.c | 79 +-
104 files changed, 11072 insertions(+), 635 deletions(-)
create mode 100644 arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx93-11x11-evk.dts
create mode 100644 arch/arm/dts/imx93-pinfunc.h
create mode 100644 arch/arm/dts/imx93.dtsi
create mode 100644 arch/arm/include/asm/arch-imx9/ccm_regs.h
create mode 100644 arch/arm/include/asm/arch-imx9/clock.h
create mode 100644 arch/arm/include/asm/arch-imx9/ddr.h
create mode 100644 arch/arm/include/asm/arch-imx9/gpio.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx93_pins.h
create mode 100644 arch/arm/include/asm/arch-imx9/sys_proto.h
create mode 100644 arch/arm/include/asm/arch-imx9/trdc.h
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/mu_hal.h (79%)
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/s400_api.h (75%)
create mode 100644 arch/arm/mach-imx/imx8ulp/ahab.c
create mode 100644 arch/arm/mach-imx/imx9/Kconfig
create mode 100644 arch/arm/mach-imx/imx9/Makefile
create mode 100644 arch/arm/mach-imx/imx9/ahab.c
create mode 100644 arch/arm/mach-imx/imx9/clock.c
create mode 100644 arch/arm/mach-imx/imx9/clock_root.c
create mode 100644 arch/arm/mach-imx/imx9/imx_bootaux.c
create mode 100644 arch/arm/mach-imx/imx9/lowlevel_init.S
create mode 100644 arch/arm/mach-imx/imx9/soc.c
create mode 100644 arch/arm/mach-imx/imx9/trdc.c
create mode 100644 arch/arm/mach-imx/imx_romapi.c
create mode 100644 board/freescale/imx93_evk/Kconfig
create mode 100644 board/freescale/imx93_evk/MAINTAINERS
create mode 100644 board/freescale/imx93_evk/Makefile
create mode 100644 board/freescale/imx93_evk/imx93_evk.c
create mode 100644 board/freescale/imx93_evk/lpddr4x_timing.c
create mode 100644 board/freescale/imx93_evk/spl.c
create mode 100644 configs/imx93_11x11_evk_defconfig
create mode 100644 drivers/ddr/imx/imx9/Kconfig
create mode 100644 drivers/ddr/imx/imx9/Makefile
create mode 100644 drivers/ddr/imx/imx9/ddr_init.c
create mode 100644 drivers/ddr/imx/phy/Kconfig
create mode 100644 drivers/ddr/imx/phy/Makefile
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c (100%)
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c (98%)
create mode 100644 drivers/ddr/imx/phy/ddrphy_utils.c
rename drivers/ddr/imx/{imx8m => phy}/helper.c (79%)
rename drivers/misc/{imx8ulp => sentinel}/Makefile (67%)
rename drivers/misc/{imx8ulp => sentinel}/fuse.c (69%)
rename drivers/misc/{imx8ulp => sentinel}/s400_api.c (69%)
rename drivers/misc/{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} (94%)
create mode 100644 drivers/net/dwc_eth_qos.h
create mode 100644 drivers/net/dwc_eth_qos_imx.c
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx93.c
create mode 100644 include/configs/imx93_evk.h
create mode 100644 include/dt-bindings/clock/imx93-clock.h
create mode 100644 include/dt-bindings/power/imx93-power.h
--
2.36.0
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-29 10:09 ` Frieder Schrempf
2022-06-27 3:24 ` [PATCH V2 02/49] arm: makefile: cleanup mach-imx usage Peng Fan (OSS)
` (48 subsequent siblings)
49 siblings, 1 reply; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Ying-Chun Liu (PaulLiu),
Jagan Teki, Matteo Lisi, Marek Vasut, Olaf Mandel, Adam Ford,
Peng Fan, Tim Harvey, Teresa Remmet, Marcel Ziswiler
Cc: u-boot
From: Peng Fan <peng.fan@nxp.com>
The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
set to 0x7E1000.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
common/spl/Kconfig | 1 +
configs/imx8mm-cl-iot-gate-optee_defconfig | 1 -
configs/imx8mm-cl-iot-gate_defconfig | 1 -
configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
configs/imx8mm-mx8menlo_defconfig | 1 -
configs/imx8mm_beacon_defconfig | 1 -
configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
configs/imx8mm_evk_defconfig | 1 -
configs/imx8mm_venice_defconfig | 1 -
configs/phycore-imx8mm_defconfig | 1 -
configs/verdin-imx8mm_defconfig | 1 -
12 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2ad2351c6eb..848237c1e85 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -82,6 +82,7 @@ config SPL_MAX_SIZE
default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x20000 && !MACH_SUN50I_H616
default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
+ default 0x27000 if IMX8MM && SPL_TEXT_BASE = 0x7E1000
default 0x0
help
Maximum size of the SPL image (text, data, rodata, and linker lists
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig
index 80055912096..a02010621ea 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
index dae7ddc20e0..f05ac98326c 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -25,7 +25,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index 69ebc6fa325..7d08b244f2c 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index a3c142feb28..acc5d34659b 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig
index ec672f8764e..2a6f3b7c412 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -34,7 +34,6 @@ CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index bf2b6486347..fd21f9f6db8 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -25,7 +25,6 @@ CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 399b388460f..1fae936bda5 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -41,7 +41,6 @@ CONFIG_CONSOLE_MUX=y
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 00af724bbaa..24bb136c7ad 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index 190209d6325..2f7857bdfb6 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -31,7 +31,6 @@ CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="gsc wd-disable"
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 0316d45caeb..3a169692735 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -26,7 +26,6 @@ CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="oftree"
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index 34afdc57911..8c5274d33f1 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -32,7 +32,6 @@ CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
CONFIG_SPL_BSS_MAX_SIZE=0x2000
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 02/49] arm: makefile: cleanup mach-imx usage
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 03/49] imx: Change USB boot device type Peng Fan (OSS)
` (47 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
All the SoCs use mach-imx has CONFIG_MACH_IMX selected, so
the macro could be the gate to build arch/arm/mach-imx to simplify
the rules.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/Makefile | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64c58f4c4a3..a69cb1f610f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -96,6 +96,8 @@ machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp
machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5
+machine-$(CONFIG_MACH_IMX) += imx
+
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs))
@@ -114,16 +116,6 @@ libs-y += arch/arm/cpu/$(CPU)/
libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
-ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
-libs-y += arch/arm/mach-imx/
-endif
-else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610))
-libs-y += arch/arm/mach-imx/
-endif
-endif
-
ifneq (,$(filter $(SOC), kirkwood))
libs-y += arch/arm/mach-mvebu/
endif
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 03/49] imx: Change USB boot device type
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 02/49] arm: makefile: cleanup mach-imx usage Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 04/49] imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device Peng Fan (OSS)
` (46 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
The SPL SDP is configured as BOOT_DEVICE_BOARD, so when booting from
USB, change its type to BOOT_DEVICE_BOARD, so we can use SDP.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 64ca2967721..e89e2277ef7 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -177,7 +177,7 @@ u32 spl_boot_device(void)
case QSPI_BOOT:
return BOOT_DEVICE_NOR;
case USB_BOOT:
- return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_BOARD;
default:
return BOOT_DEVICE_NONE;
}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 04/49] imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (2 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 03/49] imx: Change USB boot device type Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 05/49] imx: simplify dependency with SPL_BOOTROM_SUPPORT Peng Fan (OSS)
` (45 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Ye Li, Peng Fan
From: Ye Li <ye.li@nxp.com>
Move the default mapping of spl_boot_device to weak function of
spl_board_boot_device. So that every board of iMX7/8/8M can overwrite
this function to implement specific mapping.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/spl.c | 80 ++++++++++++++++++++---------------------
1 file changed, 38 insertions(+), 42 deletions(-)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index e89e2277ef7..e5ad993b8d9 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -25,7 +25,43 @@ DECLARE_GLOBAL_DATA_PTR;
__weak int spl_board_boot_device(enum boot_device boot_dev_spl)
{
- return 0;
+ switch (boot_dev_spl) {
+#if defined(CONFIG_MX7)
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8)
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ return BOOT_DEVICE_MMC2_2;
+ case SD3_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case FLEXSPI_BOOT:
+ return BOOT_DEVICE_SPI;
+#elif defined(CONFIG_IMX8M)
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC2;
+#endif
+ case NAND_BOOT:
+ return BOOT_DEVICE_NAND;
+ case SPI_NOR_BOOT:
+ return BOOT_DEVICE_SPI;
+ case QSPI_BOOT:
+ return BOOT_DEVICE_NOR;
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
}
#if defined(CONFIG_MX6)
@@ -140,47 +176,7 @@ u32 spl_boot_device(void)
enum boot_device boot_device_spl = get_boot_device();
- if (IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) ||
- IS_ENABLED(CONFIG_IMX8MP))
- return spl_board_boot_device(boot_device_spl);
-
- switch (boot_device_spl) {
-#if defined(CONFIG_MX7)
- case SD1_BOOT:
- case MMC1_BOOT:
- case SD2_BOOT:
- case MMC2_BOOT:
- case SD3_BOOT:
- case MMC3_BOOT:
- return BOOT_DEVICE_MMC1;
-#elif defined(CONFIG_IMX8)
- case MMC1_BOOT:
- return BOOT_DEVICE_MMC1;
- case SD2_BOOT:
- return BOOT_DEVICE_MMC2_2;
- case SD3_BOOT:
- return BOOT_DEVICE_MMC1;
- case FLEXSPI_BOOT:
- return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_IMX8M)
- case SD1_BOOT:
- case MMC1_BOOT:
- return BOOT_DEVICE_MMC1;
- case SD2_BOOT:
- case MMC2_BOOT:
- return BOOT_DEVICE_MMC2;
-#endif
- case NAND_BOOT:
- return BOOT_DEVICE_NAND;
- case SPI_NOR_BOOT:
- return BOOT_DEVICE_SPI;
- case QSPI_BOOT:
- return BOOT_DEVICE_NOR;
- case USB_BOOT:
- return BOOT_DEVICE_BOARD;
- default:
- return BOOT_DEVICE_NONE;
- }
+ return spl_board_boot_device(boot_device_spl);
}
#endif /* CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 05/49] imx: simplify dependency with SPL_BOOTROM_SUPPORT
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (3 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 04/49] imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 06/49] imx: move get_boot_device to common header Peng Fan (OSS)
` (44 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
For SoCs support ROM API, CONFIG_SPL_BOOTROM_SUPPORT is needed,
so use this macro to guard the code to avoid extend the list.
And drop the guard with structure definition, there is no need.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/sys_proto.h | 2 --
arch/arm/mach-imx/Kconfig | 3 ++-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index fdbbfb169cb..fc5e5c66aad 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -146,7 +146,6 @@ struct rproc_att {
u32 size; /* size of reg range */
};
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP)
struct rom_api {
u16 ver;
u16 tag;
@@ -178,7 +177,6 @@ enum boot_dev_type_e {
#define ROM_API_OKAY 0xF0
extern struct rom_api *g_rom_api;
-#endif
/* For i.MX ULP */
#define BT0CFG_LPBOOT_MASK 0x1
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ad0fb365023..5e9c4d9b355 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -166,7 +166,8 @@ config DDRMC_VF610_CALIBRATION
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
- depends on IMX8MN || IMX8MP || IMX8ULP
+ depends on SPL_BOOTROM_SUPPORT
+ default 0
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 06/49] imx: move get_boot_device to common header
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (4 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 05/49] imx: simplify dependency with SPL_BOOTROM_SUPPORT Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 07/49] imx: move get_boot_device to common file Peng Fan (OSS)
` (43 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Most i.MX implements get_boot_device, move it to common header to
simplify code
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8/sys_proto.h | 1 -
arch/arm/include/asm/arch-imx8m/sys_proto.h | 1 -
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 -
arch/arm/include/asm/arch-mx7/sys_proto.h | 1 -
arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 1 -
arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++
6 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h
index 6f1fc8f999d..d38f606e07e 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -23,7 +23,6 @@ struct pass_over_info_t {
extern unsigned long boot_pointer[];
void build_info(void);
-enum boot_device get_boot_device(void);
int print_bootinfo(void);
int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
int imx8_power_domain_lookup_name(const char *name,
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index d328542ece2..f8854e77128 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -12,6 +12,5 @@ void set_wdog_reset(struct wdog_regs *wdog);
void enable_tzc380(void);
void restore_boot_params(void);
extern unsigned long rom_pointer[];
-enum boot_device get_boot_device(void);
bool is_usb_boot(void);
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 5f030eaa0ad..05859dfc2aa 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -15,7 +15,6 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
-enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h
index e46a02198d6..634736cc09c 100644
--- a/arch/arm/include/asm/arch-mx7/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7/sys_proto.h
@@ -8,6 +8,5 @@
#include <asm/mach-imx/sys_proto.h>
void set_wdog_reset(struct wdog_regs *wdog);
-enum boot_device get_boot_device(void);
#endif /* __SYS_PROTO_IMX7_ */
diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
index 0daa922fad9..7adf4720fec 100644
--- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
@@ -8,5 +8,4 @@
#include <asm/mach-imx/sys_proto.h>
-enum boot_device get_boot_device(void);
#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index fc5e5c66aad..cd69384d8ef 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -243,4 +243,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
void enable_ca7_smp(void);
#endif
+enum boot_device get_boot_device(void);
+
#endif
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 07/49] imx: move get_boot_device to common file
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (5 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 06/49] imx: move get_boot_device to common header Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 08/49] imx: add USB2_BOOT type Peng Fan (OSS)
` (42 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
i.MX8MN/P/ULP supports ROM API, they have almost same get_boot_device
implementation, so move to a common file. And when support i.MX9,
no need to include the other function copy.
Since sys_proto.h is included in imx_romapi.c, there will be build
warning for i.MX8M because wdog_regs not defined, so include imx-regs.h
in i.MX8M sys_proro.h
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8m/sys_proto.h | 1 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/imx8m/soc.c | 47 ----------------
arch/arm/mach-imx/imx8ulp/soc.c | 44 ---------------
arch/arm/mach-imx/imx_romapi.c | 60 +++++++++++++++++++++
5 files changed, 62 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/mach-imx/imx_romapi.c
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index f8854e77128..55b46afaf78 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -7,6 +7,7 @@
#define __ARCH_NMX8M_SYS_PROTO_H
#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch/imx-regs.h>
void set_wdog_reset(struct wdog_regs *wdog);
void enable_tzc380(void);
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index aa0b6447f14..c5be63dfe4f 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -242,4 +242,5 @@ obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
obj-$(CONFIG_ARCH_IMXRT) += imxrt/
+obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP) += imx_romapi.o
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 59335356b57..d2a856f5410 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -599,53 +599,6 @@ int arch_cpu_init(void)
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
struct rom_api *g_rom_api = (struct rom_api *)0x980;
-
-enum boot_device get_boot_device(void)
-{
- volatile gd_t *pgd = gd;
- int ret;
- u32 boot;
- u16 boot_type;
- u8 boot_instance;
- enum boot_device boot_dev = SD1_BOOT;
-
- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
- ((uintptr_t)&boot) ^ QUERY_BT_DEV);
- set_gd(pgd);
-
- if (ret != ROM_API_OKAY) {
- puts("ROMAPI: failure at query_boot_info\n");
- return -1;
- }
-
- boot_type = boot >> 16;
- boot_instance = (boot >> 8) & 0xff;
-
- switch (boot_type) {
- case BT_DEV_TYPE_SD:
- boot_dev = boot_instance + SD1_BOOT;
- break;
- case BT_DEV_TYPE_MMC:
- boot_dev = boot_instance + MMC1_BOOT;
- break;
- case BT_DEV_TYPE_NAND:
- boot_dev = NAND_BOOT;
- break;
- case BT_DEV_TYPE_FLEXSPINOR:
- boot_dev = QSPI_BOOT;
- break;
- case BT_DEV_TYPE_SPI_NOR:
- boot_dev = SPI_NOR_BOOT;
- break;
- case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
- break;
- default:
- break;
- }
-
- return boot_dev;
-}
#endif
#if defined(CONFIG_IMX8M)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 35020c9714d..529fda4594e 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -34,50 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
struct rom_api *g_rom_api = (struct rom_api *)0x1980;
-enum boot_device get_boot_device(void)
-{
- volatile gd_t *pgd = gd;
- int ret;
- u32 boot;
- u16 boot_type;
- u8 boot_instance;
- enum boot_device boot_dev = SD1_BOOT;
-
- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
- ((uintptr_t)&boot) ^ QUERY_BT_DEV);
- set_gd(pgd);
-
- if (ret != ROM_API_OKAY) {
- puts("ROMAPI: failure at query_boot_info\n");
- return -1;
- }
-
- boot_type = boot >> 16;
- boot_instance = (boot >> 8) & 0xff;
-
- switch (boot_type) {
- case BT_DEV_TYPE_SD:
- boot_dev = boot_instance + SD1_BOOT;
- break;
- case BT_DEV_TYPE_MMC:
- boot_dev = boot_instance + MMC1_BOOT;
- break;
- case BT_DEV_TYPE_NAND:
- boot_dev = NAND_BOOT;
- break;
- case BT_DEV_TYPE_FLEXSPINOR:
- boot_dev = QSPI_BOOT;
- break;
- case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
- break;
- default:
- break;
- }
-
- return boot_dev;
-}
-
bool is_usb_boot(void)
{
return get_boot_device() == USB_BOOT;
diff --git a/arch/arm/mach-imx/imx_romapi.c b/arch/arm/mach-imx/imx_romapi.c
new file mode 100644
index 00000000000..3b2cc6935dc
--- /dev/null
+++ b/arch/arm/mach-imx/imx_romapi.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/global_data.h>
+#include <env.h>
+#include <env_internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct rom_api *g_rom_api;
+
+enum boot_device get_boot_device(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+ enum boot_device boot_dev = SD1_BOOT;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+ ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ set_gd(pgd);
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return -1;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ switch (boot_type) {
+ case BT_DEV_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BT_DEV_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BT_DEV_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BT_DEV_TYPE_FLEXSPINOR:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BT_DEV_TYPE_USB:
+ boot_dev = USB_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 08/49] imx: add USB2_BOOT type
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (6 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 07/49] imx: move get_boot_device to common file Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 09/49] imx: add basic i.MX9 support Peng Fan (OSS)
` (41 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add USB2_BOOT type for i.MX8ULP and i.MX9
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
arch/arm/mach-imx/imx_romapi.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h b/arch/arm/include/asm/mach-imx/boot_mode.h
index 6dc58559680..a568c443722 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -29,6 +29,7 @@ enum boot_device {
QSPI_BOOT,
FLEXSPI_BOOT,
USB_BOOT,
+ USB2_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
};
diff --git a/arch/arm/mach-imx/imx_romapi.c b/arch/arm/mach-imx/imx_romapi.c
index 3b2cc6935dc..0f94091fc53 100644
--- a/arch/arm/mach-imx/imx_romapi.c
+++ b/arch/arm/mach-imx/imx_romapi.c
@@ -50,7 +50,7 @@ enum boot_device get_boot_device(void)
boot_dev = QSPI_BOOT;
break;
case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
+ boot_dev = boot_instance + USB_BOOT;
break;
default:
break;
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 09/49] imx: add basic i.MX9 support
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (7 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 08/49] imx: add USB2_BOOT type Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 10/49] fsl_lpuart: add " Peng Fan (OSS)
` (40 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Bharat Gooty, Rayagonda Kokatanur,
NXP i.MX U-Boot Team
Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add i.MX9 Kconfig and basic files for the new SoC
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/Kconfig | 11 +
arch/arm/include/asm/arch-imx/cpu.h | 2 +
arch/arm/include/asm/arch-imx9/clock.h | 0
arch/arm/include/asm/arch-imx9/gpio.h | 0
arch/arm/include/asm/arch-imx9/imx-regs.h | 13 +
arch/arm/include/asm/arch-imx9/imx93_pins.h | 729 ++++++++++++++++++++
arch/arm/include/asm/arch-imx9/sys_proto.h | 11 +
arch/arm/include/asm/mach-imx/iomux-v3.h | 11 +-
arch/arm/include/asm/mach-imx/sys_proto.h | 3 +
arch/arm/mach-imx/Makefile | 11 +-
arch/arm/mach-imx/imx9/Kconfig | 17 +
arch/arm/mach-imx/imx9/Makefile | 6 +
arch/arm/mach-imx/imx9/clock.c | 27 +
arch/arm/mach-imx/imx9/lowlevel_init.S | 26 +
arch/arm/mach-imx/imx9/soc.c | 127 ++++
arch/arm/mach-imx/spl.c | 2 +-
16 files changed, 991 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx9/clock.h
create mode 100644 arch/arm/include/asm/arch-imx9/gpio.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx93_pins.h
create mode 100644 arch/arm/include/asm/arch-imx9/sys_proto.h
create mode 100644 arch/arm/mach-imx/imx9/Kconfig
create mode 100644 arch/arm/mach-imx/imx9/Makefile
create mode 100644 arch/arm/mach-imx/imx9/clock.c
create mode 100644 arch/arm/mach-imx/imx9/lowlevel_init.S
create mode 100644 arch/arm/mach-imx/imx9/soc.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dab785efad5..12ec661ac3b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -925,6 +925,15 @@ config ARCH_IMX8ULP
imply CMD_DM
imply DM_EVENT
+config ARCH_IMX9
+ bool "NXP i.MX9 platform"
+ select ARM64
+ select DM
+ select MACH_IMX
+ select SUPPORT_SPL
+ imply CMD_DM
+ imply DM_EVENT
+
config ARCH_IMXRT
bool "NXP i.MXRT platform"
select CPU_V7M
@@ -2251,6 +2260,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig"
source "arch/arm/mach-imx/imx8ulp/Kconfig"
+source "arch/arm/mach-imx/imx9/Kconfig"
+
source "arch/arm/mach-imx/imxrt/Kconfig"
source "arch/arm/mach-imx/mxs/Kconfig"
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 4f63803765e..d54e6e63352 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -59,6 +59,7 @@
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
+#define MXC_CPU_IMX93 0xC1 /* dummy ID */
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
@@ -66,6 +67,7 @@
#define MXC_SOC_IMX8 0x90 /* dummy */
#define MXC_SOC_IMXRT 0xB0 /* dummy */
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
+#define MXC_SOC_IMX9 0xC0 /* dummy */
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
new file mode 100644
index 00000000000..2adbdadf03c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_REGS_H__
+#define __ASM_ARCH_IMX9_REGS_H__
+
+#define ARCH_MXC
+
+#define IOMUXC_BASE_ADDR 0x443C0000UL
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h b/arch/arm/include/asm/arch-imx9/imx93_pins.h
new file mode 100644
index 00000000000..f13aef5619c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h
@@ -0,0 +1,729 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX93_PINS_H__
+#define __ASM_ARCH_IMX93_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+ MX93_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x1B0, 0x0000, 0, 0x3D8, 0, 0),
+ MX93_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x1B0, 0x0000, 1, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x1B0, 0x0000, 3, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x1B0, 0x0000, 4, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDI__GPIO3_IO28 = IOMUX_PAD(0x1B0, 0x0000, 5, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDI__LPUART5_RX = IOMUX_PAD(0x1B0, 0x0000, 6, 0x430, 0, 0),
+
+ MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS = IOMUX_PAD(0x1B4, 0x0004, 0, 0x3DC, 0, 0),
+ MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 = IOMUX_PAD(0x1B4, 0x0004, 4, 0x0000, 0, 0),
+ MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 = IOMUX_PAD(0x1B4, 0x0004, 5, 0x0000, 0, 0),
+ MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B = IOMUX_PAD(0x1B4, 0x0004, 6, 0x0000, 0, 0),
+
+ MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK = IOMUX_PAD(0x1B8, 0x0008, 0, 0x3D4, 0, 0),
+ MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 = IOMUX_PAD(0x1B8, 0x0008, 4, 0x0000, 0, 0),
+ MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 = IOMUX_PAD(0x1B8, 0x0008, 5, 0x0000, 0, 0),
+ MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B = IOMUX_PAD(0x1B8, 0x0008, 6, 0x42C, 0, 0),
+
+ MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO = IOMUX_PAD(0x1BC, 0x000C, 0, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT = IOMUX_PAD(0x1BC, 0x000C, 1, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX = IOMUX_PAD(0x1BC, 0x000C, 3, 0x364, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 = IOMUX_PAD(0x1BC, 0x000C, 4, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 = IOMUX_PAD(0x1BC, 0x000C, 5, 0x0000, 0, 0),
+ MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX = IOMUX_PAD(0x1BC, 0x000C, 6, 0x434, 0, 0),
+
+ MX93_PAD_GPIO_IO00__GPIO2_IO00 = IOMUX_PAD(0x1C0, 0x0010, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO00__LPI2C3_SDA = IOMUX_PAD(0x1C0, 0x0010, 1, 0x3E4, 0, 0),
+ MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK = IOMUX_PAD(0x1C0, 0x0010, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK = IOMUX_PAD(0x1C0, 0x0010, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO00__LPSPI6_PCS0 = IOMUX_PAD(0x1C0, 0x0010, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO00__LPUART5_TX = IOMUX_PAD(0x1C0, 0x0010, 5, 0x434, 1, 0),
+ MX93_PAD_GPIO_IO00__LPI2C5_SDA = IOMUX_PAD(0x1C0, 0x0010, 6, 0x3EC, 0, 0),
+ MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x1C0, 0x0010, 7, 0x36C, 0, 0),
+
+ MX93_PAD_GPIO_IO01__GPIO2_IO01 = IOMUX_PAD(0x1C4, 0x0014, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO01__LPI2C3_SCL = IOMUX_PAD(0x1C4, 0x0014, 1, 0x3E0, 0, 0),
+ MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 = IOMUX_PAD(0x1C4, 0x0014, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE = IOMUX_PAD(0x1C4, 0x0014, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO01__LPSPI6_SIN = IOMUX_PAD(0x1C4, 0x0014, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO01__LPUART5_RX = IOMUX_PAD(0x1C4, 0x0014, 5, 0x430, 1, 0),
+ MX93_PAD_GPIO_IO01__LPI2C5_SCL = IOMUX_PAD(0x1C4, 0x0014, 6, 0x3E8, 0, 0),
+ MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x1C4, 0x0014, 7, 0x370, 0, 0),
+
+ MX93_PAD_GPIO_IO02__GPIO2_IO02 = IOMUX_PAD(0x1C8, 0x0018, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__LPI2C4_SDA = IOMUX_PAD(0x1C8, 0x0018, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC = IOMUX_PAD(0x1C8, 0x0018, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC = IOMUX_PAD(0x1C8, 0x0018, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__LPSPI6_SOUT = IOMUX_PAD(0x1C8, 0x0018, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO02__LPUART5_CTS_B = IOMUX_PAD(0x1C8, 0x0018, 5, 0x42C, 1, 0),
+ MX93_PAD_GPIO_IO02__LPI2C6_SDA = IOMUX_PAD(0x1C8, 0x0018, 6, 0x3F4, 0, 0),
+ MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x1C8, 0x0018, 7, 0x374, 0, 0),
+
+ MX93_PAD_GPIO_IO03__GPIO2_IO03 = IOMUX_PAD(0x1CC, 0x001C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__LPI2C4_SCL = IOMUX_PAD(0x1CC, 0x001C, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC = IOMUX_PAD(0x1CC, 0x001C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC = IOMUX_PAD(0x1CC, 0x001C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__LPSPI6_SCK = IOMUX_PAD(0x1CC, 0x001C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__LPUART5_RTS_B = IOMUX_PAD(0x1CC, 0x001C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO03__LPI2C6_SCL = IOMUX_PAD(0x1CC, 0x001C, 6, 0x3F0, 0, 0),
+ MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x1CC, 0x001C, 7, 0x378, 0, 0),
+
+ MX93_PAD_GPIO_IO04__GPIO2_IO04 = IOMUX_PAD(0x1D0, 0x0020, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__TPM3_CH0 = IOMUX_PAD(0x1D0, 0x0020, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__PDM_CLK = IOMUX_PAD(0x1D0, 0x0020, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 = IOMUX_PAD(0x1D0, 0x0020, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__LPSPI7_PCS0 = IOMUX_PAD(0x1D0, 0x0020, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__LPUART6_TX = IOMUX_PAD(0x1D0, 0x0020, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO04__LPI2C6_SDA = IOMUX_PAD(0x1D0, 0x0020, 6, 0x3F4, 1, 0),
+ MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x1D0, 0x0020, 7, 0x37C, 0, 0),
+
+ MX93_PAD_GPIO_IO05__GPIO2_IO05 = IOMUX_PAD(0x1D4, 0x0024, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__TPM4_CH0 = IOMUX_PAD(0x1D4, 0x0024, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 = IOMUX_PAD(0x1D4, 0x0024, 2, 0x438, 0, 0),
+ MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 = IOMUX_PAD(0x1D4, 0x0024, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__LPSPI7_SIN = IOMUX_PAD(0x1D4, 0x0024, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__LPUART6_RX = IOMUX_PAD(0x1D4, 0x0024, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO05__LPI2C6_SCL = IOMUX_PAD(0x1D4, 0x0024, 6, 0x3F0, 1, 0),
+ MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x1D4, 0x0024, 7, 0x380, 0, 0),
+
+ MX93_PAD_GPIO_IO06__GPIO2_IO06 = IOMUX_PAD(0x1D8, 0x0028, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__TPM5_CH0 = IOMUX_PAD(0x1D8, 0x0028, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 = IOMUX_PAD(0x1D8, 0x0028, 2, 0x43C, 0, 0),
+ MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 = IOMUX_PAD(0x1D8, 0x0028, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__LPSPI7_SOUT = IOMUX_PAD(0x1D8, 0x0028, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__LPUART6_CTS_B = IOMUX_PAD(0x1D8, 0x0028, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO06__LPI2C7_SDA = IOMUX_PAD(0x1D8, 0x0028, 6, 0x3FC, 0, 0),
+ MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x1D8, 0x0028, 7, 0x384, 0, 0),
+
+ MX93_PAD_GPIO_IO07__GPIO2_IO07 = IOMUX_PAD(0x1DC, 0x002C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__LPSPI3_PCS1 = IOMUX_PAD(0x1DC, 0x002C, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 = IOMUX_PAD(0x1DC, 0x002C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 = IOMUX_PAD(0x1DC, 0x002C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__LPSPI7_SCK = IOMUX_PAD(0x1DC, 0x002C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__LPUART6_RTS_B = IOMUX_PAD(0x1DC, 0x002C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO07__LPI2C7_SCL = IOMUX_PAD(0x1DC, 0x002C, 6, 0x3F8, 0, 0),
+ MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x1DC, 0x002C, 7, 0x388, 0, 0),
+
+ MX93_PAD_GPIO_IO08__GPIO2_IO08 = IOMUX_PAD(0x1E0, 0x0030, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__LPSPI3_PCS0 = IOMUX_PAD(0x1E0, 0x0030, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 = IOMUX_PAD(0x1E0, 0x0030, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 = IOMUX_PAD(0x1E0, 0x0030, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__TPM6_CH0 = IOMUX_PAD(0x1E0, 0x0030, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__LPUART7_TX = IOMUX_PAD(0x1E0, 0x0030, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO08__LPI2C7_SDA = IOMUX_PAD(0x1E0, 0x0030, 6, 0x3FC, 1, 0),
+ MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x1E0, 0x0030, 7, 0x38C, 0, 0),
+
+ MX93_PAD_GPIO_IO09__GPIO2_IO09 = IOMUX_PAD(0x1E4, 0x0034, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__LPSPI3_SIN = IOMUX_PAD(0x1E4, 0x0034, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 = IOMUX_PAD(0x1E4, 0x0034, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 = IOMUX_PAD(0x1E4, 0x0034, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__TPM3_EXTCLK = IOMUX_PAD(0x1E4, 0x0034, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__LPUART7_RX = IOMUX_PAD(0x1E4, 0x0034, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO09__LPI2C7_SCL = IOMUX_PAD(0x1E4, 0x0034, 6, 0x3F8, 1, 0),
+ MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x1E4, 0x0034, 7, 0x390, 0, 0),
+
+ MX93_PAD_GPIO_IO10__GPIO2_IO10 = IOMUX_PAD(0x1E8, 0x0038, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__LPSPI3_SOUT = IOMUX_PAD(0x1E8, 0x0038, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 = IOMUX_PAD(0x1E8, 0x0038, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 = IOMUX_PAD(0x1E8, 0x0038, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__TPM4_EXTCLK = IOMUX_PAD(0x1E8, 0x0038, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__LPUART7_CTS_B = IOMUX_PAD(0x1E8, 0x0038, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO10__LPI2C8_SDA = IOMUX_PAD(0x1E8, 0x0038, 6, 0x404, 0, 0),
+ MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x1E8, 0x0038, 7, 0x394, 0, 0),
+
+ MX93_PAD_GPIO_IO11__GPIO2_IO11 = IOMUX_PAD(0x1EC, 0x003C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__LPSPI3_SCK = IOMUX_PAD(0x1EC, 0x003C, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 = IOMUX_PAD(0x1EC, 0x003C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 = IOMUX_PAD(0x1EC, 0x003C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__TPM5_EXTCLK = IOMUX_PAD(0x1EC, 0x003C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__LPUART7_RTS_B = IOMUX_PAD(0x1EC, 0x003C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO11__LPI2C8_SCL = IOMUX_PAD(0x1EC, 0x003C, 6, 0x400, 0, 0),
+ MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x1EC, 0x003C, 7, 0x398, 0, 0),
+
+ MX93_PAD_GPIO_IO12__GPIO2_IO12 = IOMUX_PAD(0x1F0, 0x0040, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__TPM3_CH2 = IOMUX_PAD(0x1F0, 0x0040, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 = IOMUX_PAD(0x1F0, 0x0040, 2, 0x440, 0, 0),
+ MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 = IOMUX_PAD(0x1F0, 0x0040, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__LPSPI8_PCS0 = IOMUX_PAD(0x1F0, 0x0040, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__LPUART8_TX = IOMUX_PAD(0x1F0, 0x0040, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO12__LPI2C8_SDA = IOMUX_PAD(0x1F0, 0x0040, 6, 0x404, 1, 0),
+ MX93_PAD_GPIO_IO12__SAI3_RX_SYNC = IOMUX_PAD(0x1F0, 0x0040, 7, 0x450, 0, 0),
+
+ MX93_PAD_GPIO_IO13__GPIO2_IO13 = IOMUX_PAD(0x1F4, 0x0044, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__TPM4_CH2 = IOMUX_PAD(0x1F4, 0x0044, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 = IOMUX_PAD(0x1F4, 0x0044, 2, 0x444, 0, 0),
+ MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 = IOMUX_PAD(0x1F4, 0x0044, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__LPSPI8_SIN = IOMUX_PAD(0x1F4, 0x0044, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__LPUART8_RX = IOMUX_PAD(0x1F4, 0x0044, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO13__LPI2C8_SCL = IOMUX_PAD(0x1F4, 0x0044, 6, 0x400, 1, 0),
+ MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x1F4, 0x0044, 7, 0x39C, 0, 0),
+
+ MX93_PAD_GPIO_IO14__GPIO2_IO14 = IOMUX_PAD(0x1F8, 0x0048, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__LPUART3_TX = IOMUX_PAD(0x1F8, 0x0048, 1, 0x41C, 0, 0),
+ MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 = IOMUX_PAD(0x1F8, 0x0048, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 = IOMUX_PAD(0x1F8, 0x0048, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__LPSPI8_SOUT = IOMUX_PAD(0x1F8, 0x0048, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__LPUART8_CTS_B = IOMUX_PAD(0x1F8, 0x0048, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO14__LPUART4_TX = IOMUX_PAD(0x1F8, 0x0048, 6, 0x428, 0, 0),
+ MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x1F8, 0x0048, 7, 0x3A0, 0, 0),
+
+ MX93_PAD_GPIO_IO15__GPIO2_IO15 = IOMUX_PAD(0x1FC, 0x004C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__LPUART3_RX = IOMUX_PAD(0x1FC, 0x004C, 1, 0x418, 0, 0),
+ MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 = IOMUX_PAD(0x1FC, 0x004C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 = IOMUX_PAD(0x1FC, 0x004C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__LPSPI8_SCK = IOMUX_PAD(0x1FC, 0x004C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__LPUART8_RTS_B = IOMUX_PAD(0x1FC, 0x004C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO15__LPUART4_RX = IOMUX_PAD(0x1FC, 0x004C, 6, 0x424, 0, 0),
+ MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x1FC, 0x004C, 7, 0x3A4, 0, 0),
+
+ MX93_PAD_GPIO_IO16__GPIO2_IO16 = IOMUX_PAD(0x200, 0x0050, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO16__SAI3_TX_BCLK = IOMUX_PAD(0x200, 0x0050, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 = IOMUX_PAD(0x200, 0x0050, 2, 0x440, 1, 0),
+ MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 = IOMUX_PAD(0x200, 0x0050, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO16__LPUART3_CTS_B = IOMUX_PAD(0x200, 0x0050, 4, 0x414, 0, 0),
+ MX93_PAD_GPIO_IO16__LPSPI4_PCS2 = IOMUX_PAD(0x200, 0x0050, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO16__LPUART4_CTS_B = IOMUX_PAD(0x200, 0x0050, 6, 0x420, 0, 0),
+ MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x200, 0x0050, 7, 0x3A8, 0, 0),
+
+ MX93_PAD_GPIO_IO17__GPIO2_IO17 = IOMUX_PAD(0x204, 0x0054, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__SAI3_MCLK = IOMUX_PAD(0x204, 0x0054, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 = IOMUX_PAD(0x204, 0x0054, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 = IOMUX_PAD(0x204, 0x0054, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__LPUART3_RTS_B = IOMUX_PAD(0x204, 0x0054, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__LPSPI4_PCS1 = IOMUX_PAD(0x204, 0x0054, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__LPUART4_RTS_B = IOMUX_PAD(0x204, 0x0054, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x204, 0x0054, 7, 0x3AC, 0, 0),
+
+ MX93_PAD_GPIO_IO18__GPIO2_IO18 = IOMUX_PAD(0x208, 0x0058, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__SAI3_RX_BCLK = IOMUX_PAD(0x208, 0x0058, 1, 0x44C, 0, 0),
+ MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 = IOMUX_PAD(0x208, 0x0058, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 = IOMUX_PAD(0x208, 0x0058, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__LPSPI5_PCS0 = IOMUX_PAD(0x208, 0x0058, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__LPSPI4_PCS0 = IOMUX_PAD(0x208, 0x0058, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__TPM5_CH2 = IOMUX_PAD(0x208, 0x0058, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x208, 0x0058, 7, 0x3B0, 0, 0),
+
+ MX93_PAD_GPIO_IO19__GPIO2_IO19 = IOMUX_PAD(0x20C, 0x005C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__SAI3_RX_SYNC = IOMUX_PAD(0x20C, 0x005C, 1, 0x450, 1, 0),
+ MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 = IOMUX_PAD(0x20C, 0x005C, 2, 0x444, 1, 0),
+ MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 = IOMUX_PAD(0x20C, 0x005C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__LPSPI5_SIN = IOMUX_PAD(0x20C, 0x005C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__LPSPI4_SIN = IOMUX_PAD(0x20C, 0x005C, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__TPM6_CH2 = IOMUX_PAD(0x20C, 0x005C, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 = IOMUX_PAD(0x20C, 0x005C, 7, 0x0000, 0, 0),
+
+ MX93_PAD_GPIO_IO20__GPIO2_IO20 = IOMUX_PAD(0x210, 0x0060, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 = IOMUX_PAD(0x210, 0x0060, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 = IOMUX_PAD(0x210, 0x0060, 2, 0x438, 1, 0),
+ MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 = IOMUX_PAD(0x210, 0x0060, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__LPSPI5_SOUT = IOMUX_PAD(0x210, 0x0060, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__LPSPI4_SOUT = IOMUX_PAD(0x210, 0x0060, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__TPM3_CH1 = IOMUX_PAD(0x210, 0x0060, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x210, 0x0060, 7, 0x3B4, 0, 0),
+
+ MX93_PAD_GPIO_IO21__GPIO2_IO21 = IOMUX_PAD(0x214, 0x0064, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 = IOMUX_PAD(0x214, 0x0064, 1, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__PDM_CLK = IOMUX_PAD(0x214, 0x0064, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 = IOMUX_PAD(0x214, 0x0064, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__LPSPI5_SCK = IOMUX_PAD(0x214, 0x0064, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__LPSPI4_SCK = IOMUX_PAD(0x214, 0x0064, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__TPM4_CH1 = IOMUX_PAD(0x214, 0x0064, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO21__SAI3_RX_BCLK = IOMUX_PAD(0x214, 0x0064, 7, 0x44C, 1, 0),
+
+ MX93_PAD_GPIO_IO22__GPIO2_IO22 = IOMUX_PAD(0x218, 0x0068, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO22__USDHC3_CLK = IOMUX_PAD(0x218, 0x0068, 1, 0x458, 0, 0),
+ MX93_PAD_GPIO_IO22__SPDIF_IN = IOMUX_PAD(0x218, 0x0068, 2, 0x454, 0, 0),
+ MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 = IOMUX_PAD(0x218, 0x0068, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO22__TPM5_CH1 = IOMUX_PAD(0x218, 0x0068, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO22__TPM6_EXTCLK = IOMUX_PAD(0x218, 0x0068, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO22__LPI2C5_SDA = IOMUX_PAD(0x218, 0x0068, 6, 0x3EC, 1, 0),
+ MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x218, 0x0068, 7, 0x3B8, 0, 0),
+
+ MX93_PAD_GPIO_IO23__GPIO2_IO23 = IOMUX_PAD(0x21C, 0x006C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO23__USDHC3_CMD = IOMUX_PAD(0x21C, 0x006C, 1, 0x45C, 0, 0),
+ MX93_PAD_GPIO_IO23__SPDIF_OUT = IOMUX_PAD(0x21C, 0x006C, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 = IOMUX_PAD(0x21C, 0x006C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO23__TPM6_CH1 = IOMUX_PAD(0x21C, 0x006C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO23__LPI2C5_SCL = IOMUX_PAD(0x21C, 0x006C, 6, 0x3E8, 1, 0),
+ MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x21C, 0x006C, 7, 0x3BC, 0, 0),
+
+ MX93_PAD_GPIO_IO24__GPIO2_IO24 = IOMUX_PAD(0x220, 0x0070, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__USDHC3_DATA0 = IOMUX_PAD(0x220, 0x0070, 1, 0x460, 0, 0),
+ MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 = IOMUX_PAD(0x220, 0x0070, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__TPM3_CH3 = IOMUX_PAD(0x220, 0x0070, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__JTAG_MUX_TDO = IOMUX_PAD(0x220, 0x0070, 5, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__LPSPI6_PCS1 = IOMUX_PAD(0x220, 0x0070, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x220, 0x0070, 7, 0x3C0, 0, 0),
+
+ MX93_PAD_GPIO_IO25__GPIO2_IO25 = IOMUX_PAD(0x224, 0x0074, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__USDHC3_DATA1 = IOMUX_PAD(0x224, 0x0074, 1, 0x464, 0, 0),
+ MX93_PAD_GPIO_IO25__CAN2_TX = IOMUX_PAD(0x224, 0x0074, 2, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 = IOMUX_PAD(0x224, 0x0074, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__TPM4_CH3 = IOMUX_PAD(0x224, 0x0074, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__JTAG_MUX_TCK = IOMUX_PAD(0x224, 0x0074, 5, 0x3D4, 1, 0),
+ MX93_PAD_GPIO_IO25__LPSPI7_PCS1 = IOMUX_PAD(0x224, 0x0074, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x224, 0x0074, 7, 0x3C4, 0, 0),
+
+ MX93_PAD_GPIO_IO26__GPIO2_IO26 = IOMUX_PAD(0x228, 0x0078, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO26__USDHC3_DATA2 = IOMUX_PAD(0x228, 0x0078, 1, 0x468, 0, 0),
+ MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 = IOMUX_PAD(0x228, 0x0078, 2, 0x43C, 1, 0),
+ MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 = IOMUX_PAD(0x228, 0x0078, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO26__TPM5_CH3 = IOMUX_PAD(0x228, 0x0078, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO26__JTAG_MUX_TDI = IOMUX_PAD(0x228, 0x0078, 5, 0x3D8, 1, 0),
+ MX93_PAD_GPIO_IO26__LPSPI8_PCS1 = IOMUX_PAD(0x228, 0x0078, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO26__SAI3_TX_SYNC = IOMUX_PAD(0x228, 0x0078, 7, 0x0000, 0, 0),
+
+ MX93_PAD_GPIO_IO27__GPIO2_IO27 = IOMUX_PAD(0x22C, 0x007C, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO27__USDHC3_DATA3 = IOMUX_PAD(0x22C, 0x007C, 1, 0x46C, 0, 0),
+ MX93_PAD_GPIO_IO27__CAN2_RX = IOMUX_PAD(0x22C, 0x007C, 2, 0x364, 1, 0),
+ MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 = IOMUX_PAD(0x22C, 0x007C, 3, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO27__TPM6_CH3 = IOMUX_PAD(0x22C, 0x007C, 4, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO27__JTAG_MUX_TMS = IOMUX_PAD(0x22C, 0x007C, 5, 0x3DC, 1, 0),
+ MX93_PAD_GPIO_IO27__LPSPI5_PCS1 = IOMUX_PAD(0x22C, 0x007C, 6, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x22C, 0x007C, 7, 0x3C8, 0, 0),
+
+ MX93_PAD_GPIO_IO28__GPIO2_IO28 = IOMUX_PAD(0x230, 0x0080, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO28__LPI2C3_SDA = IOMUX_PAD(0x230, 0x0080, 1, 0x3E4, 1, 0),
+ MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 = IOMUX_PAD(0x230, 0x0080, 7, 0x0000, 0, 0),
+
+ MX93_PAD_GPIO_IO29__GPIO2_IO29 = IOMUX_PAD(0x234, 0x0084, 0, 0x0000, 0, 0),
+ MX93_PAD_GPIO_IO29__LPI2C3_SCL = IOMUX_PAD(0x234, 0x0084, 1, 0x3E0, 1, 0),
+ MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 = IOMUX_PAD(0x234, 0x0084, 7, 0x0000, 0, 0),
+
+ MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x238, 0x0088, 0, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 = IOMUX_PAD(0x238, 0x0088, 4, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO1__GPIO3_IO26 = IOMUX_PAD(0x238, 0x0088, 5, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO2__GPIO3_IO27 = IOMUX_PAD(0x23C, 0x008C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x23C, 0x008C, 0, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 = IOMUX_PAD(0x23C, 0x008C, 4, 0x3C8, 1, 0),
+
+ MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 = IOMUX_PAD(0x240, 0x0090, 0, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 = IOMUX_PAD(0x240, 0x0090, 4, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO3__GPIO4_IO28 = IOMUX_PAD(0x240, 0x0090, 5, 0x0000, 0, 0),
+
+ MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 = IOMUX_PAD(0x244, 0x0094, 0, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 = IOMUX_PAD(0x244, 0x0094, 4, 0x0000, 0, 0),
+ MX93_PAD_CCM_CLKO4__GPIO4_IO29 = IOMUX_PAD(0x244, 0x0094, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC = IOMUX_PAD(0x248, 0x0098, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDC__LPUART3_DCB_B = IOMUX_PAD(0x248, 0x0098, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDC__I3C2_SCL = IOMUX_PAD(0x248, 0x0098, 2, 0x3CC, 0, 0),
+ MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 = IOMUX_PAD(0x248, 0x0098, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 = IOMUX_PAD(0x248, 0x0098, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDC__GPIO4_IO00 = IOMUX_PAD(0x248, 0x0098, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x24C, 0x009C, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDIO__LPUART3_RIN_B = IOMUX_PAD(0x24C, 0x009C, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDIO__I3C2_SDA = IOMUX_PAD(0x24C, 0x009C, 2, 0x3D0, 0, 0),
+ MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 = IOMUX_PAD(0x24C, 0x009C, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 = IOMUX_PAD(0x24C, 0x009C, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_MDIO__GPIO4_IO01 = IOMUX_PAD(0x24C, 0x009C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x250, 0x00A0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD3__CAN2_TX = IOMUX_PAD(0x250, 0x00A0, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 = IOMUX_PAD(0x250, 0x00A0, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 = IOMUX_PAD(0x250, 0x00A0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD3__GPIO4_IO02 = IOMUX_PAD(0x250, 0x00A0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x254, 0x00A4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x254, 0x00A4, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD2__CAN2_RX = IOMUX_PAD(0x254, 0x00A4, 2, 0x364, 2, 0),
+ MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 = IOMUX_PAD(0x254, 0x00A4, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 = IOMUX_PAD(0x254, 0x00A4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD2__GPIO4_IO03 = IOMUX_PAD(0x254, 0x00A4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x258, 0x00A8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__LPUART3_RTS_B = IOMUX_PAD(0x258, 0x00A8, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__I3C2_PUR = IOMUX_PAD(0x258, 0x00A8, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 = IOMUX_PAD(0x258, 0x00A8, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 = IOMUX_PAD(0x258, 0x00A8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__GPIO4_IO04 = IOMUX_PAD(0x258, 0x00A8, 5, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD1__I3C2_PUR_B = IOMUX_PAD(0x258, 0x00A8, 6, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x25C, 0x00AC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD0__LPUART3_TX = IOMUX_PAD(0x25C, 0x00AC, 1, 0x41C, 1, 0),
+ MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 = IOMUX_PAD(0x25C, 0x00AC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TD0__GPIO4_IO05 = IOMUX_PAD(0x25C, 0x00AC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x260, 0x00B0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B = IOMUX_PAD(0x260, 0x00B0, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 = IOMUX_PAD(0x260, 0x00B0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 = IOMUX_PAD(0x260, 0x00B0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x264, 0x00B4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x264, 0x00B4, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 = IOMUX_PAD(0x264, 0x00B4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_TXC__GPIO4_IO07 = IOMUX_PAD(0x264, 0x00B4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x268, 0x00B8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B = IOMUX_PAD(0x268, 0x00B8, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 = IOMUX_PAD(0x268, 0x00B8, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 = IOMUX_PAD(0x268, 0x00B8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 = IOMUX_PAD(0x268, 0x00B8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x26C, 0x00BC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x26C, 0x00BC, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 = IOMUX_PAD(0x26C, 0x00BC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RXC__GPIO4_IO09 = IOMUX_PAD(0x26C, 0x00BC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x270, 0x00C0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD0__LPUART3_RX = IOMUX_PAD(0x270, 0x00C0, 1, 0x418, 1, 0),
+ MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 = IOMUX_PAD(0x270, 0x00C0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD0__GPIO4_IO10 = IOMUX_PAD(0x270, 0x00C0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x274, 0x00C4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD1__LPUART3_CTS_B = IOMUX_PAD(0x274, 0x00C4, 1, 0x414, 1, 0),
+ MX93_PAD_ENET1_RD1__LPTMR2_ALT1 = IOMUX_PAD(0x274, 0x00C4, 3, 0x408, 0, 0),
+ MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 = IOMUX_PAD(0x274, 0x00C4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD1__GPIO4_IO11 = IOMUX_PAD(0x274, 0x00C4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x278, 0x00C8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD2__LPTMR2_ALT2 = IOMUX_PAD(0x278, 0x00C8, 3, 0x40C, 0, 0),
+ MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 = IOMUX_PAD(0x278, 0x00C8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD2__GPIO4_IO12 = IOMUX_PAD(0x278, 0x00C8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x27C, 0x00CC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER = IOMUX_PAD(0x27C, 0x00CC, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD3__LPTMR2_ALT3 = IOMUX_PAD(0x27C, 0x00CC, 3, 0x410, 0, 0),
+ MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 = IOMUX_PAD(0x27C, 0x00CC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET1_RD3__GPIO4_IO13 = IOMUX_PAD(0x27C, 0x00CC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_MDC__ENET1_MDC = IOMUX_PAD(0x280, 0x00D0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDC__LPUART4_DCB_B = IOMUX_PAD(0x280, 0x00D0, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDC__SAI2_RX_SYNC = IOMUX_PAD(0x280, 0x00D0, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 = IOMUX_PAD(0x280, 0x00D0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDC__GPIO4_IO14 = IOMUX_PAD(0x280, 0x00D0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO = IOMUX_PAD(0x284, 0x00D4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDIO__LPUART4_RIN_B = IOMUX_PAD(0x284, 0x00D4, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK = IOMUX_PAD(0x284, 0x00D4, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 = IOMUX_PAD(0x284, 0x00D4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_MDIO__GPIO4_IO15 = IOMUX_PAD(0x284, 0x00D4, 5, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 = IOMUX_PAD(0x288, 0x00D8, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 = IOMUX_PAD(0x288, 0x00D8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD3__GPIO4_IO16 = IOMUX_PAD(0x288, 0x00D8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x288, 0x00D8, 0, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x28C, 0x00DC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD2__ENET1_TX_CLK = IOMUX_PAD(0x28C, 0x00DC, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 = IOMUX_PAD(0x28C, 0x00DC, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 = IOMUX_PAD(0x28C, 0x00DC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD2__GPIO4_IO17 = IOMUX_PAD(0x28C, 0x00DC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x290, 0x00E0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD1__LPUART4_RTS_B = IOMUX_PAD(0x290, 0x00E0, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 = IOMUX_PAD(0x290, 0x00E0, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 = IOMUX_PAD(0x290, 0x00E0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD1__GPIO4_IO18 = IOMUX_PAD(0x290, 0x00E0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x294, 0x00E4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD0__LPUART4_TX = IOMUX_PAD(0x294, 0x00E4, 1, 0x428, 1, 0),
+ MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 = IOMUX_PAD(0x294, 0x00E4, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 = IOMUX_PAD(0x294, 0x00E4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TD0__GPIO4_IO19 = IOMUX_PAD(0x294, 0x00E4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x298, 0x00E8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B = IOMUX_PAD(0x298, 0x00E8, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC = IOMUX_PAD(0x298, 0x00E8, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 = IOMUX_PAD(0x298, 0x00E8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 = IOMUX_PAD(0x298, 0x00E8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC = IOMUX_PAD(0x29C, 0x00EC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TXC__ENET1_TX_ER = IOMUX_PAD(0x29C, 0x00EC, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TXC__SAI2_TX_BCLK = IOMUX_PAD(0x29C, 0x00EC, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 = IOMUX_PAD(0x29C, 0x00EC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_TXC__GPIO4_IO21 = IOMUX_PAD(0x29C, 0x00EC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x2A0, 0x00F0, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B = IOMUX_PAD(0x2A0, 0x00F0, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 = IOMUX_PAD(0x2A0, 0x00F0, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 = IOMUX_PAD(0x2A0, 0x00F0, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 = IOMUX_PAD(0x2A0, 0x00F0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC = IOMUX_PAD(0x2A4, 0x00F4, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RXC__ENET1_RX_ER = IOMUX_PAD(0x2A4, 0x00F4, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 = IOMUX_PAD(0x2A4, 0x00F4, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 = IOMUX_PAD(0x2A4, 0x00F4, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RXC__GPIO4_IO23 = IOMUX_PAD(0x2A4, 0x00F4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 = IOMUX_PAD(0x2A8, 0x00F8, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD0__LPUART4_RX = IOMUX_PAD(0x2A8, 0x00F8, 1, 0x424, 1, 0),
+ MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 = IOMUX_PAD(0x2A8, 0x00F8, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 = IOMUX_PAD(0x2A8, 0x00F8, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD0__GPIO4_IO24 = IOMUX_PAD(0x2A8, 0x00F8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 = IOMUX_PAD(0x2AC, 0x00FC, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD1__SPDIF_IN = IOMUX_PAD(0x2AC, 0x00FC, 1, 0x454, 1, 0),
+ MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 = IOMUX_PAD(0x2AC, 0x00FC, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 = IOMUX_PAD(0x2AC, 0x00FC, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD1__GPIO4_IO25 = IOMUX_PAD(0x2AC, 0x00FC, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 = IOMUX_PAD(0x2B0, 0x100, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD2__LPUART4_CTS_B = IOMUX_PAD(0x2B0, 0x100, 1, 0x420, 1, 0),
+ MX93_PAD_ENET2_RD2__SAI2_MCLK = IOMUX_PAD(0x2B0, 0x100, 2, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD2__MQS2_RIGHT = IOMUX_PAD(0x2B0, 0x100, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 = IOMUX_PAD(0x2B0, 0x100, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD2__GPIO4_IO26 = IOMUX_PAD(0x2B0, 0x100, 5, 0x0000, 0, 0),
+
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 = IOMUX_PAD(0x2B4, 0x104, 0, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD3__SPDIF_OUT = IOMUX_PAD(0x2B4, 0x104, 1, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD3__SPDIF_IN = IOMUX_PAD(0x2B4, 0x104, 2, 0x454, 2, 0),
+ MX93_PAD_ENET2_RD3__MQS2_LEFT = IOMUX_PAD(0x2B4, 0x104, 3, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 = IOMUX_PAD(0x2B4, 0x104, 4, 0x0000, 0, 0),
+ MX93_PAD_ENET2_RD3__GPIO4_IO27 = IOMUX_PAD(0x2B4, 0x104, 5, 0x0000, 0, 0),
+ MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 = IOMUX_PAD(0x2B8, 0x108, 4, 0x38C, 1, 0),
+ MX93_PAD_SD1_CLK__GPIO3_IO08 = IOMUX_PAD(0x2B8, 0x108, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x2B8, 0x108, 0, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x2BC, 0x10C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 = IOMUX_PAD(0x2BC, 0x10C, 4, 0x390, 1, 0),
+ MX93_PAD_SD1_CMD__GPIO3_IO09 = IOMUX_PAD(0x2BC, 0x10C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x2C0, 0x110, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 = IOMUX_PAD(0x2C0, 0x110, 4, 0x394, 1, 0),
+ MX93_PAD_SD1_DATA0__GPIO3_IO10 = IOMUX_PAD(0x2C0, 0x110, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x2C4, 0x114, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 = IOMUX_PAD(0x2C4, 0x114, 4, 0x398, 1, 0),
+ MX93_PAD_SD1_DATA1__GPIO3_IO11 = IOMUX_PAD(0x2C4, 0x114, 5, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x2C4, 0x114, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x2C8, 0x118, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 = IOMUX_PAD(0x2C8, 0x118, 4, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA2__GPIO3_IO12 = IOMUX_PAD(0x2C8, 0x118, 5, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x2C8, 0x118, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x2CC, 0x11C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B = IOMUX_PAD(0x2CC, 0x11C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 = IOMUX_PAD(0x2CC, 0x11C, 4, 0x39C, 1, 0),
+ MX93_PAD_SD1_DATA3__GPIO3_IO13 = IOMUX_PAD(0x2CC, 0x11C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x2D0, 0x120, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 = IOMUX_PAD(0x2D0, 0x120, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 = IOMUX_PAD(0x2D0, 0x120, 4, 0x3A0, 1, 0),
+ MX93_PAD_SD1_DATA4__GPIO3_IO14 = IOMUX_PAD(0x2D0, 0x120, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x2D4, 0x124, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 = IOMUX_PAD(0x2D4, 0x124, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA5__USDHC1_RESET_B = IOMUX_PAD(0x2D4, 0x124, 2, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 = IOMUX_PAD(0x2D4, 0x124, 4, 0x3A4, 1, 0),
+ MX93_PAD_SD1_DATA5__GPIO3_IO15 = IOMUX_PAD(0x2D4, 0x124, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x2D8, 0x128, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 = IOMUX_PAD(0x2D8, 0x128, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA6__USDHC1_CD_B = IOMUX_PAD(0x2D8, 0x128, 2, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 = IOMUX_PAD(0x2D8, 0x128, 4, 0x3A8, 1, 0),
+ MX93_PAD_SD1_DATA6__GPIO3_IO16 = IOMUX_PAD(0x2D8, 0x128, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x2DC, 0x12C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 = IOMUX_PAD(0x2DC, 0x12C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA7__USDHC1_WP = IOMUX_PAD(0x2DC, 0x12C, 2, 0x0000, 0, 0),
+ MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 = IOMUX_PAD(0x2DC, 0x12C, 4, 0x3AC, 1, 0),
+ MX93_PAD_SD1_DATA7__GPIO3_IO17 = IOMUX_PAD(0x2DC, 0x12C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x2E0, 0x130, 0, 0x0000, 0, 0),
+ MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS = IOMUX_PAD(0x2E0, 0x130, 1, 0x0000, 0, 0),
+ MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 = IOMUX_PAD(0x2E0, 0x130, 4, 0x3B0, 1, 0),
+ MX93_PAD_SD1_STROBE__GPIO3_IO18 = IOMUX_PAD(0x2E0, 0x130, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT = IOMUX_PAD(0x2E4, 0x134, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_VSELECT__USDHC2_WP = IOMUX_PAD(0x2E4, 0x134, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 = IOMUX_PAD(0x2E4, 0x134, 2, 0x410, 1, 0),
+ MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 = IOMUX_PAD(0x2E4, 0x134, 4, 0x0000, 0, 0),
+ MX93_PAD_SD2_VSELECT__GPIO3_IO19 = IOMUX_PAD(0x2E4, 0x134, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x2E4, 0x134, 6, 0x368, 0, 0),
+
+ MX93_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x2E8, 0x138, 0, 0x458, 1, 0),
+ MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK = IOMUX_PAD(0x2E8, 0x138, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 = IOMUX_PAD(0x2E8, 0x138, 4, 0x3B4, 1, 0),
+ MX93_PAD_SD3_CLK__GPIO3_IO20 = IOMUX_PAD(0x2E8, 0x138, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x2EC, 0x13C, 0, 0x45C, 1, 0),
+ MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B = IOMUX_PAD(0x2EC, 0x13C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 = IOMUX_PAD(0x2EC, 0x13C, 4, 0x0000, 0, 0),
+ MX93_PAD_SD3_CMD__GPIO3_IO21 = IOMUX_PAD(0x2EC, 0x13C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x2F0, 0x140, 0, 0x460, 1, 0),
+ MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 = IOMUX_PAD(0x2F0, 0x140, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 = IOMUX_PAD(0x2F0, 0x140, 4, 0x3B8, 1, 0),
+ MX93_PAD_SD3_DATA0__GPIO3_IO22 = IOMUX_PAD(0x2F0, 0x140, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x2F4, 0x144, 0, 0x464, 1, 0),
+ MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 = IOMUX_PAD(0x2F4, 0x144, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 = IOMUX_PAD(0x2F4, 0x144, 4, 0x3BC, 1, 0),
+ MX93_PAD_SD3_DATA1__GPIO3_IO23 = IOMUX_PAD(0x2F4, 0x144, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_DATA2__USDHC3_DATA2 = IOMUX_PAD(0x2F8, 0x148, 0, 0x468, 1, 0),
+ MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 = IOMUX_PAD(0x2F8, 0x148, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 = IOMUX_PAD(0x2F8, 0x148, 4, 0x3C0, 1, 0),
+ MX93_PAD_SD3_DATA2__GPIO3_IO24 = IOMUX_PAD(0x2F8, 0x148, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD3_DATA3__USDHC3_DATA3 = IOMUX_PAD(0x2FC, 0x14C, 0, 0x46C, 1, 0),
+ MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 = IOMUX_PAD(0x2FC, 0x14C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 = IOMUX_PAD(0x2FC, 0x14C, 4, 0x3C4, 1, 0),
+ MX93_PAD_SD3_DATA3__GPIO3_IO25 = IOMUX_PAD(0x2FC, 0x14C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x300, 0x150, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x300, 0x150, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_CD_B__I3C2_SCL = IOMUX_PAD(0x300, 0x150, 2, 0x3CC, 1, 0),
+ MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 = IOMUX_PAD(0x300, 0x150, 4, 0x36C, 1, 0),
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 = IOMUX_PAD(0x300, 0x150, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x304, 0x154, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x304, 0x154, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_CLK__I3C2_SDA = IOMUX_PAD(0x304, 0x154, 2, 0x3D0, 1, 0),
+ MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 = IOMUX_PAD(0x304, 0x154, 4, 0x370, 1, 0),
+ MX93_PAD_SD2_CLK__GPIO3_IO01 = IOMUX_PAD(0x304, 0x154, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x304, 0x154, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x308, 0x158, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x308, 0x158, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__I3C2_PUR = IOMUX_PAD(0x308, 0x158, 2, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__I3C2_PUR_B = IOMUX_PAD(0x308, 0x158, 3, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 = IOMUX_PAD(0x308, 0x158, 4, 0x374, 1, 0),
+ MX93_PAD_SD2_CMD__GPIO3_IO02 = IOMUX_PAD(0x308, 0x158, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x308, 0x158, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x30C, 0x15C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x30C, 0x15C, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA0__CAN2_TX = IOMUX_PAD(0x30C, 0x15C, 2, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 = IOMUX_PAD(0x30C, 0x15C, 4, 0x378, 1, 0),
+ MX93_PAD_SD2_DATA0__GPIO3_IO03 = IOMUX_PAD(0x30C, 0x15C, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x30C, 0x15C, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x310, 0x160, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x310, 0x160, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA1__CAN2_RX = IOMUX_PAD(0x310, 0x160, 2, 0x364, 3, 0),
+ MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 = IOMUX_PAD(0x310, 0x160, 4, 0x37C, 1, 0),
+ MX93_PAD_SD2_DATA1__GPIO3_IO04 = IOMUX_PAD(0x310, 0x160, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x310, 0x160, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x314, 0x164, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x314, 0x164, 1, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA2__MQS2_RIGHT = IOMUX_PAD(0x314, 0x164, 2, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 = IOMUX_PAD(0x314, 0x164, 4, 0x380, 1, 0),
+ MX93_PAD_SD2_DATA2__GPIO3_IO05 = IOMUX_PAD(0x314, 0x164, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x314, 0x164, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x318, 0x168, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA3__LPTMR2_ALT1 = IOMUX_PAD(0x318, 0x168, 1, 0x408, 1, 0),
+ MX93_PAD_SD2_DATA3__MQS2_LEFT = IOMUX_PAD(0x318, 0x168, 2, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 = IOMUX_PAD(0x318, 0x168, 4, 0x384, 1, 0),
+ MX93_PAD_SD2_DATA3__GPIO3_IO06 = IOMUX_PAD(0x318, 0x168, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x318, 0x168, 6, 0x0000, 0, 0),
+
+ MX93_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x31C, 0x16C, 0, 0x0000, 0, 0),
+ MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 = IOMUX_PAD(0x31C, 0x16C, 1, 0x40C, 1, 0),
+ MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 = IOMUX_PAD(0x31C, 0x16C, 4, 0x388, 1, 0),
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 = IOMUX_PAD(0x31C, 0x16C, 5, 0x0000, 0, 0),
+ MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x31C, 0x16C, 6, 0x0000, 0, 0),
+
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL = IOMUX_PAD(0x320, 0x170, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SCL__I3C1_SCL = IOMUX_PAD(0x320, 0x170, 1, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SCL__LPUART1_DCB_B = IOMUX_PAD(0x320, 0x170, 2, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SCL__TPM2_CH0 = IOMUX_PAD(0x320, 0x170, 3, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SCL__GPIO1_IO00 = IOMUX_PAD(0x320, 0x170, 5, 0x0000, 0, 0),
+
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA = IOMUX_PAD(0x324, 0x174, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SDA__I3C1_SDA = IOMUX_PAD(0x324, 0x174, 1, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SDA__LPUART1_RIN_B = IOMUX_PAD(0x324, 0x174, 2, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SDA__TPM2_CH1 = IOMUX_PAD(0x324, 0x174, 3, 0x0000, 0, 0),
+ MX93_PAD_I2C1_SDA__GPIO1_IO01 = IOMUX_PAD(0x324, 0x174, 5, 0x0000, 0, 0),
+
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL = IOMUX_PAD(0x328, 0x178, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__I3C1_PUR = IOMUX_PAD(0x328, 0x178, 1, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__LPUART2_DCB_B = IOMUX_PAD(0x328, 0x178, 2, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__TPM2_CH2 = IOMUX_PAD(0x328, 0x178, 3, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__SAI1_RX_SYNC = IOMUX_PAD(0x328, 0x178, 4, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__GPIO1_IO02 = IOMUX_PAD(0x328, 0x178, 5, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SCL__I3C1_PUR_B = IOMUX_PAD(0x328, 0x178, 6, 0x0000, 0, 0),
+
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA = IOMUX_PAD(0x32C, 0x17C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SDA__LPUART2_RIN_B = IOMUX_PAD(0x32C, 0x17C, 2, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SDA__TPM2_CH3 = IOMUX_PAD(0x32C, 0x17C, 3, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SDA__SAI1_RX_BCLK = IOMUX_PAD(0x32C, 0x17C, 4, 0x0000, 0, 0),
+ MX93_PAD_I2C2_SDA__GPIO1_IO03 = IOMUX_PAD(0x32C, 0x17C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_UART1_RXD__LPUART1_RX = IOMUX_PAD(0x330, 0x180, 0, 0x0000, 0, 0),
+ MX93_PAD_UART1_RXD__S400_UART_RX = IOMUX_PAD(0x330, 0x180, 1, 0x0000, 0, 0),
+ MX93_PAD_UART1_RXD__LPSPI2_SIN = IOMUX_PAD(0x330, 0x180, 2, 0x0000, 0, 0),
+ MX93_PAD_UART1_RXD__TPM1_CH0 = IOMUX_PAD(0x330, 0x180, 3, 0x0000, 0, 0),
+ MX93_PAD_UART1_RXD__GPIO1_IO04 = IOMUX_PAD(0x330, 0x180, 5, 0x0000, 0, 0),
+
+ MX93_PAD_UART1_TXD__LPUART1_TX = IOMUX_PAD(0x334, 0x184, 0, 0x0000, 0, 0),
+ MX93_PAD_UART1_TXD__S400_UART_TX = IOMUX_PAD(0x334, 0x184, 1, 0x0000, 0, 0),
+ MX93_PAD_UART1_TXD__LPSPI2_PCS0 = IOMUX_PAD(0x334, 0x184, 2, 0x0000, 0, 0),
+ MX93_PAD_UART1_TXD__TPM1_CH1 = IOMUX_PAD(0x334, 0x184, 3, 0x0000, 0, 0),
+ MX93_PAD_UART1_TXD__GPIO1_IO05 = IOMUX_PAD(0x334, 0x184, 5, 0x0000, 0, 0),
+
+ MX93_PAD_UART2_RXD__LPUART2_RX = IOMUX_PAD(0x338, 0x188, 0, 0x0000, 0, 0),
+ MX93_PAD_UART2_RXD__LPUART1_CTS_B = IOMUX_PAD(0x338, 0x188, 1, 0x0000, 0, 0),
+ MX93_PAD_UART2_RXD__LPSPI2_SOUT = IOMUX_PAD(0x338, 0x188, 2, 0x0000, 0, 0),
+ MX93_PAD_UART2_RXD__TPM1_CH2 = IOMUX_PAD(0x338, 0x188, 3, 0x0000, 0, 0),
+ MX93_PAD_UART2_RXD__SAI1_MCLK = IOMUX_PAD(0x338, 0x188, 4, 0x448, 0, 0),
+ MX93_PAD_UART2_RXD__GPIO1_IO06 = IOMUX_PAD(0x338, 0x188, 5, 0x0000, 0, 0),
+
+ MX93_PAD_UART2_TXD__LPUART2_TX = IOMUX_PAD(0x33C, 0x18C, 0, 0x0000, 0, 0),
+ MX93_PAD_UART2_TXD__LPUART1_RTS_B = IOMUX_PAD(0x33C, 0x18C, 1, 0x0000, 0, 0),
+ MX93_PAD_UART2_TXD__LPSPI2_SCK = IOMUX_PAD(0x33C, 0x18C, 2, 0x0000, 0, 0),
+ MX93_PAD_UART2_TXD__TPM1_CH3 = IOMUX_PAD(0x33C, 0x18C, 3, 0x0000, 0, 0),
+ MX93_PAD_UART2_TXD__GPIO1_IO07 = IOMUX_PAD(0x33C, 0x18C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_PDM_CLK__PDM_CLK = IOMUX_PAD(0x340, 0x190, 0, 0x0000, 0, 0),
+ MX93_PAD_PDM_CLK__MQS1_LEFT = IOMUX_PAD(0x340, 0x190, 1, 0x0000, 0, 0),
+ MX93_PAD_PDM_CLK__LPTMR1_ALT1 = IOMUX_PAD(0x340, 0x190, 4, 0x0000, 0, 0),
+ MX93_PAD_PDM_CLK__GPIO1_IO08 = IOMUX_PAD(0x340, 0x190, 5, 0x0000, 0, 0),
+ MX93_PAD_PDM_CLK__CAN1_TX = IOMUX_PAD(0x340, 0x190, 6, 0x0000, 0, 0),
+
+ MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 = IOMUX_PAD(0x344, 0x194, 0, 0x438, 2, 0),
+ MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT = IOMUX_PAD(0x344, 0x194, 1, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 = IOMUX_PAD(0x344, 0x194, 2, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK = IOMUX_PAD(0x344, 0x194, 3, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 = IOMUX_PAD(0x344, 0x194, 4, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 = IOMUX_PAD(0x344, 0x194, 5, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX = IOMUX_PAD(0x344, 0x194, 6, 0x360, 0, 0),
+
+ MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 = IOMUX_PAD(0x348, 0x198, 0, 0x43C, 2, 0),
+ MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI = IOMUX_PAD(0x348, 0x198, 1, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 = IOMUX_PAD(0x348, 0x198, 2, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK = IOMUX_PAD(0x348, 0x198, 3, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 = IOMUX_PAD(0x348, 0x198, 4, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 = IOMUX_PAD(0x348, 0x198, 5, 0x0000, 0, 0),
+ MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x348, 0x198, 6, 0x368, 1, 0),
+
+ MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC = IOMUX_PAD(0x34C, 0x19C, 0, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 = IOMUX_PAD(0x34C, 0x19C, 1, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 = IOMUX_PAD(0x34C, 0x19C, 2, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__LPUART2_DTR_B = IOMUX_PAD(0x34C, 0x19C, 3, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__MQS1_LEFT = IOMUX_PAD(0x34C, 0x19C, 4, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXFS__GPIO1_IO11 = IOMUX_PAD(0x34C, 0x19C, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SAI1_TXC__SAI1_TX_BCLK = IOMUX_PAD(0x350, 0x1A0, 0, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXC__LPUART2_CTS_B = IOMUX_PAD(0x350, 0x1A0, 1, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXC__LPSPI1_SIN = IOMUX_PAD(0x350, 0x1A0, 2, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXC__LPUART1_DSR_B = IOMUX_PAD(0x350, 0x1A0, 3, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXC__CAN1_RX = IOMUX_PAD(0x350, 0x1A0, 4, 0x360, 1, 0),
+ MX93_PAD_SAI1_TXC__GPIO1_IO12 = IOMUX_PAD(0x350, 0x1A0, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 = IOMUX_PAD(0x354, 0x1A4, 0, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__LPUART2_RTS_B = IOMUX_PAD(0x354, 0x1A4, 1, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__LPSPI1_SCK = IOMUX_PAD(0x354, 0x1A4, 2, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__LPUART1_DTR_B = IOMUX_PAD(0x354, 0x1A4, 3, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__CAN1_TX = IOMUX_PAD(0x354, 0x1A4, 4, 0x0000, 0, 0),
+ MX93_PAD_SAI1_TXD0__GPIO1_IO13 = IOMUX_PAD(0x354, 0x1A4, 5, 0x0000, 0, 0),
+
+ MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 = IOMUX_PAD(0x358, 0x1A8, 0, 0x0000, 0, 0),
+ MX93_PAD_SAI1_RXD0__SAI1_MCLK = IOMUX_PAD(0x358, 0x1A8, 1, 0x448, 1, 0),
+ MX93_PAD_SAI1_RXD0__LPSPI1_SOUT = IOMUX_PAD(0x358, 0x1A8, 2, 0x0000, 0, 0),
+ MX93_PAD_SAI1_RXD0__LPUART2_DSR_B = IOMUX_PAD(0x358, 0x1A8, 3, 0x0000, 0, 0),
+ MX93_PAD_SAI1_RXD0__MQS1_RIGHT = IOMUX_PAD(0x358, 0x1A8, 4, 0x0000, 0, 0),
+ MX93_PAD_SAI1_RXD0__GPIO1_IO14 = IOMUX_PAD(0x358, 0x1A8, 5, 0x0000, 0, 0),
+
+ MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY = IOMUX_PAD(0x35C, 0x1AC, 0, 0x0000, 0, 0),
+ MX93_PAD_WDOG_ANY__GPIO1_IO15 = IOMUX_PAD(0x35C, 0x1AC, 5, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_IMX93_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
new file mode 100644
index 00000000000..513aa0b9581
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 NXP
+ */
+
+#ifndef __ARCH_IMX9_SYS_PROTO_H
+#define __ARCH_NMX9_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index 231b9c027ce..0492abd298c 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -86,7 +86,16 @@ typedef u64 iomux_v3_cfg_t;
#define IOMUX_CONFIG_LPSR 0x20
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
-#ifdef CONFIG_IMX8M
+#ifdef CONFIG_IMX93
+#define PAD_CTL_FSEL2 (0x2 << 7)
+#define PAD_CTL_FSEL3 (0x3 << 7)
+#define PAD_CTL_PUE (0x1 << 9)
+#define PAD_CTL_PDE (0x1 << 10)
+#define PAD_CTL_ODE (0x1 << 11)
+#define PAD_CTL_HYS (0x1 << 12)
+#define PAD_CTL_DSE(x) (((x) << 1) & 0x7f)
+
+#elif defined(CONFIG_IMX8M)
#define PAD_CTL_FSEL0 (0x0 << 3)
#define PAD_CTL_FSEL1 (0x1 << 3)
#define PAD_CTL_FSEL2 (0x2 << 3)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index cd69384d8ef..05532ebea89 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -31,6 +31,7 @@ struct bd_info;
#define is_mx7() (is_soc_type(MXC_SOC_MX7))
#define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
#define is_imx8() (is_soc_type(MXC_SOC_IMX8))
+#define is_imx9() (is_soc_type(MXC_SOC_IMX9))
#define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
@@ -81,6 +82,8 @@ struct bd_info;
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
+#define is_imx93() (is_cpu_type(MXC_CPU_IMX93))
+
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c5be63dfe4f..fd8e236af8d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,7 +5,7 @@
#
# (C) Copyright 2011 Freescale Semiconductor, Inc.
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m imx9 vf610))
obj-y = iomux-v3.o
endif
@@ -29,7 +29,7 @@ endif
obj-$(CONFIG_GPT_TIMER) += timer.o
obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imx9 imxrt))
obj-y += misc.o
obj-$(CONFIG_CMD_PRIBLOB) += priblob.o
obj-$(CONFIG_SPL_BUILD) += spl.o
@@ -195,6 +195,10 @@ flash.bin: spl/u-boot-spl.bin FORCE
endif
endif
+ifeq ($(CONFIG_ARCH_IMX9), y)
+SPL:
+endif
+
else
MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
-T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
@@ -240,7 +244,8 @@ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
obj-$(CONFIG_ARCH_IMX8ULP) += imx8ulp/
obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
+obj-$(CONFIG_ARCH_IMX9) += imx9/
obj-$(CONFIG_ARCH_IMXRT) += imxrt/
-obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP) += imx_romapi.o
+obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP)$(CONFIG_IMX9) += imx_romapi.o
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
new file mode 100644
index 00000000000..ce58e41428f
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -0,0 +1,17 @@
+if ARCH_IMX9
+
+config IMX9
+ bool
+ select HAS_CAAM
+ select ROM_UNIFIED_SECTIONS
+
+config IMX93
+ bool
+ select IMX9
+ select ARMV8_SPL_EXCEPTION_VECTORS
+
+config SYS_SOC
+ default "imx9"
+
+endif
+
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
new file mode 100644
index 00000000000..773b12ee129
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2022 NXP
+
+obj-y += lowlevel_init.o
+obj-y += soc.o clock.o
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
new file mode 100644
index 00000000000..fe89dccb316
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <log.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_lpuart_clk(void)
+{
+ return 24000000;
+}
+
diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S
new file mode 100644
index 00000000000..1dc1dbfcddc
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/lowlevel_init.S
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+ .space 256
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+#ifndef CONFIG_SPL_BUILD
+ /* The firmware provided ATAG/FDT address can be found in r2/x0 */
+ adr x0, rom_pointer
+ stp x1, x2, [x0], #16
+ stp x3, x4, [x0], #16
+#endif
+ /* Returns */
+ b save_boot_params_ret
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
new file mode 100644
index 00000000000..d905fe76c91
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/armv8/mmu.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <env_internal.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/bitops.h>
+#include <asm/setup.h>
+#include <asm/bootm.h>
+#include <asm/arch-imx/cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_cpu_rev(void)
+{
+ return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
+}
+
+static struct mm_region imx93_mem_map[] = {
+ {
+ /* ROM */
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x100000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* OCRAM */
+ .virt = 0x20480000UL,
+ .phys = 0x20480000UL,
+ .size = 0xA0000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* AIPS */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Flexible Serial Peripheral Interface */
+ .virt = 0x28000000UL,
+ .phys = 0x28000000UL,
+ .size = 0x30000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* DRAM1 */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = PHYS_SDRAM_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* empty entrie to split table entry 5 if needed when TEEs are used */
+ 0,
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = imx93_mem_map;
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ mac[0] = 0x1;
+ mac[1] = 0x2;
+ mac[2] = 0x3;
+ mac[3] = 0x4;
+ mac[4] = 0x5;
+ mac[5] = 0x6;
+}
+
+int print_cpuinfo(void)
+{
+ u32 cpurev;
+
+ cpurev = get_cpu_rev();
+
+ printf("CPU: i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
+
+ return 0;
+}
+
+int arch_misc_init(void)
+{
+ return 0;
+}
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ return 0;
+}
+
+int arch_cpu_init(void)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index e5ad993b8d9..ef00969a5e0 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -147,7 +147,7 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_NONE;
}
-#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMX9)
/* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
u32 spl_boot_device(void)
{
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 10/49] fsl_lpuart: add i.MX9 support
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (8 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 09/49] imx: add basic i.MX9 support Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 11/49] gpio: pca953x: support pcal6524 Peng Fan (OSS)
` (39 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
i.MX9 shares same register layout as i.MX7ULP, so
add the i.MX9 define here.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
include/fsl_lpuart.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index 18e5cc15d61..93c996b764b 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -5,7 +5,7 @@
*/
#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
- defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP)
+ defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP) || defined(CONFIG_ARCH_IMX9)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 11/49] gpio: pca953x: support pcal6524
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (9 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 10/49] fsl_lpuart: add " Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 12/49] imx: pinctrl: add pinctrl and pinfunc file for i.MX93 Peng Fan (OSS)
` (38 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Support pcal6524 IO expander driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/gpio/pca953x_gpio.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index e98e1e56dbc..4654f9e0989 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -43,6 +43,8 @@
#define PCA_GPIO_MASK 0x00FF
#define PCA_INT 0x0100
+#define PCA_PCAL BIT(9)
+#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
#define PCA953X_TYPE 0x1000
#define PCA957X_TYPE 0x2000
#define PCA_TYPE_MASK 0xF000
@@ -393,6 +395,8 @@ static const struct udevice_id pca953x_ids[] = {
{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+ { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
+
{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 12/49] imx: pinctrl: add pinctrl and pinfunc file for i.MX93
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (10 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 11/49] gpio: pca953x: support pcal6524 Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 13/49] imx: imx9: Add CCM and clock API support Peng Fan (OSS)
` (37 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add the pinctrl driver and pinfunc header file to support iMX93
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/dts/imx93-pinfunc.h | 625 ++++++++++++++++++++++++++++
drivers/pinctrl/nxp/Kconfig | 13 +
drivers/pinctrl/nxp/Makefile | 1 +
drivers/pinctrl/nxp/pinctrl-imx93.c | 37 ++
4 files changed, 676 insertions(+)
create mode 100644 arch/arm/dts/imx93-pinfunc.h
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx93.c
diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h
new file mode 100644
index 00000000000..7f0136c70b6
--- /dev/null
+++ b/arch/arm/dts/imx93-pinfunc.h
@@ -0,0 +1,625 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __DTS_IMX93_PINFUNC_H
+#define __DTS_IMX93_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03E0 0x0 0x0
+#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
+#define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
+#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x03CC 0x5 0x0
+#define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0438 0x6 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03E4 0x0 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x03D0 0x5 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03DC 0x0 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x0434 0x6 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x043C 0x6 0x0
+#define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03EC 0x1 0x0
+#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x043C 0x5 0x1
+#define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03F4 0x6 0x0
+#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0
+#define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E8 0x1 0x0
+#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0438 0x5 0x1
+#define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03F0 0x6 0x0
+#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0
+#define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x0434 0x5 0x1
+#define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03FC 0x6 0x0
+#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0
+#define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F8 0x6 0x0
+#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0
+#define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03FC 0x6 0x1
+#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0
+#define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0440 0x2 0x0
+#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F8 0x6 0x1
+#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0
+#define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x0444 0x2 0x0
+#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x0404 0x6 0x0
+#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0
+#define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x0400 0x6 0x0
+#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0
+#define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x0404 0x6 0x1
+#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0
+#define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x0400 0x6 0x1
+#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0
+#define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x040C 0x6 0x0
+#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0
+#define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0408 0x6 0x0
+#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0
+#define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0448 0x2 0x0
+#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x040C 0x6 0x1
+#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0458 0x7 0x0
+#define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x044C 0x2 0x0
+#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0408 0x6 0x1
+#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0
+#define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x0424 0x1 0x0
+#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0430 0x6 0x0
+#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0
+#define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0420 0x1 0x0
+#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x042C 0x6 0x0
+#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0
+#define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0448 0x2 0x1
+#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x041C 0x4 0x0
+#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0428 0x6 0x0
+#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0
+#define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0
+#define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x0454 0x1 0x0
+#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0
+#define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0458 0x1 0x1
+#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x044C 0x2 0x1
+#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0440 0x2 0x1
+#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0
+#define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x0454 0x7 0x1
+#define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0460 0x1 0x0
+#define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x045C 0x2 0x0
+#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03F4 0x6 0x1
+#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0
+#define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x0464 0x1 0x0
+#define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03F0 0x6 0x1
+#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0
+#define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0468 0x1 0x0
+#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0
+#define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x046C 0x1 0x0
+#define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03DC 0x5 0x1
+#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0
+#define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0470 0x1 0x0
+#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x0444 0x2 0x1
+#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03E0 0x5 0x1
+#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x0474 0x1 0x0
+#define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1
+#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03E4 0x5 0x1
+#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0
+#define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03EC 0x1 0x1
+#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E8 0x1 0x1
+#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0
+#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1
+#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO3__GPIO3_IO28 0x0090 0x0240 0x03CC 0x5 0x1
+#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO4__GPIO3_IO29 0x0094 0x0244 0x03D0 0x5 0x1
+#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03D4 0x2 0x0
+#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_MDC__LPUART5_RTS_B 0x0098 0x0248 0x0000 0x6 0x0
+#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D8 0x2 0x0
+#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2
+#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0
+#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x0424 0x1 0x1
+#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0420 0x1 0x1
+#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x041C 0x1 0x1
+#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0410 0x3 0x0
+#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x0414 0x3 0x0
+#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0418 0x3 0x0
+#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0430 0x1 0x1
+#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x042C 0x1 0x1
+#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x045C 0x1 0x1
+#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0428 0x1 0x1
+#define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0
+#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x045C 0x2 0x2
+#define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0
+#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1
+#define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1
+#define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1
+#define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1
+#define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0
+#define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0
+#define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0
+#define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1
+#define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1
+#define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1
+#define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1
+#define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1
+#define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0
+#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1
+#define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0
+#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0
+#define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0
+#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0418 0x2 0x1
+#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0
+#define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0
+#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0
+#define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0460 0x0 0x1
+#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0
+#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1
+#define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0
+#define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x0464 0x0 0x1
+#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0
+#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0
+#define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0468 0x0 0x1
+#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1
+#define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x046C 0x0 0x1
+#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1
+#define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0470 0x0 0x1
+#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1
+#define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x0474 0x0 0x1
+#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1
+#define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03D4 0x2 0x1
+#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1
+#define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK 0x0150 0x0300 0x0000 0x6 0x0
+#define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D8 0x2 0x1
+#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1
+#define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0
+#define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0
+#define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0
+#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1
+#define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1
+#define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3
+#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1
+#define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1
+#define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0410 0x1 0x1
+#define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1
+#define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0
+#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0
+#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x0414 0x1 0x1
+#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1
+#define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0
+#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0
+#define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x0 0x0
+#define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0
+#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0
+#define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0
+#define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0
+#define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x0 0x0
+#define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0
+#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0
+#define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0
+#define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0
+#define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x0 0x0
+#define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0
+#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0
+#define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0
+#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0
+#define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0
+#define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0
+#define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x0 0x0
+#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0
+#define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0
+#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0
+#define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0
+#define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0
+#define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0
+#define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0
+#define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0
+#define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0
+#define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0
+#define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0
+#define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0
+#define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0
+#define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0
+#define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0
+#define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0
+#define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0
+#define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0
+#define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0450 0x4 0x0
+#define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0
+#define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0
+#define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0
+#define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0
+#define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0
+#define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0
+#define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0
+#define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0
+#define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0
+#define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0
+#define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0440 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x0444 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1
+#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1
+#define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0450 0x1 0x1
+#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0
+#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0
+#define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX93_PINFUNC_H */
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 3657e9deb9e..06c26f156f6 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -102,6 +102,19 @@ config PINCTRL_IMX8M
only parses the 'fsl,pins' property and configure related
registers.
+config PINCTRL_IMX93
+ bool "IMX8M pinctrl driver"
+ depends on ARCH_IMX9 && PINCTRL_FULL
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx8m pinctrl driver
+
+ This provides a simple pinctrl driver for i.MX8M SoC familiy.
+ This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configure related
+ registers.
+
config PINCTRL_MXS
bool "NXP MXS pinctrl driver"
depends on ARCH_MX28 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index f2fe0d8efa6..f10aa6ef188 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o
obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX8) += pinctrl-imx8.o
obj-$(CONFIG_PINCTRL_IMX8M) += pinctrl-imx8m.o
+obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_VYBRID) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_IMXRT) += pinctrl-imxrt.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx93.c b/drivers/pinctrl/nxp/pinctrl-imx93.c
new file mode 100644
index 00000000000..9a5b9de6d75
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx93.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imx93_pinctrl_soc_info __section(".data") = {
+ .flags = ZERO_OFFSET_VALID,
+};
+
+static int imx93_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_pinctrl_soc_info *info =
+ (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imx93_pinctrl_match[] = {
+ { .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imx93_pinctrl) = {
+ .name = "imx93-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imx93_pinctrl_match),
+ .probe = imx93_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+ .priv_auto = sizeof(struct imx_pinctrl_priv),
+ .ops = &imx_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 13/49] imx: imx9: Add CCM and clock API support
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (11 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 12/49] imx: pinctrl: add pinctrl and pinfunc file for i.MX93 Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 14/49] mmc: fsl_esdhc_imx: Support i.MX9 Peng Fan (OSS)
` (36 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add clock API to support CCM root clock and LPCG setting
Set the CCM AUTHEN register to allow non-secure world to set
root clock and lpcg.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 ++++++++
arch/arm/include/asm/arch-imx9/clock.h | 239 +++++++
arch/arm/include/asm/arch-imx9/imx-regs.h | 6 +-
arch/arm/mach-imx/imx9/Makefile | 2 +-
arch/arm/mach-imx/imx9/clock.c | 769 +++++++++++++++++++++-
arch/arm/mach-imx/imx9/clock_root.c | 438 ++++++++++++
arch/arm/mach-imx/imx9/soc.c | 3 +
7 files changed, 1720 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx9/ccm_regs.h
create mode 100644 arch/arm/mach-imx/imx9/clock_root.c
diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h
new file mode 100644
index 00000000000..d326a6ea516
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h
@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__
+#define __ASM_ARCH_IMX9_CCM_REGS_H__
+#define IMX93_CLK_ROOT_MAX 95
+#define IMX93_CLK_CCGR_MAX 127
+
+#define ARM_A55_PERIPH_CLK_ROOT 0
+#define ARM_A55_MTR_BUS_CLK_ROOT 1
+#define ARM_A55_CLK_ROOT 2
+#define M33_CLK_ROOT 3
+#define SENTINEL_CLK_ROOT 4
+#define BUS_WAKEUP_CLK_ROOT 5
+#define BUS_AON_CLK_ROOT 6
+#define WAKEUP_AXI_CLK_ROOT 7
+#define SWO_TRACE_CLK_ROOT 8
+#define M33_SYSTICK_CLK_ROOT 9
+#define FLEXIO1_CLK_ROOT 10
+#define FLEXIO2_CLK_ROOT 11
+#define LPIT1_CLK_ROOT 12
+#define LPIT2_CLK_ROOT 13
+#define LPTMR1_CLK_ROOT 14
+#define LPTMR2_CLK_ROOT 15
+#define TPM1_CLK_ROOT 16
+#define TPM2_CLK_ROOT 17
+#define TPM3_CLK_ROOT 18
+#define TPM4_CLK_ROOT 19
+#define TPM5_CLK_ROOT 20
+#define TPM6_CLK_ROOT 21
+#define FLEXSPI1_CLK_ROOT 22
+#define CAN1_CLK_ROOT 23
+#define CAN2_CLK_ROOT 24
+#define LPUART1_CLK_ROOT 25
+#define LPUART2_CLK_ROOT 26
+#define LPUART3_CLK_ROOT 27
+#define LPUART4_CLK_ROOT 28
+#define LPUART5_CLK_ROOT 29
+#define LPUART6_CLK_ROOT 30
+#define LPUART7_CLK_ROOT 31
+#define LPUART8_CLK_ROOT 32
+#define LPI2C1_CLK_ROOT 33
+#define LPI2C2_CLK_ROOT 34
+#define LPI2C3_CLK_ROOT 35
+#define LPI2C4_CLK_ROOT 36
+#define LPI2C5_CLK_ROOT 37
+#define LPI2C6_CLK_ROOT 38
+#define LPI2C7_CLK_ROOT 39
+#define LPI2C8_CLK_ROOT 40
+#define LPSPI1_CLK_ROOT 41
+#define LPSPI2_CLK_ROOT 42
+#define LPSPI3_CLK_ROOT 43
+#define LPSPI4_CLK_ROOT 44
+#define LPSPI5_CLK_ROOT 45
+#define LPSPI6_CLK_ROOT 46
+#define LPSPI7_CLK_ROOT 47
+#define LPSPI8_CLK_ROOT 48
+#define I3C1_CLK_ROOT 49
+#define I3C2_CLK_ROOT 50
+#define USDHC1_CLK_ROOT 51
+#define USDHC2_CLK_ROOT 52
+#define USDHC3_CLK_ROOT 53
+#define SAI1_CLK_ROOT 54
+#define SAI2_CLK_ROOT 55
+#define SAI3_CLK_ROOT 56
+#define CCM_CKO1_CLK_ROOT 57
+#define CCM_CKO2_CLK_ROOT 58
+#define CCM_CKO3_CLK_ROOT 59
+#define CCM_CKO4_CLK_ROOT 60
+#define HSIO_CLK_ROOT 61
+#define HSIO_USB_TEST_60M_CLK_ROOT 62
+#define HSIO_ACSCAN_80M_CLK_ROOT 63
+#define HSIO_ACSCAN_480M_CLK_ROOT 64
+#define NIC_CLK_ROOT 65
+#define NIC_APB_CLK_ROOT 66
+#define ML_APB_CLK_ROOT 67
+#define ML_CLK_ROOT 68
+#define MEDIA_AXI_CLK_ROOT 69
+#define MEDIA_APB_CLK_ROOT 70
+#define MEDIA_LDB_CLK_ROOT 71
+#define MEDIA_DISP_PIX_CLK_ROOT 72
+#define CAM_PIX_CLK_ROOT 73
+#define MIPI_TEST_BYTE_CLK_ROOT 74
+#define MIPI_PHY_CFG_CLK_ROOT 75
+#define DRAM_ALT_CLK_ROOT 76
+#define DRAM_APB_CLK_ROOT 77
+#define ADC_CLK_ROOT 78
+#define PDM_CLK_ROOT 79
+#define TSTMR1_CLK_ROOT 80
+#define TSTMR2_CLK_ROOT 81
+#define MQS1_CLK_ROOT 82
+#define MQS2_CLK_ROOT 83
+#define AUDIO_XCVR_CLK_ROOT 84
+#define SPDIF_CLK_ROOT 85
+#define ENET_CLK_ROOT 86
+#define ENET_TIMER1_CLK_ROOT 87
+#define ENET_TIMER2_CLK_ROOT 88
+#define ENET_REF_CLK_ROOT 89
+#define ENET_REF_PHY_CLK_ROOT 90
+#define I3C1_SLOW_CLK_ROOT 91
+#define I3C2_SLOW_CLK_ROOT 92
+#define USB_PHY_BURUNIN_CLK_ROOT 93
+#define PAL_CAME_SCAN_CLK_ROOT 94
+#define CLK_ROOT_NUM 95
+
+#define CCGR_A55 0
+#define CCGR_CM33 1
+#define CCGR_ARMTROUT 2
+#define CCGR_SENT 3
+#define CCGR_BUSM 4
+#define CCGR_BUS7 5
+#define CCGR_BUSD 6
+#define CCGR_ANAD 7
+#define CCGR_SRC 8
+#define CCGR_CCM 9
+#define CCGR_GPC 10
+#define CCGR_ADC 11
+#define CCGR_WDG1 12
+#define CCGR_WDG2 13
+#define CCGR_WDG3 14
+#define CCGR_WDG4 15
+#define CCGR_WDG5 16
+#define CCGR_SEM1 17
+#define CCGR_SEM2 18
+#define CCGR_MUA 19
+#define CCGR_MUB 20
+#define CCGR_DMA1 21
+#define CCGR_DMA2 22
+#define CCGR_ROMCA55 23
+#define CCGR_ROMCM33 24
+#define CCGR_QSP1 25
+#define CCGR_AONRDC 26
+#define CCGR_WKUPRDC 27
+#define CCGR_FUSE 28
+#define CCGR_SNVH 29
+#define CCGR_SNVS 30
+#define CCGR_TRAC 31
+#define CCGR_SWO 32
+#define CCGR_IOCG 33
+#define CCGR_PIO1 34
+#define CCGR_PIO2 35
+#define CCGR_PIO3 36
+#define CCGR_PIO4 37
+#define CCGR_FIO1 38
+#define CCGR_FIO2 39
+#define CCGR_PIT1 40
+#define CCGR_PIT2 41
+#define CCGR_GPT1 42
+#define CCGR_GPT2 43
+#define CCGR_TPM1 44
+#define CCGR_TPM2 45
+#define CCGR_TPM3 46
+#define CCGR_TPM4 47
+#define CCGR_TPM5 48
+#define CCGR_TPM6 49
+#define CCGR_CAN1 50
+#define CCGR_CAN2 51
+#define CCGR_URT1 52
+#define CCGR_URT2 53
+#define CCGR_URT3 54
+#define CCGR_URT4 55
+#define CCGR_URT5 56
+#define CCGR_URT6 57
+#define CCGR_URT7 58
+#define CCGR_URT8 59
+#define CCGR_I2C1 60
+#define CCGR_I2C2 61
+#define CCGR_I2C3 62
+#define CCGR_I2C4 63
+#define CCGR_I2C5 64
+#define CCGR_I2C6 65
+#define CCGR_I2C7 66
+#define CCGR_I2C8 67
+#define CCGR_SPI1 68
+#define CCGR_SPI2 69
+#define CCGR_SPI3 70
+#define CCGR_SPI4 71
+#define CCGR_SPI5 72
+#define CCGR_SPI6 73
+#define CCGR_SPI7 74
+#define CCGR_SPI8 75
+#define CCGR_I3C1 76
+#define CCGR_I3C2 77
+#define CCGR_USDHC1 78
+#define CCGR_USDHC2 79
+#define CCGR_USDHC3 80
+#define CCGR_SAI1 81
+#define CCGR_SAI2 82
+#define CCGR_SAI3 83
+#define CCGR_W2AO 84
+#define CCGR_AO2W 85
+#define CCGR_MIPIC 86
+#define CCGR_MIPID 87
+#define CCGR_LVDS 88
+#define CCGR_LCDIF 89
+#define CCGR_PXP 90
+#define CCGR_ISI 91
+#define CCGR_NMED 92
+#define CCGR_DFI 93
+#define CCGR_DDRC 94
+#define CCGR_DFIC 95
+#define CCGR_DSSI 96
+#define CCGR_DBYP 97
+#define CCGR_DAPB 98
+#define CCGR_DRAMP 99
+#define CCGR_DCLKC 100
+#define CCGR_NCTL 101
+#define CCGR_GIC 102
+#define CCGR_NICAPB 103
+#define CCGR_USBC 104
+#define CCGR_USBT 105
+#define CCGR_HSIO 106
+#define CCGR_PDM 107
+#define CCGR_MQS1 108
+#define CCGR_MQS2 109
+#define CCGR_AXCVR 110
+#define CCGR_MECC 111
+#define CCGR_SPDIF 112
+#define CCGR_ML2NIC 113
+#define CCGR_MED2NIC 114
+#define CCGR_HSIO2NIC 115
+#define CCGR_W2NIC 116
+#define CCGR_NIC2W 117
+#define CCGR_NIC2DDR 118
+#define CCGR_HSIO32K 119
+#define CCGR_ENET1 120
+#define CCGR_ENETQOS 121
+#define CCGR_SYSCNT 122
+#define CCGR_TSTMR1 123
+#define CCGR_TSTMR2 124
+#define CCGR_TMC 125
+#define CCGR_PMRO 126
+#define CCGR_NUM 127
+
+#define SHARED_GPR_EXT_CLK 0
+#define SHARED_GPR_EXT_CLK_SEL_EXT1 0
+#define SHARED_GPR_EXT_CLK_SEL_EXT2 BIT(0)
+#define SHARED_GPR_EXT_CLK_SEL_EXT3 BIT(1)
+#define SHARED_GPR_EXT_CLK_SEL_EXT4 GENMASK(1, 0)
+
+#define SHARED_GPR_A55_CLK 1
+#define SHARED_GPR_A55_CLK_SEL_CCM 0
+#define SHARED_GPR_A55_CLK_SEL_PLL BIT(0)
+
+#define SHARED_GPR_DRAM_CLK 2
+#define SHARED_GPR_DRAM_CLK_SEL_PLL 0
+#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0)
+
+#define SHARED_GPR_NUM 8
+#define PRIVATE_GPR_NUM 8
+
+#define CLK_ROOT_STATUS_OFF BIT(24)
+#define CLK_ROOT_STATUS_CHANGING BIT(31)
+#define CLK_ROOT_MUX_MASK GENMASK(9, 8)
+#define CLK_ROOT_MUX_SHIFT 8
+#define CLK_ROOT_DIV_MASK GENMASK(7, 0)
+
+#define CCM_AUTHEN_LOCK_TZ BIT(11)
+#define CCM_AUTHEN_TZ_NS BIT(9)
+#define CCM_AUTHEN_TZ_USER BIT(8)
+#define CCM_AUTHEN_CPULPM_MODE BIT(2)
+#define CCM_AUTHEN_AUTO_CTRL BIT(3)
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
index e69de29bb2d..fcf04d66f05 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan at nxp.com>
+ */
+
+#ifndef __CLOCK_IMX9__
+#define __CLOCK_IMX9__
+
+#include <linux/bitops.h>
+
+#define MHZ(x) ((x) * 1000000UL)
+
+enum enet_freq {
+ ENET_25MHZ = 0,
+ ENET_50MHZ,
+ ENET_125MHZ,
+};
+
+enum ccm_clk_src {
+ OSC_24M_CLK,
+ ARM_PLL,
+ ARM_PLL_CLK,
+ SYS_PLL_PG,
+ SYS_PLL_PFD0_PG,
+ SYS_PLL_PFD0,
+ SYS_PLL_PFD0_DIV2,
+ SYS_PLL_PFD1_PG,
+ SYS_PLL_PFD1,
+ SYS_PLL_PFD1_DIV2,
+ SYS_PLL_PFD2_PG,
+ SYS_PLL_PFD2,
+ SYS_PLL_PFD2_DIV2,
+ AUDIO_PLL,
+ AUDIO_PLL_CLK,
+ DRAM_PLL,
+ DRAM_PLL_CLK,
+ VIDEO_PLL,
+ VIDEO_PLL_CLK,
+ OSCPLL_END,
+ EXT_CLK,
+};
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_IPG_CLK,
+ MXC_FLEXSPI_CLK,
+ MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_UART_CLK,
+ MXC_I2C_CLK,
+ MXC_FEC_CLK,
+};
+
+struct ccm_obs {
+ u32 direct;
+ u32 reserved[31];
+};
+
+struct ccm_gpr {
+ u32 gpr;
+ u32 gpr_set;
+ u32 gpr_clr;
+ u32 gpr_tog;
+ u32 authen;
+ u32 authen_set;
+ u32 authen_clr;
+ u32 authen_tog;
+};
+
+struct ccm_lpcg_oscpll {
+ u32 direct;
+ u32 lpm_status0;
+ u32 lpm_status1;
+ u32 reserved0;
+ u32 lpm0;
+ u32 lpm1;
+ u32 reserved1;
+ u32 lpm_cur;
+ u32 status0;
+ u32 status1;
+ u32 reserved2[2];
+ u32 authen;
+ u32 reserved3[3];
+};
+
+struct ccm_root {
+ u32 control;
+ u32 control_set;
+ u32 control_clr;
+ u32 control_tog;
+ u32 reserved[4];
+ u32 status0;
+ u32 reserved1[3];
+ u32 authen;
+ u32 reserved2[19];
+};
+
+struct ccm_reg {
+ struct ccm_root clk_roots[95]; /* 0x0 */
+ u32 reserved_0[1312];
+ struct ccm_obs clk_obs[6]; /* 0x4400 */
+ u32 reserved_1[64];
+ struct ccm_gpr clk_shared_gpr[8]; /* 0x4800 */
+ u32 reserved_2[192];
+ struct ccm_gpr clk_private_gpr[8]; /* 0x4C00 */
+ u32 reserved_3[192];
+ struct ccm_lpcg_oscpll clk_oscplls[19]; /* 0x5000 */
+ u32 reserved_4[2768];
+ struct ccm_lpcg_oscpll clk_lpcgs[122]; /* 0x8000 */
+};
+
+struct ana_pll_reg_elem {
+ u32 reg;
+ u32 reg_set;
+ u32 reg_clr;
+ u32 reg_tog;
+};
+
+struct ana_pll_dfs {
+ struct ana_pll_reg_elem dfs_ctrl;
+ struct ana_pll_reg_elem dfs_div;
+};
+
+struct ana_pll_reg {
+ struct ana_pll_reg_elem ctrl;
+ struct ana_pll_reg_elem ana_prg;
+ struct ana_pll_reg_elem test;
+ struct ana_pll_reg_elem ss; /* Spread spectrum */
+ struct ana_pll_reg_elem num; /* numerator */
+ struct ana_pll_reg_elem denom; /* demoninator */
+ struct ana_pll_reg_elem div;
+ struct ana_pll_dfs dfs[4];
+ u32 pll_status;
+ u32 dfs_status;
+ u32 reserved[2];
+};
+
+struct anatop_reg {
+ u32 osc_ctrl;
+ u32 osc_state;
+ u32 reserved_0[510];
+ u32 chip_version;
+ u32 reserved_1[511];
+ struct ana_pll_reg arm_pll;
+ struct ana_pll_reg sys_pll;
+ struct ana_pll_reg audio_pll;
+ struct ana_pll_reg dram_pll;
+ struct ana_pll_reg video_pll;
+};
+
+#define PLL_CTRL_HW_CTRL_SEL BIT(16)
+#define PLL_CTRL_CLKMUX_BYPASS BIT(2)
+#define PLL_CTRL_CLKMUX_EN BIT(1)
+#define PLL_CTRL_POWERUP BIT(0)
+
+#define PLL_STATUS_PLL_LOCK BIT(0)
+#define PLL_DFS_CTRL_ENABLE BIT(31)
+#define PLL_DFS_CTRL_CLKOUT BIT(30)
+#define PLL_DFS_CTRL_CLKOUT_DIV2 BIT(29)
+#define PLL_DFS_CTRL_BYPASS BIT(23)
+
+#define PLL_SS_EN BIT(15)
+
+struct imx_intpll_rate_table {
+ u32 rate; /*khz*/
+ int rdiv;
+ int mfi;
+ int odiv;
+};
+
+struct imx_fracpll_rate_table {
+ u32 rate; /*khz*/
+ int rdiv;
+ int mfi;
+ int odiv;
+ int mfn;
+ int mfd;
+};
+
+#define INT_PLL_RATE(_rate, _r, _m, _o) \
+ { \
+ .rate = (_rate), \
+ .rdiv = (_r), \
+ .mfi = (_m), \
+ .odiv = (_o), \
+ }
+
+#define FRAC_PLL_RATE(_rate, _r, _m, _o, _n, _d) \
+ { \
+ .rate = (_rate), \
+ .rdiv = (_r), \
+ .mfi = (_m), \
+ .odiv = (_o), \
+ .mfn = (_n), \
+ .mfd = (_d), \
+ }
+
+struct clk_root_map {
+ u32 clk_root_id;
+ u32 mux_type;
+};
+
+int clock_init(void);
+u32 get_clk_src_rate(enum ccm_clk_src source);
+u32 get_lpuart_clk(void);
+void init_uart_clk(u32 index);
+void init_clk_usdhc(u32 index);
+int enable_i2c_clk(unsigned char enable, u32 i2c_num);
+u32 imx_get_i2cclk(u32 i2c_num);
+u32 mxc_get_clock(enum mxc_clock clk);
+
+int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
+int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
+int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
+int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val);
+bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll);
+int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, bool non_secure, bool user_mode, bool lock_tz);
+int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div);
+u32 ccm_clk_root_get_rate(u32 clk_root_id);
+int ccm_clk_root_tz_access(u32 clk_root_id, bool non_secure, bool user_mode, bool lock_tz);
+int ccm_lpcg_on(u32 lpcg, bool enable);
+int ccm_lpcg_lpm(u32 lpcg, bool enable);
+int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val);
+bool ccm_lpcg_is_clk_on(u32 lpcg);
+int ccm_lpcg_tz_access(u32 lpcg, bool non_secure, bool user_mode, bool lock_tz);
+int ccm_shared_gpr_set(u32 gpr, u32 val);
+int ccm_shared_gpr_get(u32 gpr, u32 *val);
+int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock_tz);
+
+void enable_usboh3_clk(unsigned char enable);
+int set_clk_enet(enum enet_freq type);
+int set_clk_eqos(enum enet_freq type);
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 2adbdadf03c..50ec902987d 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -8,6 +8,10 @@
#define ARCH_MXC
-#define IOMUXC_BASE_ADDR 0x443C0000UL
+#define IOMUXC_BASE_ADDR 0x443C0000UL
+#define CCM_BASE_ADDR 0x44450000UL
+#define CCM_CCGR_BASE_ADDR 0x44458000UL
+
+#define ANATOP_BASE_ADDR 0x44480000UL
#endif
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 773b12ee129..7be0343d52e 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -3,4 +3,4 @@
# Copyright 2022 NXP
obj-y += lowlevel_init.o
-obj-y += soc.o clock.o
+obj-y += soc.o clock.o clock_root.o
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index fe89dccb316..55cbb40f328 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -9,6 +9,7 @@
#include <command.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/ccm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/io.h>
@@ -20,8 +21,774 @@
DECLARE_GLOBAL_DATA_PTR;
+static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR;
+
+static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
+ INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */
+ INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */
+ INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
+ INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
+ INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
+};
+
+static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
+ FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
+ FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
+ FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
+ FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
+ FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
+};
+
+/* return in khz */
+static u32 decode_pll_vco(struct ana_pll_reg *reg, bool fracpll)
+{
+ u32 ctrl;
+ u32 pll_status;
+ u32 div;
+ int rdiv, mfi, mfn, mfd;
+ int clk = 24000;
+
+ ctrl = readl(®->ctrl.reg);
+ pll_status = readl(®->pll_status);
+ div = readl(®->div.reg);
+
+ if (!(ctrl & PLL_CTRL_POWERUP))
+ return 0;
+
+ if (!(pll_status & PLL_STATUS_PLL_LOCK))
+ return 0;
+
+ mfi = (div & GENMASK(24, 16)) >> 16;
+ rdiv = (div & GENMASK(15, 13)) >> 13;
+
+ if (rdiv == 0)
+ rdiv = 1;
+
+ if (fracpll) {
+ mfn = (int)readl(®->num.reg);
+ mfn >>= 2;
+ mfd = (int)(readl(®->denom.reg) & GENMASK(29, 0));
+
+ clk = clk * (mfi * mfd + mfn) / mfd / rdiv;
+ } else {
+ clk = clk * mfi / rdiv;
+ }
+
+ return (u32)clk;
+}
+
+/* return in khz */
+static u32 decode_pll_out(struct ana_pll_reg *reg, bool fracpll)
+{
+ u32 ctrl = readl(®->ctrl.reg);
+ u32 div;
+
+ if (ctrl & PLL_CTRL_CLKMUX_BYPASS)
+ return 24000;
+
+ if (!(ctrl & PLL_CTRL_CLKMUX_EN))
+ return 0;
+
+ div = readl(®->div.reg);
+ div &= 0xff; /* odiv */
+
+ if (div == 0)
+ div = 2;
+ else if (div == 1)
+ div = 3;
+
+ return decode_pll_vco(reg, fracpll) / div;
+}
+
+/* return in khz */
+static u32 decode_pll_pfd(struct ana_pll_reg *reg, struct ana_pll_dfs *dfs_reg,
+ bool div2, bool fracpll)
+{
+ u32 pllvco = decode_pll_vco(reg, fracpll);
+ u32 dfs_ctrl = readl(&dfs_reg->dfs_ctrl.reg);
+ u32 dfs_div = readl(&dfs_reg->dfs_div.reg);
+ u32 mfn, mfi;
+ u32 output;
+
+ if (dfs_ctrl & PLL_DFS_CTRL_BYPASS)
+ return pllvco;
+
+ if (!(dfs_ctrl & PLL_DFS_CTRL_ENABLE) ||
+ (div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT_DIV2)) ||
+ (!div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT)))
+ return 0;
+
+ mfn = dfs_div & GENMASK(2, 0);
+ mfi = (dfs_div & GENMASK(15, 8)) >> 8;
+
+ if (mfn > 3)
+ return 0; /* valid mfn 0-3 */
+
+ if (mfi == 0 || mfi == 1)
+ return 0; /* valid mfi 2-255 */
+
+ output = (pllvco * 5) / (mfi * 5 + mfn);
+
+ if (div2)
+ return output >> 1;
+
+ return output;
+}
+
+static u32 decode_pll(enum ccm_clk_src pll)
+{
+ switch (pll) {
+ case ARM_PLL_CLK:
+ return decode_pll_out(&ana_regs->arm_pll, false);
+ case SYS_PLL_PG:
+ return decode_pll_out(&ana_regs->sys_pll, false);
+ case SYS_PLL_PFD0:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[0], false, true);
+ case SYS_PLL_PFD0_DIV2:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[0], true, true);
+ case SYS_PLL_PFD1:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[1], false, true);
+ case SYS_PLL_PFD1_DIV2:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[1], true, true);
+ case SYS_PLL_PFD2:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[2], false, true);
+ case SYS_PLL_PFD2_DIV2:
+ return decode_pll_pfd(&ana_regs->sys_pll,
+ &ana_regs->sys_pll.dfs[2], true, true);
+ case AUDIO_PLL_CLK:
+ return decode_pll_out(&ana_regs->audio_pll, true);
+ case DRAM_PLL_CLK:
+ return decode_pll_out(&ana_regs->dram_pll, true);
+ case VIDEO_PLL_CLK:
+ return decode_pll_out(&ana_regs->video_pll, true);
+ default:
+ printf("Invalid clock source to decode\n");
+ break;
+ }
+
+ return 0;
+}
+
+int configure_intpll(enum ccm_clk_src pll, u32 freq)
+{
+ int i;
+ struct imx_intpll_rate_table *rate;
+ struct ana_pll_reg *reg;
+ u32 pll_status;
+
+ for (i = 0; i < ARRAY_SIZE(imx9_intpll_tbl); i++) {
+ if (freq == imx9_intpll_tbl[i].rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx9_intpll_tbl)) {
+ debug("No matched freq table %u\n", freq);
+ return -EINVAL;
+ }
+
+ rate = &imx9_intpll_tbl[i];
+
+ /* ROM has configured SYS PLL and PFD, no need for it */
+ switch (pll) {
+ case ARM_PLL_CLK:
+ reg = &ana_regs->arm_pll;
+ break;
+ default:
+ return -EPERM;
+ }
+
+ /* Bypass the PLL to ref */
+ writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_set);
+
+ /* disable pll and output */
+ writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, ®->ctrl.reg_clr);
+
+ /* Program the ODIV, RDIV, MFI */
+ writel((rate->odiv & GENMASK(7, 0)) | ((rate->rdiv << 13) & GENMASK(15, 13)) |
+ ((rate->mfi << 16) & GENMASK(24, 16)), ®->div.reg);
+
+ /* wait 5us */
+ udelay(5);
+
+ /* power up the PLL and wait lock (max wait time 100 us) */
+ writel(PLL_CTRL_POWERUP, ®->ctrl.reg_set);
+
+ udelay(100);
+
+ pll_status = readl(®->pll_status);
+ if (pll_status & PLL_STATUS_PLL_LOCK) {
+ writel(PLL_CTRL_CLKMUX_EN, ®->ctrl.reg_set);
+
+ /* clear bypass */
+ writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_clr);
+
+ } else {
+ debug("Fail to lock PLL %u\n", pll);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+int configure_fracpll(enum ccm_clk_src pll, u32 freq)
+{
+ struct imx_fracpll_rate_table *rate;
+ struct ana_pll_reg *reg;
+ u32 pll_status;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) {
+ if (freq == imx9_fracpll_tbl[i].rate)
+ break;
+ }
+
+ if (i == ARRAY_SIZE(imx9_fracpll_tbl)) {
+ debug("No matched freq table %u\n", freq);
+ return -EINVAL;
+ }
+
+ rate = &imx9_fracpll_tbl[i];
+
+ switch (pll) {
+ case SYS_PLL_PG:
+ reg = &ana_regs->sys_pll;
+ break;
+ case DRAM_PLL_CLK:
+ reg = &ana_regs->dram_pll;
+ break;
+ case VIDEO_PLL_CLK:
+ reg = &ana_regs->video_pll;
+ break;
+ default:
+ return -EPERM;
+ }
+
+ /* Bypass the PLL to ref */
+ writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_set);
+
+ /* disable pll and output */
+ writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, ®->ctrl.reg_clr);
+
+ /* Program the ODIV, RDIV, MFI */
+ writel((rate->odiv & GENMASK(7, 0)) | ((rate->rdiv << 13) & GENMASK(15, 13)) |
+ ((rate->mfi << 16) & GENMASK(24, 16)), ®->div.reg);
+
+ /* Set SPREAD_SPECRUM enable to 0 */
+ writel(PLL_SS_EN, ®->ss.reg_clr);
+
+ /* Program NUMERATOR and DENOMINATOR */
+ writel((rate->mfn << 2), ®->num.reg);
+ writel((rate->mfd & GENMASK(29, 0)), ®->denom.reg);
+
+ /* wait 5us */
+ udelay(5);
+
+ /* power up the PLL and wait lock (max wait time 100 us) */
+ writel(PLL_CTRL_POWERUP, ®->ctrl.reg_set);
+
+ udelay(100);
+
+ pll_status = readl(®->pll_status);
+ if (pll_status & PLL_STATUS_PLL_LOCK) {
+ writel(PLL_CTRL_CLKMUX_EN, ®->ctrl.reg_set);
+
+ /* check the MFN is updated */
+ pll_status = readl(®->pll_status);
+ if ((pll_status & ~0x3) != (rate->mfn << 2)) {
+ debug("MFN update not matched, pll_status 0x%x, mfn 0x%x\n",
+ pll_status, rate->mfn);
+ return -EIO;
+ }
+
+ /* clear bypass */
+ writel(PLL_CTRL_CLKMUX_BYPASS, ®->ctrl.reg_clr);
+
+ } else {
+ debug("Fail to lock PLL %u\n", pll);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+int configure_pll_pfd(enum ccm_clk_src pll_pfg, u32 mfi, u32 mfn, bool div2_en)
+{
+ struct ana_pll_dfs *dfs;
+ struct ana_pll_reg *reg;
+ u32 dfs_status;
+ u32 index;
+
+ if (mfn > 3)
+ return -EINVAL; /* valid mfn 0-3 */
+
+ if (mfi < 2 || mfi > 255)
+ return -EINVAL; /* valid mfi 2-255 */
+
+ switch (pll_pfg) {
+ case SYS_PLL_PFD0:
+ reg = &ana_regs->sys_pll;
+ index = 0;
+ break;
+ case SYS_PLL_PFD1:
+ reg = &ana_regs->sys_pll;
+ index = 1;
+ break;
+ case SYS_PLL_PFD2:
+ reg = &ana_regs->sys_pll;
+ index = 2;
+ break;
+ default:
+ return -EPERM;
+ }
+
+ dfs = ®->dfs[index];
+
+ /* Bypass the DFS to PLL VCO */
+ writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_set);
+
+ /* disable DFS and output */
+ writel(PLL_DFS_CTRL_ENABLE | PLL_DFS_CTRL_CLKOUT |
+ PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_clr);
+
+ writel(((mfi << 8) & GENMASK(15, 8)) | (mfn & GENMASK(2, 0)), &dfs->dfs_div.reg);
+
+ writel(PLL_DFS_CTRL_CLKOUT, &dfs->dfs_ctrl.reg_set);
+ if (div2_en)
+ writel(PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_set);
+ writel(PLL_DFS_CTRL_ENABLE, &dfs->dfs_ctrl.reg_set);
+
+ /*
+ * As HW expert said: after enabling the DFS, clock will start
+ * coming after 6 cycles output clock period.
+ * 5us is much bigger than expected, so it will be safe
+ */
+ udelay(5);
+
+ dfs_status = readl(®->dfs_status);
+
+ if (!(dfs_status & (1 << index))) {
+ debug("DFS lock failed\n");
+ return -EIO;
+ }
+
+ /* Bypass the DFS to PLL VCO */
+ writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_clr);
+
+ return 0;
+}
+
+int update_fracpll_mfn(enum ccm_clk_src pll, int mfn)
+{
+ struct ana_pll_reg *reg;
+ bool repoll = false;
+ u32 pll_status;
+ int count = 20;
+
+ switch (pll) {
+ case AUDIO_PLL_CLK:
+ reg = &ana_regs->audio_pll;
+ break;
+ case DRAM_PLL_CLK:
+ reg = &ana_regs->dram_pll;
+ break;
+ case VIDEO_PLL_CLK:
+ reg = &ana_regs->video_pll;
+ break;
+ default:
+ printf("Invalid pll %u for update FRAC PLL MFN\n", pll);
+ return -EINVAL;
+ }
+
+ if (readl(®->pll_status) & PLL_STATUS_PLL_LOCK)
+ repoll = true;
+
+ mfn <<= 2;
+ writel(mfn, ®->num);
+
+ if (repoll) {
+ do {
+ pll_status = readl(®->pll_status);
+ udelay(5);
+ count--;
+ } while (((pll_status & ~0x3) != (u32)mfn) && count > 0);
+
+ if (count <= 0) {
+ printf("update MFN timeout, pll_status 0x%x, mfn 0x%x\n", pll_status, mfn);
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+int update_pll_pfd_mfn(enum ccm_clk_src pll_pfd, u32 mfn)
+{
+ struct ana_pll_dfs *dfs;
+ u32 val;
+ u32 index;
+
+ switch (pll_pfd) {
+ case SYS_PLL_PFD0:
+ case SYS_PLL_PFD0_DIV2:
+ index = 0;
+ break;
+ case SYS_PLL_PFD1:
+ case SYS_PLL_PFD1_DIV2:
+ index = 1;
+ break;
+ case SYS_PLL_PFD2:
+ case SYS_PLL_PFD2_DIV2:
+ index = 2;
+ break;
+ default:
+ printf("Invalid pfd %u for update PLL PFD MFN\n", pll_pfd);
+ return -EINVAL;
+ }
+
+ dfs = &ana_regs->sys_pll.dfs[index];
+
+ val = readl(&dfs->dfs_div.reg);
+ val &= ~0x3;
+ val |= mfn & 0x3;
+ writel(val, &dfs->dfs_div.reg);
+
+ return 0;
+}
+
+/* return in khz */
+u32 get_clk_src_rate(enum ccm_clk_src source)
+{
+ u32 ctrl;
+ bool clk_on;
+
+ switch (source) {
+ case ARM_PLL_CLK:
+ ctrl = readl(&ana_regs->arm_pll.ctrl.reg);
+ case AUDIO_PLL_CLK:
+ ctrl = readl(&ana_regs->audio_pll.ctrl.reg);
+ break;
+ case DRAM_PLL_CLK:
+ ctrl = readl(&ana_regs->dram_pll.ctrl.reg);
+ break;
+ case VIDEO_PLL_CLK:
+ ctrl = readl(&ana_regs->video_pll.ctrl.reg);
+ break;
+ case SYS_PLL_PFD0:
+ case SYS_PLL_PFD0_DIV2:
+ ctrl = readl(&ana_regs->sys_pll.dfs[0].dfs_ctrl.reg);
+ break;
+ case SYS_PLL_PFD1:
+ case SYS_PLL_PFD1_DIV2:
+ ctrl = readl(&ana_regs->sys_pll.dfs[1].dfs_ctrl.reg);
+ break;
+ case SYS_PLL_PFD2:
+ case SYS_PLL_PFD2_DIV2:
+ ctrl = readl(&ana_regs->sys_pll.dfs[2].dfs_ctrl.reg);
+ break;
+ case OSC_24M_CLK:
+ return 24000;
+ default:
+ printf("Invalid clock source to get rate\n");
+ return 0;
+ }
+
+ if (ctrl & PLL_CTRL_HW_CTRL_SEL) {
+ /* When using HW ctrl, check OSCPLL */
+ clk_on = ccm_clk_src_is_clk_on(source);
+ if (clk_on)
+ return decode_pll(source);
+ else
+ return 0;
+ } else {
+ /* controlled by pll registers */
+ return decode_pll(source);
+ }
+}
+
+u32 get_arm_core_clk(void)
+{
+ u32 val;
+
+ ccm_shared_gpr_get(SHARED_GPR_A55_CLK, &val);
+
+ if (val & SHARED_GPR_A55_CLK_SEL_PLL)
+ return decode_pll(ARM_PLL_CLK) * 1000;
+
+ return ccm_clk_root_get_rate(ARM_A55_CLK_ROOT);
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_arm_core_clk();
+ case MXC_IPG_CLK:
+ return ccm_clk_root_get_rate(BUS_WAKEUP_CLK_ROOT);
+ case MXC_CSPI_CLK:
+ return ccm_clk_root_get_rate(LPSPI1_CLK_ROOT);
+ case MXC_ESDHC_CLK:
+ return ccm_clk_root_get_rate(USDHC1_CLK_ROOT);
+ case MXC_ESDHC2_CLK:
+ return ccm_clk_root_get_rate(USDHC2_CLK_ROOT);
+ case MXC_ESDHC3_CLK:
+ return ccm_clk_root_get_rate(USDHC3_CLK_ROOT);
+ case MXC_UART_CLK:
+ return ccm_clk_root_get_rate(LPUART1_CLK_ROOT);
+ case MXC_FLEXSPI_CLK:
+ return ccm_clk_root_get_rate(FLEXSPI1_CLK_ROOT);
+ default:
+ return -1;
+ };
+
+ return -1;
+};
+
+int enable_i2c_clk(unsigned char enable, u32 i2c_num)
+{
+ if (i2c_num > 7)
+ return -EINVAL;
+
+ if (enable) {
+ /* 24M */
+ ccm_lpcg_on(CCGR_I2C1 + i2c_num, false);
+ ccm_clk_root_cfg(LPI2C1_CLK_ROOT + i2c_num, OSC_24M_CLK, 1);
+ ccm_lpcg_on(CCGR_I2C1 + i2c_num, true);
+ } else {
+ ccm_lpcg_on(CCGR_I2C1 + i2c_num, false);
+ }
+
+ return 0;
+}
+
+u32 imx_get_i2cclk(u32 i2c_num)
+{
+ if (i2c_num > 7)
+ return -EINVAL;
+
+ return ccm_clk_root_get_rate(LPUART1_CLK_ROOT + i2c_num);
+}
+
u32 get_lpuart_clk(void)
{
- return 24000000;
+ return mxc_get_clock(MXC_UART_CLK);
+}
+
+void init_uart_clk(u32 index)
+{
+ switch (index) {
+ case LPUART1_CLK_ROOT:
+ /* 24M */
+ ccm_lpcg_on(CCGR_URT1, false);
+ ccm_clk_root_cfg(LPUART1_CLK_ROOT, OSC_24M_CLK, 1);
+ ccm_lpcg_on(CCGR_URT1, true);
+ break;
+ default:
+ break;
+ }
+}
+
+void init_clk_usdhc(u32 index)
+{
+ /* 400 Mhz */
+ switch (index) {
+ case 0:
+ ccm_lpcg_on(CCGR_USDHC1, 0);
+ ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2);
+ ccm_lpcg_on(CCGR_USDHC1, 1);
+ break;
+ case 1:
+ ccm_lpcg_on(CCGR_USDHC2, 0);
+ ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2);
+ ccm_lpcg_on(CCGR_USDHC2, 1);
+ break;
+ case 2:
+ ccm_lpcg_on(CCGR_USDHC3, 0);
+ ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2);
+ ccm_lpcg_on(CCGR_USDHC3, 1);
+ break;
+ default:
+ return;
+ };
}
+void enable_usboh3_clk(unsigned char enable)
+{
+ if (enable) {
+ ccm_clk_root_cfg(HSIO_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ ccm_lpcg_on(CCGR_USBC, 1);
+ } else {
+ ccm_lpcg_on(CCGR_USBC, 0);
+ }
+}
+
+int clock_init(void)
+{
+ int i;
+
+ /* Set A55 periphal to 333M */
+ ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3);
+ /* Set A55 mtr bus to 133M */
+ ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+
+ /* Sentinel to 200M */
+ ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+ /* Bus_wakeup to 133M */
+ ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Bus_AON to 133M */
+ ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* M33 to 200M */
+ ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+ /*
+ * WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
+ * generating MII clock at 2.5M
+ */
+ ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2);
+ /* SWO TRACE to 133M */
+ ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* M33 systetick to 133M */
+ ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* NIC to 400M */
+ ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2);
+ /* NIC_APB to 133M */
+ ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+
+ /* allow for non-secure access */
+ for (i = 0; i < OSCPLL_END; i++)
+ ccm_clk_src_tz_access(i, true, false, false);
+
+ for (i = 0; i < CLK_ROOT_NUM; i++)
+ ccm_clk_root_tz_access(i, true, false, false);
+
+ for (i = 0; i < CCGR_NUM; i++)
+ ccm_lpcg_tz_access(i, true, false, false);
+
+ for (i = 0; i < SHARED_GPR_NUM; i++)
+ ccm_shared_gpr_tz_access(i, true, false, false);
+
+ return 0;
+}
+
+int set_clk_eqos(enum enet_freq type)
+{
+ u32 eqos_post_div;
+
+ switch (type) {
+ case ENET_125MHZ:
+ eqos_post_div = 2; /* 250M clock */
+ break;
+ case ENET_50MHZ:
+ eqos_post_div = 5; /* 100M clock */
+ break;
+ case ENET_25MHZ:
+ eqos_post_div = 10; /* 50M clock*/
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* disable the clock first */
+ ccm_lpcg_on(CCGR_ENETQOS, false);
+
+ ccm_clk_root_cfg(ENET_CLK_ROOT, SYS_PLL_PFD0_DIV2, eqos_post_div);
+ ccm_clk_root_cfg(ENET_TIMER2_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
+
+ /* enable clock */
+ ccm_lpcg_on(CCGR_ENETQOS, true);
+
+ return 0;
+}
+
+u32 imx_get_eqos_csr_clk(void)
+{
+ return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
+}
+
+u32 imx_get_fecclk(void)
+{
+ return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
+}
+
+int set_clk_enet(enum enet_freq type)
+{
+ u32 div;
+
+ /* disable the clock first */
+ ccm_lpcg_on(CCGR_ENET1, false);
+
+ switch (type) {
+ case ENET_125MHZ:
+ div = 2; /* 250Mhz */
+ break;
+ case ENET_50MHZ:
+ div = 5; /* 100Mhz */
+ break;
+ case ENET_25MHZ:
+ div = 10; /* 50Mhz */
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div);
+ ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+ ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20);
+#endif
+
+ /* enable clock */
+ ccm_lpcg_on(CCGR_ENET1, true);
+
+ return 0;
+}
+
+/*
+ * Dump some clockes.
+ */
+#ifndef CONFIG_SPL_BUILD
+int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 freq;
+
+ freq = decode_pll(ARM_PLL_CLK);
+ printf("ARM_PLL %8d MHz\n", freq / 1000);
+ freq = decode_pll(DRAM_PLL_CLK);
+ printf("DRAM_PLL %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD0);
+ printf("SYS_PLL_PFD0 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD0_DIV2);
+ printf("SYS_PLL_PFD0_DIV2 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD1);
+ printf("SYS_PLL_PFD1 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD1_DIV2);
+ printf("SYS_PLL_PFD1_DIV2 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD2);
+ printf("SYS_PLL_PFD2 %8d MHz\n", freq / 1000);
+ freq = decode_pll(SYS_PLL_PFD2_DIV2);
+ printf("SYS_PLL_PFD2_DIV2 %8d MHz\n", freq / 1000);
+ freq = mxc_get_clock(MXC_ARM_CLK);
+ printf("ARM CORE %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_IPG_CLK);
+ printf("IPG %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_UART_CLK);
+ printf("UART3 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_ESDHC_CLK);
+ printf("USDHC1 %8d MHz\n", freq / 1000000);
+ freq = mxc_get_clock(MXC_FLEXSPI_CLK);
+ printf("FLEXSPI %8d MHz\n", freq / 1000000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
+ "display clocks",
+ ""
+);
+#endif
+
diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c
new file mode 100644
index 00000000000..06b93f60996
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/clock_root.c
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/global_data.h>
+#include <linux/iopoll.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+
+static enum ccm_clk_src clk_root_mux[][4] = {
+ { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, SYS_PLL_PFD2 }, /* bus */
+ { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, SYS_PLL_PFD2_DIV2 }, /* non-IO */
+ { OSC_24M_CLK, SYS_PLL_PFD0_DIV2, SYS_PLL_PFD1_DIV2, VIDEO_PLL_CLK }, /* IO*/
+ { OSC_24M_CLK, SYS_PLL_PFD0, AUDIO_PLL_CLK, EXT_CLK }, /* TPM */
+ { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, EXT_CLK }, /* Audio */
+ { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD0 }, /* Video */
+ { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, AUDIO_PLL_CLK }, /* CKO1 */
+ { OSC_24M_CLK, SYS_PLL_PFD0, SYS_PLL_PFD1, VIDEO_PLL_CLK }, /* CKO2 */
+ { OSC_24M_CLK, AUDIO_PLL_CLK, VIDEO_PLL_CLK, SYS_PLL_PFD2 }, /* CAMSCAN */
+};
+
+static struct clk_root_map clk_root_array[] = {
+ { ARM_A55_PERIPH_CLK_ROOT, 0 },
+ { ARM_A55_MTR_BUS_CLK_ROOT, 2 },
+ { ARM_A55_CLK_ROOT, 0 },
+ { M33_CLK_ROOT, 2 },
+ { SENTINEL_CLK_ROOT, 2 },
+ { BUS_WAKEUP_CLK_ROOT, 2 },
+ { BUS_AON_CLK_ROOT, 2 },
+ { WAKEUP_AXI_CLK_ROOT, 0 },
+ { SWO_TRACE_CLK_ROOT, 2 },
+ { M33_SYSTICK_CLK_ROOT, 2 },
+ { FLEXIO1_CLK_ROOT, 2 },
+ { FLEXIO2_CLK_ROOT, 2 },
+ { LPIT1_CLK_ROOT, 2 },
+ { LPIT2_CLK_ROOT, 2 },
+ { LPTMR1_CLK_ROOT, 2 },
+ { LPTMR2_CLK_ROOT, 2 },
+ { TPM1_CLK_ROOT, 3 },
+ { TPM2_CLK_ROOT, 3 },
+ { TPM3_CLK_ROOT, 3 },
+ { TPM4_CLK_ROOT, 3 },
+ { TPM5_CLK_ROOT, 3 },
+ { TPM6_CLK_ROOT, 3 },
+ { FLEXSPI1_CLK_ROOT, 0 },
+ { CAN1_CLK_ROOT, 2 },
+ { CAN2_CLK_ROOT, 2 },
+ { LPUART1_CLK_ROOT, 2 },
+ { LPUART2_CLK_ROOT, 2 },
+ { LPUART3_CLK_ROOT, 2 },
+ { LPUART4_CLK_ROOT, 2 },
+ { LPUART5_CLK_ROOT, 2 },
+ { LPUART6_CLK_ROOT, 2 },
+ { LPUART7_CLK_ROOT, 2 },
+ { LPUART8_CLK_ROOT, 2 },
+ { LPI2C1_CLK_ROOT, 2 },
+ { LPI2C2_CLK_ROOT, 2 },
+ { LPI2C3_CLK_ROOT, 2 },
+ { LPI2C4_CLK_ROOT, 2 },
+ { LPI2C5_CLK_ROOT, 2 },
+ { LPI2C6_CLK_ROOT, 2 },
+ { LPI2C7_CLK_ROOT, 2 },
+ { LPI2C8_CLK_ROOT, 2 },
+ { LPSPI1_CLK_ROOT, 2 },
+ { LPSPI2_CLK_ROOT, 2 },
+ { LPSPI3_CLK_ROOT, 2 },
+ { LPSPI4_CLK_ROOT, 2 },
+ { LPSPI5_CLK_ROOT, 2 },
+ { LPSPI6_CLK_ROOT, 2 },
+ { LPSPI7_CLK_ROOT, 2 },
+ { LPSPI8_CLK_ROOT, 2 },
+ { I3C1_CLK_ROOT, 2 },
+ { I3C2_CLK_ROOT, 2 },
+ { USDHC1_CLK_ROOT, 0 },
+ { USDHC2_CLK_ROOT, 0 },
+ { USDHC3_CLK_ROOT, 0 },
+ { SAI1_CLK_ROOT, 4 },
+ { SAI2_CLK_ROOT, 4 },
+ { SAI3_CLK_ROOT, 4 },
+ { CCM_CKO1_CLK_ROOT, 6 },
+ { CCM_CKO2_CLK_ROOT, 7 },
+ { CCM_CKO3_CLK_ROOT, 6 },
+ { CCM_CKO4_CLK_ROOT, 7 },
+ { HSIO_CLK_ROOT, 2 },
+ { HSIO_USB_TEST_60M_CLK_ROOT, 2 },
+ { HSIO_ACSCAN_80M_CLK_ROOT, 2 },
+ { HSIO_ACSCAN_480M_CLK_ROOT, 0 },
+ { NIC_CLK_ROOT, 0 },
+ { NIC_APB_CLK_ROOT, 2 },
+ { ML_APB_CLK_ROOT, 2 },
+ { ML_CLK_ROOT, 0 },
+ { MEDIA_AXI_CLK_ROOT, 0 },
+ { MEDIA_APB_CLK_ROOT, 2 },
+ { MEDIA_LDB_CLK_ROOT, 5 },
+ { MEDIA_DISP_PIX_CLK_ROOT, 5 },
+ { CAM_PIX_CLK_ROOT, 5 },
+ { MIPI_TEST_BYTE_CLK_ROOT, 5 },
+ { MIPI_PHY_CFG_CLK_ROOT, 5 },
+ { DRAM_ALT_CLK_ROOT, 0 },
+ { DRAM_APB_CLK_ROOT, 1 },
+ { ADC_CLK_ROOT, 2 },
+ { PDM_CLK_ROOT, 4 },
+ { TSTMR1_CLK_ROOT, 2 },
+ { TSTMR2_CLK_ROOT, 2 },
+ { MQS1_CLK_ROOT, 4 },
+ { MQS2_CLK_ROOT, 4 },
+ { AUDIO_XCVR_CLK_ROOT, 1 },
+ { SPDIF_CLK_ROOT, 4 },
+ { ENET_CLK_ROOT, 1 },
+ { ENET_TIMER1_CLK_ROOT, 2 },
+ { ENET_TIMER2_CLK_ROOT, 2 },
+ { ENET_REF_CLK_ROOT, 1 },
+ { ENET_REF_PHY_CLK_ROOT, 2 },
+ { I3C1_SLOW_CLK_ROOT, 2 },
+ { I3C2_SLOW_CLK_ROOT, 2 },
+ { USB_PHY_BURUNIN_CLK_ROOT, 2 },
+ { PAL_CAME_SCAN_CLK_ROOT, 8 },
+};
+
+int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable)
+{
+ u32 authen;
+
+ if (oscpll >= OSCPLL_END)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+ /* If using cpulpm, need disable it first */
+ if (authen & CCM_AUTHEN_CPULPM_MODE)
+ return -EPERM;
+
+ if (enable)
+ writel(1, &ccm_reg->clk_oscplls[oscpll].direct);
+ else
+ writel(0, &ccm_reg->clk_oscplls[oscpll].direct);
+
+ return 0;
+}
+
+/* auto mode, enable = DIRECT[ON] | STATUS0[IN_USE] */
+int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable)
+{
+ u32 authen;
+
+ if (oscpll >= OSCPLL_END)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+ /* AUTO CTRL and CPULPM are mutual exclusion, need disable CPULPM first */
+ if (authen & CCM_AUTHEN_CPULPM_MODE)
+ return -EPERM;
+
+ if (enable)
+ writel(authen | CCM_AUTHEN_AUTO_CTRL, &ccm_reg->clk_oscplls[oscpll].authen);
+ else
+ writel((authen & ~CCM_AUTHEN_AUTO_CTRL), &ccm_reg->clk_oscplls[oscpll].authen);
+
+ return 0;
+}
+
+int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable)
+{
+ u32 authen;
+
+ if (oscpll >= OSCPLL_END)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+ /* AUTO CTRL and CPULPM are mutual exclusion, need disable AUTO CTRL first */
+ if (authen & CCM_AUTHEN_AUTO_CTRL)
+ return -EPERM;
+
+ if (enable)
+ writel(authen | CCM_AUTHEN_CPULPM_MODE, &ccm_reg->clk_oscplls[oscpll].authen);
+ else
+ writel((authen & ~CCM_AUTHEN_CPULPM_MODE), &ccm_reg->clk_oscplls[oscpll].authen);
+
+ return 0;
+}
+
+int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val)
+{
+ u32 lpm, authen;
+
+ if (oscpll >= OSCPLL_END || domain >= 16)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+ if (!(authen & CCM_AUTHEN_CPULPM_MODE))
+ return -EPERM;
+
+ if (domain > 7) {
+ lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm1);
+ lpm &= ~(0x3 << ((domain - 8) * 4));
+ lpm |= (lpm_val & 0x3) << ((domain - 8) * 4);
+ writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm1);
+ } else {
+ lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm0);
+ lpm &= ~(0x3 << (domain * 4));
+ lpm |= (lpm_val & 0x3) << (domain * 4);
+ writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm0);
+ }
+
+ return 0;
+}
+
+bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll)
+{
+ return !!(readl(&ccm_reg->clk_oscplls[oscpll].status0) & 0x1);
+}
+
+int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, bool non_secure, bool user_mode, bool lock_tz)
+{
+ u32 authen;
+
+ if (oscpll >= OSCPLL_END)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+ authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+ authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+ authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+ writel(authen, &ccm_reg->clk_oscplls[oscpll].authen);
+
+ return 0;
+}
+
+int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div)
+{
+ int i;
+ int ret;
+ u32 mux, status;
+
+ if (clk_root_id >= CLK_ROOT_NUM || div > 256 || div == 0)
+ return -EINVAL;
+
+ mux = clk_root_array[clk_root_id].mux_type;
+
+ for (i = 0; i < 4; i++) {
+ if (src == clk_root_mux[mux][i])
+ break;
+ }
+
+ if (i == 4) {
+ printf("Invalid source [%u] for this clk root\n", src);
+ return -EINVAL;
+ }
+
+ writel((i << 8) | (div - 1), &ccm_reg->clk_roots[clk_root_id].control);
+
+ ret = readl_poll_timeout(&ccm_reg->clk_roots[clk_root_id].status0, status,
+ !(status & CLK_ROOT_STATUS_CHANGING), 200000);
+ if (ret)
+ printf("%s: failed, status: 0x%x\n", __func__,
+ readl(&ccm_reg->clk_roots[clk_root_id].status0));
+
+ return ret;
+};
+
+u32 ccm_clk_root_get_rate(u32 clk_root_id)
+{
+ u32 mux, status, div, rate;
+ enum ccm_clk_src src;
+
+ if (clk_root_id >= CLK_ROOT_NUM)
+ return 0;
+
+ status = readl(&ccm_reg->clk_roots[clk_root_id].control);
+
+ if (status & CLK_ROOT_STATUS_OFF)
+ return 0; /* clock is off */
+
+ mux = (status & CLK_ROOT_MUX_MASK) >> CLK_ROOT_MUX_SHIFT;
+ div = status & CLK_ROOT_DIV_MASK;
+ src = clk_root_mux[clk_root_array[clk_root_id].mux_type][mux];
+
+ rate = get_clk_src_rate(src) * 1000;
+
+ return rate / (div + 1); /* return in hz */
+}
+
+int ccm_clk_root_tz_access(u32 clk_root_id, bool non_secure, bool user_mode, bool lock_tz)
+{
+ u32 authen;
+
+ if (clk_root_id >= CLK_ROOT_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_roots[clk_root_id].authen);
+
+ authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+ authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+ authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+ writel(authen, &ccm_reg->clk_roots[clk_root_id].authen);
+
+ return 0;
+}
+
+int ccm_lpcg_on(u32 lpcg, bool enable)
+{
+ u32 authen;
+
+ if (lpcg >= CCGR_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+
+ /* If using cpulpm, need disable it first */
+ if (authen & CCM_AUTHEN_CPULPM_MODE)
+ return -EPERM;
+
+ if (enable)
+ writel(1, &ccm_reg->clk_lpcgs[lpcg].direct);
+ else
+ writel(0, &ccm_reg->clk_lpcgs[lpcg].direct);
+
+ return 0;
+}
+
+int ccm_lpcg_lpm(u32 lpcg, bool enable)
+{
+ u32 authen;
+
+ if (lpcg >= CCGR_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+
+ if (enable)
+ writel(authen | CCM_AUTHEN_CPULPM_MODE, &ccm_reg->clk_lpcgs[lpcg].authen);
+ else
+ writel((authen & ~CCM_AUTHEN_CPULPM_MODE), &ccm_reg->clk_lpcgs[lpcg].authen);
+
+ return 0;
+}
+
+int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val)
+{
+ u32 lpm, authen;
+
+ if (lpcg >= CCGR_NUM || domain >= 16)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+ if (!(authen & CCM_AUTHEN_CPULPM_MODE))
+ return -EPERM;
+
+ if (domain > 7) {
+ lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm1);
+ lpm &= ~(0x3 << ((domain - 8) * 4));
+ lpm |= (lpm_val & 0x3) << ((domain - 8) * 4);
+ writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm1);
+ } else {
+ lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm0);
+ lpm &= ~(0x3 << (domain * 4));
+ lpm |= (lpm_val & 0x3) << (domain * 4);
+ writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm0);
+ }
+
+ return 0;
+}
+
+bool ccm_lpcg_is_clk_on(u32 lpcg)
+{
+ return !!(readl(&ccm_reg->clk_lpcgs[lpcg].status0) & 0x1);
+}
+
+int ccm_lpcg_tz_access(u32 lpcg, bool non_secure, bool user_mode, bool lock_tz)
+{
+ u32 authen;
+
+ if (lpcg >= CCGR_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+
+ authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+ authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+ authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+ writel(authen, &ccm_reg->clk_lpcgs[lpcg].authen);
+
+ return 0;
+}
+
+int ccm_shared_gpr_set(u32 gpr, u32 val)
+{
+ if (gpr >= SHARED_GPR_NUM)
+ return -EINVAL;
+
+ writel(val, &ccm_reg->clk_shared_gpr[gpr].gpr);
+
+ return 0;
+}
+
+int ccm_shared_gpr_get(u32 gpr, u32 *val)
+{
+ if (gpr >= SHARED_GPR_NUM || !val)
+ return -EINVAL;
+
+ *val = readl(&ccm_reg->clk_shared_gpr[gpr].gpr);
+
+ return 0;
+}
+
+int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock_tz)
+{
+ u32 authen;
+
+ if (gpr >= SHARED_GPR_NUM)
+ return -EINVAL;
+
+ authen = readl(&ccm_reg->clk_shared_gpr[gpr].authen);
+
+ authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+ authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+ authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+ writel(authen, &ccm_reg->clk_shared_gpr[gpr].authen);
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index d905fe76c91..d4a97729c67 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -123,5 +123,8 @@ int ft_system_setup(void *blob, struct bd_info *bd)
int arch_cpu_init(void)
{
+ if (IS_ENABLED(CONFIG_SPL_BUILD))
+ clock_init();
+
return 0;
}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 14/49] mmc: fsl_esdhc_imx: Support i.MX9
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (12 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 13/49] imx: imx9: Add CCM and clock API support Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 15/49] spl: Use SPL_FIT_IMAGE_TINY for iMX9 Peng Fan (OSS)
` (35 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Peng Fan, Jaehoon Chung; +Cc: u-boot
From: Peng Fan <peng.fan@nxp.com>
Support i.MX9 for fsl_esdhc_imx driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/mmc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 5a87db6be08..4d31fbcd527 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -852,7 +852,7 @@ config FSL_ESDHC_IMX
config FSL_USDHC
bool "Freescale/NXP i.MX uSDHC controller support"
- depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMXRT
+ depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT
select FSL_ESDHC_IMX
help
This enables the Ultra Secured Digital Host Controller enhancements
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 15/49] spl: Use SPL_FIT_IMAGE_TINY for iMX9
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (13 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 14/49] mmc: fsl_esdhc_imx: Support i.MX9 Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 16/49] imx: imx9: Add function to initialize timer Peng Fan (OSS)
` (34 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Select SPL_FIT_IMAGE_TINY for i.MX9
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
common/spl/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 848237c1e85..06cbad2ca85 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -537,7 +537,7 @@ config SPL_FIT_IMAGE_TINY
bool "Remove functionality from SPL FIT loading to reduce size"
depends on SPL_FIT
default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6
- default y if ARCH_IMX8M
+ default y if ARCH_IMX8M || ARCH_IMX9
help
Enable this to reduce the size of the FIT image loading code
in SPL, if space for the SPL binary is very tight.
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 16/49] imx: imx9: Add function to initialize timer
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (14 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 15/49] spl: Use SPL_FIT_IMAGE_TINY for iMX9 Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 17/49] imx: imx9: disable watchdog Peng Fan (OSS)
` (33 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Jian Li
From: Jian Li <jian.li@nxp.com>
Add timer_init to update ARM arch timer with correct frequency
from system counter and enable system counter.
Signed-off-by: Jian Li <jian.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 50ec902987d..32c76ce9c3b 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -11,6 +11,7 @@
#define IOMUXC_BASE_ADDR 0x443C0000UL
#define CCM_BASE_ADDR 0x44450000UL
#define CCM_CCGR_BASE_ADDR 0x44458000UL
+#define SYSCNT_CTRL_BASE_ADDR 0x44290000
#define ANATOP_BASE_ADDR 0x44480000UL
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index d4a97729c67..4b8f1ca30d5 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -128,3 +128,22 @@ int arch_cpu_init(void)
return 0;
}
+
+int timer_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+ unsigned long freq = readl(&sctr->cntfid0);
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
+
+ clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+ SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+#endif
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 17/49] imx: imx9: disable watchdog
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (15 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 16/49] imx: imx9: Add function to initialize timer Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 18/49] imx: imx9: support romapi Peng Fan (OSS)
` (32 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 4 ++
arch/arm/mach-imx/imx9/soc.c | 45 ++++++++++++++++++++++-
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 32c76ce9c3b..e4babed40fc 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -15,4 +15,8 @@
#define ANATOP_BASE_ADDR 0x44480000UL
+#define WDG3_BASE_ADDR 0x42490000UL
+#define WDG4_BASE_ADDR 0x424a0000UL
+#define WDG5_BASE_ADDR 0x424b0000UL
+
#endif
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 4b8f1ca30d5..8b620832b5d 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -34,6 +34,45 @@ u32 get_cpu_rev(void)
return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
}
+#define UNLOCK_WORD 0xD928C520 /* unlock word */
+#define REFRESH_WORD 0xB480A602 /* refresh word */
+
+static void disable_wdog(void __iomem *wdog_base)
+{
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ /* default is 32bits cmd */
+ writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */
+
+ if (!(val_cs & 0x800)) {
+ writel(UNLOCK_WORD, (wdog_base + 0x04));
+ while (!(readl(wdog_base + 0x00) & 0x800))
+ ;
+ }
+ writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+ writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */
+
+ while (!(readl(wdog_base + 0x00) & 0x400))
+ ;
+}
+
+void init_wdog(void)
+{
+ u32 src_val;
+
+ disable_wdog((void __iomem *)WDG3_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG4_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG5_BASE_ADDR);
+
+ src_val = readl(0x54460018); /* reset mask */
+ src_val &= ~0x1c;
+ writel(src_val, 0x54460018);
+}
+
static struct mm_region imx93_mem_map[] = {
{
/* ROM */
@@ -123,8 +162,12 @@ int ft_system_setup(void *blob, struct bd_info *bd)
int arch_cpu_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ /* Disable wdog */
+ init_wdog();
+
clock_init();
+ }
return 0;
}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 18/49] imx: imx9: support romapi
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (16 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 17/49] imx: imx9: disable watchdog Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 19/49] misc: imx: S400_API: Move S400 MU and API to a common place Peng Fan (OSS)
` (31 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function
prototype common and usable by i.MX9.
Also include mmc env functions that use ROM API.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 4 --
arch/arm/include/asm/mach-imx/sys_proto.h | 4 ++
arch/arm/mach-imx/imx9/soc.c | 37 +++++++++++++++++++
3 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 05859dfc2aa..a7869fbb573 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -8,10 +8,6 @@
#include <asm/mach-imx/sys_proto.h>
-extern unsigned long rom_pointer[];
-
-ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
-ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 05532ebea89..17c5f44b208 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -180,6 +180,10 @@ enum boot_dev_type_e {
#define ROM_API_OKAY 0xF0
extern struct rom_api *g_rom_api;
+extern unsigned long rom_pointer[];
+
+ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
+ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
/* For i.MX ULP */
#define BT0CFG_LPBOOT_MASK 0x1
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 8b620832b5d..9ea2d51495b 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -29,6 +29,43 @@
DECLARE_GLOBAL_DATA_PTR;
+struct rom_api *g_rom_api = (struct rom_api *)0x1980;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return devno; }
+
+int mmc_get_env_dev(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+ ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ set_gd(pgd);
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ debug("boot_type %d, instance %d\n", boot_type, boot_instance);
+
+ /* If not boot from sd/mmc, use default value */
+ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
+ return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+
+ return board_mmc_get_env_dev(boot_instance);
+}
+#endif
+
u32 get_cpu_rev(void)
{
return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 19/49] misc: imx: S400_API: Move S400 MU and API to a common place
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (17 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 18/49] imx: imx9: support romapi Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 20/49] misc: s4mu: Support iMX93 with Sentinel MU Peng Fan (OSS)
` (30 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Bharat Gooty, Rayagonda Kokatanur,
NXP i.MX U-Boot Team, Peng Fan
Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400
MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/Kconfig | 4 +
arch/arm/include/asm/global_data.h | 2 +-
.../asm/{arch-imx8ulp => mach-imx}/mu_hal.h | 4 +-
.../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 0
arch/arm/mach-imx/imx8ulp/ahab.c | 345 ++++++++++++++++++
arch/arm/mach-imx/imx8ulp/rdc.c | 4 +-
arch/arm/mach-imx/imx8ulp/soc.c | 4 +-
board/freescale/imx8ulp_evk/spl.c | 2 +-
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 2 +
drivers/misc/imx8ulp/Makefile | 1 -
drivers/misc/imx8ulp/fuse.c | 2 +-
drivers/misc/sentinel/Makefile | 3 +
drivers/misc/{imx8ulp => sentinel}/s400_api.c | 6 +-
.../{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} | 4 +-
15 files changed, 375 insertions(+), 15 deletions(-)
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/mu_hal.h (79%)
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/s400_api.h (100%)
create mode 100644 arch/arm/mach-imx/imx8ulp/ahab.c
create mode 100644 drivers/misc/sentinel/Makefile
rename drivers/misc/{imx8ulp => sentinel}/s400_api.c (98%)
rename drivers/misc/{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} (98%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 12ec661ac3b..29b831422ff 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -922,6 +922,8 @@ config ARCH_IMX8ULP
select OF_CONTROL
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
+ select MISC
+ select IMX_SENTINEL
imply CMD_DM
imply DM_EVENT
@@ -931,6 +933,8 @@ config ARCH_IMX9
select DM
select MACH_IMX
select SUPPORT_SPL
+ select MISC
+ select IMX_SENTINEL
imply CMD_DM
imply DM_EVENT
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 085e12b5d4d..09f352269e5 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -90,7 +90,7 @@ struct arch_global_data {
struct udevice *scu_dev;
#endif
-#ifdef CONFIG_ARCH_IMX8ULP
+#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h b/arch/arm/include/asm/mach-imx/mu_hal.h
similarity index 79%
rename from arch/arm/include/asm/arch-imx8ulp/mu_hal.h
rename to arch/arm/include/asm/mach-imx/mu_hal.h
index 10d966d5d43..5db559c1ac5 100644
--- a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
+++ b/arch/arm/include/asm/mach-imx/mu_hal.h
@@ -3,8 +3,8 @@
* Copyright 2021 NXP
*/
-#ifndef __IMX8ULP_MU_HAL_H__
-#define __IMX8ULP_MU_HAL_H__
+#ifndef __SNT_MU_HAL_H__
+#define __SNT_MU_HAL_H__
void mu_hal_init(ulong base);
int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg);
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h
similarity index 100%
rename from arch/arm/include/asm/arch-imx8ulp/s400_api.h
rename to arch/arm/include/asm/mach-imx/s400_api.h
diff --git a/arch/arm/mach-imx/imx8ulp/ahab.c b/arch/arm/mach-imx/imx8ulp/ahab.c
new file mode 100644
index 00000000000..87c4c66a087
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/ahab.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/image.h>
+#include <console.h>
+#include <cpu_func.h>
+#include <asm/mach-imx/ahab.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_BASE (0x22010000UL)
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL)
+
+#define AHAB_NO_AUTHENTICATION_IND 0xee
+#define AHAB_BAD_KEY_HASH_IND 0xfa
+#define AHAB_INVALID_KEY_IND 0xf9
+#define AHAB_BAD_SIGNATURE_IND 0xf0
+#define AHAB_BAD_HASH_IND 0xf1
+
+static void display_ahab_auth_ind(u32 event)
+{
+ u8 resp_ind = (event >> 8) & 0xff;
+
+ switch (resp_ind) {
+ case AHAB_NO_AUTHENTICATION_IND:
+ printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_KEY_HASH_IND:
+ printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_INVALID_KEY_IND:
+ printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_SIGNATURE_IND:
+ printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_HASH_IND:
+ printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ default:
+ printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
+ break;
+ }
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+ int err;
+ u32 resp;
+
+ memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
+ ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+ flush_dcache_range(IMG_CONTAINER_BASE,
+ IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+ err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
+ if (err) {
+ printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
+ err, resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_auth_release(void)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_release_container(&resp);
+ if (err) {
+ printf("Error: release container failed, resp 0x%x!\n", resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_verify_image(image_index, &resp);
+ if (err) {
+ printf("Authenticate img %d failed, return %d, resp 0x%x\n",
+ image_index, err, resp);
+ display_ahab_auth_ind(resp);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static inline bool check_in_dram(ulong addr)
+{
+ int i;
+ struct bd_info *bd = gd->bd;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ if (addr >= bd->bi_dram[i].start &&
+ addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+ return true;
+ }
+ }
+
+ return false;
+}
+
+int authenticate_os_container(ulong addr)
+{
+ struct container_hdr *phdr;
+ int i, ret = 0;
+ int err;
+ u16 length;
+ struct boot_img_t *img;
+ unsigned long s, e;
+
+ if (addr % 4) {
+ puts("Error: Image's address is not 4 byte aligned\n");
+ return -EINVAL;
+ }
+
+ if (!check_in_dram(addr)) {
+ puts("Error: Image's address is invalid\n");
+ return -EINVAL;
+ }
+
+ phdr = (struct container_hdr *)addr;
+ if (phdr->tag != 0x87 || phdr->version != 0x0) {
+ printf("Error: Wrong container header\n");
+ return -EFAULT;
+ }
+
+ if (!phdr->num_images) {
+ printf("Error: Wrong container, no image found\n");
+ return -EFAULT;
+ }
+
+ length = phdr->length_lsb + (phdr->length_msb << 8);
+
+ debug("container length %u\n", length);
+
+ err = ahab_auth_cntr_hdr(phdr, length);
+ if (err) {
+ ret = -EIO;
+ goto exit;
+ }
+
+ debug("Verify images\n");
+
+ /* Copy images to dest address */
+ for (i = 0; i < phdr->num_images; i++) {
+ img = (struct boot_img_t *)(addr +
+ sizeof(struct container_hdr) +
+ i * sizeof(struct boot_img_t));
+
+ debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n",
+ i, (uint32_t)img->dst, img->offset + addr, img->size);
+
+ memcpy((void *)img->dst, (const void *)(img->offset + addr), img->size);
+
+ s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
+
+ flush_dcache_range(s, e);
+
+ ret = ahab_verify_cntr_image(img, i);
+ if (ret)
+ goto exit;
+ }
+
+exit:
+ debug("ahab_auth_release, 0x%x\n", ret);
+ ahab_auth_release();
+
+ return ret;
+}
+
+static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong addr;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ printf("Authenticate OS container at 0x%lx\n", addr);
+
+ if (authenticate_os_container(addr))
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static void display_life_cycle(u32 lc)
+{
+ printf("Lifecycle: 0x%08X, ", lc);
+ switch (lc) {
+ case 0x1:
+ printf("BLANK\n\n");
+ break;
+ case 0x2:
+ printf("FAB\n\n");
+ break;
+ case 0x4:
+ printf("NXP Provisioned\n\n");
+ break;
+ case 0x8:
+ printf("OEM Open\n\n");
+ break;
+ case 0x10:
+ printf("OEM Secure World Closed\n\n");
+ break;
+ case 0x20:
+ printf("OEM closed\n\n");
+ break;
+ case 0x40:
+ printf("Field Return OEM\n\n");
+ break;
+ case 0x80:
+ printf("Field Return NXP\n\n");
+ break;
+ case 0x100:
+ printf("OEM Locked\n\n");
+ break;
+ case 0x200:
+ printf("BRICKED\n\n");
+ break;
+ default:
+ printf("Unknown\n\n");
+ break;
+ }
+}
+
+static int confirm_close(void)
+{
+ puts("Warning: Please ensure your sample is in NXP closed state, "
+ "OEM SRK hash has been fused, \n"
+ " and you are able to boot a signed image successfully "
+ "without any SECO events reported.\n"
+ " If not, your sample will be unrecoverable.\n"
+ "\nReally perform this operation? <y/N>\n");
+
+ if (confirm_yesno())
+ return 1;
+
+ puts("Ahab close aborted\n");
+ return 0;
+}
+
+static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int err;
+ u32 resp;
+
+ if (!confirm_close())
+ return -EACCES;
+
+ err = ahab_forward_lifecycle(8, &resp);
+ if (err != 0) {
+ printf("Error in forward lifecycle to OEM closed\n");
+ return -EIO;
+ }
+
+ printf("Change to OEM closed successfully\n");
+
+ return 0;
+}
+
+int ahab_dump(void)
+{
+ u32 buffer[32];
+ int ret, i = 0;
+
+ do {
+ ret = ahab_dump_buffer(buffer, 32);
+ if (ret < 0) {
+ printf("Error in dump AHAB log\n");
+ return -EIO;
+ }
+
+ if (ret == 1)
+ break;
+
+ for (i = 0; i < ret; i++)
+ printf("0x%x\n", buffer[i]);
+ } while (ret >= 21);
+
+ return 0;
+}
+
+static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ return ahab_dump();
+}
+
+static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ u32 lc;
+
+ lc = readl(FSB_BASE_ADDR + 0x41c);
+ lc &= 0x3f;
+
+ display_life_cycle(lc);
+ return 0;
+}
+
+U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
+ "autenticate OS container via AHAB",
+ "addr\n"
+ "addr - OS container hex address\n"
+);
+
+U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
+ "Change AHAB lifecycle to OEM closed",
+ ""
+);
+
+U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump,
+ "Dump AHAB log for debug",
+ ""
+);
+
+U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
+ "display AHAB lifecycle only",
+ ""
+);
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index e2eca0633e3..cc47079d8f5 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -8,8 +8,8 @@
#include <asm/types.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/mu_hal.h>
-#include <asm/arch/s400_api.h>
+#include <asm/mach-imx/mu_hal.h>
+#include <asm/mach-imx/s400_api.h>
#include <asm/arch/rdc.h>
#include <div64.h>
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 529fda4594e..999fb1f301f 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -14,8 +14,8 @@
#include <event.h>
#include <spl.h>
#include <asm/arch/rdc.h>
-#include <asm/arch/s400_api.h>
-#include <asm/arch/mu_hal.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/mu_hal.h>
#include <cpu_func.h>
#include <asm/setup.h>
#include <dm.h>
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index ece9ff26e92..e672f6ee6cb 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -19,7 +19,7 @@
#include <asm/arch/ddr.h>
#include <asm/arch/rdc.h>
#include <asm/arch/upower.h>
-#include <asm/arch/s400_api.h>
+#include <asm/mach-imx/s400_api.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 28d5da49ff1..4603b54f598 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -330,6 +330,13 @@ config NPCM_OTP
To compile this driver as a module, choose M here: the module
will be called npcm_otp.
+config IMX_SENTINEL
+ bool "Enable i.MX Sentinel MU driver and API"
+ depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
+ help
+ If you say Y here to enable Message Unit driver to work with
+ Sentinel core on some NXP i.MX processors.
+
config NUVOTON_NCT6102D
bool "Enable Nuvoton NCT6102D Super I/O driver"
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 0bf05ca05ef..dcba39a15fc 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -50,6 +50,8 @@ obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
obj-$(CONFIG_IMX8ULP) += imx8ulp/
+obj-$(CONFIG_IMX8ULP) += imx8ulp/
+obj-$(CONFIG_IMX_SENTINEL) += sentinel/
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile
index 927cc552163..450e615e645 100644
--- a/drivers/misc/imx8ulp/Makefile
+++ b/drivers/misc/imx8ulp/Makefile
@@ -1,4 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
-obj-y += s400_api.o imx8ulp_mu.o
obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/imx8ulp/fuse.c
index 090e702d9f7..83d2c25731f 100644
--- a/drivers/misc/imx8ulp/fuse.c
+++ b/drivers/misc/imx8ulp/fuse.c
@@ -10,7 +10,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/imx-regs.h>
#include <env.h>
-#include <asm/arch/s400_api.h>
+#include <asm/mach-imx/s400_api.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/misc/sentinel/Makefile b/drivers/misc/sentinel/Makefile
new file mode 100644
index 00000000000..3e2f623b278
--- /dev/null
+++ b/drivers/misc/sentinel/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += s400_api.o s4mu.o
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/sentinel/s400_api.c
similarity index 98%
rename from drivers/misc/imx8ulp/s400_api.c
rename to drivers/misc/sentinel/s400_api.c
index 87f5880ccb8..3d791bc868e 100644
--- a/drivers/misc/imx8ulp/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -9,7 +9,7 @@
#include <malloc.h>
#include <asm/io.h>
#include <dm.h>
-#include <asm/arch/s400_api.h>
+#include <asm/mach-imx/s400_api.h>
#include <misc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -275,8 +275,8 @@ int ahab_release_caam(u32 core_did, u32 *response)
int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/sentinel/s4mu.c
similarity index 98%
rename from drivers/misc/imx8ulp/imx8ulp_mu.c
rename to drivers/misc/sentinel/s4mu.c
index 333ebdf5765..121a81060a6 100644
--- a/drivers/misc/imx8ulp/imx8ulp_mu.c
+++ b/drivers/misc/sentinel/s4mu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2022 NXP
*/
#include <common.h>
@@ -9,7 +9,7 @@
#include <dm/lists.h>
#include <dm/root.h>
#include <dm/device-internal.h>
-#include <asm/arch/s400_api.h>
+#include <asm/mach-imx/s400_api.h>
#include <asm/arch/imx-regs.h>
#include <linux/iopoll.h>
#include <misc.h>
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 20/49] misc: s4mu: Support iMX93 with Sentinel MU
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (18 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 19/49] misc: imx: S400_API: Move S400 MU and API to a common place Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 21/49] misc: S400_API: Update release RDC API Peng Fan (OSS)
` (29 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Support iMX93 communicate with Sentinel
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 30 +++++++++++++++++++++++
drivers/misc/sentinel/s4mu.c | 1 +
2 files changed, 31 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index e4babed40fc..7b84b970b75 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -19,4 +19,34 @@
#define WDG4_BASE_ADDR 0x424a0000UL
#define WDG5_BASE_ADDR 0x424b0000UL
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#include <stdbool.h>
+
+struct mu_type {
+ u32 ver;
+ u32 par;
+ u32 cr;
+ u32 sr;
+ u32 reserved0[60];
+ u32 fcr;
+ u32 fsr;
+ u32 reserved1[2];
+ u32 gier;
+ u32 gcr;
+ u32 gsr;
+ u32 reserved2;
+ u32 tcr;
+ u32 tsr;
+ u32 rcr;
+ u32 rsr;
+ u32 reserved3[52];
+ u32 tr[16];
+ u32 reserved4[16];
+ u32 rr[16];
+ u32 reserved5[14];
+ u32 mu_attr;
+};
+#endif
+
#endif
diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/sentinel/s4mu.c
index 121a81060a6..18aea27105e 100644
--- a/drivers/misc/sentinel/s4mu.c
+++ b/drivers/misc/sentinel/s4mu.c
@@ -219,6 +219,7 @@ static struct misc_ops imx8ulp_mu_ops = {
static const struct udevice_id imx8ulp_mu_ids[] = {
{ .compatible = "fsl,imx8ulp-mu" },
+ { .compatible = "fsl,imx93-mu-s4" },
{ }
};
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 21/49] misc: S400_API: Update release RDC API
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (19 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 20/49] misc: s4mu: Support iMX93 with Sentinel MU Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 22/49] misc: S400_API: New API for FW status and chip info Peng Fan (OSS)
` (28 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
To support more RDC instances on i.MX93, update API to latest
definition.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 +-
drivers/misc/sentinel/s400_api.c | 21 +++++++++++++++++----
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h
index b3e6b3fa45d..d09c078df01 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -32,7 +32,7 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response);
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
int ahab_verify_image(u32 img_id, u32 *response);
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 3d791bc868e..4e90171420f 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
int size = sizeof(struct imx8ulp_s400_msg);
@@ -30,10 +30,23 @@ int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
- if (xrdc)
- msg.data[0] = (0x78 << 8) | core_id;
- else
+ switch (xrdc) {
+ case 0:
msg.data[0] = (0x74 << 8) | core_id;
+ break;
+ case 1:
+ msg.data[0] = (0x78 << 8) | core_id;
+ break;
+ case 2:
+ msg.data[0] = (0x82 << 8) | core_id;
+ break;
+ case 3:
+ msg.data[0] = (0x86 << 8) | core_id;
+ break;
+ default:
+ printf("Error: wrong xrdc index %u\n", xrdc);
+ return -EINVAL;
+ }
ret = misc_call(dev, false, &msg, size, &msg, size);
if (ret)
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 22/49] misc: S400_API: New API for FW status and chip info
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (20 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 21/49] misc: S400_API: Update release RDC API Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 23/49] misc: s400_api: introduce ahab_release_m33_trout Peng Fan (OSS)
` (27 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add new API to get sentinel FW status and SoC chip info
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/s400_api.h | 13 +++++
drivers/misc/sentinel/s400_api.c | 61 ++++++++++++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h
index d09c078df01..d95f8227b29 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -19,8 +19,10 @@
#define AHAB_READ_FUSE_REQ_CID 0x97
#define AHAB_GET_FW_VERSION_CID 0x9D
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_GET_FW_STATUS_CID 0xC5
#define AHAB_WRITE_FUSE_REQ_CID 0xD6
#define AHAB_CAAM_RELEASE_CID 0xD7
+#define AHAB_GET_INFO_CID 0xDA
#define S400_MAX_MSG 255U
@@ -32,6 +34,15 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
+struct sentinel_get_info_data {
+ u32 hdr;
+ u32 soc;
+ u32 lc;
+ u32 uid[4];
+ u32 sha256_rom_patch[8];
+ u32 sha_fw[8];
+};
+
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
@@ -42,5 +53,7 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo
int ahab_release_caam(u32 core_did, u32 *response);
int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
+int ahab_get_fw_status(u32 *status, u32 *response);
#endif
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 4e90171420f..ca7903670ed 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -359,3 +359,64 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
return i;
}
+
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 4;
+ msg.command = AHAB_GET_INFO_CID;
+ msg.data[0] = upper_32_bits((ulong)info);
+ msg.data[1] = lower_32_bits((ulong)info);
+ msg.data[2] = sizeof(struct sentinel_get_info_data);
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_get_fw_status(u32 *status, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_GET_FW_STATUS_CID;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ *status = msg.data[1] & 0xF;
+
+ return ret;
+}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 23/49] misc: s400_api: introduce ahab_release_m33_trout
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (21 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 22/49] misc: S400_API: New API for FW status and chip info Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 24/49] imx: imx9: Add TRDC driver for TRDC init Peng Fan (OSS)
` (26 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel
release M33 trout and make sure M33 could boot.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/s400_api.h | 1 +
drivers/misc/sentinel/s400_api.c | 25 ++++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h
index d95f8227b29..dc176e1f619 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -55,5 +55,6 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
int ahab_get_fw_status(u32 *status, u32 *response);
+int ahab_release_m33_trout(void);
#endif
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index ca7903670ed..01a673e5e13 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -420,3 +420,28 @@ int ahab_get_fw_status(u32 *status, u32 *response)
return ret;
}
+
+int ahab_release_m33_trout(void)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = 0xd3;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ return ret;
+}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 24/49] imx: imx9: Add TRDC driver for TRDC init
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (22 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 23/49] misc: s400_api: introduce ahab_release_m33_trout Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 25/49] imx: imx9: Add AHAB boot support Peng Fan (OSS)
` (25 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Add TRDC driver to iMX9. The TRDC init splits to two phases:
1. Early init phase will release TRDC from Sentinel and open write
permission to the memory where SPL image runs. Sentinel will set
the memory to RX only after ROM authentication for the OEM
closed part.
2. Init phase will configure TRDC to allow non-secure master to
access DDR. So the peripherals can work in u-boot.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/trdc.h | 19 +
arch/arm/mach-imx/imx9/Makefile | 2 +-
arch/arm/mach-imx/imx9/soc.c | 3 +
arch/arm/mach-imx/imx9/trdc.c | 581 ++++++++++++++++++++++++++
4 files changed, 604 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx9/trdc.h
create mode 100644 arch/arm/mach-imx/imx9/trdc.c
diff --git a/arch/arm/include/asm/arch-imx9/trdc.h b/arch/arm/include/asm/arch-imx9/trdc.h
new file mode 100644
index 00000000000..1481ee375b7
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/trdc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_TRDC_H
+#define __ASM_ARCH_IMX9_TRDC_H
+
+int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32 glbac_val);
+int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x,
+ bool sec_access, u32 glbac_id);
+int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32 glbac_val);
+int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start,
+ u32 addr_end, bool sec_access, u32 glbac_id);
+
+void trdc_early_init(void);
+void trdc_init(void);
+
+#endif
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 7be0343d52e..0124212f266 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -3,4 +3,4 @@
# Copyright 2022 NXP
obj-y += lowlevel_init.o
-obj-y += soc.o clock.o clock_root.o
+obj-y += soc.o clock.o clock_root.o trdc.o
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 9ea2d51495b..7c71cbdd55a 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -14,6 +14,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/trdc.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/syscounter.h>
#include <asm/armv8/mmu.h>
@@ -204,6 +205,8 @@ int arch_cpu_init(void)
init_wdog();
clock_init();
+
+ trdc_early_init();
}
return 0;
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
new file mode 100644
index 00000000000..b0881697a10
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <div64.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/mu_hal.h>
+
+#define DID_NUM 16
+#define MBC_MAX_NUM 4
+#define MRC_MAX_NUM 2
+#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
+#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+
+struct mbc_mem_dom {
+ u32 mem_glbcfg[4];
+ u32 nse_blk_index;
+ u32 nse_blk_set;
+ u32 nse_blk_clr;
+ u32 nsr_blk_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MBC */
+ u32 mem0_blk_cfg_w[64];
+ u32 mem0_blk_nse_w[16];
+ u32 mem1_blk_cfg_w[8];
+ u32 mem1_blk_nse_w[2];
+ u32 mem2_blk_cfg_w[8];
+ u32 mem2_blk_nse_w[2];
+ u32 mem3_blk_cfg_w[8];
+ u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+ u32 reserved[2];
+};
+
+struct mrc_rgn_dom {
+ u32 mrc_glbcfg[4];
+ u32 nse_rgn_indirect;
+ u32 nse_rgn_set;
+ u32 nse_rgn_clr;
+ u32 nse_rgn_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MRC */
+ u32 rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */
+ u32 rgn_nse;
+ u32 reserved2[15];
+};
+
+struct mda_inst {
+ u32 mda_w[8];
+};
+
+struct trdc_mgr {
+ u32 trdc_cr;
+ u32 res0[59];
+ u32 trdc_hwcfg0;
+ u32 trdc_hwcfg1;
+ u32 res1[450];
+ struct mda_inst mda[8];
+ u32 res2[15808];
+};
+
+struct trdc_mbc {
+ struct mbc_mem_dom mem_dom[DID_NUM];
+};
+
+struct trdc_mrc {
+ struct mrc_rgn_dom mrc_dom[DID_NUM];
+};
+
+int trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids,
+ u8 did, u8 pe, u8 pidm, u8 pid)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg];
+ u32 val = readl(mda_w);
+
+ if (val & BIT(29)) /* non-cpu */
+ return -EINVAL;
+
+ val = BIT(31) | ((pid & 0x3f) << 16) | ((pidm & 0x3f) << 8) |
+ ((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) |
+ (did & 0xf);
+
+ writel(val, mda_w);
+
+ return 0;
+}
+
+int trdc_mda_set_noncpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg,
+ bool did_bypass, u8 sa, u8 pa, u8 did)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg];
+ u32 val = readl(mda_w);
+
+ if (!(val & BIT(29))) /* cpu */
+ return -EINVAL;
+
+ val = BIT(31) | ((sa & 0x3) << 6) | ((pa & 0x3) << 4) | (did & 0xf);
+ if (did_bypass)
+ val |= BIT(8);
+
+ writel(val, mda_w);
+
+ return 0;
+}
+
+static ulong trdc_get_mbc_base(ulong trdc_reg, u32 mbc_x)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
+
+ if (mbc_x >= mbc_num)
+ return 0;
+
+ return trdc_reg + 0x10000 + 0x2000 * mbc_x;
+}
+
+static ulong trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
+ u32 mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0);
+
+ if (mrc_x >= mrc_num)
+ return 0;
+
+ return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x;
+}
+
+int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32 glbac_val)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+
+ if (mbc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ /* only first dom has the glbac */
+ mbc_dom = &mbc_base->mem_dom[0];
+
+ debug("mbc 0x%lx\n", (ulong)mbc_dom);
+
+ writel(glbac_val, &mbc_dom->memn_glbac[glbac_id]);
+
+ return 0;
+}
+
+int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x,
+ u32 blk_x, bool sec_access, u32 glbac_id)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+ u32 *cfg_w, *nse_w;
+ u32 index, offset, val;
+
+ if (mbc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ mbc_dom = &mbc_base->mem_dom[dom_x];
+
+ debug("mbc 0x%lx\n", (ulong)mbc_dom);
+
+ switch (mem_x) {
+ case 0:
+ cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32];
+ break;
+ case 1:
+ cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32];
+ break;
+ case 2:
+ cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32];
+ break;
+ case 3:
+ cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
+ nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32];
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ index = blk_x % 8;
+ offset = index * 4;
+
+ val = readl((void __iomem *)cfg_w);
+
+ val &= ~(0xFU << offset);
+
+ /* MBC0-3
+ * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * So select MBC0_MEMN_GLBAC0
+ */
+ if (sec_access) {
+ val |= ((0x0 | (glbac_id & 0x7)) << offset);
+ writel(val, (void __iomem *)cfg_w);
+ } else {
+ val |= ((0x8 | (glbac_id & 0x7)) << offset); /* nse bit set */
+ writel(val, (void __iomem *)cfg_w);
+ }
+
+ return 0;
+}
+
+int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32 glbac_val)
+{
+ struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
+ struct mrc_rgn_dom *mrc_dom;
+
+ if (mrc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ /* only first dom has the glbac */
+ mrc_dom = &mrc_base->mrc_dom[0];
+
+ debug("mrc_dom 0x%lx\n", (ulong)mrc_dom);
+
+ writel(glbac_val, &mrc_dom->memn_glbac[glbac_id]);
+
+ return 0;
+}
+
+int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start,
+ u32 addr_end, bool sec_access, u32 glbac_id)
+{
+ struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
+ struct mrc_rgn_dom *mrc_dom;
+ u32 *desc_w;
+ u32 start, end;
+ u32 i, free = 8;
+ bool vld, hit = false;
+
+ if (mrc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ mrc_dom = &mrc_base->mrc_dom[dom_x];
+
+ addr_start &= ~0x3fff;
+ addr_end &= ~0x3fff;
+
+ debug("mrc_dom 0x%lx\n", (ulong)mrc_dom);
+
+ for (i = 0; i < 8; i++) {
+ desc_w = &mrc_dom->rgn_desc_words[i][0];
+
+ debug("desc_w 0x%lx\n", (ulong)desc_w);
+
+ start = readl((void __iomem *)desc_w) & (~0x3fff);
+ end = readl((void __iomem *)(desc_w + 1));
+ vld = end & 0x1;
+ end = end & (~0x3fff);
+
+ if (start == 0 && end == 0 && !vld && free >= 8)
+ free = i;
+
+ /* Check all the region descriptors, even overlap */
+ if (addr_start >= end || addr_end <= start || !vld)
+ continue;
+
+ /* MRC0,1
+ * Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+ * So select MRCx_MEMN_GLBAC0
+ */
+ if (sec_access) {
+ writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
+ writel(end | 0x1, (void __iomem *)(desc_w + 1));
+ } else {
+ writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
+ writel(end | 0x1 | 0x10, (void __iomem *)(desc_w + 1));
+ }
+
+ if (addr_start >= start && addr_end <= end)
+ hit = true;
+ }
+
+ if (!hit) {
+ if (free >= 8)
+ return -EFAULT;
+
+ desc_w = &mrc_dom->rgn_desc_words[free][0];
+
+ debug("free desc_w 0x%lx\n", (ulong)desc_w);
+ debug("[0x%x] [0x%x]\n", addr_start | (glbac_id & 0x7), addr_end | 0x1);
+
+ if (sec_access) {
+ writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
+ writel(addr_end | 0x1, (void __iomem *)(desc_w + 1));
+ } else {
+ writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
+ writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1));
+ }
+ }
+
+ return 0;
+}
+
+bool trdc_mrc_enabled(ulong trdc_base)
+{
+ return (!!(readl((void __iomem *)trdc_base) & 0x8000));
+}
+
+bool trdc_mbc_enabled(ulong trdc_base)
+{
+ return (!!(readl((void __iomem *)trdc_base) & 0x4000));
+}
+
+int release_rdc(u8 xrdc)
+{
+ ulong s_mu_base = 0x47520000UL;
+ struct imx8ulp_s400_msg msg;
+ int ret;
+ u32 rdc_id;
+
+ switch (xrdc) {
+ case 0:
+ rdc_id = 0x74;
+ break;
+ case 1:
+ rdc_id = 0x78;
+ break;
+ case 2:
+ rdc_id = 0x82;
+ break;
+ case 3:
+ rdc_id = 0x86;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 2;
+ msg.command = AHAB_RELEASE_RDC_REQ_CID;
+ msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */
+
+ mu_hal_init(s_mu_base);
+ mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg));
+ mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);
+
+ ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
+ if (!ret) {
+ ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
+ if (!ret) {
+ if ((msg.data[0] & 0xff) == 0xd6)
+ return 0;
+ }
+
+ return -EIO;
+ }
+
+ return ret;
+}
+
+void trdc_early_init(void)
+{
+ int ret = 0, i;
+
+ ret |= release_rdc(0);
+ ret |= release_rdc(2);
+ ret |= release_rdc(1);
+ ret |= release_rdc(3);
+
+ if (!ret) {
+ /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
+ trdc_mbc_set_control(0x49010000, 3, 0, 0x7700);
+
+ for (i = 0; i < 40; i++)
+ trdc_mbc_blk_config(0x49010000, 3, 3, 0, i, true, 0);
+
+ for (i = 0; i < 40; i++)
+ trdc_mbc_blk_config(0x49010000, 3, 3, 1, i, true, 0);
+
+ for (i = 0; i < 40; i++)
+ trdc_mbc_blk_config(0x49010000, 3, 0, 0, i, true, 0);
+
+ for (i = 0; i < 40; i++)
+ trdc_mbc_blk_config(0x49010000, 3, 0, 1, i, true, 0);
+ }
+}
+
+void trdc_init(void)
+{
+ /* TRDC mega */
+ if (trdc_mrc_enabled(0x49010000)) {
+ /* DDR */
+ trdc_mrc_set_control(0x49010000, 0, 0, 0x7777);
+
+ /* S400*/
+ trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* MTR */
+ trdc_mrc_region_config(0x49010000, 0, 1, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* M33 */
+ trdc_mrc_region_config(0x49010000, 0, 2, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* A55*/
+ trdc_mrc_region_config(0x49010000, 0, 3, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* For USDHC1 to DDR, USDHC1 is default force to non-secure */
+ trdc_mrc_region_config(0x49010000, 0, 5, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* For USDHC2 to DDR, USDHC2 is default force to non-secure */
+ trdc_mrc_region_config(0x49010000, 0, 6, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* eDMA */
+ trdc_mrc_region_config(0x49010000, 0, 7, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /*CoreSight, TestPort*/
+ trdc_mrc_region_config(0x49010000, 0, 8, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /* DAP */
+ trdc_mrc_region_config(0x49010000, 0, 9, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /*SoC masters */
+ trdc_mrc_region_config(0x49010000, 0, 10, 0x80000000, 0xFFFFFFFF, false, 0);
+
+ /*USB*/
+ trdc_mrc_region_config(0x49010000, 0, 11, 0x80000000, 0xFFFFFFFF, false, 0);
+ }
+}
+
+#if DEBUG
+int trdc_mbc_control_dump(ulong trdc_reg, u32 mbc_x, u32 glbac_id)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+
+ if (mbc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ /* only first dom has the glbac */
+ mbc_dom = &mbc_base->mem_dom[0];
+
+ printf("mbc_dom %u glbac %u: 0x%x\n",
+ mbc_x, glbac_id, readl(&mbc_dom->memn_glbac[glbac_id]));
+
+ return 0;
+}
+
+int trdc_mbc_mem_dump(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 word)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+ u32 *cfg_w;
+
+ if (mbc_base == 0)
+ return -EINVAL;
+
+ mbc_dom = &mbc_base->mem_dom[dom_x];
+
+ switch (mem_x) {
+ case 0:
+ cfg_w = &mbc_dom->mem0_blk_cfg_w[word];
+ break;
+ case 1:
+ cfg_w = &mbc_dom->mem1_blk_cfg_w[word];
+ break;
+ case 2:
+ cfg_w = &mbc_dom->mem2_blk_cfg_w[word];
+ break;
+ case 3:
+ cfg_w = &mbc_dom->mem3_blk_cfg_w[word];
+ break;
+ default:
+ return -EINVAL;
+ };
+
+ printf("mbc_dom %u dom %u mem %u word %u: 0x%x\n",
+ mbc_x, dom_x, mem_x, word, readl((void __iomem *)cfg_w));
+
+ return 0;
+}
+
+int trdc_mrc_control_dump(ulong trdc_reg, u32 mrc_x, u32 glbac_id)
+{
+ struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
+ struct mrc_rgn_dom *mrc_dom;
+
+ if (mrc_base == 0 || glbac_id >= 8)
+ return -EINVAL;
+
+ /* only first dom has the glbac */
+ mrc_dom = &mrc_base->mrc_dom[0];
+
+ printf("mrc_dom %u glbac %u: 0x%x\n",
+ mrc_x, glbac_id, readl(&mrc_dom->memn_glbac[glbac_id]));
+
+ return 0;
+}
+
+void trdc_dump(void)
+{
+ u32 i;
+
+ printf("TRDC AONMIX MBC\n");
+
+ trdc_mbc_control_dump(0x44270000, 0, 0);
+ trdc_mbc_control_dump(0x44270000, 1, 0);
+
+ for (i = 0; i < 11; i++)
+ trdc_mbc_mem_dump(0x44270000, 0, 3, 0, i);
+ for (i = 0; i < 1; i++)
+ trdc_mbc_mem_dump(0x44270000, 0, 3, 1, i);
+
+ for (i = 0; i < 4; i++)
+ trdc_mbc_mem_dump(0x44270000, 1, 3, 0, i);
+ for (i = 0; i < 4; i++)
+ trdc_mbc_mem_dump(0x44270000, 1, 3, 1, i);
+
+ printf("TRDC WAKEUP MBC\n");
+
+ trdc_mbc_control_dump(0x42460000, 0, 0);
+ trdc_mbc_control_dump(0x42460000, 1, 0);
+
+ for (i = 0; i < 15; i++)
+ trdc_mbc_mem_dump(0x42460000, 0, 3, 0, i);
+
+ trdc_mbc_mem_dump(0x42460000, 0, 3, 1, 0);
+ trdc_mbc_mem_dump(0x42460000, 0, 3, 2, 0);
+
+ for (i = 0; i < 2; i++)
+ trdc_mbc_mem_dump(0x42460000, 1, 3, 0, i);
+
+ trdc_mbc_mem_dump(0x42460000, 1, 3, 1, 0);
+ trdc_mbc_mem_dump(0x42460000, 1, 3, 2, 0);
+ trdc_mbc_mem_dump(0x42460000, 1, 3, 3, 0);
+
+ printf("TRDC NICMIX MBC\n");
+
+ trdc_mbc_control_dump(0x49010000, 0, 0);
+ trdc_mbc_control_dump(0x49010000, 1, 0);
+ trdc_mbc_control_dump(0x49010000, 2, 0);
+ trdc_mbc_control_dump(0x49010000, 3, 0);
+
+ for (i = 0; i < 7; i++)
+ trdc_mbc_mem_dump(0x49010000, 0, 3, 0, i);
+
+ for (i = 0; i < 2; i++)
+ trdc_mbc_mem_dump(0x49010000, 0, 3, 1, i);
+
+ for (i = 0; i < 5; i++)
+ trdc_mbc_mem_dump(0x49010000, 0, 3, 2, i);
+
+ for (i = 0; i < 6; i++)
+ trdc_mbc_mem_dump(0x49010000, 0, 3, 3, i);
+
+ for (i = 0; i < 1; i++)
+ trdc_mbc_mem_dump(0x49010000, 1, 3, 0, i);
+
+ for (i = 0; i < 1; i++)
+ trdc_mbc_mem_dump(0x49010000, 1, 3, 1, i);
+
+ for (i = 0; i < 3; i++)
+ trdc_mbc_mem_dump(0x49010000, 1, 3, 2, i);
+
+ for (i = 0; i < 3; i++)
+ trdc_mbc_mem_dump(0x49010000, 1, 3, 3, i);
+
+ for (i = 0; i < 2; i++)
+ trdc_mbc_mem_dump(0x49010000, 2, 3, 0, i);
+
+ for (i = 0; i < 2; i++)
+ trdc_mbc_mem_dump(0x49010000, 2, 3, 1, i);
+
+ for (i = 0; i < 5; i++)
+ trdc_mbc_mem_dump(0x49010000, 3, 3, 0, i);
+
+ for (i = 0; i < 5; i++)
+ trdc_mbc_mem_dump(0x49010000, 3, 3, 1, i);
+}
+#endif
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 25/49] imx: imx9: Add AHAB boot support
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (23 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 24/49] imx: imx9: Add TRDC driver for TRDC init Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 26/49] imx: imx9: Get the chip revision through S400 API Peng Fan (OSS)
` (24 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Add AHAB driver for iMX9 to do authentication by calling sentinel API
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx9/Kconfig | 5 +
arch/arm/mach-imx/imx9/Makefile | 1 +
arch/arm/mach-imx/imx9/ahab.c | 346 ++++++++++++++++++++++++++++++++
3 files changed, 352 insertions(+)
create mode 100644 arch/arm/mach-imx/imx9/ahab.c
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index ce58e41428f..dae9f658e65 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -1,5 +1,10 @@
if ARCH_IMX9
+config AHAB_BOOT
+ bool "Support i.MX9 AHAB features"
+ help
+ This option enables the support for AHAB secure boot.
+
config IMX9
bool
select HAS_CAAM
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 0124212f266..41a22500c95 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -4,3 +4,4 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
+obj-$(CONFIG_AHAB_BOOT) += ahab.o
diff --git a/arch/arm/mach-imx/imx9/ahab.c b/arch/arm/mach-imx/imx9/ahab.c
new file mode 100644
index 00000000000..6aa949619b5
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/ahab.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/image.h>
+#include <console.h>
+#include <cpu_func.h>
+#include <asm/mach-imx/ahab.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_BASE (0x80000000UL)
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xFFFFUL)
+
+#define AHAB_NO_AUTHENTICATION_IND 0xee
+#define AHAB_BAD_KEY_HASH_IND 0xfa
+#define AHAB_INVALID_KEY_IND 0xf9
+#define AHAB_BAD_SIGNATURE_IND 0xf0
+#define AHAB_BAD_HASH_IND 0xf1
+
+static void display_ahab_auth_ind(u32 event)
+{
+ u8 resp_ind = (event >> 8) & 0xff;
+
+ switch (resp_ind) {
+ case AHAB_NO_AUTHENTICATION_IND:
+ printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_KEY_HASH_IND:
+ printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_INVALID_KEY_IND:
+ printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_SIGNATURE_IND:
+ printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_HASH_IND:
+ printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ default:
+ printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
+ break;
+ }
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+ int err;
+ u32 resp;
+
+ memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
+ ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+ flush_dcache_range(IMG_CONTAINER_BASE,
+ IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+ err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
+ if (err) {
+ printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
+ err, resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_auth_release(void)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_release_container(&resp);
+ if (err) {
+ printf("Error: release container failed, resp 0x%x!\n", resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_verify_image(image_index, &resp);
+ if (err) {
+ printf("Authenticate img %d failed, return %d, resp 0x%x\n",
+ image_index, err, resp);
+ display_ahab_auth_ind(resp);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static inline bool check_in_dram(ulong addr)
+{
+ int i;
+ struct bd_info *bd = gd->bd;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ if (addr >= bd->bi_dram[i].start &&
+ addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+ return true;
+ }
+ }
+
+ return false;
+}
+
+int authenticate_os_container(ulong addr)
+{
+ struct container_hdr *phdr;
+ int i, ret = 0;
+ int err;
+ u16 length;
+ struct boot_img_t *img;
+ unsigned long s, e;
+
+ if (addr % 4) {
+ puts("Error: Image's address is not 4 byte aligned\n");
+ return -EINVAL;
+ }
+
+ if (!check_in_dram(addr)) {
+ puts("Error: Image's address is invalid\n");
+ return -EINVAL;
+ }
+
+ phdr = (struct container_hdr *)addr;
+ if (phdr->tag != 0x87 || phdr->version != 0x0) {
+ printf("Error: Wrong container header\n");
+ return -EFAULT;
+ }
+
+ if (!phdr->num_images) {
+ printf("Error: Wrong container, no image found\n");
+ return -EFAULT;
+ }
+
+ length = phdr->length_lsb + (phdr->length_msb << 8);
+
+ debug("container length %u\n", length);
+
+ err = ahab_auth_cntr_hdr(phdr, length);
+ if (err) {
+ ret = -EIO;
+ goto exit;
+ }
+
+ debug("Verify images\n");
+
+ /* Copy images to dest address */
+ for (i = 0; i < phdr->num_images; i++) {
+ img = (struct boot_img_t *)(addr +
+ sizeof(struct container_hdr) +
+ i * sizeof(struct boot_img_t));
+
+ debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n",
+ i, (uint32_t)img->dst, img->offset + addr, img->size);
+
+ memcpy((void *)img->dst, (const void *)(img->offset + addr),
+ img->size);
+
+ s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
+
+ flush_dcache_range(s, e);
+
+ ret = ahab_verify_cntr_image(img, i);
+ if (ret)
+ goto exit;
+ }
+
+exit:
+ debug("ahab_auth_release, 0x%x\n", ret);
+ ahab_auth_release();
+
+ return ret;
+}
+
+static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong addr;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ printf("Authenticate OS container at 0x%lx\n", addr);
+
+ if (authenticate_os_container(addr))
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static void display_life_cycle(u32 lc)
+{
+ printf("Lifecycle: 0x%08X, ", lc);
+ switch (lc) {
+ case 0x1:
+ printf("BLANK\n\n");
+ break;
+ case 0x2:
+ printf("FAB\n\n");
+ break;
+ case 0x4:
+ printf("NXP Provisioned\n\n");
+ break;
+ case 0x8:
+ printf("OEM Open\n\n");
+ break;
+ case 0x10:
+ printf("OEM Secure World Closed\n\n");
+ break;
+ case 0x20:
+ printf("OEM closed\n\n");
+ break;
+ case 0x40:
+ printf("Field Return OEM\n\n");
+ break;
+ case 0x80:
+ printf("Field Return NXP\n\n");
+ break;
+ case 0x100:
+ printf("OEM Locked\n\n");
+ break;
+ case 0x200:
+ printf("BRICKED\n\n");
+ break;
+ default:
+ printf("Unknown\n\n");
+ break;
+ }
+}
+
+static int confirm_close(void)
+{
+ puts("Warning: Please ensure your sample is in NXP closed state, "
+ "OEM SRK hash has been fused, \n"
+ " and you are able to boot a signed image successfully "
+ "without any SECO events reported.\n"
+ " If not, your sample will be unrecoverable.\n"
+ "\nReally perform this operation? <y/N>\n");
+
+ if (confirm_yesno())
+ return 1;
+
+ puts("Ahab close aborted\n");
+ return 0;
+}
+
+static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int err;
+ u32 resp;
+
+ if (!confirm_close())
+ return -EACCES;
+
+ err = ahab_forward_lifecycle(8, &resp);
+ if (err != 0) {
+ printf("Error in forward lifecycle to OEM closed\n");
+ return -EIO;
+ }
+
+ printf("Change to OEM closed successfully\n");
+
+ return 0;
+}
+
+int ahab_dump(void)
+{
+ u32 buffer[32];
+ int ret, i = 0;
+
+ do {
+ ret = ahab_dump_buffer(buffer, 32);
+ if (ret < 0) {
+ printf("Error in dump AHAB log\n");
+ return -EIO;
+ }
+
+ if (ret == 1)
+ break;
+ for (i = 0; i < ret; i++)
+ printf("0x%x\n", buffer[i]);
+ } while (ret >= 21);
+
+ return 0;
+}
+
+static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ return ahab_dump();
+}
+
+static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ u32 lc;
+
+ lc = readl(FSB_BASE_ADDR + 0x41c);
+ lc &= 0x3ff;
+
+ display_life_cycle(lc);
+ return 0;
+}
+
+U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
+ "autenticate OS container via AHAB",
+ "addr\n"
+ "addr - OS container hex address\n"
+);
+
+U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
+ "Change AHAB lifecycle to OEM closed",
+ ""
+);
+
+U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump,
+ "Dump AHAB log for debug",
+ ""
+);
+
+U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
+ "display AHAB lifecycle only",
+ ""
+);
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 26/49] imx: imx9: Get the chip revision through S400 API
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (24 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 25/49] imx: imx9: Add AHAB boot support Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 27/49] misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg Peng Fan (OSS)
` (23 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Update the get chip revision methond to use S400 API, also record
other information like lifecycle and UID to global data.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/global_data.h | 3 ++
arch/arm/mach-imx/imx9/soc.c | 49 +++++++++++++++++++++++++++++-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 09f352269e5..6ee2a767615 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -92,6 +92,9 @@ struct arch_global_data {
#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
+ u32 soc_rev;
+ u32 lifecycle;
+ u32 uid[4];
#endif
};
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 7c71cbdd55a..c71a5a92504 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -27,6 +27,7 @@
#include <asm/setup.h>
#include <asm/bootm.h>
#include <asm/arch-imx/cpu.h>
+#include <asm/mach-imx/s400_api.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -67,9 +68,18 @@ int mmc_get_env_dev(void)
}
#endif
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+ gd->arch.soc_rev = info->soc;
+ gd->arch.lifecycle = info->lc;
+ memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
+}
+
u32 get_cpu_rev(void)
{
- return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
+ u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+
+ return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev);
}
#define UNLOCK_WORD 0xD928C520 /* unlock word */
@@ -198,6 +208,17 @@ int ft_system_setup(void *blob, struct bd_info *bd)
return 0;
}
+#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
+ gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2], gd->arch.uid[3]);
+
+ serialnr->low = gd->arch.uid[0];
+ serialnr->high = gd->arch.uid[3];
+}
+#endif
+
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
@@ -212,6 +233,32 @@ int arch_cpu_init(void)
return 0;
}
+int imx9_probe_mu(void *ctx, struct event *event)
+{
+ struct udevice *devp;
+ int node, ret;
+ u32 res;
+ struct sentinel_get_info_data info;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
+ if (ret)
+ return ret;
+
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
+
+ ret = ahab_get_info(&info, &res);
+ if (ret)
+ return ret;
+
+ set_cpu_info(&info);
+
+ return 0;
+}
+EVENT_SPY(EVT_DM_POST_INIT, imx9_probe_mu);
+
int timer_init(void)
{
#ifdef CONFIG_SPL_BUILD
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 27/49] misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (25 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 26/49] imx: imx9: Get the chip revision through S400 API Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 28/49] misc: imx8ulp: move fuse.c from imx8ulp to sentinel Peng Fan (OSS)
` (22 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Use more generic name for S40x msg structure
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 +-
arch/arm/mach-imx/imx8ulp/rdc.c | 2 +-
arch/arm/mach-imx/imx9/trdc.c | 2 +-
drivers/misc/sentinel/s400_api.c | 44 ++++++++++++------------
drivers/misc/sentinel/s4mu.c | 6 ++--
5 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h
index dc176e1f619..89fa373d06f 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -26,7 +26,7 @@
#define S400_MAX_MSG 255U
-struct imx8ulp_s400_msg {
+struct sentinel_msg {
u8 version;
u8 size;
u8 command;
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index cc47079d8f5..e24eeff8a20 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -184,7 +184,7 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x27020000UL;
- struct imx8ulp_s400_msg msg;
+ struct sentinel_msg msg;
int ret;
u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index b0881697a10..3f37ce712c0 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -315,7 +315,7 @@ bool trdc_mbc_enabled(ulong trdc_base)
int release_rdc(u8 xrdc)
{
ulong s_mu_base = 0x47520000UL;
- struct imx8ulp_s400_msg msg;
+ struct sentinel_msg msg;
int ret;
u32 rdc_id;
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 01a673e5e13..65032f77362 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -17,8 +17,8 @@ DECLARE_GLOBAL_DATA_PTR;
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -62,8 +62,8 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -92,8 +92,8 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
int ahab_release_container(u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -120,8 +120,8 @@ int ahab_release_container(u32 *response)
int ahab_verify_image(u32 img_id, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -149,8 +149,8 @@ int ahab_verify_image(u32 img_id, u32 *response)
int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -178,8 +178,8 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -226,8 +226,8 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *respo
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -259,8 +259,8 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
int ahab_release_caam(u32 core_did, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -329,8 +329,8 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret, i = 0;
if (!dev) {
@@ -363,8 +363,8 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -394,8 +394,8 @@ int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
int ahab_get_fw_status(u32 *status, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/sentinel/s4mu.c
index 18aea27105e..794fc40c620 100644
--- a/drivers/misc/sentinel/s4mu.c
+++ b/drivers/misc/sentinel/s4mu.c
@@ -85,7 +85,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
static int imx8ulp_mu_read(struct mu_type *base, void *data)
{
- struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
+ struct sentinel_msg *msg = (struct sentinel_msg *)data;
int ret;
u8 count = 0;
@@ -118,7 +118,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)
static int imx8ulp_mu_write(struct mu_type *base, void *data)
{
- struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
+ struct sentinel_msg *msg = (struct sentinel_msg *)data;
int ret;
u8 count = 0;
@@ -171,7 +171,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg,
return ret;
}
- result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0];
+ result = ((struct sentinel_msg *)rx_msg)->data[0];
if ((result & 0xff) == 0xd6)
return 0;
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 28/49] misc: imx8ulp: move fuse.c from imx8ulp to sentinel
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (26 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 27/49] misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 29/49] misc: fuse: support to access fuse on i.MX93 Peng Fan (OSS)
` (21 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
The i.MX93 platform wants to reuse drivers/misc/imx8ulp/fuse.c. Moving
fuse.c from the folder imx8ulp to sentinel makes it can be used by other
platforms.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/misc/Makefile | 2 --
drivers/misc/imx8ulp/Makefile | 3 ---
drivers/misc/sentinel/Makefile | 1 +
drivers/misc/{imx8ulp => sentinel}/fuse.c | 0
4 files changed, 1 insertion(+), 5 deletions(-)
delete mode 100644 drivers/misc/imx8ulp/Makefile
rename drivers/misc/{imx8ulp => sentinel}/fuse.c (100%)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index dcba39a15fc..33ccaf04f6a 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -49,8 +49,6 @@ obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
-obj-$(CONFIG_IMX8ULP) += imx8ulp/
-obj-$(CONFIG_IMX8ULP) += imx8ulp/
obj-$(CONFIG_IMX_SENTINEL) += sentinel/
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile
deleted file mode 100644
index 450e615e645..00000000000
--- a/drivers/misc/imx8ulp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/sentinel/Makefile b/drivers/misc/sentinel/Makefile
index 3e2f623b278..446154cb201 100644
--- a/drivers/misc/sentinel/Makefile
+++ b/drivers/misc/sentinel/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += s400_api.o s4mu.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/sentinel/fuse.c
similarity index 100%
rename from drivers/misc/imx8ulp/fuse.c
rename to drivers/misc/sentinel/fuse.c
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 29/49] misc: fuse: support to access fuse on i.MX93
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (27 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 28/49] misc: imx8ulp: move fuse.c from imx8ulp to sentinel Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 30/49] misc: fuse: update the code for accessing fuse of i.MX93 Peng Fan (OSS)
` (20 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Alice Guo
From: Alice Guo <alice.guo@nxp.com>
i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables
for i.MX93. The offset address of FSB accessing OTP shadow registers is
different between i.MX8ULP and i.MX93, so use macro to define the offset
address instead of hardcode.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 2 ++
drivers/misc/sentinel/fuse.c | 30 ++++++++++++++++++++++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 7b84b970b75..fa6951ebbe8 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -19,6 +19,8 @@
#define WDG4_BASE_ADDR 0x424a0000UL
#define WDG5_BASE_ADDR 0x424b0000UL
+#define FSB_BASE_ADDR 0x47510000UL
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#include <stdbool.h>
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index 83d2c25731f..abb4c072f9b 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -31,6 +31,9 @@ struct s400_map_entry {
u32 s400_index;
};
+#if defined(CONFIG_IMX8ULP)
+#define FSB_OTP_SHADOW 0x800
+
struct fsb_map_entry fsb_mapping_table[] = {
{ 3, 8 },
{ 4, 8 },
@@ -65,6 +68,31 @@ struct s400_map_entry s400_api_mapping_table[] = {
{ 23, 1, 4, 2 }, /* OTFAD */
{ 25, 8 }, /* Test config2 */
};
+#elif defined(CONFIG_ARCH_IMX9)
+#define FSB_OTP_SHADOW 0x8000
+
+struct fsb_map_entry fsb_mapping_table[] = {
+ { 0, 8 },
+ { 1, 8 },
+ { 2, 8 },
+ { -1, 8 },
+ { 4, 8 },
+ { 5, 8 },
+ { 6, 8 }, /* UID */
+ { -1, 8 },
+ { 8, 8 },
+ { 9, 8 },
+ { 10, 8 },
+};
+
+struct s400_map_entry s400_api_mapping_table[] = {
+ { 3, 11 }, /* 24 .. 34 */
+ { 7, 8 },
+ { 16, 11 }, /* 128 .. 143 */
+ { 22, 8 },
+ { 23, 8 },
+};
+#endif
static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
{
@@ -128,7 +156,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
word_index = map_fsb_fuse_index(bank, word, &redundancy);
if (word_index >= 0) {
- *val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2));
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
if (redundancy)
*val = (*val >> ((word % 2) * 16)) & 0xFFFF;
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 30/49] misc: fuse: update the code for accessing fuse of i.MX93
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (28 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 29/49] misc: fuse: support to access fuse on i.MX93 Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 31/49] imx: imx9: Add gpio registers structure Peng Fan (OSS)
` (19 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Alice Guo, Ye Li
From: Alice Guo <alice.guo@nxp.com>
Sentinel have read access of OTP shadow register 0-511, and fsb have
read access of shadow 0-51/312-511.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/misc/sentinel/fuse.c | 86 +++++++++++++++++++++++++++++++-----
1 file changed, 74 insertions(+), 12 deletions(-)
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index abb4c072f9b..e2b68757664 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -75,22 +75,44 @@ struct fsb_map_entry fsb_mapping_table[] = {
{ 0, 8 },
{ 1, 8 },
{ 2, 8 },
- { -1, 8 },
+ { 3, 8 },
{ 4, 8 },
{ 5, 8 },
- { 6, 8 }, /* UID */
- { -1, 8 },
- { 8, 8 },
- { 9, 8 },
- { 10, 8 },
+ { 6, 4 },
+ { -1, 260 },
+ { 39, 8 },
+ { 40, 8 },
+ { 41, 8 },
+ { 42, 8 },
+ { 43, 8 },
+ { 44, 8 },
+ { 45, 8 },
+ { 46, 8 },
+ { 47, 8 },
+ { 48, 8 },
+ { 49, 8 },
+ { 50, 8 },
+ { 51, 8 },
+ { 52, 8 },
+ { 53, 8 },
+ { 54, 8 },
+ { 55, 8 },
+ { 56, 8 },
+ { 57, 8 },
+ { 58, 8 },
+ { 59, 8 },
+ { 60, 8 },
+ { 61, 8 },
+ { 62, 8 },
+ { 63, 8 },
};
struct s400_map_entry s400_api_mapping_table[] = {
- { 3, 11 }, /* 24 .. 34 */
- { 7, 8 },
- { 16, 11 }, /* 128 .. 143 */
- { 22, 8 },
- { 23, 8 },
+ { 7, 1, 7, 63 },
+ { 16, 8, },
+ { 17, 8, },
+ { 22, 1, 6 },
+ { 23, 1, 4 },
};
#endif
@@ -102,7 +124,8 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
/* map the fuse from ocotp fuse map to FSB*/
for (i = 0; i < size; i++) {
if (fsb_mapping_table[i].fuse_bank != -1 &&
- fsb_mapping_table[i].fuse_bank == bank) {
+ fsb_mapping_table[i].fuse_bank == bank &&
+ fsb_mapping_table[i].fuse_words > word) {
break;
}
@@ -146,6 +169,7 @@ static s32 map_s400_fuse_index(u32 bank, u32 word)
return s400_api_mapping_table[i].fuse_bank * 8 + word;
}
+#if defined(CONFIG_IMX8ULP)
int fuse_sense(u32 bank, u32 word, u32 *val)
{
s32 word_index;
@@ -198,6 +222,44 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
return -ENOENT;
}
+#elif defined(CONFIG_ARCH_IMX9)
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ s32 word_index;
+ bool redundancy;
+
+ if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ word_index = map_fsb_fuse_index(bank, word, &redundancy);
+ if (word_index >= 0) {
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
+ if (redundancy)
+ *val = (*val >> ((word % 2) * 16)) & 0xFFFF;
+
+ return 0;
+ }
+
+ word_index = map_s400_fuse_index(bank, word);
+ if (word_index >= 0) {
+ u32 data;
+ u32 res, size = 1;
+ int ret;
+
+ ret = ahab_read_common_fuse(word_index, &data, size, &res);
+ if (ret) {
+ printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ *val = data;
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+#endif
int fuse_read(u32 bank, u32 word, u32 *val)
{
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 31/49] imx: imx9: Add gpio registers structure
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (29 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 30/49] misc: fuse: update the code for accessing fuse of i.MX93 Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 32/49] imx: imx9: Add MIX power init Peng Fan (OSS)
` (18 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Bharat Gooty, Rayagonda Kokatanur; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Add GPIO registers structure for iMX93, so that we can enable lpgpio
driver
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arch-imx9/gpio.h | 20 ++++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 29b831422ff..7dcf5614e9b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -933,6 +933,7 @@ config ARCH_IMX9
select DM
select MACH_IMX
select SUPPORT_SPL
+ select GPIO_EXTRA_HEADER
select MISC
select IMX_SENTINEL
imply CMD_DM
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h
index e69de29bb2d..40732022e7e 100644
--- a/arch/arm/include/asm/arch-imx9/gpio.h
+++ b/arch/arm/include/asm/arch-imx9/gpio.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_GPIO_H
+#define __ASM_ARCH_IMX9_GPIO_H
+
+struct gpio_regs {
+ u32 gpio_pdor;
+ u32 gpio_psor;
+ u32 gpio_pcor;
+ u32 gpio_ptor;
+ u32 gpio_pdir;
+ u32 gpio_pddr;
+ u32 gpio_pidr;
+ u8 gpio_pxdr[32];
+};
+
+#endif
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 32/49] imx: imx9: Add MIX power init
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (30 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 31/49] imx: imx9: Add gpio registers structure Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 33/49] imx: imx9: Add M33 release prepare function Peng Fan (OSS)
` (17 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation
of MIPI DSI/CSI, USBPHY after the power up.
SPL should call the power init in its boot sequence before accessing
above three MIX and USB.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 173 +++++++++++++++++++++
arch/arm/include/asm/arch-imx9/sys_proto.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 101 ++++++++++++
3 files changed, 275 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index fa6951ebbe8..049eca4f3a7 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -21,6 +21,24 @@
#define FSB_BASE_ADDR 0x47510000UL
+#define ANATOP_BASE_ADDR 0x44480000UL
+
+#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x42420000
+#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f0000
+
+#define SRC_IPS_BASE_ADDR (0x44460000)
+#define SRC_GLOBAL_RBASE (SRC_IPS_BASE_ADDR + 0x0000)
+
+#define SRC_DDR_RBASE (SRC_IPS_BASE_ADDR + 0x1000)
+#define SRC_ML_RBASE (SRC_IPS_BASE_ADDR + 0x1800)
+#define SRC_MEDIA_RBASE (SRC_IPS_BASE_ADDR + 0x2400)
+#define SRC_M33P_RBASE (SRC_IPS_BASE_ADDR + 0x2800)
+
+#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
+#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
+#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#include <stdbool.h>
@@ -49,6 +67,161 @@ struct mu_type {
u32 reserved5[14];
u32 mu_attr;
};
+
+enum mix_power_domain {
+ MIX_PD_MEDIAMIX,
+ MIX_PD_MLMIX,
+ MIX_PD_DDRMIX,
+};
+
+enum src_mix_slice_id {
+ SRC_MIX_EDGELOCK = 0,
+ SRC_MIX_AONMIX = 1,
+ SRC_MIX_WAKEUPMIX = 2,
+ SRC_MIX_DDRMIX = 3,
+ SRC_MIX_DDRPHY = 4,
+ SRC_MIX_ML = 5,
+ SRC_MIX_NIC = 6,
+ SRC_MIX_HSIO = 7,
+ SRC_MIX_MEDIA = 8,
+ SRC_MIX_CM33 = 9,
+ SRC_MIX_CA55C0 = 10,
+ SRC_MIX_CA55C1 = 11,
+ SRC_MIX_CA55CLUSTER = 12,
+};
+
+enum src_mem_slice_id {
+ SRC_MEM_AONMIX = 0,
+ SRC_MEM_WAKEUPMIX = 1,
+ SRC_MEM_DDRMIX = 2,
+ SRC_MEM_DDRPHY = 3,
+ SRC_MEM_ML = 4,
+ SRC_MEM_NIC = 5,
+ SRC_MEM_OCRAM = 6,
+ SRC_MEM_HSIO = 7,
+ SRC_MEM_MEDIA = 8,
+ SRC_MEM_CA55C0 = 9,
+ SRC_MEM_CA55C1 = 10,
+ SRC_MEM_CA55CLUSTER = 11,
+ SRC_MEM_L3 = 12,
+};
+
+struct blk_ctrl_s_aonmix_regs {
+ u32 cm33_irq_mask[7];
+ u32 initnsvtor;
+ u32 reserved1[8];
+ u32 ca55_irq_mask[7];
+ u32 initsvtor;
+ u32 m33_cfg;
+ u32 reserved2[11];
+ u32 axbs_aon_ctrl;
+ u32 reserved3[27];
+ u32 dap_access_stkybit;
+ u32 reserved4[3];
+ u32 lp_handshake[2];
+ u32 ca55_cpuwait;
+ u32 ca55_rvbaraddr0_l;
+ u32 ca55_rvbaraddr0_h;
+ u32 ca55_rvbaraddr1_l;
+ u32 ca55_rvbaraddr1_h;
+ u32 s401_irq_mask;
+ u32 s401_reset_req_mask;
+ u32 s401_halt_st;
+ u32 ca55_mode;
+ u32 nmi_mask;
+ u32 nmi_clr;
+ u32 wdog_any_mask;
+ u32 s4v1_ipi_noclk_ref1;
+};
+
+struct blk_ctrl_wakeupmix_regs {
+ u32 upper_addr;
+ u32 ipg_debug_cm33;
+ u32 reserved[2];
+ u32 qch_dis;
+ u32 ssi;
+ u32 reserved1[1];
+ u32 dexsc_err;
+ u32 mqs_setting;
+ u32 sai_clk_sel;
+ u32 eqos_gpr;
+ u32 enet_clk_sel;
+ u32 reserved2[1];
+ u32 volt_detect;
+ u32 i3c2_wakeup;
+ u32 ipg_debug_ca55c0;
+ u32 ipg_debug_ca55c1;
+ u32 axi_attr_cfg;
+ u32 i3c2_sda_irq;
+};
+
+struct src_general_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 scr;
+ u32 srtmr;
+ u32 srmask;
+ u32 reserved2[1];
+ u32 srmr[6];
+ u32 reserved3[2];
+ u32 sbmr[2];
+ u32 reserved4[2];
+ u32 srsr;
+ u32 gpr[19];
+ u32 reserved5[24];
+ u32 gpr20;
+ u32 cm_quiesce;
+ u32 cold_reset_ssar_ack_ctrl;
+ u32 sp_iso_ctrl;
+ u32 rom_lp_ctrl;
+ u32 a55_deny_stat;
+};
+
+struct src_mem_slice_regs {
+ u32 reserved[1];
+ u32 mem_ctrl;
+ u32 memlp_ctrl_0;
+ u32 reserved1[1];
+ u32 memlp_ctrl_1;
+ u32 memlp_ctrl_2;
+ u32 mem_stat;
+};
+
+struct src_mix_slice_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 lpm_setting[3];
+ u32 reserved2[1];
+ u32 slice_sw_ctrl;
+ u32 single_reset_sw_ctrl;
+ u32 reserved3[6];
+ u32 a55_hdsk_ack_ctrl;
+ u32 a55_hdsk_ack_stat;
+ u32 reserved4[2];
+ u32 ssar_ack_ctrl;
+ u32 ssar_ack_stat;
+ u32 reserved5[1];
+ u32 iso_off_dly_por;
+ u32 iso_on_dly;
+ u32 iso_off_dly;
+ u32 psw_off_lf_dly;
+ u32 reserved6[1];
+ u32 psw_off_hf_dly;
+ u32 psw_on_lf_dly;
+ u32 psw_on_hf_dly;
+ u32 reserved7[1];
+ u32 psw_ack_ctrl[2];
+ u32 psw_ack_stat;
+ u32 reserved8[1];
+ u32 mtr_ack_ctrl;
+ u32 mtr_ack_stat;
+ u32 reserved9[2];
+ u32 upi_stat[4];
+ u32 fsm_stat;
+ u32 func_stat;
+};
#endif
#endif
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 513aa0b9581..5ae7a043398 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -8,4 +8,5 @@
#include <asm/mach-imx/sys_proto.h>
+void soc_power_init(void);
#endif
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index c71a5a92504..68f3ddd4287 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -28,6 +28,7 @@
#include <asm/bootm.h>
#include <asm/arch-imx/cpu.h>
#include <asm/mach-imx/s400_api.h>
+#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -277,3 +278,103 @@ int timer_init(void)
return 0;
}
+
+static int mix_power_init(enum mix_power_domain pd)
+{
+ enum src_mix_slice_id mix_id;
+ enum src_mem_slice_id mem_id;
+ struct src_mix_slice_regs *mix_regs;
+ struct src_mem_slice_regs *mem_regs;
+ struct src_general_regs *global_regs;
+ u32 scr, val;
+
+ switch (pd) {
+ case MIX_PD_MEDIAMIX:
+ mix_id = SRC_MIX_MEDIA;
+ mem_id = SRC_MEM_MEDIA;
+ scr = BIT(5);
+
+ /* Enable S400 handshake */
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+
+ setbits_le32(&s_regs->lp_handshake[0], BIT(13));
+ break;
+ case MIX_PD_MLMIX:
+ mix_id = SRC_MIX_ML;
+ mem_id = SRC_MEM_ML;
+ scr = BIT(4);
+ break;
+ case MIX_PD_DDRMIX:
+ mix_id = SRC_MIX_DDRMIX;
+ mem_id = SRC_MEM_DDRMIX;
+ scr = BIT(6);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mix_regs = (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (mix_id + 1));
+ mem_regs =
+ (struct src_mem_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x3800 + 0x400 * mem_id);
+ global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+
+ /* Allow NS to set it */
+ setbits_le32(&mix_regs->authen_ctrl, BIT(9));
+
+ clrsetbits_le32(&mix_regs->psw_ack_ctrl[0], BIT(28), BIT(29));
+
+ /* mix reset will be held until boot core write this bit to 1 */
+ setbits_le32(&global_regs->scr, scr);
+
+ /* Enable mem in Low power auto sequence */
+ setbits_le32(&mem_regs->mem_ctrl, BIT(2));
+
+ /* Set the power down state */
+ val = readl(&mix_regs->func_stat);
+ if (val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT) {
+ /* The mix is default power off, power down it to make PDN_SFT bit
+ * aligned with FUNC STAT
+ */
+ setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
+ val = readl(&mix_regs->func_stat);
+
+ /* Since PSW_STAT is 1, can't be used for power off status (SW_CTRL BIT31 set)) */
+ /* Check the MEM STAT change to ensure SSAR is completed */
+ while (!(val & SRC_MIX_SLICE_FUNC_STAT_MEM_STAT))
+ val = readl(&mix_regs->func_stat);
+
+ /* wait few ipg clock cycles to ensure FSM done and power off status is correct */
+ /* About 5 cycles at 24Mhz, 1us is enough */
+ udelay(1);
+ } else {
+ /* The mix is default power on, Do mix power cycle */
+ setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
+ val = readl(&mix_regs->func_stat);
+ while (!(val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT))
+ val = readl(&mix_regs->func_stat);
+ }
+
+ /* power on */
+ clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
+ val = readl(&mix_regs->func_stat);
+ while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT)
+ val = readl(&mix_regs->func_stat);
+
+ return 0;
+}
+
+void disable_isolation(void)
+{
+ struct src_general_regs *global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+ /* clear isolation for usbphy, dsi, csi*/
+ writel(0x0, &global_regs->sp_iso_ctrl);
+}
+
+void soc_power_init(void)
+{
+ mix_power_init(MIX_PD_MEDIAMIX);
+ mix_power_init(MIX_PD_MLMIX);
+
+ disable_isolation();
+}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 33/49] imx: imx9: Add M33 release prepare function
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (31 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 32/49] imx: imx9: Add MIX power init Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 34/49] imx: imx9: Support booting m33 from Acore Peng Fan (OSS)
` (16 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
To support on-demand booting M33 image from A core. SPL needs
to follow M33 kick up sequence to release M33 firstly,
then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick
M33 to run.
The prepare function also works around the M33 TCM ECC issue by
clean the TCM. Also enable sentinel handshake and WDOG1 clock
for M33 stop and reset.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/sys_proto.h | 2 +
arch/arm/mach-imx/imx9/soc.c | 51 ++++++++++++++++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 5ae7a043398..ba97f92f5ae 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -9,4 +9,6 @@
#include <asm/mach-imx/sys_proto.h>
void soc_power_init(void);
+bool m33_is_rom_kicked(void);
+int m33_prepare(void);
#endif
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 68f3ddd4287..2a29454d1eb 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -13,6 +13,7 @@
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch/ccm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/trdc.h>
#include <asm/mach-imx/boot_mode.h>
@@ -378,3 +379,53 @@ void soc_power_init(void)
disable_isolation();
}
+
+static bool m33_is_rom_kicked(void)
+{
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+
+ if (!(readl(&s_regs->m33_cfg) & BIT(2)))
+ return true;
+
+ return false;
+}
+
+int m33_prepare(void)
+{
+ struct src_mix_slice_regs *mix_regs =
+ (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (SRC_MIX_CM33 + 1));
+ struct src_general_regs *global_regs =
+ (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+ u32 val;
+
+ if (m33_is_rom_kicked())
+ return -EPERM;
+
+ /* Release reset of M33 */
+ setbits_le32(&global_regs->scr, BIT(0));
+
+ /* Check the reset released in M33 MIX func stat */
+ val = readl(&mix_regs->func_stat);
+ while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT))
+ val = readl(&mix_regs->func_stat);
+
+ /* Release Sentinel TROUT */
+ ahab_release_m33_trout();
+
+ /* Mask WDOG1 IRQ from A55, we use it for M33 reset */
+ setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6));
+
+ /* Turn on WDOG1 clock */
+ ccm_lpcg_on(CCGR_WDG1, 1);
+
+ /* Set sentinel LP handshake for M33 reset */
+ setbits_le32(&s_regs->lp_handshake[0], BIT(6));
+
+ /* Clear M33 TCM for ECC */
+ memset((void *)(ulong)0x201e0000, 0, 0x40000);
+
+ return 0;
+}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 34/49] imx: imx9: Support booting m33 from Acore
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (32 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 33/49] imx: imx9: Add M33 release prepare function Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 35/49] imx: imx9: Support multiple env storages at runtime Peng Fan (OSS)
` (15 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add bootaux command to support on-demand booting M33 from u-boot.
It kicks M33 via ATF by "bootaux 0x201e0000 0"
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx9/Makefile | 4 +
arch/arm/mach-imx/imx9/imx_bootaux.c | 133 +++++++++++++++++++++++++++
arch/arm/mach-imx/imx9/soc.c | 10 +-
include/imx_sip.h | 1 +
4 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-imx/imx9/imx_bootaux.c
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 41a22500c95..6d038a60c67 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -5,3 +5,7 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
obj-$(CONFIG_AHAB_BOOT) += ahab.o
+
+#ifndef CONFIG_SPL_BUILD
+obj-y += imx_bootaux.o
+#endif
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c
new file mode 100644
index 00000000000..3b6662aeb81
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <log.h>
+#include <imx_sip.h>
+#include <linux/arm-smccc.h>
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
+ 0, 0, 0, 0, &res);
+
+ return res.a0;
+}
+
+int arch_auxiliary_core_down(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ printf("## Stopping auxiliary core\n");
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
+ 0, 0, 0, 0, &res);
+
+ return 0;
+}
+
+int arch_auxiliary_core_up(u32 core_id, ulong addr)
+{
+ struct arm_smccc_res res;
+ u32 stack, pc;
+
+ if (!addr)
+ return -EINVAL;
+
+ stack = *(u32 *)addr;
+ pc = *(u32 *)(addr + 4);
+
+ printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc);
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
+ 0, 0, 0, 0, &res);
+
+ return 0;
+}
+
+/*
+ * To i.MX6SX and i.MX7D, the image supported by bootaux needs
+ * the reset vector at the head for the image, with SP and PC
+ * as the first two words.
+ *
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset
+ * vector with getting the PC and SP from image and filling them to
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
+ */
+static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong addr;
+ int ret, up;
+ u32 core = 0;
+ u32 stop = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (argc > 2)
+ core = simple_strtoul(argv[2], NULL, 10);
+
+ if (argc > 3)
+ stop = simple_strtoul(argv[3], NULL, 10);
+
+ up = arch_auxiliary_core_check_up(core);
+ if (up) {
+ printf("## Auxiliary core is already up\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ if (!addr)
+ return CMD_RET_FAILURE;
+
+ ret = arch_auxiliary_core_up(core, addr);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret, up;
+
+ up = arch_auxiliary_core_check_up(0);
+ if (!up) {
+ printf("## Auxiliary core is already down\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ ret = arch_auxiliary_core_down(0);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ stopaux, CONFIG_SYS_MAXARGS, 1, do_stopaux,
+ "Stop auxiliary core",
+ "<address> [<core>]\n"
+ " - start auxiliary core [<core>] (default 0),\n"
+ " at address <address>\n"
+);
+
+U_BOOT_CMD(
+ bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
+ "Start auxiliary core",
+ "<address> [<core>]\n"
+ " - start auxiliary core [<core>] (default 0),\n"
+ " at address <address>\n"
+);
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 2a29454d1eb..ca88271564c 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -131,6 +131,14 @@ static struct mm_region imx93_mem_map[] = {
.size = 0x100000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* TCM */
+ .virt = 0x201c0000UL,
+ .phys = 0x201c0000UL,
+ .size = 0x80000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* OCRAM */
.virt = 0x20480000UL,
@@ -380,7 +388,7 @@ void soc_power_init(void)
disable_isolation();
}
-static bool m33_is_rom_kicked(void)
+bool m33_is_rom_kicked(void)
{
struct blk_ctrl_s_aonmix_regs *s_regs =
(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
diff --git a/include/imx_sip.h b/include/imx_sip.h
index 26dbe0421a0..1b873f231be 100644
--- a/include/imx_sip.h
+++ b/include/imx_sip.h
@@ -15,5 +15,6 @@
#define IMX_SIP_SRC 0xC2000005
#define IMX_SIP_SRC_M4_START 0x00
#define IMX_SIP_SRC_M4_STARTED 0x01
+#define IMX_SIP_SRC_M4_STOP 0x02
#endif
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 35/49] imx: imx9: Support multiple env storages at runtime
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (33 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 34/49] imx: imx9: Support booting m33 from Acore Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 36/49] imx: imx9: clock: Add DDR clock support Peng Fan (OSS)
` (14 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Select env storages according to boot device at runtime
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx9/soc.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index ca88271564c..797d7a802ba 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -288,6 +288,40 @@ int timer_init(void)
return 0;
}
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ switch (dev) {
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+ case QSPI_BOOT:
+ env_loc = ENVL_SPI_FLASH;
+ break;
+#endif
+#if defined(CONFIG_ENV_IS_IN_MMC)
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+#endif
+ default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+ env_loc = ENVL_NOWHERE;
+#endif
+ break;
+ }
+
+ return env_loc;
+}
+
static int mix_power_init(enum mix_power_domain pd)
{
enum src_mix_slice_id mix_id;
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 36/49] imx: imx9: clock: Add DDR clock support
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (34 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 35/49] imx: imx9: Support multiple env storages at runtime Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 37/49] ddr: imx: Add i.MX9 DDR controller driver Peng Fan (OSS)
` (13 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Implement the DDR driver clock interfaces for set DDR rate and
bypass DDR PLL
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/clock.h | 3 ++
arch/arm/mach-imx/imx9/clock.c | 41 ++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
index fcf04d66f05..d96f126a1d1 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -213,6 +213,9 @@ void init_clk_usdhc(u32 index);
int enable_i2c_clk(unsigned char enable, u32 i2c_num);
u32 imx_get_i2cclk(u32 i2c_num);
u32 mxc_get_clock(enum mxc_clock clk);
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
+void dram_disable_bypass(void);
int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 55cbb40f328..5d2bc0d2f8f 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -626,6 +626,47 @@ void enable_usboh3_clk(unsigned char enable)
}
}
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
+{
+ configure_fracpll(DRAM_PLL_CLK, pll_val);
+}
+
+void dram_enable_bypass(ulong clk_val)
+{
+ switch (clk_val) {
+ case MHZ(400):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
+ break;
+ case MHZ(333):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3);
+ break;
+ case MHZ(200):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4);
+ break;
+ case MHZ(100):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8);
+ break;
+ default:
+ printf("No matched freq table %lu\n", clk_val);
+ return;
+ }
+
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from PLL to CCM */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM);
+}
+
+void dram_disable_bypass(void)
+{
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from CCM to PLL */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
+}
+#endif
+
int clock_init(void)
{
int i;
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 37/49] ddr: imx: Add i.MX9 DDR controller driver
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (35 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 36/49] imx: imx9: clock: Add DDR clock support Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 38/49] ddr: imx9: enable Performance monitor counter Peng Fan (OSS)
` (12 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.
The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx8m/ddr.h | 6 +-
arch/arm/include/asm/arch-imx9/ddr.h | 126 +++++
drivers/Makefile | 1 +
drivers/ddr/imx/Kconfig | 2 +
drivers/ddr/imx/imx8m/Kconfig | 1 +
drivers/ddr/imx/imx8m/Makefile | 3 +-
drivers/ddr/imx/imx8m/ddr_init.c | 219 ++++++++
drivers/ddr/imx/imx9/Kconfig | 21 +
drivers/ddr/imx/imx9/Makefile | 10 +
drivers/ddr/imx/imx9/ddr_init.c | 485 ++++++++++++++++++
drivers/ddr/imx/phy/Kconfig | 4 +
drivers/ddr/imx/phy/Makefile | 9 +
drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c | 0
drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c | 1 -
drivers/ddr/imx/phy/ddrphy_utils.c | 169 ++++++
drivers/ddr/imx/{imx8m => phy}/helper.c | 45 +-
16 files changed, 1077 insertions(+), 25 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx9/ddr.h
create mode 100644 drivers/ddr/imx/imx9/Kconfig
create mode 100644 drivers/ddr/imx/imx9/Makefile
create mode 100644 drivers/ddr/imx/imx9/ddr_init.c
create mode 100644 drivers/ddr/imx/phy/Kconfig
create mode 100644 drivers/ddr/imx/phy/Makefile
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c (100%)
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c (98%)
create mode 100644 drivers/ddr/imx/phy/ddrphy_utils.c
rename drivers/ddr/imx/{imx8m => phy}/helper.c (79%)
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 2ce8a8f2d41..2f76e7d69b9 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -725,6 +725,8 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num);
void get_trained_CDD(unsigned int fsp);
unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr);
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr);
+
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);
@@ -741,9 +743,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
}
#define dwc_ddrphy_apb_wr(addr, data) \
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
#define dwc_ddrphy_apb_rd(addr) \
- reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
+ reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
extern struct dram_cfg_param ddrphy_trained_csr[];
extern uint32_t ddrphy_trained_csr_num;
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
new file mode 100644
index 00000000000..62e6f7dda53
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_DDR_H
+#define __ASM_ARCH_IMX8M_DDR_H
+
+#include <asm/io.h>
+#include <asm/types.h>
+
+#define DDR_CTL_BASE 0x4E300000
+#define DDR_PHY_BASE 0x4E100000
+#define DDRMIX_BLK_CTRL_BASE 0x4E010000
+
+#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
+#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
+#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
+
+#define SRC_BASE_ADDR (0x44460000)
+#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
+#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20)
+#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24)
+
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + ((X) * 0x2000000))
+#define DDRPHY_MEM(X) (DDR_PHY_BASE + ((X) * 0x2000000) + 0x50000)
+
+/* PHY State */
+enum pstate {
+ PS0,
+ PS1,
+ PS2,
+ PS3,
+};
+
+enum msg_response {
+ TRAIN_SUCCESS = 0x7,
+ TRAIN_STREAM_START = 0x8,
+ TRAIN_FAIL = 0xff,
+};
+
+/* user data type */
+enum fw_type {
+ FW_1D_IMAGE,
+ FW_2D_IMAGE,
+};
+
+struct dram_cfg_param {
+ unsigned int reg;
+ unsigned int val;
+};
+
+struct dram_fsp_msg {
+ unsigned int drate;
+ enum fw_type fw_type;
+ struct dram_cfg_param *fsp_cfg;
+ unsigned int fsp_cfg_num;
+};
+
+struct dram_timing_info {
+ /* umctl2 config */
+ struct dram_cfg_param *ddrc_cfg;
+ unsigned int ddrc_cfg_num;
+ /* ddrphy config */
+ struct dram_cfg_param *ddrphy_cfg;
+ unsigned int ddrphy_cfg_num;
+ /* ddr fsp train info */
+ struct dram_fsp_msg *fsp_msg;
+ unsigned int fsp_msg_num;
+ /* ddr phy trained CSR */
+ struct dram_cfg_param *ddrphy_trained_csr;
+ unsigned int ddrphy_trained_csr_num;
+ /* ddr phy PIE */
+ struct dram_cfg_param *ddrphy_pie;
+ unsigned int ddrphy_pie_num;
+ /* initialized drate table */
+ unsigned int fsp_table[4];
+};
+
+extern struct dram_timing_info dram_timing;
+
+void ddr_load_train_firmware(enum fw_type type);
+int ddr_init(struct dram_timing_info *timing_info);
+int ddr_cfg_phy(struct dram_timing_info *timing_info);
+void load_lpddr4_phy_pie(void);
+void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
+void dram_config_save(struct dram_timing_info *info, unsigned long base);
+void board_dram_ecc_scrub(void);
+void ddrc_inline_ecc_scrub(unsigned int start_address,
+ unsigned int range_address);
+void ddrc_inline_ecc_scrub_end(unsigned int start_address,
+ unsigned int range_address);
+
+/* utils function for ddr phy training */
+int wait_ddrphy_training_complete(void);
+void ddrphy_init_set_dfi_clk(unsigned int drate);
+void ddrphy_init_read_msg_block(enum fw_type type);
+
+void get_trained_CDD(unsigned int fsp);
+
+ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+ writel(val, addr);
+}
+
+static inline u32 reg32_read(unsigned long addr)
+{
+ return readl(addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+ setbits_le32(addr, (1 << bit));
+}
+
+#define dwc_ddrphy_apb_wr(addr, data) \
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
+#define dwc_ddrphy_apb_rd(addr) \
+ reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
+
+extern struct dram_cfg_param ddrphy_trained_csr[];
+extern u32 ddrphy_trained_csr_num;
+
+#endif
diff --git a/drivers/Makefile b/drivers/Makefile
index d63fd1c04d1..eba9940231f 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
+obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/
obj-$(CONFIG_SPL_DM_RESET) += reset/
obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/
obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/
diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig
index 179f34530d7..328fbabb6db 100644
--- a/drivers/ddr/imx/Kconfig
+++ b/drivers/ddr/imx/Kconfig
@@ -1,2 +1,4 @@
source "drivers/ddr/imx/imx8m/Kconfig"
source "drivers/ddr/imx/imx8ulp/Kconfig"
+source "drivers/ddr/imx/imx9/Kconfig"
+source "drivers/ddr/imx/phy/Kconfig"
diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
index a90b7db4940..08b6787a543 100644
--- a/drivers/ddr/imx/imx8m/Kconfig
+++ b/drivers/ddr/imx/imx8m/Kconfig
@@ -3,6 +3,7 @@ menu "i.MX8M DDR controllers"
config IMX8M_DRAM
bool "imx8m dram"
+ select IMX_SNPS_DDR_PHY
config IMX8M_LPDDR4
bool "imx8m lpddr4"
diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile
index bd9bcb8d53b..aed91dc23f4 100644
--- a/drivers/ddr/imx/imx8m/Makefile
+++ b/drivers/ddr/imx/imx8m/Makefile
@@ -5,5 +5,6 @@
#
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o ddr_init.o
+obj-$(CONFIG_IMX8M_DRAM) += ddr_init.o
+obj-y += ../phy/
endif
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index b70bcc383fa..d964184ddc8 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -11,6 +11,11 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
+static unsigned int g_cdd_rr_max[4];
+static unsigned int g_cdd_rw_max[4];
+static unsigned int g_cdd_wr_max[4];
+static unsigned int g_cdd_ww_max[4];
+
void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
{
int i = 0;
@@ -91,6 +96,215 @@ void __weak board_dram_ecc_scrub(void)
{
}
+void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
+ unsigned int mr_data)
+{
+ unsigned int tmp;
+ /*
+ * 1. Poll MRSTAT.mr_wr_busy until it is 0.
+ * This checks that there is no outstanding MR transaction.
+ * No writes should be performed to MRCTRL0 and MRCTRL1 if
+ * MRSTAT.mr_wr_busy = 1.
+ */
+ do {
+ tmp = reg32_read(DDRC_MRSTAT(0));
+ } while (tmp & 0x1);
+ /*
+ * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
+ * (for MRWs) MRCTRL1.mr_data to define the MR transaction.
+ */
+ reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
+ reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
+ reg32setbit(DDRC_MRCTRL0(0), 31);
+}
+
+unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
+{
+ unsigned int tmp;
+
+ reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
+ do {
+ tmp = reg32_read(DDRC_MRSTAT(0));
+ } while (tmp & 0x1);
+
+ reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
+ reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
+ reg32setbit(DDRC_MRCTRL0(0), 31);
+ do {
+ tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
+ } while ((tmp & 0x8) == 0);
+ tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
+ tmp = tmp & 0xff;
+ reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+
+ return tmp;
+}
+
+static unsigned int look_for_max(unsigned int data[], unsigned int addr_start,
+ unsigned int addr_end)
+{
+ unsigned int i, imax = 0;
+
+ for (i = addr_start; i <= addr_end; i++) {
+ if (((data[i] >> 7) == 0) && data[i] > imax)
+ imax = data[i];
+ }
+
+ return imax;
+}
+
+void get_trained_CDD(u32 fsp)
+{
+ unsigned int i, ddr_type, tmp;
+ unsigned int cdd_cha[12], cdd_chb[12];
+ unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
+ unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
+
+ ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
+ if (ddr_type == 0x20) {
+ for (i = 0; i < 6; i++) {
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4);
+ cdd_cha[i * 2] = tmp & 0xff;
+ cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
+ }
+
+ for (i = 0; i < 7; i++) {
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4);
+ if (i == 0) {
+ cdd_cha[0] = (tmp >> 8) & 0xff;
+ } else if (i == 6) {
+ cdd_cha[11] = tmp & 0xff;
+ } else {
+ cdd_chb[i * 2 - 1] = tmp & 0xff;
+ cdd_chb[i * 2] = (tmp >> 8) & 0xff;
+ }
+ }
+
+ cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
+ cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
+ cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
+ cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
+ cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
+ cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
+ cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
+ cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
+ g_cdd_rr_max[fsp] =
+ cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
+ g_cdd_rw_max[fsp] =
+ cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
+ g_cdd_wr_max[fsp] =
+ cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
+ g_cdd_ww_max[fsp] =
+ cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
+ } else {
+ unsigned int ddr4_cdd[64];
+
+ for (i = 0; i < 29; i++) {
+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
+ ddr4_cdd[i * 2] = tmp & 0xff;
+ ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
+ }
+
+ g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
+ g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
+ g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
+ g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
+ }
+}
+
+void update_umctl2_rank_space_setting(unsigned int pstat_num)
+{
+ unsigned int i, ddr_type;
+ unsigned int addr_slot, rdata, tmp, tmp_t;
+ unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap;
+
+ ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
+ for (i = 0; i < pstat_num; i++) {
+ addr_slot = i ? (i + 1) * 0x1000 : 0;
+ if (ddr_type == 0x20) {
+ /* update r2w:[13:8], w2r:[5:0] */
+ rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
+ ddrc_w2r = rdata & 0x3f;
+ if (is_imx8mp())
+ tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
+ else
+ tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
+ ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
+
+ ddrc_r2w = (rdata >> 8) & 0x3f;
+ if (is_imx8mp())
+ tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
+ else
+ tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
+ ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
+
+ tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
+ reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
+ } else {
+ /* update w2r:[5:0] */
+ rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
+ ddrc_w2r = rdata & 0x3f;
+ if (is_imx8mp())
+ tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
+ else
+ tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
+ ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
+ tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
+ reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
+
+ /* update r2w:[13:8] */
+ rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
+ ddrc_r2w = (rdata >> 8) & 0x3f;
+ if (is_imx8mp())
+ tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
+ else
+ tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
+ ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
+
+ tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
+ reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
+ }
+
+ if (!is_imx8mq()) {
+ /*
+ * update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static)
+ */
+ rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
+ ddrc_wr_gap = (rdata >> 8) & 0xf;
+ if (is_imx8mp())
+ tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
+ else
+ tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
+ ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
+
+ ddrc_rd_gap = (rdata >> 4) & 0xf;
+ if (is_imx8mp())
+ tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
+ else
+ tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
+ ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
+
+ tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
+ reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
+ }
+ }
+
+ if (is_imx8mq()) {
+ /* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
+ rdata = reg32_read(DDRC_RANKCTL(0));
+ ddrc_wr_gap = (rdata >> 8) & 0xf;
+ tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
+ ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
+
+ ddrc_rd_gap = (rdata >> 4) & 0xf;
+ tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
+ ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
+
+ tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
+ reg32_write(DDRC_RANKCTL(0), tmp_t);
+ }
+}
+
int ddr_init(struct dram_timing_info *dram_timing)
{
unsigned int tmp, initial_drate, target_freq;
@@ -250,3 +464,8 @@ int ddr_init(struct dram_timing_info *dram_timing)
return 0;
}
+
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr)
+{
+ return 4 * paddr_apb_from_ctlr;
+}
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
new file mode 100644
index 00000000000..a16ddc65e01
--- /dev/null
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -0,0 +1,21 @@
+menu "i.MX9 DDR controllers"
+ depends on ARCH_IMX9
+
+config IMX9_DRAM
+ bool "imx9 dram"
+ select IMX_SNPS_DDR_PHY
+
+config IMX9_LPDDR4X
+ bool "imx9 lpddr4 and lpddr4x"
+ select IMX9_DRAM
+ help
+ Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC.
+
+config SAVED_DRAM_TIMING_BASE
+ hex "Define the base address for saved dram timing"
+ help
+ after DRAM is trained, need to save the dram related timming
+ info into memory for low power use.
+ default 0x204DC000
+
+endmenu
diff --git a/drivers/ddr/imx/imx9/Makefile b/drivers/ddr/imx/imx9/Makefile
new file mode 100644
index 00000000000..9403f988b32
--- /dev/null
+++ b/drivers/ddr/imx/imx9/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_IMX9_DRAM) += ddr_init.o
+obj-y += ../phy/
+endif
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
new file mode 100644
index 00000000000..16eac65105f
--- /dev/null
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -0,0 +1,485 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+
+void ddrphy_coldreset(void)
+{
+ /* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */
+ /* dramphy_reset_n default 0 , assert -> 0, de_assert -> 1 */
+ /* dramphy_PwrOKIn default 0 , assert -> 1, de_assert -> 0 */
+
+ /* src_gen_dphy_apb_sw_rst_de_assert */
+ clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
+ /* src_gen_dphy_sw_rst_de_assert */
+ clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
+ /* src_gen_dphy_PwrOKIn_sw_rst_de_assert() */
+ setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
+ mdelay(10);
+
+ /* src_gen_dphy_apb_sw_rst_assert */
+ setbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
+ /* src_gen_dphy_sw_rst_assert */
+ setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
+ mdelay(10);
+ /* src_gen_dphy_PwrOKIn_sw_rst_assert */
+ clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
+ mdelay(10);
+
+ /* src_gen_dphy_apb_sw_rst_de_assert */
+ clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
+ /* src_gen_dphy_sw_rst_de_assert() */
+ clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
+}
+
+void check_ddrc_idle(void)
+{
+ u32 regval;
+
+ do {
+ regval = readl(REG_DDRDSR_2);
+ if (regval & BIT(31))
+ break;
+ } while (1);
+}
+
+void check_dfi_init_complete(void)
+{
+ u32 regval;
+
+ do {
+ regval = readl(REG_DDRDSR_2);
+ if (regval & BIT(2))
+ break;
+ } while (1);
+ setbits_le32(REG_DDRDSR_2, BIT(2));
+}
+
+void ddrc_config(struct dram_cfg_param *ddrc_config, int num)
+{
+ int i = 0;
+
+ for (i = 0; i < num; i++) {
+ writel(ddrc_config->val, (ulong)ddrc_config->reg);
+ ddrc_config++;
+ }
+}
+
+void get_trained_CDD(u32 fsp)
+{
+}
+
+int ddr_init(struct dram_timing_info *dram_timing)
+{
+ unsigned int initial_drate;
+ int ret;
+ u32 regval;
+
+ debug("DDRINFO: start DRAM init\n");
+
+ /* reset ddrphy */
+ ddrphy_coldreset();
+
+ debug("DDRINFO: cfg clk\n");
+
+ initial_drate = dram_timing->fsp_msg[0].drate;
+ /* default to the frequency point 0 clock */
+ ddrphy_init_set_dfi_clk(initial_drate);
+
+ /*
+ * Start PHY initialization and training by
+ * accessing relevant PUB registers
+ */
+ debug("DDRINFO:ddrphy config start\n");
+
+ ret = ddr_cfg_phy(dram_timing);
+ if (ret)
+ return ret;
+
+ debug("DDRINFO: ddrphy config done\n");
+
+ /* rogram the ddrc registers */
+ debug("DDRINFO: ddrc config start\n");
+ ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
+ debug("DDRINFO: ddrc config done\n");
+
+ check_dfi_init_complete();
+
+ regval = readl(REG_DDR_SDRAM_CFG);
+ writel((regval | 0x80000000), REG_DDR_SDRAM_CFG);
+
+ check_ddrc_idle();
+
+ /* save the dram timing config into memory */
+ dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
+
+ return 0;
+}
+
+ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr)
+{
+ u32 paddr_apb_qual;
+ u32 paddr_apb_unqual_dec_22_13;
+ u32 paddr_apb_unqual_dec_19_13;
+ u32 paddr_apb_unqual_dec_12_1;
+ u32 paddr_apb_unqual;
+ u32 paddr_apb_phy;
+
+ paddr_apb_qual = (paddr_apb_from_ctlr << 1);
+ paddr_apb_unqual_dec_22_13 = ((paddr_apb_qual & 0x7fe000) >> 13);
+ paddr_apb_unqual_dec_12_1 = ((paddr_apb_qual & 0x1ffe) >> 1);
+
+ switch (paddr_apb_unqual_dec_22_13) {
+ case 0x000:
+ paddr_apb_unqual_dec_19_13 = 0x00;
+ break;
+ case 0x001:
+ paddr_apb_unqual_dec_19_13 = 0x01;
+ break;
+ case 0x002:
+ paddr_apb_unqual_dec_19_13 = 0x02;
+ break;
+ case 0x003:
+ paddr_apb_unqual_dec_19_13 = 0x03;
+ break;
+ case 0x004:
+ paddr_apb_unqual_dec_19_13 = 0x04;
+ break;
+ case 0x005:
+ paddr_apb_unqual_dec_19_13 = 0x05;
+ break;
+ case 0x006:
+ paddr_apb_unqual_dec_19_13 = 0x06;
+ break;
+ case 0x007:
+ paddr_apb_unqual_dec_19_13 = 0x07;
+ break;
+ case 0x008:
+ paddr_apb_unqual_dec_19_13 = 0x08;
+ break;
+ case 0x009:
+ paddr_apb_unqual_dec_19_13 = 0x09;
+ break;
+ case 0x00a:
+ paddr_apb_unqual_dec_19_13 = 0x0a;
+ break;
+ case 0x00b:
+ paddr_apb_unqual_dec_19_13 = 0x0b;
+ break;
+ case 0x100:
+ paddr_apb_unqual_dec_19_13 = 0x0c;
+ break;
+ case 0x101:
+ paddr_apb_unqual_dec_19_13 = 0x0d;
+ break;
+ case 0x102:
+ paddr_apb_unqual_dec_19_13 = 0x0e;
+ break;
+ case 0x103:
+ paddr_apb_unqual_dec_19_13 = 0x0f;
+ break;
+ case 0x104:
+ paddr_apb_unqual_dec_19_13 = 0x10;
+ break;
+ case 0x105:
+ paddr_apb_unqual_dec_19_13 = 0x11;
+ break;
+ case 0x106:
+ paddr_apb_unqual_dec_19_13 = 0x12;
+ break;
+ case 0x107:
+ paddr_apb_unqual_dec_19_13 = 0x13;
+ break;
+ case 0x108:
+ paddr_apb_unqual_dec_19_13 = 0x14;
+ break;
+ case 0x109:
+ paddr_apb_unqual_dec_19_13 = 0x15;
+ break;
+ case 0x10a:
+ paddr_apb_unqual_dec_19_13 = 0x16;
+ break;
+ case 0x10b:
+ paddr_apb_unqual_dec_19_13 = 0x17;
+ break;
+ case 0x200:
+ paddr_apb_unqual_dec_19_13 = 0x18;
+ break;
+ case 0x201:
+ paddr_apb_unqual_dec_19_13 = 0x19;
+ break;
+ case 0x202:
+ paddr_apb_unqual_dec_19_13 = 0x1a;
+ break;
+ case 0x203:
+ paddr_apb_unqual_dec_19_13 = 0x1b;
+ break;
+ case 0x204:
+ paddr_apb_unqual_dec_19_13 = 0x1c;
+ break;
+ case 0x205:
+ paddr_apb_unqual_dec_19_13 = 0x1d;
+ break;
+ case 0x206:
+ paddr_apb_unqual_dec_19_13 = 0x1e;
+ break;
+ case 0x207:
+ paddr_apb_unqual_dec_19_13 = 0x1f;
+ break;
+ case 0x208:
+ paddr_apb_unqual_dec_19_13 = 0x20;
+ break;
+ case 0x209:
+ paddr_apb_unqual_dec_19_13 = 0x21;
+ break;
+ case 0x20a:
+ paddr_apb_unqual_dec_19_13 = 0x22;
+ break;
+ case 0x20b:
+ paddr_apb_unqual_dec_19_13 = 0x23;
+ break;
+ case 0x300:
+ paddr_apb_unqual_dec_19_13 = 0x24;
+ break;
+ case 0x301:
+ paddr_apb_unqual_dec_19_13 = 0x25;
+ break;
+ case 0x302:
+ paddr_apb_unqual_dec_19_13 = 0x26;
+ break;
+ case 0x303:
+ paddr_apb_unqual_dec_19_13 = 0x27;
+ break;
+ case 0x304:
+ paddr_apb_unqual_dec_19_13 = 0x28;
+ break;
+ case 0x305:
+ paddr_apb_unqual_dec_19_13 = 0x29;
+ break;
+ case 0x306:
+ paddr_apb_unqual_dec_19_13 = 0x2a;
+ break;
+ case 0x307:
+ paddr_apb_unqual_dec_19_13 = 0x2b;
+ break;
+ case 0x308:
+ paddr_apb_unqual_dec_19_13 = 0x2c;
+ break;
+ case 0x309:
+ paddr_apb_unqual_dec_19_13 = 0x2d;
+ break;
+ case 0x30a:
+ paddr_apb_unqual_dec_19_13 = 0x2e;
+ break;
+ case 0x30b:
+ paddr_apb_unqual_dec_19_13 = 0x2f;
+ break;
+ case 0x010:
+ paddr_apb_unqual_dec_19_13 = 0x30;
+ break;
+ case 0x011:
+ paddr_apb_unqual_dec_19_13 = 0x31;
+ break;
+ case 0x012:
+ paddr_apb_unqual_dec_19_13 = 0x32;
+ break;
+ case 0x013:
+ paddr_apb_unqual_dec_19_13 = 0x33;
+ break;
+ case 0x014:
+ paddr_apb_unqual_dec_19_13 = 0x34;
+ break;
+ case 0x015:
+ paddr_apb_unqual_dec_19_13 = 0x35;
+ break;
+ case 0x016:
+ paddr_apb_unqual_dec_19_13 = 0x36;
+ break;
+ case 0x017:
+ paddr_apb_unqual_dec_19_13 = 0x37;
+ break;
+ case 0x018:
+ paddr_apb_unqual_dec_19_13 = 0x38;
+ break;
+ case 0x019:
+ paddr_apb_unqual_dec_19_13 = 0x39;
+ break;
+ case 0x110:
+ paddr_apb_unqual_dec_19_13 = 0x3a;
+ break;
+ case 0x111:
+ paddr_apb_unqual_dec_19_13 = 0x3b;
+ break;
+ case 0x112:
+ paddr_apb_unqual_dec_19_13 = 0x3c;
+ break;
+ case 0x113:
+ paddr_apb_unqual_dec_19_13 = 0x3d;
+ break;
+ case 0x114:
+ paddr_apb_unqual_dec_19_13 = 0x3e;
+ break;
+ case 0x115:
+ paddr_apb_unqual_dec_19_13 = 0x3f;
+ break;
+ case 0x116:
+ paddr_apb_unqual_dec_19_13 = 0x40;
+ break;
+ case 0x117:
+ paddr_apb_unqual_dec_19_13 = 0x41;
+ break;
+ case 0x118:
+ paddr_apb_unqual_dec_19_13 = 0x42;
+ break;
+ case 0x119:
+ paddr_apb_unqual_dec_19_13 = 0x43;
+ break;
+ case 0x210:
+ paddr_apb_unqual_dec_19_13 = 0x44;
+ break;
+ case 0x211:
+ paddr_apb_unqual_dec_19_13 = 0x45;
+ break;
+ case 0x212:
+ paddr_apb_unqual_dec_19_13 = 0x46;
+ break;
+ case 0x213:
+ paddr_apb_unqual_dec_19_13 = 0x47;
+ break;
+ case 0x214:
+ paddr_apb_unqual_dec_19_13 = 0x48;
+ break;
+ case 0x215:
+ paddr_apb_unqual_dec_19_13 = 0x49;
+ break;
+ case 0x216:
+ paddr_apb_unqual_dec_19_13 = 0x4a;
+ break;
+ case 0x217:
+ paddr_apb_unqual_dec_19_13 = 0x4b;
+ break;
+ case 0x218:
+ paddr_apb_unqual_dec_19_13 = 0x4c;
+ break;
+ case 0x219:
+ paddr_apb_unqual_dec_19_13 = 0x4d;
+ break;
+ case 0x310:
+ paddr_apb_unqual_dec_19_13 = 0x4e;
+ break;
+ case 0x311:
+ paddr_apb_unqual_dec_19_13 = 0x4f;
+ break;
+ case 0x312:
+ paddr_apb_unqual_dec_19_13 = 0x50;
+ break;
+ case 0x313:
+ paddr_apb_unqual_dec_19_13 = 0x51;
+ break;
+ case 0x314:
+ paddr_apb_unqual_dec_19_13 = 0x52;
+ break;
+ case 0x315:
+ paddr_apb_unqual_dec_19_13 = 0x53;
+ break;
+ case 0x316:
+ paddr_apb_unqual_dec_19_13 = 0x54;
+ break;
+ case 0x317:
+ paddr_apb_unqual_dec_19_13 = 0x55;
+ break;
+ case 0x318:
+ paddr_apb_unqual_dec_19_13 = 0x56;
+ break;
+ case 0x319:
+ paddr_apb_unqual_dec_19_13 = 0x57;
+ break;
+ case 0x020:
+ paddr_apb_unqual_dec_19_13 = 0x58;
+ break;
+ case 0x120:
+ paddr_apb_unqual_dec_19_13 = 0x59;
+ break;
+ case 0x220:
+ paddr_apb_unqual_dec_19_13 = 0x5a;
+ break;
+ case 0x320:
+ paddr_apb_unqual_dec_19_13 = 0x5b;
+ break;
+ case 0x040:
+ paddr_apb_unqual_dec_19_13 = 0x5c;
+ break;
+ case 0x140:
+ paddr_apb_unqual_dec_19_13 = 0x5d;
+ break;
+ case 0x240:
+ paddr_apb_unqual_dec_19_13 = 0x5e;
+ break;
+ case 0x340:
+ paddr_apb_unqual_dec_19_13 = 0x5f;
+ break;
+ case 0x050:
+ paddr_apb_unqual_dec_19_13 = 0x60;
+ break;
+ case 0x051:
+ paddr_apb_unqual_dec_19_13 = 0x61;
+ break;
+ case 0x052:
+ paddr_apb_unqual_dec_19_13 = 0x62;
+ break;
+ case 0x053:
+ paddr_apb_unqual_dec_19_13 = 0x63;
+ break;
+ case 0x054:
+ paddr_apb_unqual_dec_19_13 = 0x64;
+ break;
+ case 0x055:
+ paddr_apb_unqual_dec_19_13 = 0x65;
+ break;
+ case 0x056:
+ paddr_apb_unqual_dec_19_13 = 0x66;
+ break;
+ case 0x057:
+ paddr_apb_unqual_dec_19_13 = 0x67;
+ break;
+ case 0x070:
+ paddr_apb_unqual_dec_19_13 = 0x68;
+ break;
+ case 0x090:
+ paddr_apb_unqual_dec_19_13 = 0x69;
+ break;
+ case 0x190:
+ paddr_apb_unqual_dec_19_13 = 0x6a;
+ break;
+ case 0x290:
+ paddr_apb_unqual_dec_19_13 = 0x6b;
+ break;
+ case 0x390:
+ paddr_apb_unqual_dec_19_13 = 0x6c;
+ break;
+ case 0x0c0:
+ paddr_apb_unqual_dec_19_13 = 0x6d;
+ break;
+ case 0x0d0:
+ paddr_apb_unqual_dec_19_13 = 0x6e;
+ break;
+ default:
+ paddr_apb_unqual_dec_19_13 = 0x00;
+ break;
+ }
+
+ paddr_apb_unqual = ((paddr_apb_unqual_dec_19_13 << 13) | (paddr_apb_unqual_dec_12_1 << 1));
+
+ paddr_apb_phy = (paddr_apb_unqual << 1);
+
+ return paddr_apb_phy;
+}
diff --git a/drivers/ddr/imx/phy/Kconfig b/drivers/ddr/imx/phy/Kconfig
new file mode 100644
index 00000000000..d3e589b23c4
--- /dev/null
+++ b/drivers/ddr/imx/phy/Kconfig
@@ -0,0 +1,4 @@
+config IMX_SNPS_DDR_PHY
+ bool "i.MX Snopsys DDR PHY"
+ help
+ Select the DDR PHY driver support on i.MX8M and i.MX9 SOC.
diff --git a/drivers/ddr/imx/phy/Makefile b/drivers/ddr/imx/phy/Makefile
new file mode 100644
index 00000000000..bb3d4ee5b74
--- /dev/null
+++ b/drivers/ddr/imx/phy/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
+endif
diff --git a/drivers/ddr/imx/imx8m/ddrphy_csr.c b/drivers/ddr/imx/phy/ddrphy_csr.c
similarity index 100%
rename from drivers/ddr/imx/imx8m/ddrphy_csr.c
rename to drivers/ddr/imx/phy/ddrphy_csr.c
diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c
similarity index 98%
rename from drivers/ddr/imx/imx8m/ddrphy_train.c
rename to drivers/ddr/imx/phy/ddrphy_train.c
index 08fed6178f3..cd905f952c6 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_train.c
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -7,7 +7,6 @@
#include <log.h>
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
-#include <asm/arch/lpddr4_define.h>
#include <asm/arch/sys_proto.h>
int ddr_cfg_phy(struct dram_timing_info *dram_timing)
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
new file mode 100644
index 00000000000..b852c870f90
--- /dev/null
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/sys_proto.h>
+
+static inline void poll_pmu_message_ready(void)
+{
+ unsigned int reg;
+
+ do {
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
+ } while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_receive(void)
+{
+ unsigned int reg;
+
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0);
+
+ do {
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
+ } while (!(reg & 0x1));
+
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+ unsigned int reg;
+
+ poll_pmu_message_ready();
+
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
+
+ ack_pmu_message_receive();
+
+ return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+ unsigned int reg, reg2;
+
+ poll_pmu_message_ready();
+
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
+
+ reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034));
+
+ reg2 = (reg2 << 16) | reg;
+
+ ack_pmu_message_receive();
+
+ return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+ debug("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+ unsigned int string_index, arg __maybe_unused;
+ int i = 0;
+
+ string_index = get_stream_message();
+ debug("PMU String index = 0x%08x\n", string_index);
+ while (i < (string_index & 0xffff)) {
+ arg = get_stream_message();
+ debug("arg[%d] = 0x%08x\n", i, arg);
+ i++;
+ }
+
+ debug("\n");
+}
+
+int wait_ddrphy_training_complete(void)
+{
+ unsigned int mail;
+
+ while (1) {
+ mail = get_mail();
+ decode_major_message(mail);
+ if (mail == 0x08) {
+ decode_streaming_message();
+ } else if (mail == 0x07) {
+ debug("Training PASS\n");
+ return 0;
+ } else if (mail == 0xff) {
+ printf("Training FAILED\n");
+ return -1;
+ }
+ }
+}
+
+void ddrphy_init_set_dfi_clk(unsigned int drate)
+{
+ switch (drate) {
+ case 4000:
+ dram_pll_init(MHZ(1000));
+ dram_disable_bypass();
+ break;
+ case 3733:
+ dram_pll_init(MHZ(933));
+ dram_disable_bypass();
+ break;
+ case 3200:
+ dram_pll_init(MHZ(800));
+ dram_disable_bypass();
+ break;
+ case 3000:
+ dram_pll_init(MHZ(750));
+ dram_disable_bypass();
+ break;
+ case 2800:
+ dram_pll_init(MHZ(700));
+ dram_disable_bypass();
+ break;
+ case 2400:
+ dram_pll_init(MHZ(600));
+ dram_disable_bypass();
+ break;
+ case 1866:
+ dram_pll_init(MHZ(466));
+ dram_disable_bypass();
+ break;
+ case 1600:
+ dram_pll_init(MHZ(400));
+ dram_disable_bypass();
+ break;
+ case 1066:
+ dram_pll_init(MHZ(266));
+ dram_disable_bypass();
+ break;
+ case 667:
+ dram_pll_init(MHZ(167));
+ dram_disable_bypass();
+ break;
+ case 400:
+ dram_enable_bypass(MHZ(400));
+ break;
+ case 333:
+ dram_enable_bypass(MHZ(333));
+ break;
+ case 200:
+ dram_enable_bypass(MHZ(200));
+ break;
+ case 100:
+ dram_enable_bypass(MHZ(100));
+ break;
+ default:
+ return;
+ }
+}
+
+void ddrphy_init_read_msg_block(enum fw_type type)
+{
+}
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/phy/helper.c
similarity index 79%
rename from drivers/ddr/imx/imx8m/helper.c
rename to drivers/ddr/imx/phy/helper.c
index f23904bf712..60d650e3089 100644
--- a/drivers/ddr/imx/imx8m/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -12,7 +12,6 @@
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/ddr.h>
-#include <asm/arch/lpddr4_define.h>
#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -46,43 +45,46 @@ void ddr_load_train_firmware(enum fw_type type)
dmem_start = imem_start + IMEM_LEN;
pr_from32 = imem_start;
- pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+ pr_to32 = IMEM_OFFSET_ADDR;
for (i = 0x0; i < IMEM_LEN; ) {
tmp32 = readl(pr_from32);
- writew(tmp32 & 0x0000ffff, pr_to32);
- pr_to32 += 4;
- writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
- pr_to32 += 4;
+ writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+ pr_to32 += 1;
+ writew((tmp32 >> 16) & 0x0000ffff,
+ DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+ pr_to32 += 1;
pr_from32 += 4;
i += 4;
}
pr_from32 = dmem_start;
- pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+ pr_to32 = DMEM_OFFSET_ADDR;
for (i = 0x0; i < DMEM_LEN; ) {
tmp32 = readl(pr_from32);
- writew(tmp32 & 0x0000ffff, pr_to32);
- pr_to32 += 4;
- writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
- pr_to32 += 4;
+ writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+ pr_to32 += 1;
+ writew((tmp32 >> 16) & 0x0000ffff,
+ DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+ pr_to32 += 1;
pr_from32 += 4;
i += 4;
}
debug("check ddr_pmu_train_imem code\n");
pr_from32 = imem_start;
- pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+ pr_to32 = IMEM_OFFSET_ADDR;
for (i = 0x0; i < IMEM_LEN; ) {
- tmp32 = (readw(pr_to32) & 0x0000ffff);
- pr_to32 += 4;
- tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+ tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff);
+ pr_to32 += 1;
+ tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
+ ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16);
if (tmp32 != readl(pr_from32)) {
debug("%lx %lx\n", pr_from32, pr_to32);
error++;
}
pr_from32 += 4;
- pr_to32 += 4;
+ pr_to32 += 1;
i += 4;
}
if (error)
@@ -92,17 +94,18 @@ void ddr_load_train_firmware(enum fw_type type)
debug("check ddr4_pmu_train_dmem code\n");
pr_from32 = dmem_start;
- pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+ pr_to32 = DMEM_OFFSET_ADDR;
for (i = 0x0; i < DMEM_LEN;) {
- tmp32 = (readw(pr_to32) & 0x0000ffff);
- pr_to32 += 4;
- tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+ tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff);
+ pr_to32 += 1;
+ tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
+ ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16);
if (tmp32 != readl(pr_from32)) {
debug("%lx %lx\n", pr_from32, pr_to32);
error++;
}
pr_from32 += 4;
- pr_to32 += 4;
+ pr_to32 += 1;
i += 4;
}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 38/49] ddr: imx9: enable Performance monitor counter
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (36 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 37/49] ddr: imx: Add i.MX9 DDR controller driver Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 39/49] arm: dts: Add i.MX93 SoC DTSi file Peng Fan (OSS)
` (11 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Add Kconfig for enabling reference events counter in DDRC performance
monitor by default
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/ddr/imx/imx9/Kconfig | 6 ++++++
drivers/ddr/imx/imx9/ddr_init.c | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
index a16ddc65e01..123ad173cfc 100644
--- a/drivers/ddr/imx/imx9/Kconfig
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -11,6 +11,12 @@ config IMX9_LPDDR4X
help
Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC.
+config IMX9_DRAM_PM_COUNTER
+ bool "imx9 DDRC performance monitor counter"
+ default y
+ help
+ Enable DDR controller performance monitor counter for reference events.
+
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
help
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 16eac65105f..8b8ec7f8de3 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -112,6 +112,10 @@ int ddr_init(struct dram_timing_info *dram_timing)
ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
debug("DDRINFO: ddrc config done\n");
+#ifdef CONFIG_IMX9_DRAM_PM_COUNTER
+ writel(0x200000, REG_DDR_DEBUG_19);
+#endif
+
check_dfi_init_complete();
regval = readl(REG_DDR_SDRAM_CFG);
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 39/49] arm: dts: Add i.MX93 SoC DTSi file
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (37 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 38/49] ddr: imx9: enable Performance monitor counter Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 40/49] imx: imx93_evk: Add basic board support Peng Fan (OSS)
` (10 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Add the DTSi file and DT header files for i.MX93 SoC
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/dts/imx93.dtsi | 688 ++++++++++++++++++++++++
include/dt-bindings/clock/imx93-clock.h | 203 +++++++
include/dt-bindings/power/imx93-power.h | 12 +
3 files changed, 903 insertions(+)
create mode 100644 arch/arm/dts/imx93.dtsi
create mode 100644 include/dt-bindings/clock/imx93-clock.h
create mode 100644 include/dt-bindings/power/imx93-power.h
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
new file mode 100644
index 00000000000..28026ccecc8
--- /dev/null
+++ b/arch/arm/dts/imx93.dtsi
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <dt-bindings/clock/imx93-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/imx93-power.h>
+#include <dt-bindings/usb/pd.h>
+
+#include "imx93-pinfunc.h"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ ethernet0 = &fec;
+ ethernet1 = &eqos;
+ serial0 = &lpuart1;
+ serial1 = &lpuart2;
+ serial2 = &lpuart3;
+ serial3 = &lpuart4;
+ serial4 = &lpuart5;
+ serial5 = &lpuart6;
+ serial6 = &lpuart7;
+ serial7 = &lpuart8;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ i2c3 = &lpi2c4;
+ i2c4 = &lpi2c5;
+ i2c5 = &lpi2c6;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ A55_1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <133000000>;
+ clock-output-names = "clk_ext1";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,no-tick-in-suspend;
+ interrupt-parent = <&gic>;
+ };
+
+ gic: interrupt-controller@48000000 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x48000000 0 0x10000>,
+ <0 0x48040000 0 0xc0000>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x80000000>,
+ <0x28000000 0x0 0x28000000 0x10000000>;
+
+ aips1: bus@44000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x44000000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mu1: mailbox@44230000 {
+ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+ reg = <0x44230000 0x10000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ anomix_ns_gpr: blk-ctrl-anomix@42420000 {
+ compatible = "syscon";
+ reg = <0x44210000 0x1000>;
+ };
+
+ system_counter: timer@44290000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x44290000 0x30000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_24m>;
+ clock-names = "per";
+ };
+
+ i3c1: i3c-master@44330000 {
+ #address-cells = <3>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
+ reg = <0x44330000 0x10000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_I3C1_GATE>,
+ <&clk IMX93_CLK_I3C1_GATE>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ lpi2c1: i2c@44340000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44340000 0x10000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
+ <&clk IMX93_CLK_LPI2C1_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpi2c2: i2c@44350000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x44350000 0x10000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
+ <&clk IMX93_CLK_LPI2C2_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi1: spi@44360000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x44360000 0x10000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
+ <&clk IMX93_CLK_LPSPI1_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi2: spi@44370000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x44370000 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
+ <&clk IMX93_CLK_LPSPI2_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpuart1: serial@44380000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x44380000 0x1000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART1_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart2: serial@44390000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x44390000 0x1000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART2_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ iomuxc: pinctrl@443c0000 {
+ compatible = "fsl,imx93-iomuxc";
+ reg = <0x443c0000 0x10000>;
+ };
+
+ clk: clock-controller@44450000 {
+ compatible = "fsl,imx93-ccm";
+ reg = <0x44450000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
+ clock-names = "osc_32k", "osc_24m", "clk_ext1";
+ assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <393216000>;
+ status = "okay";
+ };
+
+ anatop: anatop@44480000 {
+ compatible = "fsl,imx93-anatop", "syscon";
+ reg = <0x44480000 0x10000>;
+ };
+
+ adc1: adc@44530000 {
+ compatible = "nxp,imx93-adc";
+ reg = <0x44530000 0x10000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_ADC1_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+ };
+
+ aips2: bus@42000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x42000000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 {
+ compatible = "syscon";
+ reg = <0x42420000 0x1000>;
+ };
+
+ mu2: mailbox@42440000 {
+ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+ reg = <0x42440000 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ wdog3: wdog@42490000 {
+ compatible = "fsl,imx93-wdt";
+ reg = <0x42490000 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_WDOG3_GATE>;
+ timeout-sec = <40>;
+ status = "disabled";
+ };
+
+ tpm4: pwm@424f0000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x424f0000 0x1000>;
+ clocks = <&clk IMX93_CLK_TPM4_GATE>;
+ assigned-clocks = <&clk IMX93_CLK_TPM4>;
+ assigned-clock-parents = <&clk IMX93_CLK_24M>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ i3c2: i3c-master@42520000 {
+ #address-cells = <3>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
+ reg = <0x42520000 0x10000>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_I3C2_GATE>,
+ <&clk IMX93_CLK_I3C2_GATE>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "pclk", "fast_clk", "slow_clk";
+ status = "disabled";
+ };
+
+ lpi2c3: i2c@42530000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42530000 0x10000>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
+ <&clk IMX93_CLK_LPI2C3_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpi2c4: i2c@42540000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x42540000 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
+ <&clk IMX93_CLK_LPI2C4_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi3: spi@42550000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42550000 0x10000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
+ <&clk IMX93_CLK_LPSPI3_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpspi4: spi@42560000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+ reg = <0x42560000 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
+ <&clk IMX93_CLK_LPSPI4_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpuart3: serial@42570000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42570000 0x1000>;
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART3_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart4: serial@42580000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42580000 0x1000>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART4_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart5: serial@42590000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42590000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART5_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart6: serial@425a0000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x425a0000 0x1000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART6_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ flexspi: spi@425e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8mm-fspi";
+ reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>;
+ clock-names = "fspi", "fspi_en";
+ status = "disabled";
+ };
+
+ lpuart7: serial@42690000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x42690000 0x1000>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART7_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpuart8: serial@426a0000 {
+ compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart",
+ "fsl,imx7ulp-lpuart";
+ reg = <0x426a0000 0x1000>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPUART8_GATE>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ lpi2c5: i2c@426b0000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426b0000 0x10000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
+ <&clk IMX93_CLK_LPI2C5_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+
+ lpi2c6: i2c@426c0000 {
+ compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x426c0000 0x10000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
+ <&clk IMX93_CLK_LPI2C6_GATE>;
+ clock-names = "per", "ipg";
+ status = "disabled";
+ };
+ };
+
+ aips3: bus@42800000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x42800000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ usdhc1: mmc@42850000 {
+ compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42850000 0x10000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_USDHC1_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <8>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usdhc2: mmc@42860000 {
+ compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x42860000 0x10000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_USDHC2_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ fec: ethernet@42890000 {
+ compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";
+ reg = <0x42890000 0x10000>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
+ <&clk IMX93_CLK_WAKEUP_AXI>,
+ <&clk IMX93_CLK_ENET_TIMER1>,
+ <&clk IMX93_CLK_ENET_REF>,
+ <&clk IMX93_CLK_ENET_REF_PHY>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
+ <&clk IMX93_CLK_ENET_REF>,
+ <&clk IMX93_CLK_ENET_REF_PHY>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+ assigned-clock-rates = <100000000>, <250000000>, <50000000>;
+ fsl,num-tx-queues = <3>;
+ fsl,num-rx-queues = <3>;
+ fsl,wakeup_irq = <2>;
+ status = "disabled";
+ };
+
+ eqos: ethernet@428a0000 {
+ compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
+ reg = <0x428a0000 0x10000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eth_wake_irq", "macirq";
+ clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
+ <&clk IMX93_CLK_WAKEUP_AXI>,
+ <&clk IMX93_CLK_ENET_TIMER2>,
+ <&clk IMX93_CLK_ENET>,
+ <&clk IMX93_CLK_WAKEUP_AXI>;
+ clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
+ assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
+ <&clk IMX93_CLK_ENET>;
+ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+ <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
+ assigned-clock-rates = <100000000>, <250000000>;
+ intf_mode = <&wakeupmix_gpr 0x28>;
+ clk_csr = <0>;
+ status = "disabled";
+ };
+
+ usdhc3: mmc@428b0000 {
+ compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+ reg = <0x428b0000 0x10000>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_DUMMY>,
+ <&clk IMX93_CLK_USDHC3_GATE>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+ };
+
+ gpio2: gpio@43810000 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x43810080 0x1000>, <0x43810040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 32 32>;
+ };
+
+ gpio3: gpio@43820000 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x43820080 0x1000>, <0x43820040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 64 32>;
+ };
+
+ gpio4: gpio@43830000 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x43830080 0x1000>, <0x43830040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 96 32>;
+ };
+
+ gpio1: gpio@47400000 {
+ compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+ reg = <0x47400080 0x1000>, <0x47400040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&iomuxc 0 0 32>;
+ };
+
+ ocotp: efuse@47510000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,imx93-ocotp", "syscon";
+ reg = <0x47510000 0x1000>;
+ status = "disabled";
+ };
+
+ s4muap: s4muap@47520000 {
+ compatible = "fsl,imx93-mu-s4";
+ reg = <0x47520000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "txirq", "rxirq";
+ #mbox-cells = <2>;
+ status = "okay";
+ };
+
+ sentnl_mu: sentnl-mu {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,imx-sentnl";
+ mboxes = <&s4muap 0 0 &s4muap 1 0>;
+ mbox-names = "tx", "rx";
+ fsl,sentnl_mu_id = <2>;
+ fsl,sentnl_mu_max_users = <4>;
+ status = "okay";
+ dma-ranges = <0x80000000 0x80000000 0x20000000>;
+ };
+
+ ddr-pmu@4e300e00 {
+ compatible = "fsl,imx93-ddr-pmu";
+ reg = <0x4e300dc0 0x200>; /* _dc0 ~ _eb8 */
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ usbphynop1: usbphynop1 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+ clock-names = "main_clk";
+ };
+
+ usbotg1: usb@4c100000 {
+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+ reg = <0x4c100000 0x200>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+ clock-names = "usb1_ctrl_root_clk";
+ assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+ assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
+ fsl,usbphy = <&usbphynop1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@4c100200 {
+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+ #index-cells = <1>;
+ reg = <0x4c100200 0x200>;
+ };
+
+ usbphynop2: usbphynop2 {
+ compatible = "usb-nop-xceiv";
+ clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+ clock-names = "main_clk";
+ };
+
+ usbotg2: usb@4c200000 {
+ compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+ reg = <0x4c200000 0x200>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+ clock-names = "usb2_ctrl_root_clk";
+ assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+ assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
+ fsl,usbphy = <&usbphynop2>;
+ fsl,usbmisc = <&usbmisc2 0>;
+ status = "disabled";
+ };
+
+ usbmisc2: usbmisc@4c200200 {
+ compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+ #index-cells = <1>;
+ reg = <0x4c200200 0x200>;
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h
new file mode 100644
index 00000000000..4ea6864b418
--- /dev/null
+++ b/include/dt-bindings/clock/imx93-clock.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H
+#define __DT_BINDINGS_CLOCK_IMX93_CLK_H
+
+#define IMX93_CLK_DUMMY 0
+#define IMX93_CLK_24M 1
+#define IMX93_CLK_EXT1 2
+#define IMX93_CLK_SYS_PLL_PFD0 3
+#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4
+#define IMX93_CLK_SYS_PLL_PFD1 5
+#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6
+#define IMX93_CLK_SYS_PLL_PFD2 7
+#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8
+#define IMX93_CLK_AUDIO_PLL 9
+#define IMX93_CLK_VIDEO_PLL 10
+#define IMX93_CLK_A55_PERIPH 11
+#define IMX93_CLK_A55_MTR_BUS 12
+#define IMX93_CLK_A55 13
+#define IMX93_CLK_M33 14
+#define IMX93_CLK_BUS_WAKEUP 15
+#define IMX93_CLK_BUS_AON 16
+#define IMX93_CLK_WAKEUP_AXI 17
+#define IMX93_CLK_SWO_TRACE 18
+#define IMX93_CLK_M33_SYSTICK 19
+#define IMX93_CLK_FLEXIO1 20
+#define IMX93_CLK_FLEXIO2 21
+#define IMX93_CLK_LPIT1 22
+#define IMX93_CLK_LPIT2 23
+#define IMX93_CLK_LPTMR1 24
+#define IMX93_CLK_LPTMR2 25
+#define IMX93_CLK_TPM1 26
+#define IMX93_CLK_TPM2 27
+#define IMX93_CLK_TPM3 28
+#define IMX93_CLK_TPM4 29
+#define IMX93_CLK_TPM5 30
+#define IMX93_CLK_TPM6 31
+#define IMX93_CLK_FLEXSPI1 32
+#define IMX93_CLK_CAN1 33
+#define IMX93_CLK_CAN2 34
+#define IMX93_CLK_LPUART1 35
+#define IMX93_CLK_LPUART2 36
+#define IMX93_CLK_LPUART3 37
+#define IMX93_CLK_LPUART4 38
+#define IMX93_CLK_LPUART5 39
+#define IMX93_CLK_LPUART6 40
+#define IMX93_CLK_LPUART7 41
+#define IMX93_CLK_LPUART8 42
+#define IMX93_CLK_LPI2C1 43
+#define IMX93_CLK_LPI2C2 44
+#define IMX93_CLK_LPI2C3 45
+#define IMX93_CLK_LPI2C4 46
+#define IMX93_CLK_LPI2C5 47
+#define IMX93_CLK_LPI2C6 48
+#define IMX93_CLK_LPI2C7 49
+#define IMX93_CLK_LPI2C8 50
+#define IMX93_CLK_LPSPI1 51
+#define IMX93_CLK_LPSPI2 52
+#define IMX93_CLK_LPSPI3 53
+#define IMX93_CLK_LPSPI4 54
+#define IMX93_CLK_LPSPI5 55
+#define IMX93_CLK_LPSPI6 56
+#define IMX93_CLK_LPSPI7 57
+#define IMX93_CLK_LPSPI8 58
+#define IMX93_CLK_I3C1 59
+#define IMX93_CLK_I3C2 60
+#define IMX93_CLK_USDHC1 61
+#define IMX93_CLK_USDHC2 62
+#define IMX93_CLK_USDHC3 63
+#define IMX93_CLK_SAI1 64
+#define IMX93_CLK_SAI2 65
+#define IMX93_CLK_SAI3 66
+#define IMX93_CLK_CCM_CKO1 67
+#define IMX93_CLK_CCM_CKO2 68
+#define IMX93_CLK_CCM_CKO3 69
+#define IMX93_CLK_CCM_CKO4 70
+#define IMX93_CLK_HSIO 71
+#define IMX93_CLK_HSIO_USB_TEST_60M 72
+#define IMX93_CLK_HSIO_ACSCAN_80M 73
+#define IMX93_CLK_HSIO_ACSCAN_480M 74
+#define IMX93_CLK_ML_APB 75
+#define IMX93_CLK_ML 76
+#define IMX93_CLK_MEDIA_AXI 77
+#define IMX93_CLK_MEDIA_APB 78
+#define IMX93_CLK_MEDIA_LDB 79
+#define IMX93_CLK_MEDIA_DISP_PIX 80
+#define IMX93_CLK_CAM_PIX 81
+#define IMX93_CLK_MIPI_TEST_BYTE 82
+#define IMX93_CLK_MIPI_PHY_CFG 83
+#define IMX93_CLK_ADC 84
+#define IMX93_CLK_PDM 85
+#define IMX93_CLK_TSTMR1 86
+#define IMX93_CLK_TSTMR2 87
+#define IMX93_CLK_MQS1 88
+#define IMX93_CLK_MQS2 89
+#define IMX93_CLK_AUDIO_XCVR 90
+#define IMX93_CLK_SPDIF 91
+#define IMX93_CLK_ENET 92
+#define IMX93_CLK_ENET_TIMER1 93
+#define IMX93_CLK_ENET_TIMER2 94
+#define IMX93_CLK_ENET_REF 95
+#define IMX93_CLK_ENET_REF_PHY 96
+#define IMX93_CLK_I3C1_SLOW 97
+#define IMX93_CLK_I3C2_SLOW 98
+#define IMX93_CLK_USB_PHY_BURUNIN 99
+#define IMX93_CLK_PAL_CAME_SCAN 100
+#define IMX93_CLK_A55_GATE 101
+#define IMX93_CLK_CM33_GATE 102
+#define IMX93_CLK_ADC1_GATE 103
+#define IMX93_CLK_WDOG1_GATE 104
+#define IMX93_CLK_WDOG2_GATE 105
+#define IMX93_CLK_WDOG3_GATE 106
+#define IMX93_CLK_WDOG4_GATE 107
+#define IMX93_CLK_WDOG5_GATE 108
+#define IMX93_CLK_SEMA1_GATE 109
+#define IMX93_CLK_SEMA2_GATE 110
+#define IMX93_CLK_MU_A_GATE 111
+#define IMX93_CLK_MU_B_GATE 112
+#define IMX93_CLK_EDMA1_GATE 113
+#define IMX93_CLK_EDMA2_GATE 114
+#define IMX93_CLK_FLEXSPI1_GATE 115
+#define IMX93_CLK_GPIO1_GATE 116
+#define IMX93_CLK_GPIO2_GATE 117
+#define IMX93_CLK_GPIO3_GATE 118
+#define IMX93_CLK_GPIO4_GATE 119
+#define IMX93_CLK_FLEXIO1_GATE 120
+#define IMX93_CLK_FLEXIO2_GATE 121
+#define IMX93_CLK_LPIT1_GATE 122
+#define IMX93_CLK_LPIT2_GATE 123
+#define IMX93_CLK_LPTMR1_GATE 124
+#define IMX93_CLK_LPTMR2_GATE 125
+#define IMX93_CLK_TPM1_GATE 126
+#define IMX93_CLK_TPM2_GATE 127
+#define IMX93_CLK_TPM3_GATE 128
+#define IMX93_CLK_TPM4_GATE 129
+#define IMX93_CLK_TPM5_GATE 130
+#define IMX93_CLK_TPM6_GATE 131
+#define IMX93_CLK_CAN1_GATE 132
+#define IMX93_CLK_CAN2_GATE 133
+#define IMX93_CLK_LPUART1_GATE 134
+#define IMX93_CLK_LPUART2_GATE 135
+#define IMX93_CLK_LPUART3_GATE 136
+#define IMX93_CLK_LPUART4_GATE 137
+#define IMX93_CLK_LPUART5_GATE 138
+#define IMX93_CLK_LPUART6_GATE 139
+#define IMX93_CLK_LPUART7_GATE 140
+#define IMX93_CLK_LPUART8_GATE 141
+#define IMX93_CLK_LPI2C1_GATE 142
+#define IMX93_CLK_LPI2C2_GATE 143
+#define IMX93_CLK_LPI2C3_GATE 144
+#define IMX93_CLK_LPI2C4_GATE 145
+#define IMX93_CLK_LPI2C5_GATE 146
+#define IMX93_CLK_LPI2C6_GATE 147
+#define IMX93_CLK_LPI2C7_GATE 148
+#define IMX93_CLK_LPI2C8_GATE 149
+#define IMX93_CLK_LPSPI1_GATE 150
+#define IMX93_CLK_LPSPI2_GATE 151
+#define IMX93_CLK_LPSPI3_GATE 152
+#define IMX93_CLK_LPSPI4_GATE 153
+#define IMX93_CLK_LPSPI5_GATE 154
+#define IMX93_CLK_LPSPI6_GATE 155
+#define IMX93_CLK_LPSPI7_GATE 156
+#define IMX93_CLK_LPSPI8_GATE 157
+#define IMX93_CLK_I3C1_GATE 158
+#define IMX93_CLK_I3C2_GATE 159
+#define IMX93_CLK_USDHC1_GATE 160
+#define IMX93_CLK_USDHC2_GATE 161
+#define IMX93_CLK_USDHC3_GATE 162
+#define IMX93_CLK_SAI1_GATE 163
+#define IMX93_CLK_SAI2_GATE 164
+#define IMX93_CLK_SAI3_GATE 165
+#define IMX93_CLK_MIPI_CSI_GATE 166
+#define IMX93_CLK_MIPI_DSI_GATE 167
+#define IMX93_CLK_LVDS_GATE 168
+#define IMX93_CLK_LCDIF_GATE 169
+#define IMX93_CLK_PXP_GATE 170
+#define IMX93_CLK_ISI_GATE 171
+#define IMX93_CLK_NIC_MEDIA_GATE 172
+#define IMX93_CLK_USB_CONTROLLER_GATE 173
+#define IMX93_CLK_USB_TEST_60M_GATE 174
+#define IMX93_CLK_HSIO_TROUT_24M_GATE 175
+#define IMX93_CLK_PDM_GATE 176
+#define IMX93_CLK_MQS1_GATE 177
+#define IMX93_CLK_MQS2_GATE 178
+#define IMX93_CLK_AUD_XCVR_GATE 179
+#define IMX93_CLK_SPDIF_GATE 180
+#define IMX93_CLK_HSIO_32K_GATE 181
+#define IMX93_CLK_ENET1_GATE 182
+#define IMX93_CLK_ENET_QOS_GATE 183
+#define IMX93_CLK_SYS_CNT_GATE 184
+#define IMX93_CLK_TSTMR1_GATE 185
+#define IMX93_CLK_TSTMR2_GATE 186
+#define IMX93_CLK_TMC_GATE 187
+#define IMX93_CLK_PMRO_GATE 188
+#define IMX93_CLK_32K 189
+#define IMX93_CLK_SAI1_IPG 190
+#define IMX93_CLK_SAI2_IPG 191
+#define IMX93_CLK_SAI3_IPG 192
+#define IMX93_CLK_END 193
+#endif
diff --git a/include/dt-bindings/power/imx93-power.h b/include/dt-bindings/power/imx93-power.h
new file mode 100644
index 00000000000..4e27a2e2809
--- /dev/null
+++ b/include/dt-bindings/power/imx93-power.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __DT_BINDINGS_IMX93_POWER_H__
+#define __DT_BINDINGS_IMX93_POWER_H__
+
+#define IMX93_POWER_DOMAIN_MLMIX 0
+#define IMX93_POWER_DOMAIN_MEDIAMIX 1
+
+#endif
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 40/49] imx: imx93_evk: Add basic board support
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (38 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 39/49] arm: dts: Add i.MX93 SoC DTSi file Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 41/49] imx: imx93_evk: Set ARM clock to 1.7Ghz Peng Fan (OSS)
` (9 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team, Peng Fan; +Cc: u-boot
From: Peng Fan <peng.fan@nxp.com>
Add basic board codes and defconfig for i.MX93 11x11 EVK board.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 +++
arch/arm/dts/imx93-11x11-evk.dts | 527 +++++++
arch/arm/mach-imx/imx9/Kconfig | 12 +
board/freescale/common/Makefile | 2 +-
board/freescale/imx93_evk/Kconfig | 21 +
board/freescale/imx93_evk/MAINTAINERS | 6 +
board/freescale/imx93_evk/Makefile | 12 +
board/freescale/imx93_evk/imx93_evk.c | 58 +
board/freescale/imx93_evk/lpddr4x_timing.c | 1486 ++++++++++++++++++++
board/freescale/imx93_evk/spl.c | 126 ++
configs/imx93_11x11_evk_defconfig | 108 ++
include/configs/imx93_evk.h | 149 ++
13 files changed, 2666 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx93-11x11-evk.dts
create mode 100644 board/freescale/imx93_evk/Kconfig
create mode 100644 board/freescale/imx93_evk/MAINTAINERS
create mode 100644 board/freescale/imx93_evk/Makefile
create mode 100644 board/freescale/imx93_evk/imx93_evk.c
create mode 100644 board/freescale/imx93_evk/lpddr4x_timing.c
create mode 100644 board/freescale/imx93_evk/spl.c
create mode 100644 configs/imx93_11x11_evk_defconfig
create mode 100644 include/configs/imx93_evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4b940f85169..1217f156bea 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -966,6 +966,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb
+dtb-$(CONFIG_ARCH_IMX9) += \
+ imx93-11x11-evk.dtb
+
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
new file mode 100644
index 00000000000..6f02b389893
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog3>;
+ u-boot,dm-spl;
+ };
+
+ aliases {
+ usbgadget0 = &usbg1;
+ usbgadget1 = &usbg2;
+ };
+
+ usbg1: usbg1 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usbotg1>;
+ status = "okay";
+ };
+
+ usbg2: usbg2 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usbotg2>;
+ status = "okay";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <20000>;
+ u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&lpuart1 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c2 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_lpi2c2 {
+ u-boot,dm-spl;
+};
+
+&fec {
+ phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+&eqos {
+ compatible = "fsl,imx-eqos";
+};
+
+ðphy1 {
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <100000>;
+};
+
+&usbotg1 {
+ status = "okay";
+ extcon = <&ptn5110>;
+};
+
+&usbotg2 {
+ status = "okay";
+ extcon = <&ptn5110_2>;
+};
+
+&s4muap {
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts
new file mode 100644
index 00000000000..b3a5a3d71e2
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -0,0 +1,527 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/{
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ audio: audio@a4120000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4120000 0 0x100000>;
+ no-map;
+ };
+ };
+
+ reg_can2_stby: regulator-can2-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can2-stby";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>;
+ enable-active-low;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usdhc3_pwrseq: usdhc3_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+};
+
+&lpi2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1>;
+ status = "okay";
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110";
+ reg = <0x50>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ status = "okay";
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+ };
+ };
+
+ ptn5110_2: tcpc@51 {
+ compatible = "nxp,ptn5110";
+ reg = <0x51>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ status = "okay";
+
+ port {
+ typec2_dr_sw: endpoint {
+ remote-endpoint = <&usb2_drd_sw>;
+ };
+ };
+
+ typec2_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+ };
+ };
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-1 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ interrupt-parent = <&pcal6524>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ adp5585gpio: gpio@34 {
+ compatible = "adp5585";
+ reg = <0x34>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "disabled";
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ disable-over-current;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ status = "okay";
+
+ port {
+ usb2_drd_sw: endpoint {
+ remote-endpoint = <&typec2_dr_sw>;
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ bus-width = <4>;
+ status = "okay";
+ no-sdio;
+ no-mmc;
+};
+
+&usdhc3 {
+ status = "disabled";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy2>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ eee-broken-1000t;
+ rtl821x,aldps-disable;
+ rtl821x,clkout-disable;
+ };
+ };
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ eee-broken-1000t;
+ rtl821x,aldps-disable;
+ rtl821x,clkout-disable;
+ };
+ };
+};
+
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi>;
+ status = "disabled";
+
+ flash0: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ status = "okay";
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_flexspi: flexspigrp {
+ fsl,pins = <
+ MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x42
+ MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x42
+ MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x42
+ MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x42
+ MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x42
+ MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x42
+ MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x42
+ MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x42
+ MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x42
+ MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x42
+ MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x42
+ MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x42
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
+ MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x17fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17fe
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+};
+
+&wdog3 {
+ status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index dae9f658e65..c06102bae07 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -18,5 +18,17 @@ config IMX93
config SYS_SOC
default "imx9"
+choice
+ prompt "NXP i.MX9 board select"
+ optional
+
+config TARGET_IMX93_11X11_EVK
+ bool "imx93_11x11_evk"
+ select IMX93
+
+endchoice
+
+source "board/freescale/imx93_evk/Kconfig"
+
endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 4214c6e46e4..7c93d30e1d2 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -65,7 +65,7 @@ obj-$(CONFIG_ZM7300) += zm7300.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
-ifneq (,$(filter $(SOC), imx8ulp))
+ifneq (,$(filter $(SOC), imx8ulp imx9))
obj-y += mmc.o
endif
diff --git a/board/freescale/imx93_evk/Kconfig b/board/freescale/imx93_evk/Kconfig
new file mode 100644
index 00000000000..032e523198d
--- /dev/null
+++ b/board/freescale/imx93_evk/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_IMX93_11X11_EVK
+
+config SYS_BOARD
+ default "imx93_evk"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx93_evk"
+
+config IMX93_EVK_LPDDR4X
+ bool "Using LPDDR4X Timing and PMIC voltage"
+ default y
+ select IMX9_LPDDR4X
+ help
+ Select the LPDDR4X timing and 0.6V VDDQ
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx93_evk/MAINTAINERS b/board/freescale/imx93_evk/MAINTAINERS
new file mode 100644
index 00000000000..389f17ae1e4
--- /dev/null
+++ b/board/freescale/imx93_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX93 MEK BOARD
+M: Peng Fan <peng.fan@nxp.com>
+S: Maintained
+F: board/freescale/imx93_evk/
+F: include/configs/imx93_evk.h
+F: configs/imx93_11x11_evk_defconfig
diff --git a/board/freescale/imx93_evk/Makefile b/board/freescale/imx93_evk/Makefile
new file mode 100644
index 00000000000..575f8e94604
--- /dev/null
+++ b/board/freescale/imx93_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2022 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx93_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
+endif
diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c
new file mode 100644
index 00000000000..77b92b35db4
--- /dev/null
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/arch-imx9/ccm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-imx9/imx93_pins.h>
+#include <asm/arch/clock.h>
+#include <power/pmic.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ init_uart_clk(LPUART1_CLK_ROOT);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board_name", "11X11_EVK");
+ env_set("board_rev", "iMX93");
+#endif
+ return 0;
+}
+
diff --git a/board/freescale/imx93_evk/lpddr4x_timing.c b/board/freescale/imx93_evk/lpddr4x_timing.c
new file mode 100644
index 00000000000..3fbae55bc7f
--- /dev/null
+++ b/board/freescale/imx93_evk/lpddr4x_timing.c
@@ -0,0 +1,1486 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Generated code from NXP_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ { 0x4e300110, 0x44140001 },
+ { 0x4e300000, 0x8000ff },
+ { 0x4e300008, 0x0 },
+ { 0x4e300080, 0x80000512 },
+ { 0x4e300084, 0x0 },
+ { 0x4e300114, 0x2 },
+ { 0x4e300260, 0x0 },
+ { 0x4e30017c, 0x0 },
+ { 0x4e300104, 0xaaee001b },
+ { 0x4e300108, 0x626ee273 },
+ { 0x4e30010c, 0x5c18b },
+ { 0x4e300100, 0x25ab321b },
+ { 0x4e300160, 0x9002 },
+ { 0x4e30016c, 0x35f00000 },
+ { 0x4e300250, 0x2b },
+ { 0x4e300254, 0x0 },
+ { 0x4e30025c, 0x400 },
+ { 0x4e300300, 0x16291314 },
+ { 0x4e300304, 0x163110c },
+ { 0x4e300308, 0xa200e3c },
+ { 0x4e300170, 0x8b0b0608 },
+ { 0x4e300124, 0x1c77071d },
+ { 0x4e300f04, 0x80 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ { 0x100a0, 0x4 },
+ { 0x100a1, 0x5 },
+ { 0x100a2, 0x6 },
+ { 0x100a3, 0x7 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x1 },
+ { 0x100a6, 0x2 },
+ { 0x100a7, 0x3 },
+ { 0x110a0, 0x3 },
+ { 0x110a1, 0x2 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x1 },
+ { 0x110a4, 0x7 },
+ { 0x110a5, 0x6 },
+ { 0x110a6, 0x4 },
+ { 0x110a7, 0x5 },
+ { 0x1005f, 0x5ff },
+ { 0x1015f, 0x5ff },
+ { 0x1105f, 0x5ff },
+ { 0x1115f, 0x5ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x2002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x20024, 0x1e3 },
+ { 0x2003a, 0x2 },
+ { 0x2007d, 0x212 },
+ { 0x2007c, 0x61 },
+ { 0x20056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x10049, 0xe00 },
+ { 0x10149, 0xe00 },
+ { 0x11049, 0xe00 },
+ { 0x11149, 0xe00 },
+ { 0x43, 0x60 },
+ { 0x1043, 0x60 },
+ { 0x2043, 0x60 },
+ { 0x20018, 0x1 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x2009b, 0x2 },
+ { 0x20008, 0x3a5 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x10c },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x200fa, 0x2 },
+ { 0x20019, 0x1 },
+ { 0x200f0, 0x0 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5555 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x1004a, 0x500 },
+ { 0x1104a, 0x500 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x20021, 0x0 },
+ { 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xe94 },
+ { 0x54004, 0x4 },
+ { 0x54006, 0x15 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xff },
+ { 0x5400b, 0x4 },
+ { 0x5400c, 0x1 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x36e4 },
+ { 0x5401a, 0x32 },
+ { 0x5401b, 0x1146 },
+ { 0x5401c, 0x1108 },
+ { 0x5401e, 0x4 },
+ { 0x5401f, 0x36e4 },
+ { 0x54020, 0x32 },
+ { 0x54021, 0x1146 },
+ { 0x54022, 0x1108 },
+ { 0x54024, 0x4 },
+ { 0x54032, 0xe400 },
+ { 0x54033, 0x3236 },
+ { 0x54034, 0x4600 },
+ { 0x54035, 0x811 },
+ { 0x54036, 0x11 },
+ { 0x54037, 0x400 },
+ { 0x54038, 0xe400 },
+ { 0x54039, 0x3236 },
+ { 0x5403a, 0x4600 },
+ { 0x5403b, 0x811 },
+ { 0x5403c, 0x11 },
+ { 0x5403d, 0x400 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xe94 },
+ { 0x54004, 0x4 },
+ { 0x54006, 0x15 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xff },
+ { 0x5400b, 0x4 },
+ { 0x5400c, 0x1 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x2080 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x36e4 },
+ { 0x5401a, 0x32 },
+ { 0x5401b, 0x1146 },
+ { 0x5401c, 0x1108 },
+ { 0x5401e, 0x4 },
+ { 0x5401f, 0x36e4 },
+ { 0x54020, 0x32 },
+ { 0x54021, 0x1146 },
+ { 0x54022, 0x1108 },
+ { 0x54024, 0x4 },
+ { 0x54032, 0xe400 },
+ { 0x54033, 0x3236 },
+ { 0x54034, 0x4600 },
+ { 0x54035, 0x811 },
+ { 0x54036, 0x11 },
+ { 0x54037, 0x400 },
+ { 0x54038, 0xe400 },
+ { 0x54039, 0x3236 },
+ { 0x5403a, 0x4600 },
+ { 0x5403b, 0x811 },
+ { 0x5403c, 0x11 },
+ { 0x5403d, 0x400 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x633 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x633 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x633 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x30 },
+ { 0x90051, 0x65a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x45a },
+ { 0x90055, 0x9 },
+ { 0x90056, 0x0 },
+ { 0x90057, 0x448 },
+ { 0x90058, 0x109 },
+ { 0x90059, 0x40 },
+ { 0x9005a, 0x633 },
+ { 0x9005b, 0x179 },
+ { 0x9005c, 0x1 },
+ { 0x9005d, 0x618 },
+ { 0x9005e, 0x109 },
+ { 0x9005f, 0x40c0 },
+ { 0x90060, 0x633 },
+ { 0x90061, 0x149 },
+ { 0x90062, 0x8 },
+ { 0x90063, 0x4 },
+ { 0x90064, 0x48 },
+ { 0x90065, 0x4040 },
+ { 0x90066, 0x633 },
+ { 0x90067, 0x149 },
+ { 0x90068, 0x0 },
+ { 0x90069, 0x4 },
+ { 0x9006a, 0x48 },
+ { 0x9006b, 0x40 },
+ { 0x9006c, 0x633 },
+ { 0x9006d, 0x149 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x658 },
+ { 0x90070, 0x109 },
+ { 0x90071, 0x10 },
+ { 0x90072, 0x4 },
+ { 0x90073, 0x18 },
+ { 0x90074, 0x0 },
+ { 0x90075, 0x4 },
+ { 0x90076, 0x78 },
+ { 0x90077, 0x549 },
+ { 0x90078, 0x633 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0xd49 },
+ { 0x9007b, 0x633 },
+ { 0x9007c, 0x159 },
+ { 0x9007d, 0x94a },
+ { 0x9007e, 0x633 },
+ { 0x9007f, 0x159 },
+ { 0x90080, 0x441 },
+ { 0x90081, 0x633 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x42 },
+ { 0x90084, 0x633 },
+ { 0x90085, 0x149 },
+ { 0x90086, 0x1 },
+ { 0x90087, 0x633 },
+ { 0x90088, 0x149 },
+ { 0x90089, 0x0 },
+ { 0x9008a, 0xe0 },
+ { 0x9008b, 0x109 },
+ { 0x9008c, 0xa },
+ { 0x9008d, 0x10 },
+ { 0x9008e, 0x109 },
+ { 0x9008f, 0x9 },
+ { 0x90090, 0x3c0 },
+ { 0x90091, 0x149 },
+ { 0x90092, 0x9 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x159 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x10 },
+ { 0x90097, 0x109 },
+ { 0x90098, 0x0 },
+ { 0x90099, 0x3c0 },
+ { 0x9009a, 0x109 },
+ { 0x9009b, 0x18 },
+ { 0x9009c, 0x4 },
+ { 0x9009d, 0x48 },
+ { 0x9009e, 0x18 },
+ { 0x9009f, 0x4 },
+ { 0x900a0, 0x58 },
+ { 0x900a1, 0xb },
+ { 0x900a2, 0x10 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x1 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x900a7, 0x5 },
+ { 0x900a8, 0x7c0 },
+ { 0x900a9, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x625 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x625 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900aa, 0x0 },
+ { 0x900ab, 0x790 },
+ { 0x900ac, 0x11a },
+ { 0x900ad, 0x8 },
+ { 0x900ae, 0x7aa },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x7b2 },
+ { 0x900b2, 0x2a },
+ { 0x900b3, 0x0 },
+ { 0x900b4, 0x7c8 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x10 },
+ { 0x900b7, 0x10 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x10 },
+ { 0x900ba, 0x2a8 },
+ { 0x900bb, 0x129 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x370 },
+ { 0x900be, 0x129 },
+ { 0x900bf, 0xa },
+ { 0x900c0, 0x3c8 },
+ { 0x900c1, 0x1a9 },
+ { 0x900c2, 0xc },
+ { 0x900c3, 0x408 },
+ { 0x900c4, 0x199 },
+ { 0x900c5, 0x14 },
+ { 0x900c6, 0x790 },
+ { 0x900c7, 0x11a },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x4 },
+ { 0x900ca, 0x18 },
+ { 0x900cb, 0xe },
+ { 0x900cc, 0x408 },
+ { 0x900cd, 0x199 },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x8568 },
+ { 0x900d0, 0x108 },
+ { 0x900d1, 0x18 },
+ { 0x900d2, 0x790 },
+ { 0x900d3, 0x16a },
+ { 0x900d4, 0x8 },
+ { 0x900d5, 0x1d8 },
+ { 0x900d6, 0x169 },
+ { 0x900d7, 0x10 },
+ { 0x900d8, 0x8558 },
+ { 0x900d9, 0x168 },
+ { 0x900da, 0x1ff8 },
+ { 0x900db, 0x85a8 },
+ { 0x900dc, 0x1e8 },
+ { 0x900dd, 0x50 },
+ { 0x900de, 0x798 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x60 },
+ { 0x900e1, 0x7a0 },
+ { 0x900e2, 0x16a },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0x8310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0x8 },
+ { 0x900e7, 0xa310 },
+ { 0x900e8, 0x168 },
+ { 0x900e9, 0xa },
+ { 0x900ea, 0x408 },
+ { 0x900eb, 0x169 },
+ { 0x900ec, 0x6e },
+ { 0x900ed, 0x0 },
+ { 0x900ee, 0x68 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x408 },
+ { 0x900f1, 0x169 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0x8310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x0 },
+ { 0x900f6, 0xa310 },
+ { 0x900f7, 0x168 },
+ { 0x900f8, 0x1ff8 },
+ { 0x900f9, 0x85a8 },
+ { 0x900fa, 0x1e8 },
+ { 0x900fb, 0x68 },
+ { 0x900fc, 0x798 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x78 },
+ { 0x900ff, 0x7a0 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x68 },
+ { 0x90102, 0x790 },
+ { 0x90103, 0x16a },
+ { 0x90104, 0x8 },
+ { 0x90105, 0x8b10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0x8 },
+ { 0x90108, 0xab10 },
+ { 0x90109, 0x168 },
+ { 0x9010a, 0xa },
+ { 0x9010b, 0x408 },
+ { 0x9010c, 0x169 },
+ { 0x9010d, 0x58 },
+ { 0x9010e, 0x0 },
+ { 0x9010f, 0x68 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x408 },
+ { 0x90112, 0x169 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0x8b10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x1 },
+ { 0x90117, 0xab10 },
+ { 0x90118, 0x168 },
+ { 0x90119, 0x0 },
+ { 0x9011a, 0x1d8 },
+ { 0x9011b, 0x169 },
+ { 0x9011c, 0x80 },
+ { 0x9011d, 0x790 },
+ { 0x9011e, 0x16a },
+ { 0x9011f, 0x18 },
+ { 0x90120, 0x7aa },
+ { 0x90121, 0x6a },
+ { 0x90122, 0xa },
+ { 0x90123, 0x0 },
+ { 0x90124, 0x1e9 },
+ { 0x90125, 0x8 },
+ { 0x90126, 0x8080 },
+ { 0x90127, 0x108 },
+ { 0x90128, 0xf },
+ { 0x90129, 0x408 },
+ { 0x9012a, 0x169 },
+ { 0x9012b, 0xc },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x68 },
+ { 0x9012e, 0x9 },
+ { 0x9012f, 0x0 },
+ { 0x90130, 0x1a9 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x408 },
+ { 0x90133, 0x169 },
+ { 0x90134, 0x0 },
+ { 0x90135, 0x8080 },
+ { 0x90136, 0x108 },
+ { 0x90137, 0x8 },
+ { 0x90138, 0x7aa },
+ { 0x90139, 0x6a },
+ { 0x9013a, 0x0 },
+ { 0x9013b, 0x8568 },
+ { 0x9013c, 0x108 },
+ { 0x9013d, 0xb7 },
+ { 0x9013e, 0x790 },
+ { 0x9013f, 0x16a },
+ { 0x90140, 0x1f },
+ { 0x90141, 0x0 },
+ { 0x90142, 0x68 },
+ { 0x90143, 0x8 },
+ { 0x90144, 0x8558 },
+ { 0x90145, 0x168 },
+ { 0x90146, 0xf },
+ { 0x90147, 0x408 },
+ { 0x90148, 0x169 },
+ { 0x90149, 0xd },
+ { 0x9014a, 0x0 },
+ { 0x9014b, 0x68 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x408 },
+ { 0x9014e, 0x169 },
+ { 0x9014f, 0x0 },
+ { 0x90150, 0x8558 },
+ { 0x90151, 0x168 },
+ { 0x90152, 0x8 },
+ { 0x90153, 0x3c8 },
+ { 0x90154, 0x1a9 },
+ { 0x90155, 0x3 },
+ { 0x90156, 0x370 },
+ { 0x90157, 0x129 },
+ { 0x90158, 0x20 },
+ { 0x90159, 0x2aa },
+ { 0x9015a, 0x9 },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x104 },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x448 },
+ { 0x90166, 0x109 },
+ { 0x90167, 0xf },
+ { 0x90168, 0x7c0 },
+ { 0x90169, 0x109 },
+ { 0x9016a, 0x0 },
+ { 0x9016b, 0xe8 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0x47 },
+ { 0x9016e, 0x630 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0x618 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x8 },
+ { 0x90174, 0xe0 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x0 },
+ { 0x90177, 0x7c8 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0x8140 },
+ { 0x9017b, 0x10c },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x478 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x0 },
+ { 0x90180, 0x1 },
+ { 0x90181, 0x8 },
+ { 0x90182, 0x8 },
+ { 0x90183, 0x4 },
+ { 0x90184, 0x0 },
+ { 0x90006, 0x8 },
+ { 0x90007, 0x7c8 },
+ { 0x90008, 0x109 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x400 },
+ { 0x9000b, 0x106 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2b },
+ { 0x90026, 0x69 },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x200be, 0x0 },
+ { 0x2000b, 0x419 },
+ { 0x2000c, 0xe9 },
+ { 0x2000d, 0x91c },
+ { 0x2000e, 0x2c },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x2060 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x400f1, 0xe },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x0 },
+ { 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3733mts 1D */
+ .drate = 3733,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P0 3733mts 1D */
+ .drate = 3733,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3733, },
+};
+
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
new file mode 100644
index 00000000000..ca33f943424
--- /dev/null
+++ b/board/freescale/imx93_evk/spl.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx93_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch-mx7ulp/gpio.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/mach-imx/s400_api.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <linux/delay.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <asm/arch/trdc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_board_init(void)
+{
+ puts("Normal Boot\n");
+}
+
+void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pmic@25", &dev);
+ if (ret == -ENODEV) {
+ puts("No pca9450@25\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+ /* 0.9v
+ */
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
+
+ /* I2C_LT_EN*/
+ pmic_reg_write(dev, 0xa, 0x3);
+
+ /* set WDOG_B_CFG to cold reset */
+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+ return 0;
+}
+#endif
+
+extern int imx9_probe_mu(void *ctx, struct event *event);
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ timer_init();
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ spl_early_init();
+
+ preloader_console_init();
+
+ ret = imx9_probe_mu(NULL, NULL);
+ if (ret) {
+ printf("Fail to init Sentinel API\n");
+ } else {
+ printf("SOC: 0x%x\n", gd->arch.soc_rev);
+ printf("LC: 0x%x\n", gd->arch.lifecycle);
+ }
+ power_init_board();
+
+ /* Init power of mix */
+ soc_power_init();
+
+ /* Setup TRDC for DDR access */
+ trdc_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Put M33 into CPUWAIT for following kick */
+ ret = m33_prepare();
+ if (!ret)
+ printf("M33 prepare ok\n");
+
+ board_init_r(NULL, 0);
+}
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
new file mode 100644
index 00000000000..8a396ed1c13
--- /dev/null
+++ b/configs/imx93_11x11_evk_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
+CONFIG_SPL_TEXT_BASE=0x2049A000
+CONFIG_TARGET_IMX93_11X11_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x26000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x2051e000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x2051ddd0
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x83200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=2048
+CONFIG_SYS_PBSIZE=2074
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SYS_I2C_SPEED=100000
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX93=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
new file mode 100644
index 00000000000..56f52b84577
--- /dev/null
+++ b/include/configs/imx93_evk.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __IMX93_EVK_H
+#define __IMX93_EVK_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN (SZ_64M)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_MALLOC_F_ADDR 0x204D0000
+#endif
+
+#ifdef CONFIG_DISTRO_DEFAULTS
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+
+#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ "scriptaddr=0x83500000\0" \
+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "image=Image\0" \
+ "splashimage=0x90000000\0" \
+ "console=ttyLP0,115200 earlycon\0" \
+ "fdt_addr_r=0x83000000\0" \
+ "fdt_addr=0x83000000\0" \
+ "cntr_addr=0x98000000\0" \
+ "cntr_file=os_cntr_signed.bin\0" \
+ "boot_fit=no\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "bootm_size=0x10000000\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+ "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
+ "auth_os=auth_cntr ${cntr_addr}\0" \
+ "boot_os=booti ${loadaddr} - ${fdt_addr_r};\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${sec_boot} = yes; then " \
+ "if run auth_os; then " \
+ "run boot_os; " \
+ "else " \
+ "echo ERR: failed to authenticate; " \
+ "fi; " \
+ "else " \
+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+ "bootm ${loadaddr}; " \
+ "else " \
+ "if run loadfdt; then " \
+ "run boot_os; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi;" \
+ "fi;\0" \
+ "netargs=setenv bootargs ${jh_clk} console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if test ${sec_boot} = yes; then " \
+ "${get_cmd} ${cntr_addr} ${cntr_file}; " \
+ "if run auth_os; then " \
+ "run boot_os; " \
+ "else " \
+ "echo ERR: failed to authenticate; " \
+ "fi; " \
+ "else " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+ "bootm ${loadaddr}; " \
+ "else " \
+ "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+ "run boot_os; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi;" \
+ "fi;\0" \
+ "bsp_bootcmd=echo Running BSP bootcmd ...; " \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if test ${sec_boot} = yes; then " \
+ "if run loadcntr; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "fi; " \
+ "fi;"
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define PHYS_SDRAM 0x80000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR WDG3_BASE_ADDR
+
+/* USB configs */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#if defined(CONFIG_CMD_NET)
+#define DWC_NET_PHYADDR 1
+#define PHY_ANEG_TIMEOUT 20000
+#endif
+
+#endif
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 41/49] imx: imx93_evk: Set ARM clock to 1.7Ghz
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (39 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 40/49] imx: imx93_evk: Add basic board support Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 42/49] net: fec_mxc: support i.MX93 Peng Fan (OSS)
` (8 subsequent siblings)
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team, Peng Fan; +Cc: u-boot
From: Peng Fan <peng.fan@nxp.com>
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/clock.h | 4 +++-
arch/arm/mach-imx/imx9/clock.c | 9 +++++++++
board/freescale/imx93_evk/spl.c | 3 +++
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
index d96f126a1d1..336d8613181 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -217,6 +217,8 @@ void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
+int configure_intpll(enum ccm_clk_src pll, u32 freq);
+
int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
@@ -238,5 +240,5 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock
void enable_usboh3_clk(unsigned char enable);
int set_clk_enet(enum enet_freq type);
int set_clk_eqos(enum enet_freq type);
-
+void set_arm_clk(ulong freq);
#endif
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 5d2bc0d2f8f..8240afc6172 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -665,6 +665,15 @@ void dram_disable_bypass(void)
/* Switch from DRAM clock root from CCM to PLL */
ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
}
+
+void set_arm_clk(ulong freq)
+{
+ /* Increase ARM clock to 1.7Ghz */
+ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
+ configure_intpll(ARM_PLL_CLK, 1700000000);
+ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
+}
+
#endif
int clock_init(void)
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index ca33f943424..38cfbac6ea6 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -108,6 +108,9 @@ void board_init_f(ulong dummy)
}
power_init_board();
+ /* 1.7GHz */
+ set_arm_clk(1700000000);
+
/* Init power of mix */
soc_power_init();
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 42/49] net: fec_mxc: support i.MX93
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (40 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 41/49] imx: imx93_evk: Set ARM clock to 1.7Ghz Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-07-03 19:13 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 43/49] net: dwc_eth_qos: fix build break when CLK not enabled Peng Fan (OSS)
` (7 subsequent siblings)
49 siblings, 1 reply; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Joe Hershberger, Ramon Fried; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Support i.MX93 in fec_mxc driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/net/Kconfig | 2 +-
drivers/net/fec_mxc.c | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 84d859c21eb..8cf8621467f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -340,7 +340,7 @@ config FEC_MXC_MDIO_BASE
config FEC_MXC
bool "FEC Ethernet controller"
- depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || VF610
+ depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || IMX93 || VF610
help
This driver supports the 10/100 Fast Ethernet controller for
NXP i.MX processors.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index a623a5c45e4..8bc2b46d403 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -598,7 +598,8 @@ static int fecmxc_init(struct udevice *dev)
writel(0x00000000, &fec->eth->gaddr2);
/* Do not access reserved register */
- if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp()) {
+ if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp() &&
+ !is_imx93()) {
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
@@ -1357,6 +1358,7 @@ static const struct udevice_id fecmxc_ids[] = {
{ .compatible = "fsl,imx53-fec" },
{ .compatible = "fsl,imx7d-fec" },
{ .compatible = "fsl,mvf600-fec" },
+ { .compatible = "fsl,imx93-fec" },
{ }
};
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 43/49] net: dwc_eth_qos: fix build break when CLK not enabled
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (41 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 42/49] net: fec_mxc: support i.MX93 Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-07-03 19:21 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 44/49] net: dwc_eth_qos: public some functions Peng Fan (OSS)
` (6 subsequent siblings)
49 siblings, 1 reply; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Joe Hershberger, Ramon Fried; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
When CONFIG_CLK is not enabled, there will be buil break:
"error: ‘eqos’ undeclared (first use in this function)"
Should not guard the eqos under CONFIG_CLK macro
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/net/dwc_eth_qos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9d255cf95ff..6048d56ff8c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1774,11 +1774,11 @@ static int eqos_remove_resources_tegra186(struct udevice *dev)
static int eqos_remove_resources_stm32(struct udevice *dev)
{
-#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
+#ifdef CONFIG_CLK
clk_free(&eqos->clk_tx);
clk_free(&eqos->clk_rx);
clk_free(&eqos->clk_master_bus);
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 44/49] net: dwc_eth_qos: public some functions
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (42 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 43/49] net: dwc_eth_qos: fix build break when CLK not enabled Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-07-03 19:14 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 45/49] net: dwc_eth_qos: move i.MX code out Peng Fan (OSS)
` (5 subsequent siblings)
49 siblings, 1 reply; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Joe Hershberger, Ramon Fried; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Move macros and structures to header file and make some functions
public, so that could used by other files, this is to
prepare split platform specific config to one file.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/net/dwc_eth_qos.c | 280 +-------------------------------------
drivers/net/dwc_eth_qos.h | 280 ++++++++++++++++++++++++++++++++++++++
2 files changed, 287 insertions(+), 273 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos.h
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 6048d56ff8c..b69a9feb824 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -51,275 +51,9 @@
#include <asm/arch/clock.h>
#include <asm/mach-imx/sys_proto.h>
#endif
-#include <linux/bitops.h>
#include <linux/delay.h>
-/* Core registers */
-
-#define EQOS_MAC_REGS_BASE 0x000
-struct eqos_mac_regs {
- uint32_t configuration; /* 0x000 */
- uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
- uint32_t q0_tx_flow_ctrl; /* 0x070 */
- uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
- uint32_t rx_flow_ctrl; /* 0x090 */
- uint32_t unused_094; /* 0x094 */
- uint32_t txq_prty_map0; /* 0x098 */
- uint32_t unused_09c; /* 0x09c */
- uint32_t rxq_ctrl0; /* 0x0a0 */
- uint32_t unused_0a4; /* 0x0a4 */
- uint32_t rxq_ctrl2; /* 0x0a8 */
- uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
- uint32_t us_tic_counter; /* 0x0dc */
- uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
- uint32_t hw_feature0; /* 0x11c */
- uint32_t hw_feature1; /* 0x120 */
- uint32_t hw_feature2; /* 0x124 */
- uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
- uint32_t mdio_address; /* 0x200 */
- uint32_t mdio_data; /* 0x204 */
- uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
- uint32_t address0_high; /* 0x300 */
- uint32_t address0_low; /* 0x304 */
-};
-
-#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
-#define EQOS_MAC_CONFIGURATION_CST BIT(21)
-#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
-#define EQOS_MAC_CONFIGURATION_WD BIT(19)
-#define EQOS_MAC_CONFIGURATION_JD BIT(17)
-#define EQOS_MAC_CONFIGURATION_JE BIT(16)
-#define EQOS_MAC_CONFIGURATION_PS BIT(15)
-#define EQOS_MAC_CONFIGURATION_FES BIT(14)
-#define EQOS_MAC_CONFIGURATION_DM BIT(13)
-#define EQOS_MAC_CONFIGURATION_LM BIT(12)
-#define EQOS_MAC_CONFIGURATION_TE BIT(1)
-#define EQOS_MAC_CONFIGURATION_RE BIT(0)
-
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
-
-#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
-
-#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
-#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
-
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
-
-#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
-#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
-
-#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
-#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
-#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
-#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
-
-#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
-#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
-#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
-#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
-
-#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
-#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
-
-#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
-#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
-#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
-#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
-#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
-#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
-#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
-#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
-#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
-#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
-#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
-
-#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
-
-#define EQOS_MTL_REGS_BASE 0xd00
-struct eqos_mtl_regs {
- uint32_t txq0_operation_mode; /* 0xd00 */
- uint32_t unused_d04; /* 0xd04 */
- uint32_t txq0_debug; /* 0xd08 */
- uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
- uint32_t txq0_quantum_weight; /* 0xd18 */
- uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
- uint32_t rxq0_operation_mode; /* 0xd30 */
- uint32_t unused_d34; /* 0xd34 */
- uint32_t rxq0_debug; /* 0xd38 */
-};
-
-#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
-#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
-#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
-#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
-#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
-#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
-#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
-
-#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
-#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
-#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
-
-#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
-#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
-#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
-#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
-#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
-#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
-#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
-#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
-
-#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
-#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
-#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
-#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
-
-#define EQOS_DMA_REGS_BASE 0x1000
-struct eqos_dma_regs {
- uint32_t mode; /* 0x1000 */
- uint32_t sysbus_mode; /* 0x1004 */
- uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
- uint32_t ch0_control; /* 0x1100 */
- uint32_t ch0_tx_control; /* 0x1104 */
- uint32_t ch0_rx_control; /* 0x1108 */
- uint32_t unused_110c; /* 0x110c */
- uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
- uint32_t ch0_txdesc_list_address; /* 0x1114 */
- uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
- uint32_t ch0_rxdesc_list_address; /* 0x111c */
- uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
- uint32_t unused_1124; /* 0x1124 */
- uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
- uint32_t ch0_txdesc_ring_length; /* 0x112c */
- uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
-};
-
-#define EQOS_DMA_MODE_SWR BIT(0)
-
-#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
-#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
-#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
-#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
-#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
-#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
-
-#define EQOS_DMA_CH0_CONTROL_DSL_SHIFT 18
-#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
-
-#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
-#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
-#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
-#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
-
-#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
-#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
-#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
-#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
-#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
-
-/* These registers are Tegra186-specific */
-#define EQOS_TEGRA186_REGS_BASE 0x8800
-struct eqos_tegra186_regs {
- uint32_t sdmemcomppadctrl; /* 0x8800 */
- uint32_t auto_cal_config; /* 0x8804 */
- uint32_t unused_8808; /* 0x8808 */
- uint32_t auto_cal_status; /* 0x880c */
-};
-
-#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
-
-#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
-#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
-
-#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
-
-/* Descriptors */
-#define EQOS_DESCRIPTORS_TX 4
-#define EQOS_DESCRIPTORS_RX 4
-#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
-#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
-#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
-#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
-
-struct eqos_desc {
- u32 des0;
- u32 des1;
- u32 des2;
- u32 des3;
-};
-
-#define EQOS_DESC3_OWN BIT(31)
-#define EQOS_DESC3_FD BIT(29)
-#define EQOS_DESC3_LD BIT(28)
-#define EQOS_DESC3_BUF1V BIT(24)
-
-#define EQOS_AXI_WIDTH_32 4
-#define EQOS_AXI_WIDTH_64 8
-#define EQOS_AXI_WIDTH_128 16
-
-struct eqos_config {
- bool reg_access_always_ok;
- int mdio_wait;
- int swr_wait;
- int config_mac;
- int config_mac_mdio;
- unsigned int axi_bus_width;
- phy_interface_t (*interface)(const struct udevice *dev);
- struct eqos_ops *ops;
-};
-
-struct eqos_ops {
- void (*eqos_inval_desc)(void *desc);
- void (*eqos_flush_desc)(void *desc);
- void (*eqos_inval_buffer)(void *buf, size_t size);
- void (*eqos_flush_buffer)(void *buf, size_t size);
- int (*eqos_probe_resources)(struct udevice *dev);
- int (*eqos_remove_resources)(struct udevice *dev);
- int (*eqos_stop_resets)(struct udevice *dev);
- int (*eqos_start_resets)(struct udevice *dev);
- int (*eqos_stop_clks)(struct udevice *dev);
- int (*eqos_start_clks)(struct udevice *dev);
- int (*eqos_calibrate_pads)(struct udevice *dev);
- int (*eqos_disable_calibration)(struct udevice *dev);
- int (*eqos_set_tx_clk_speed)(struct udevice *dev);
- ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
-};
-
-struct eqos_priv {
- struct udevice *dev;
- const struct eqos_config *config;
- fdt_addr_t regs;
- struct eqos_mac_regs *mac_regs;
- struct eqos_mtl_regs *mtl_regs;
- struct eqos_dma_regs *dma_regs;
- struct eqos_tegra186_regs *tegra186_regs;
- struct reset_ctl reset_ctl;
- struct gpio_desc phy_reset_gpio;
- struct clk clk_master_bus;
- struct clk clk_rx;
- struct clk clk_ptp_ref;
- struct clk clk_tx;
- struct clk clk_ck;
- struct clk clk_slave_bus;
- struct mii_dev *mii;
- struct phy_device *phy;
- u32 max_speed;
- void *descs;
- int tx_desc_idx, rx_desc_idx;
- unsigned int desc_size;
- void *tx_dma_buf;
- void *rx_dma_buf;
- void *rx_pkt;
- bool started;
- bool reg_access_ok;
- bool clk_ck_enabled;
-};
+#include "dwc_eth_qos.h"
/*
* TX and RX descriptors are 16 bytes. This causes problems with the cache
@@ -359,7 +93,7 @@ static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos,
((rx ? EQOS_DESCRIPTORS_TX : 0) + num) * eqos->desc_size;
}
-static void eqos_inval_desc_generic(void *desc)
+void eqos_inval_desc_generic(void *desc)
{
unsigned long start = (unsigned long)desc;
unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
@@ -368,7 +102,7 @@ static void eqos_inval_desc_generic(void *desc)
invalidate_dcache_range(start, end);
}
-static void eqos_flush_desc_generic(void *desc)
+void eqos_flush_desc_generic(void *desc)
{
unsigned long start = (unsigned long)desc;
unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
@@ -377,7 +111,7 @@ static void eqos_flush_desc_generic(void *desc)
flush_dcache_range(start, end);
}
-static void eqos_inval_buffer_tegra186(void *buf, size_t size)
+void eqos_inval_buffer_tegra186(void *buf, size_t size)
{
unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
@@ -385,7 +119,7 @@ static void eqos_inval_buffer_tegra186(void *buf, size_t size)
invalidate_dcache_range(start, end);
}
-static void eqos_inval_buffer_generic(void *buf, size_t size)
+void eqos_inval_buffer_generic(void *buf, size_t size)
{
unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
unsigned long end = roundup((unsigned long)buf + size,
@@ -399,7 +133,7 @@ static void eqos_flush_buffer_tegra186(void *buf, size_t size)
flush_cache((unsigned long)buf, size);
}
-static void eqos_flush_buffer_generic(void *buf, size_t size)
+void eqos_flush_buffer_generic(void *buf, size_t size)
{
unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
unsigned long end = roundup((unsigned long)buf + size,
@@ -1890,7 +1624,7 @@ static int eqos_remove(struct udevice *dev)
return 0;
}
-static int eqos_null_ops(struct udevice *dev)
+int eqos_null_ops(struct udevice *dev)
{
return 0;
}
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
new file mode 100644
index 00000000000..68b367b068a
--- /dev/null
+++ b/drivers/net/dwc_eth_qos.h
@@ -0,0 +1,280 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <phy_interface.h>
+#include <linux/bitops.h>
+
+/* Core registers */
+
+#define EQOS_MAC_REGS_BASE 0x000
+struct eqos_mac_regs {
+ u32 configuration; /* 0x000 */
+ u32 unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
+ u32 q0_tx_flow_ctrl; /* 0x070 */
+ u32 unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
+ u32 rx_flow_ctrl; /* 0x090 */
+ u32 unused_094; /* 0x094 */
+ u32 txq_prty_map0; /* 0x098 */
+ u32 unused_09c; /* 0x09c */
+ u32 rxq_ctrl0; /* 0x0a0 */
+ u32 unused_0a4; /* 0x0a4 */
+ u32 rxq_ctrl2; /* 0x0a8 */
+ u32 unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
+ u32 us_tic_counter; /* 0x0dc */
+ u32 unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
+ u32 hw_feature0; /* 0x11c */
+ u32 hw_feature1; /* 0x120 */
+ u32 hw_feature2; /* 0x124 */
+ u32 unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
+ u32 mdio_address; /* 0x200 */
+ u32 mdio_data; /* 0x204 */
+ u32 unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
+ u32 address0_high; /* 0x300 */
+ u32 address0_low; /* 0x304 */
+};
+
+#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
+#define EQOS_MAC_CONFIGURATION_CST BIT(21)
+#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
+#define EQOS_MAC_CONFIGURATION_WD BIT(19)
+#define EQOS_MAC_CONFIGURATION_JD BIT(17)
+#define EQOS_MAC_CONFIGURATION_JE BIT(16)
+#define EQOS_MAC_CONFIGURATION_PS BIT(15)
+#define EQOS_MAC_CONFIGURATION_FES BIT(14)
+#define EQOS_MAC_CONFIGURATION_DM BIT(13)
+#define EQOS_MAC_CONFIGURATION_LM BIT(12)
+#define EQOS_MAC_CONFIGURATION_TE BIT(1)
+#define EQOS_MAC_CONFIGURATION_RE BIT(0)
+
+#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
+#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
+#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
+
+#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
+
+#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
+#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
+
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
+
+#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
+#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
+
+#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
+#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
+#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
+#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
+
+#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
+#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
+#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
+#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
+
+#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
+#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
+
+#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
+#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
+#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
+#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
+#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
+#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
+#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
+#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
+#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
+#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
+#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
+
+#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
+
+#define EQOS_MTL_REGS_BASE 0xd00
+struct eqos_mtl_regs {
+ u32 txq0_operation_mode; /* 0xd00 */
+ u32 unused_d04; /* 0xd04 */
+ u32 txq0_debug; /* 0xd08 */
+ u32 unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
+ u32 txq0_quantum_weight; /* 0xd18 */
+ u32 unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
+ u32 rxq0_operation_mode; /* 0xd30 */
+ u32 unused_d34; /* 0xd34 */
+ u32 rxq0_debug; /* 0xd38 */
+};
+
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
+#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
+
+#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
+#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
+#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
+
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
+#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
+
+#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
+#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
+#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
+#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
+
+#define EQOS_DMA_REGS_BASE 0x1000
+struct eqos_dma_regs {
+ u32 mode; /* 0x1000 */
+ u32 sysbus_mode; /* 0x1004 */
+ u32 unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
+ u32 ch0_control; /* 0x1100 */
+ u32 ch0_tx_control; /* 0x1104 */
+ u32 ch0_rx_control; /* 0x1108 */
+ u32 unused_110c; /* 0x110c */
+ u32 ch0_txdesc_list_haddress; /* 0x1110 */
+ u32 ch0_txdesc_list_address; /* 0x1114 */
+ u32 ch0_rxdesc_list_haddress; /* 0x1118 */
+ u32 ch0_rxdesc_list_address; /* 0x111c */
+ u32 ch0_txdesc_tail_pointer; /* 0x1120 */
+ u32 unused_1124; /* 0x1124 */
+ u32 ch0_rxdesc_tail_pointer; /* 0x1128 */
+ u32 ch0_txdesc_ring_length; /* 0x112c */
+ u32 ch0_rxdesc_ring_length; /* 0x1130 */
+};
+
+#define EQOS_DMA_MODE_SWR BIT(0)
+
+#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
+#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
+#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
+#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
+#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
+#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
+
+#define EQOS_DMA_CH0_CONTROL_DSL_SHIFT 18
+#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
+
+#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
+#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
+#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
+#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
+
+#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
+#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
+#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
+#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
+#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
+
+/* These registers are Tegra186-specific */
+#define EQOS_TEGRA186_REGS_BASE 0x8800
+struct eqos_tegra186_regs {
+ u32 sdmemcomppadctrl; /* 0x8800 */
+ u32 auto_cal_config; /* 0x8804 */
+ u32 unused_8808; /* 0x8808 */
+ u32 auto_cal_status; /* 0x880c */
+};
+
+#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
+
+#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
+#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
+
+#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
+
+/* Descriptors */
+#define EQOS_DESCRIPTORS_TX 4
+#define EQOS_DESCRIPTORS_RX 4
+#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
+#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
+#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
+#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
+
+struct eqos_desc {
+ u32 des0;
+ u32 des1;
+ u32 des2;
+ u32 des3;
+};
+
+#define EQOS_DESC3_OWN BIT(31)
+#define EQOS_DESC3_FD BIT(29)
+#define EQOS_DESC3_LD BIT(28)
+#define EQOS_DESC3_BUF1V BIT(24)
+
+#define EQOS_AXI_WIDTH_32 4
+#define EQOS_AXI_WIDTH_64 8
+#define EQOS_AXI_WIDTH_128 16
+
+struct eqos_config {
+ bool reg_access_always_ok;
+ int mdio_wait;
+ int swr_wait;
+ int config_mac;
+ int config_mac_mdio;
+ unsigned int axi_bus_width;
+ phy_interface_t (*interface)(const struct udevice *dev);
+ struct eqos_ops *ops;
+};
+
+struct eqos_ops {
+ void (*eqos_inval_desc)(void *desc);
+ void (*eqos_flush_desc)(void *desc);
+ void (*eqos_inval_buffer)(void *buf, size_t size);
+ void (*eqos_flush_buffer)(void *buf, size_t size);
+ int (*eqos_probe_resources)(struct udevice *dev);
+ int (*eqos_remove_resources)(struct udevice *dev);
+ int (*eqos_stop_resets)(struct udevice *dev);
+ int (*eqos_start_resets)(struct udevice *dev);
+ int (*eqos_stop_clks)(struct udevice *dev);
+ int (*eqos_start_clks)(struct udevice *dev);
+ int (*eqos_calibrate_pads)(struct udevice *dev);
+ int (*eqos_disable_calibration)(struct udevice *dev);
+ int (*eqos_set_tx_clk_speed)(struct udevice *dev);
+ ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
+};
+
+struct eqos_priv {
+ struct udevice *dev;
+ const struct eqos_config *config;
+ fdt_addr_t regs;
+ struct eqos_mac_regs *mac_regs;
+ struct eqos_mtl_regs *mtl_regs;
+ struct eqos_dma_regs *dma_regs;
+ struct eqos_tegra186_regs *tegra186_regs;
+ struct reset_ctl reset_ctl;
+ struct gpio_desc phy_reset_gpio;
+ struct clk clk_master_bus;
+ struct clk clk_rx;
+ struct clk clk_ptp_ref;
+ struct clk clk_tx;
+ struct clk clk_ck;
+ struct clk clk_slave_bus;
+ struct mii_dev *mii;
+ struct phy_device *phy;
+ u32 max_speed;
+ void *descs;
+ int tx_desc_idx, rx_desc_idx;
+ unsigned int desc_size;
+ void *tx_dma_buf;
+ void *rx_dma_buf;
+ void *rx_pkt;
+ bool started;
+ bool reg_access_ok;
+ bool clk_ck_enabled;
+};
+
+void eqos_inval_desc_generic(void *desc);
+void eqos_flush_desc_generic(void *desc);
+void eqos_inval_buffer_generic(void *buf, size_t size);
+void eqos_flush_buffer_generic(void *buf, size_t size);
+int eqos_null_ops(struct udevice *dev);
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 45/49] net: dwc_eth_qos: move i.MX code out
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (43 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 44/49] net: dwc_eth_qos: public some functions Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-07-03 19:15 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 46/49] net: eqos: add function to get phy node and address Peng Fan (OSS)
` (4 subsequent siblings)
49 siblings, 1 reply; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Joe Hershberger, Ramon Fried; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Move i.MX code to a standalone file to make it easy for adding new
platform support
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 92 --------------------------
drivers/net/dwc_eth_qos.h | 2 +
drivers/net/dwc_eth_qos_imx.c | 121 ++++++++++++++++++++++++++++++++++
4 files changed, 124 insertions(+), 92 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos_imx.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 69fb3bbbf7c..9536af11946 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b69a9feb824..1f24f5cb0cf 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -506,20 +506,6 @@ static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
#endif
}
-__weak u32 imx_get_eqos_csr_clk(void)
-{
- return 100 * 1000000;
-}
-__weak int imx_eqos_txclk_set_rate(unsigned long rate)
-{
- return 0;
-}
-
-static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
-{
- return imx_get_eqos_csr_clk();
-}
-
static int eqos_set_full_duplex(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -616,38 +602,6 @@ static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
return 0;
}
-static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
- ulong rate;
- int ret;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- switch (eqos->phy->speed) {
- case SPEED_1000:
- rate = 125 * 1000 * 1000;
- break;
- case SPEED_100:
- rate = 25 * 1000 * 1000;
- break;
- case SPEED_10:
- rate = 2.5 * 1000 * 1000;
- break;
- default:
- pr_err("invalid speed %d", eqos->phy->speed);
- return -EINVAL;
- }
-
- ret = imx_eqos_txclk_set_rate(rate);
- if (ret < 0) {
- pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
- return ret;
- }
-
- return 0;
-}
-
static int eqos_adjust_link(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1468,24 +1422,6 @@ static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev)
return PHY_INTERFACE_MODE_MII;
}
-static int eqos_probe_resources_imx(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
- phy_interface_t interface;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- interface = eqos->config->interface(dev);
-
- if (interface == PHY_INTERFACE_MODE_NA) {
- pr_err("Invalid PHY interface\n");
- return -EINVAL;
- }
-
- debug("%s: OK\n", __func__);
- return 0;
-}
-
static int eqos_remove_resources_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1695,34 +1631,6 @@ static const struct eqos_config __maybe_unused eqos_stm32_config = {
.ops = &eqos_stm32_ops
};
-static struct eqos_ops eqos_imx_ops = {
- .eqos_inval_desc = eqos_inval_desc_generic,
- .eqos_flush_desc = eqos_flush_desc_generic,
- .eqos_inval_buffer = eqos_inval_buffer_generic,
- .eqos_flush_buffer = eqos_flush_buffer_generic,
- .eqos_probe_resources = eqos_probe_resources_imx,
- .eqos_remove_resources = eqos_null_ops,
- .eqos_stop_resets = eqos_null_ops,
- .eqos_start_resets = eqos_null_ops,
- .eqos_stop_clks = eqos_null_ops,
- .eqos_start_clks = eqos_null_ops,
- .eqos_calibrate_pads = eqos_null_ops,
- .eqos_disable_calibration = eqos_null_ops,
- .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
-};
-
-struct eqos_config __maybe_unused eqos_imx_config = {
- .reg_access_always_ok = false,
- .mdio_wait = 10,
- .swr_wait = 50,
- .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
- .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .axi_bus_width = EQOS_AXI_WIDTH_64,
- .interface = dev_read_phy_mode,
- .ops = &eqos_imx_ops
-};
-
static const struct udevice_id eqos_ids[] = {
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
{
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 68b367b068a..ce90e1f1ce1 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -278,3 +278,5 @@ void eqos_flush_desc_generic(void *desc);
void eqos_inval_buffer_generic(void *buf, size_t size);
void eqos_flush_buffer_generic(void *buf, size_t size);
int eqos_null_ops(struct udevice *dev);
+
+extern struct eqos_config eqos_imx_config;
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
new file mode 100644
index 00000000000..2d1b5104af2
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <eth_phy.h>
+#include <log.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <miiphy.h>
+#include <net.h>
+#include <netdev.h>
+#include <phy.h>
+#include <reset.h>
+#include <wait_bit.h>
+#include <asm/arch/clock.h>
+#include <asm/cache.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <linux/delay.h>
+
+#include "dwc_eth_qos.h"
+
+__weak u32 imx_get_eqos_csr_clk(void)
+{
+ return 100 * 1000000;
+}
+
+__weak int imx_eqos_txclk_set_rate(unsigned long rate)
+{
+ return 0;
+}
+
+static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
+{
+ return imx_get_eqos_csr_clk();
+}
+
+static int eqos_probe_resources_imx(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ phy_interface_t interface;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ interface = eqos->config->interface(dev);
+
+ if (interface == PHY_INTERFACE_MODE_NA) {
+ pr_err("Invalid PHY interface\n");
+ return -EINVAL;
+ }
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ ulong rate;
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ switch (eqos->phy->speed) {
+ case SPEED_1000:
+ rate = 125 * 1000 * 1000;
+ break;
+ case SPEED_100:
+ rate = 25 * 1000 * 1000;
+ break;
+ case SPEED_10:
+ rate = 2.5 * 1000 * 1000;
+ break;
+ default:
+ pr_err("invalid speed %d", eqos->phy->speed);
+ return -EINVAL;
+ }
+
+ ret = imx_eqos_txclk_set_rate(rate);
+ if (ret < 0) {
+ pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct eqos_ops eqos_imx_ops = {
+ .eqos_inval_desc = eqos_inval_desc_generic,
+ .eqos_flush_desc = eqos_flush_desc_generic,
+ .eqos_inval_buffer = eqos_inval_buffer_generic,
+ .eqos_flush_buffer = eqos_flush_buffer_generic,
+ .eqos_probe_resources = eqos_probe_resources_imx,
+ .eqos_remove_resources = eqos_null_ops,
+ .eqos_stop_resets = eqos_null_ops,
+ .eqos_start_resets = eqos_null_ops,
+ .eqos_stop_clks = eqos_null_ops,
+ .eqos_start_clks = eqos_null_ops,
+ .eqos_calibrate_pads = eqos_null_ops,
+ .eqos_disable_calibration = eqos_null_ops,
+ .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
+};
+
+struct eqos_config __maybe_unused eqos_imx_config = {
+ .reg_access_always_ok = false,
+ .mdio_wait = 10,
+ .swr_wait = 50,
+ .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
+ .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
+ .axi_bus_width = EQOS_AXI_WIDTH_64,
+ .interface = dev_read_phy_mode,
+ .ops = &eqos_imx_ops
+};
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 46/49] net: eqos: add function to get phy node and address
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (44 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 45/49] net: dwc_eth_qos: move i.MX code out Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-07-03 19:17 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 47/49] net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr Peng Fan (OSS)
` (3 subsequent siblings)
49 siblings, 1 reply; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Joe Hershberger, Ramon Fried; +Cc: u-boot, Ye Li
From: Ye Li <ye.li@nxp.com>
Since new atheros PHY driver needs to access its PHY node through
phy device, we have to assign the phy node in ethernet controller
driver. Otherwise the PHY driver will fail to get some nodes
and properties.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/net/dwc_eth_qos.c | 23 ++++++++++++++++++++---
drivers/net/dwc_eth_qos.h | 1 +
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 1f24f5cb0cf..a4380d17d9c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -719,6 +719,24 @@ static int eqos_read_rom_hwaddr(struct udevice *dev)
return !is_valid_ethaddr(pdata->enetaddr);
}
+static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle_args;
+ int reg;
+
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args)) {
+ debug("Failed to find phy-handle");
+ return -ENODEV;
+ }
+
+ priv->phy_of_node = phandle_args.node;
+
+ reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+ return reg;
+}
+
static int eqos_start(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -767,9 +785,7 @@ static int eqos_start(struct udevice *dev)
*/
if (!eqos->phy) {
int addr = -1;
-#ifdef CONFIG_DM_ETH_PHY
- addr = eth_phy_get_addr(dev);
-#endif
+ addr = eqos_get_phy_addr(eqos, dev);
#ifdef DWC_NET_PHYADDR
addr = DWC_NET_PHYADDR;
#endif
@@ -788,6 +804,7 @@ static int eqos_start(struct udevice *dev)
}
}
+ eqos->phy->node = eqos->phy_of_node;
ret = phy_config(eqos->phy);
if (ret < 0) {
pr_err("phy_config() failed: %d", ret);
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index ce90e1f1ce1..f470189e8d4 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -261,6 +261,7 @@ struct eqos_priv {
struct clk clk_slave_bus;
struct mii_dev *mii;
struct phy_device *phy;
+ ofnode phy_of_node;
u32 max_speed;
void *descs;
int tx_desc_idx, rx_desc_idx;
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 47/49] net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (45 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 46/49] net: eqos: add function to get phy node and address Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-07-03 19:19 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 48/49] board: freescale: imx93_evk: support ethernet Peng Fan (OSS)
` (2 subsequent siblings)
49 siblings, 1 reply; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Joe Hershberger, Ramon Fried; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
i.MX has specific hook to get MAC address, so introduce a hook and move
i.MX code to its own driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/net/dwc_eth_qos.c | 9 ++++++---
drivers/net/dwc_eth_qos.h | 1 +
drivers/net/dwc_eth_qos_imx.c | 12 +++++++++++-
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index a4380d17d9c..c1f2391d635 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -712,10 +712,13 @@ static int eqos_write_hwaddr(struct udevice *dev)
static int eqos_read_rom_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ int ret;
+
+ ret = eqos->config->ops->eqos_get_enetaddr(dev);
+ if (ret < 0)
+ return ret;
-#ifdef CONFIG_ARCH_IMX8M
- imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
-#endif
return !is_valid_ethaddr(pdata->enetaddr);
}
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index f470189e8d4..b35e7742634 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -240,6 +240,7 @@ struct eqos_ops {
int (*eqos_calibrate_pads)(struct udevice *dev);
int (*eqos_disable_calibration)(struct udevice *dev);
int (*eqos_set_tx_clk_speed)(struct udevice *dev);
+ int (*eqos_get_enetaddr)(struct udevice *dev);
ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
};
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 2d1b5104af2..42cb164ad14 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -92,6 +92,15 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
return 0;
}
+static int eqos_get_enetaddr_imx(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+
+ imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
+
+ return 0;
+}
+
static struct eqos_ops eqos_imx_ops = {
.eqos_inval_desc = eqos_inval_desc_generic,
.eqos_flush_desc = eqos_flush_desc_generic,
@@ -106,7 +115,8 @@ static struct eqos_ops eqos_imx_ops = {
.eqos_calibrate_pads = eqos_null_ops,
.eqos_disable_calibration = eqos_null_ops,
.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
+ .eqos_get_enetaddr = eqos_get_enetaddr_imx,
+ .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx,
};
struct eqos_config __maybe_unused eqos_imx_config = {
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 48/49] board: freescale: imx93_evk: support ethernet
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (46 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 47/49] net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 49/49] tools: image: support i.MX93 Peng Fan (OSS)
2022-06-27 6:45 ` [PATCH V2 00/49] imx: " Peng Fan
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam, Peng Fan, NXP i.MX U-Boot Team; +Cc: u-boot
From: Peng Fan <peng.fan@nxp.com>
Add ethernet support
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 7 +++++
board/freescale/imx93_evk/imx93_evk.c | 32 +++++++++++++++++++++++
configs/imx93_11x11_evk_defconfig | 9 +++++++
3 files changed, 48 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 049eca4f3a7..f575805c7da 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -7,6 +7,7 @@
#define __ASM_ARCH_IMX9_REGS_H__
#define ARCH_MXC
+#define FEC_QUIRK_ENET_MAC
#define IOMUXC_BASE_ADDR 0x443C0000UL
#define CCM_BASE_ADDR 0x44450000UL
@@ -39,6 +40,12 @@
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
+#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#include <stdbool.h>
diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c
index 77b92b35db4..f111b99fc2e 100644
--- a/board/freescale/imx93_evk/imx93_evk.c
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -38,8 +38,40 @@ int board_early_init_f(void)
return 0;
}
+static int setup_fec(void)
+{
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+static int setup_eqos(void)
+{
+ struct blk_ctrl_wakeupmix_regs *bctrl =
+ (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(&bctrl->eqos_gpr,
+ BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
+ BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+
int board_init(void)
{
+ if (CONFIG_IS_ENABLED(FEC_MXC))
+ setup_fec();
+
+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
+ setup_eqos();
+
return 0;
}
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
index 8a396ed1c13..1f59f7e365d 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -75,6 +75,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
@@ -89,6 +90,14 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH V2 49/49] tools: image: support i.MX93
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (47 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 48/49] board: freescale: imx93_evk: support ethernet Peng Fan (OSS)
@ 2022-06-27 3:24 ` Peng Fan (OSS)
2022-06-27 6:45 ` [PATCH V2 00/49] imx: " Peng Fan
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan (OSS) @ 2022-06-27 3:24 UTC (permalink / raw)
To: sbabic, festevam; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
Support build i.MX93 container image with mkimage
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
include/imx8image.h | 15 +++++++--
tools/imx8image.c | 79 +++++++++++++++++++++++++++++++++++++--------
2 files changed, 78 insertions(+), 16 deletions(-)
diff --git a/include/imx8image.h b/include/imx8image.h
index 00c614ab6cc..32064bfeeb8 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -165,6 +165,7 @@ enum imx8image_core_type {
CFG_M40,
CFG_M41,
CFG_A35,
+ CFG_A55,
CFG_A53,
CFG_A72
};
@@ -180,7 +181,9 @@ enum imx8image_fld_types {
typedef enum SOC_TYPE {
NONE = 0,
QX,
- QM
+ QM,
+ ULP,
+ IMX9
} soc_type_t;
typedef enum option_type {
@@ -201,7 +204,9 @@ typedef enum option_type {
DATA,
PARTITION,
FILEOFF,
- MSG_BLOCK
+ MSG_BLOCK,
+ SENTINEL,
+ UPOWER
} option_type_t;
typedef struct {
@@ -221,6 +226,11 @@ typedef struct {
#define CORE_CA72 5
#define CORE_SECO 6
+#define CORE_ULP_CM33 0x1
+#define CORE_ULP_CA35 0x2
+#define CORE_ULP_UPOWER 0x4
+#define CORE_ULP_SENTINEL 0x6
+
#define SC_R_OTP 357U
#define SC_R_DEBUG 354U
#define SC_R_ROM_0 236U
@@ -235,6 +245,7 @@ typedef struct {
#define IMG_TYPE_DATA 0x04 /* Data image type */
#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */
#define IMG_TYPE_SECO 0x06 /* SECO image type */
+#define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */
#define IMG_TYPE_PROV 0x07 /* Provisioning image type */
#define IMG_TYPE_DEK 0x08 /* DEK validation type */
diff --git a/tools/imx8image.c b/tools/imx8image.c
index fa8f2274876..01e14869114 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -60,6 +60,7 @@ static table_entry_t imx8image_core_entries[] = {
{CFG_M40, "M40", "M4 core 0", },
{CFG_M41, "M41", "M4 core 1", },
{CFG_A35, "A35", "A35 core", },
+ {CFG_A55, "A55", "A55 core", },
{CFG_A53, "A53", "A53 core", },
{CFG_A72, "A72", "A72 core", },
{-1, "", "", },
@@ -117,6 +118,10 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t cmd, char *token,
soc = QX;
} else if (!strncmp(token, "IMX8QM", 6)) {
soc = QM;
+ } else if (!strncmp(token, "ULP", 3)) {
+ soc = IMX9;
+ } else if (!strncmp(token, "IMX9", 4)) {
+ soc = IMX9;
} else {
fprintf(stderr, "Unknown CMD_SOC_TYPE");
exit(EXIT_FAILURE);
@@ -187,6 +192,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t *cmd, char *token,
param_stack[p_idx].filename = token;
break;
case CFG_A35:
+ case CFG_A55:
param_stack[p_idx].ext = CORE_CA35;
param_stack[p_idx].option =
(*cmd == CMD_DATA) ? DATA : AP;
@@ -219,6 +225,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t *cmd, char *token,
case CFG_M41:
case CFG_A35:
case CFG_A53:
+ case CFG_A55:
case CFG_A72:
param_stack[p_idx++].entry =
(uint32_t)strtoll(token, NULL, 0);
@@ -548,6 +555,18 @@ static void set_image_array_entry(flash_header_v3_t *container,
img->dst = 0x20C00000;
img->entry = 0x20000000;
break;
+ case SENTINEL:
+ if (container->num_images > 0) {
+ fprintf(stderr, "Error: SENTINEL container only allows 1 image\n");
+ return;
+ }
+
+ img->hab_flags |= IMG_TYPE_SENTINEL;
+ img->hab_flags |= CORE_ULP_SENTINEL << BOOT_IMG_FLAGS_CORE_SHIFT;
+ tmp_name = "SENTINEL";
+ img->dst = 0xe4000000; /* S400 IRAM base */
+ img->entry = 0xe4000000;
+ break;
case AP:
if (soc == QX && core == CORE_CA35) {
meta = IMAGE_A35_DEFAULT_META(custom_partition);
@@ -555,6 +574,8 @@ static void set_image_array_entry(flash_header_v3_t *container,
meta = IMAGE_A53_DEFAULT_META(custom_partition);
} else if (soc == QM && core == CORE_CA72) {
meta = IMAGE_A72_DEFAULT_META(custom_partition);
+ } else if (((soc == ULP) || (soc == IMX9)) && core == CORE_CA35) {
+ meta = 0;
} else {
fprintf(stderr,
"Error: invalid AP core id: %" PRIu64 "\n",
@@ -562,8 +583,10 @@ static void set_image_array_entry(flash_header_v3_t *container,
exit(EXIT_FAILURE);
}
img->hab_flags |= IMG_TYPE_EXEC;
- /* On B0, only core id = 4 is valid */
- img->hab_flags |= CORE_CA53 << BOOT_IMG_FLAGS_CORE_SHIFT;
+ if ((soc == ULP) || (soc == IMX9))
+ img->hab_flags |= CORE_ULP_CA35 << BOOT_IMG_FLAGS_CORE_SHIFT;
+ else
+ img->hab_flags |= CORE_CA53 << BOOT_IMG_FLAGS_CORE_SHIFT; /* On B0, only core id = 4 is valid */
tmp_name = "AP";
img->dst = entry;
img->entry = entry;
@@ -572,17 +595,22 @@ static void set_image_array_entry(flash_header_v3_t *container,
break;
case M40:
case M41:
- if (core == 0) {
- core = CORE_CM4_0;
- meta = IMAGE_M4_0_DEFAULT_META(custom_partition);
- } else if (core == 1) {
- core = CORE_CM4_1;
- meta = IMAGE_M4_1_DEFAULT_META(custom_partition);
+ if ((soc == ULP) || (soc == IMX9)) {
+ core = CORE_ULP_CM33;
+ meta = 0;
} else {
- fprintf(stderr,
- "Error: invalid m4 core id: %" PRIu64 "\n",
- core);
- exit(EXIT_FAILURE);
+ if (core == 0) {
+ core = CORE_CM4_0;
+ meta = IMAGE_M4_0_DEFAULT_META(custom_partition);
+ } else if (core == 1) {
+ core = CORE_CM4_1;
+ meta = IMAGE_M4_1_DEFAULT_META(custom_partition);
+ } else {
+ fprintf(stderr,
+ "Error: invalid m4 core id: %" PRIu64 "\n",
+ core);
+ exit(EXIT_FAILURE);
+ }
}
img->hab_flags |= IMG_TYPE_EXEC;
img->hab_flags |= core << BOOT_IMG_FLAGS_CORE_SHIFT;
@@ -598,7 +626,14 @@ static void set_image_array_entry(flash_header_v3_t *container,
break;
case DATA:
img->hab_flags |= IMG_TYPE_DATA;
- img->hab_flags |= CORE_CA35 << BOOT_IMG_FLAGS_CORE_SHIFT;
+ if ((soc == ULP) || (soc == IMX9)) {
+ if (core == CORE_CM4_0)
+ img->hab_flags |= CORE_ULP_CM33 << BOOT_IMG_FLAGS_CORE_SHIFT;
+ else
+ img->hab_flags |= CORE_ULP_CA35 << BOOT_IMG_FLAGS_CORE_SHIFT;
+ } else {
+ img->hab_flags |= CORE_CA35 << BOOT_IMG_FLAGS_CORE_SHIFT;
+ }
tmp_name = "DATA";
img->dst = entry;
break;
@@ -630,6 +665,15 @@ static void set_image_array_entry(flash_header_v3_t *container,
img->dst = img->entry - 1;
}
break;
+ case UPOWER:
+ if (soc == ULP) {
+ img->hab_flags |= IMG_TYPE_EXEC;
+ img->hab_flags |= CORE_ULP_UPOWER << BOOT_IMG_FLAGS_CORE_SHIFT;
+ tmp_name = "UPOWER";
+ img->dst = 0x28300200; /* UPOWER code RAM */
+ img->entry = 0x28300200;
+ }
+ break;
default:
fprintf(stderr, "unrecognized image type (%d)\n", type);
exit(EXIT_FAILURE);
@@ -797,6 +841,10 @@ static int build_container(soc_type_t soc, uint32_t sector_size,
fprintf(stdout, "Platform:\ti.MX8QXP B0\n");
else if (soc == QM)
fprintf(stdout, "Platform:\ti.MX8QM B0\n");
+ else if (soc == ULP)
+ fprintf(stdout, "Platform:\ti.MX8ULP A0\n");
+ else if (soc == IMX9)
+ fprintf(stdout, "Platform:\ti.MX9\n");
set_imx_hdr_v3(&imx_header, 0);
set_imx_hdr_v3(&imx_header, 1);
@@ -815,6 +863,7 @@ static int build_container(soc_type_t soc, uint32_t sector_size,
case M41:
case SCFW:
case DATA:
+ case UPOWER:
case MSG_BLOCK:
if (container < 0) {
fprintf(stderr, "No container found\n");
@@ -833,6 +882,7 @@ static int build_container(soc_type_t soc, uint32_t sector_size,
break;
case SECO:
+ case SENTINEL:
if (container < 0) {
fprintf(stderr, "No container found\n");
exit(EXIT_FAILURE);
@@ -941,7 +991,8 @@ static int build_container(soc_type_t soc, uint32_t sector_size,
if (img_sp->option == M40 || img_sp->option == M41 ||
img_sp->option == AP || img_sp->option == DATA ||
img_sp->option == SCD || img_sp->option == SCFW ||
- img_sp->option == SECO || img_sp->option == MSG_BLOCK) {
+ img_sp->option == SECO || img_sp->option == MSG_BLOCK ||
+ img_sp->option == UPOWER || img_sp->option == SENTINEL) {
copy_file_aligned(ofd, img_sp->filename, img_sp->src,
sector_size);
}
--
2.36.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* RE: [PATCH V2 00/49] imx: support i.MX93
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
` (48 preceding siblings ...)
2022-06-27 3:24 ` [PATCH V2 49/49] tools: image: support i.MX93 Peng Fan (OSS)
@ 2022-06-27 6:45 ` Peng Fan
49 siblings, 0 replies; 61+ messages in thread
From: Peng Fan @ 2022-06-27 6:45 UTC (permalink / raw)
To: Peng Fan (OSS), sbabic, festevam; +Cc: u-boot
Hi Stefano,
> Subject: [PATCH V2 00/49] imx: support i.MX93
This should be V3, not V2. Hope this not matter, I have
marked the previous V2 as changes requested in patchwork.
Thanks,
Peng.
>
> From: Peng Fan <peng.fan@nxp.com>
>
> V2:
> Fix issue reported by CI build
> - Enlarge SPL_MAX_SIZE for i.MX8MM
> - Fix i.MX8ULP break
>
> This patchset is to support i.MX93, during the development, there are some
> code cleanup and restructure to make i.MX93 code porting cleaner.
>
> i.MX9 is a new i.MX family and i.MX93 is the first one that we would support
> in upstream. It features two Cortex-A55 core, one NPU, one M33 and others.
>
> There are some driver changes that also included to make i.MX93 function well,
> lpuart/mmc/network.
>
> mkimage also included, but I have not enable BINMAN which is under
> development, will post a follow patchset to switch to binman.
>
> Alice Guo (3):
> misc: imx8ulp: move fuse.c from imx8ulp to sentinel
> misc: fuse: support to access fuse on i.MX93
> misc: fuse: update the code for accessing fuse of i.MX93
>
> Jian Li (1):
> imx: imx9: Add function to initialize timer
>
> Peng Fan (31):
> spl: imx8mm: enlarge SPL_MAX_SIZE
> arm: makefile: cleanup mach-imx usage
> imx: simplify dependency with SPL_BOOTROM_SUPPORT
> imx: move get_boot_device to common header
> imx: move get_boot_device to common file
> imx: add USB2_BOOT type
> imx: add basic i.MX9 support
> fsl_lpuart: add i.MX9 support
> gpio: pca953x: support pcal6524
> imx: pinctrl: add pinctrl and pinfunc file for i.MX93
> imx: imx9: Add CCM and clock API support
> mmc: fsl_esdhc_imx: Support i.MX9
> spl: Use SPL_FIT_IMAGE_TINY for iMX9
> imx: imx9: support romapi
> misc: s4mu: Support iMX93 with Sentinel MU
> misc: S400_API: New API for FW status and chip info
> misc: s400_api: introduce ahab_release_m33_trout
> imx: imx9: Get the chip revision through S400 API
> imx: imx9: Add MIX power init
> imx: imx9: Add M33 release prepare function
> imx: imx9: Support booting m33 from Acore
> arm: dts: Add i.MX93 SoC DTSi file
> imx: imx93_evk: Add basic board support
> imx: imx93_evk: Set ARM clock to 1.7Ghz
> net: fec_mxc: support i.MX93
> net: dwc_eth_qos: fix build break when CLK not enabled
> net: dwc_eth_qos: public some functions
> net: dwc_eth_qos: move i.MX code out
> net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr
> board: freescale: imx93_evk: support ethernet
> tools: image: support i.MX93
>
> Ye Li (14):
> imx: Change USB boot device type
> imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device
> imx: imx9: disable watchdog
> misc: imx: S400_API: Move S400 MU and API to a common place
> misc: S400_API: Update release RDC API
> imx: imx9: Add TRDC driver for TRDC init
> imx: imx9: Add AHAB boot support
> misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
> imx: imx9: Add gpio registers structure
> imx: imx9: Support multiple env storages at runtime
> imx: imx9: clock: Add DDR clock support
> ddr: imx: Add i.MX9 DDR controller driver
> ddr: imx9: enable Performance monitor counter
> net: eqos: add function to get phy node and address
>
> arch/arm/Kconfig | 16 +
> arch/arm/Makefile | 12 +-
> arch/arm/dts/Makefile | 3 +
> arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 ++
> arch/arm/dts/imx93-11x11-evk.dts | 527 ++++++
> arch/arm/dts/imx93-pinfunc.h | 625 +++++++
> arch/arm/dts/imx93.dtsi | 688 ++++++++
> arch/arm/include/asm/arch-imx/cpu.h | 2 +
> arch/arm/include/asm/arch-imx8/sys_proto.h | 1 -
> arch/arm/include/asm/arch-imx8m/ddr.h | 6 +-
> arch/arm/include/asm/arch-imx8m/sys_proto.h | 2 +-
> arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 5 -
> arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 +++
> arch/arm/include/asm/arch-imx9/clock.h | 244 +++
> arch/arm/include/asm/arch-imx9/ddr.h | 126 ++
> arch/arm/include/asm/arch-imx9/gpio.h | 20 +
> arch/arm/include/asm/arch-imx9/imx-regs.h | 234 +++
> arch/arm/include/asm/arch-imx9/imx93_pins.h | 729 ++++++++
> arch/arm/include/asm/arch-imx9/sys_proto.h | 14 +
> arch/arm/include/asm/arch-imx9/trdc.h | 19 +
> arch/arm/include/asm/arch-mx7/sys_proto.h | 1 -
> arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 1 -
> arch/arm/include/asm/global_data.h | 5 +-
> arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
> arch/arm/include/asm/mach-imx/iomux-v3.h | 11 +-
> .../asm/{arch-imx8ulp => mach-imx}/mu_hal.h | 4 +-
> .../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 18 +-
> arch/arm/include/asm/mach-imx/sys_proto.h | 11 +-
> arch/arm/mach-imx/Kconfig | 3 +-
> arch/arm/mach-imx/Makefile | 10 +-
> arch/arm/mach-imx/imx8m/soc.c | 47 -
> arch/arm/mach-imx/imx8ulp/ahab.c | 345 ++++
> arch/arm/mach-imx/imx8ulp/rdc.c | 6 +-
> arch/arm/mach-imx/imx8ulp/soc.c | 48 +-
> arch/arm/mach-imx/imx9/Kconfig | 34 +
> arch/arm/mach-imx/imx9/Makefile | 11 +
> arch/arm/mach-imx/imx9/ahab.c | 346 ++++
> arch/arm/mach-imx/imx9/clock.c | 844 ++++++++++
> arch/arm/mach-imx/imx9/clock_root.c | 438 +++++
> arch/arm/mach-imx/imx9/imx_bootaux.c | 133 ++
> arch/arm/mach-imx/imx9/lowlevel_init.S | 26 +
> arch/arm/mach-imx/imx9/soc.c | 473 ++++++
> arch/arm/mach-imx/imx9/trdc.c | 581 +++++++
> arch/arm/mach-imx/imx_romapi.c | 60 +
> arch/arm/mach-imx/spl.c | 82 +-
> board/freescale/common/Makefile | 2 +-
> board/freescale/imx8ulp_evk/spl.c | 2 +-
> board/freescale/imx93_evk/Kconfig | 21 +
> board/freescale/imx93_evk/MAINTAINERS | 6 +
> board/freescale/imx93_evk/Makefile | 12 +
> board/freescale/imx93_evk/imx93_evk.c | 90 +
> board/freescale/imx93_evk/lpddr4x_timing.c | 1486
> +++++++++++++++++
> board/freescale/imx93_evk/spl.c | 129 ++
> common/spl/Kconfig | 3 +-
> configs/imx8mm-cl-iot-gate-optee_defconfig | 1 -
> configs/imx8mm-cl-iot-gate_defconfig | 1 -
> configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
> configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
> configs/imx8mm-mx8menlo_defconfig | 1 -
> configs/imx8mm_beacon_defconfig | 1 -
> configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
> configs/imx8mm_evk_defconfig | 1 -
> configs/imx8mm_venice_defconfig | 1 -
> configs/imx93_11x11_evk_defconfig | 117 ++
> configs/phycore-imx8mm_defconfig | 1 -
> configs/verdin-imx8mm_defconfig | 1 -
> drivers/Makefile | 1 +
> drivers/ddr/imx/Kconfig | 2 +
> drivers/ddr/imx/imx8m/Kconfig | 1 +
> drivers/ddr/imx/imx8m/Makefile | 3 +-
> drivers/ddr/imx/imx8m/ddr_init.c | 219 +++
> drivers/ddr/imx/imx9/Kconfig | 27 +
> drivers/ddr/imx/imx9/Makefile | 10 +
> drivers/ddr/imx/imx9/ddr_init.c | 489 ++++++
> drivers/ddr/imx/phy/Kconfig | 4 +
> drivers/ddr/imx/phy/Makefile | 9 +
> drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c | 0
> drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c | 1 -
> drivers/ddr/imx/phy/ddrphy_utils.c | 169 ++
> drivers/ddr/imx/{imx8m => phy}/helper.c | 45 +-
> drivers/gpio/pca953x_gpio.c | 4 +
> drivers/misc/Kconfig | 7 +
> drivers/misc/Makefile | 2 +-
> drivers/misc/{imx8ulp => sentinel}/Makefile | 2 +-
> drivers/misc/{imx8ulp => sentinel}/fuse.c | 96 +-
> drivers/misc/{imx8ulp => sentinel}/s400_api.c | 149 +-
> .../{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} | 11 +-
> drivers/mmc/Kconfig | 2 +-
> drivers/net/Kconfig | 2 +-
> drivers/net/Makefile | 1 +
> drivers/net/dwc_eth_qos.c | 406 +----
> drivers/net/dwc_eth_qos.h | 284 ++++
> drivers/net/dwc_eth_qos_imx.c | 131 ++
> drivers/net/fec_mxc.c | 4 +-
> drivers/pinctrl/nxp/Kconfig | 13 +
> drivers/pinctrl/nxp/Makefile | 1 +
> drivers/pinctrl/nxp/pinctrl-imx93.c | 37 +
> include/configs/imx93_evk.h | 149 ++
> include/dt-bindings/clock/imx93-clock.h | 203 +++
> include/dt-bindings/power/imx93-power.h | 12 +
> include/fsl_lpuart.h | 2 +-
> include/imx8image.h | 15 +-
> include/imx_sip.h | 1 +
> tools/imx8image.c | 79 +-
> 104 files changed, 11072 insertions(+), 635 deletions(-) create mode
> 100644 arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
> create mode 100644 arch/arm/dts/imx93-11x11-evk.dts create mode
> 100644 arch/arm/dts/imx93-pinfunc.h create mode 100644
> arch/arm/dts/imx93.dtsi create mode 100644
> arch/arm/include/asm/arch-imx9/ccm_regs.h
> create mode 100644 arch/arm/include/asm/arch-imx9/clock.h
> create mode 100644 arch/arm/include/asm/arch-imx9/ddr.h
> create mode 100644 arch/arm/include/asm/arch-imx9/gpio.h
> create mode 100644 arch/arm/include/asm/arch-imx9/imx-regs.h
> create mode 100644 arch/arm/include/asm/arch-imx9/imx93_pins.h
> create mode 100644 arch/arm/include/asm/arch-imx9/sys_proto.h
> create mode 100644 arch/arm/include/asm/arch-imx9/trdc.h
> rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/mu_hal.h (79%)
> rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/s400_api.h (75%)
> create mode 100644 arch/arm/mach-imx/imx8ulp/ahab.c create mode
> 100644 arch/arm/mach-imx/imx9/Kconfig create mode 100644
> arch/arm/mach-imx/imx9/Makefile create mode 100644
> arch/arm/mach-imx/imx9/ahab.c create mode 100644
> arch/arm/mach-imx/imx9/clock.c create mode 100644
> arch/arm/mach-imx/imx9/clock_root.c
> create mode 100644 arch/arm/mach-imx/imx9/imx_bootaux.c
> create mode 100644 arch/arm/mach-imx/imx9/lowlevel_init.S
> create mode 100644 arch/arm/mach-imx/imx9/soc.c create mode 100644
> arch/arm/mach-imx/imx9/trdc.c create mode 100644
> arch/arm/mach-imx/imx_romapi.c create mode 100644
> board/freescale/imx93_evk/Kconfig create mode 100644
> board/freescale/imx93_evk/MAINTAINERS
> create mode 100644 board/freescale/imx93_evk/Makefile
> create mode 100644 board/freescale/imx93_evk/imx93_evk.c
> create mode 100644 board/freescale/imx93_evk/lpddr4x_timing.c
> create mode 100644 board/freescale/imx93_evk/spl.c create mode 100644
> configs/imx93_11x11_evk_defconfig create mode 100644
> drivers/ddr/imx/imx9/Kconfig create mode 100644
> drivers/ddr/imx/imx9/Makefile create mode 100644
> drivers/ddr/imx/imx9/ddr_init.c create mode 100644
> drivers/ddr/imx/phy/Kconfig create mode 100644
> drivers/ddr/imx/phy/Makefile rename drivers/ddr/imx/{imx8m =>
> phy}/ddrphy_csr.c (100%) rename drivers/ddr/imx/{imx8m =>
> phy}/ddrphy_train.c (98%) create mode 100644
> drivers/ddr/imx/phy/ddrphy_utils.c
> rename drivers/ddr/imx/{imx8m => phy}/helper.c (79%) rename
> drivers/misc/{imx8ulp => sentinel}/Makefile (67%) rename
> drivers/misc/{imx8ulp => sentinel}/fuse.c (69%) rename
> drivers/misc/{imx8ulp => sentinel}/s400_api.c (69%) rename
> drivers/misc/{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} (94%) create mode
> 100644 drivers/net/dwc_eth_qos.h create mode 100644
> drivers/net/dwc_eth_qos_imx.c create mode 100644
> drivers/pinctrl/nxp/pinctrl-imx93.c
> create mode 100644 include/configs/imx93_evk.h create mode 100644
> include/dt-bindings/clock/imx93-clock.h
> create mode 100644 include/dt-bindings/power/imx93-power.h
>
> --
> 2.36.0
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE
2022-06-27 3:24 ` [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE Peng Fan (OSS)
@ 2022-06-29 10:09 ` Frieder Schrempf
2022-07-05 1:35 ` Peng Fan
0 siblings, 1 reply; 61+ messages in thread
From: Frieder Schrempf @ 2022-06-29 10:09 UTC (permalink / raw)
To: Peng Fan (OSS), sbabic, festevam, Ying-Chun Liu (PaulLiu),
Jagan Teki, Matteo Lisi, Marek Vasut, Olaf Mandel, Adam Ford,
Peng Fan, Tim Harvey, Teresa Remmet, Marcel Ziswiler
Cc: u-boot
Am 27.06.22 um 05:24 schrieb Peng Fan (OSS):
> From: Peng Fan <peng.fan@nxp.com>
>
> The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
> set to 0x7E1000.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> common/spl/Kconfig | 1 +
> configs/imx8mm-cl-iot-gate-optee_defconfig | 1 -
> configs/imx8mm-cl-iot-gate_defconfig | 1 -
> configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
> configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
> configs/imx8mm-mx8menlo_defconfig | 1 -
> configs/imx8mm_beacon_defconfig | 1 -
> configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
> configs/imx8mm_evk_defconfig | 1 -
> configs/imx8mm_venice_defconfig | 1 -
> configs/phycore-imx8mm_defconfig | 1 -
> configs/verdin-imx8mm_defconfig | 1 -
> 12 files changed, 1 insertion(+), 11 deletions(-)
Is there any reason, why you didn't include kontron-sl-mx8mm_defconfig
in this patch?
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 42/49] net: fec_mxc: support i.MX93
2022-06-27 3:24 ` [PATCH V2 42/49] net: fec_mxc: support i.MX93 Peng Fan (OSS)
@ 2022-07-03 19:13 ` Ramon Fried
0 siblings, 0 replies; 61+ messages in thread
From: Ramon Fried @ 2022-07-03 19:13 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Stefano Babic, Fabio Estevam, Joe Hershberger,
U-Boot Mailing List, Peng Fan
On Mon, Jun 27, 2022 at 5:43 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> Support i.MX93 in fec_mxc driver
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/net/Kconfig | 2 +-
> drivers/net/fec_mxc.c | 4 +++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 84d859c21eb..8cf8621467f 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -340,7 +340,7 @@ config FEC_MXC_MDIO_BASE
>
> config FEC_MXC
> bool "FEC Ethernet controller"
> - depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || VF610
> + depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || IMX93 || VF610
> help
> This driver supports the 10/100 Fast Ethernet controller for
> NXP i.MX processors.
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index a623a5c45e4..8bc2b46d403 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -598,7 +598,8 @@ static int fecmxc_init(struct udevice *dev)
> writel(0x00000000, &fec->eth->gaddr2);
>
> /* Do not access reserved register */
> - if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp()) {
> + if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp() &&
> + !is_imx93()) {
> /* clear MIB RAM */
> for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
> writel(0, i);
> @@ -1357,6 +1358,7 @@ static const struct udevice_id fecmxc_ids[] = {
> { .compatible = "fsl,imx53-fec" },
> { .compatible = "fsl,imx7d-fec" },
> { .compatible = "fsl,mvf600-fec" },
> + { .compatible = "fsl,imx93-fec" },
> { }
> };
>
> --
> 2.36.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 44/49] net: dwc_eth_qos: public some functions
2022-06-27 3:24 ` [PATCH V2 44/49] net: dwc_eth_qos: public some functions Peng Fan (OSS)
@ 2022-07-03 19:14 ` Ramon Fried
0 siblings, 0 replies; 61+ messages in thread
From: Ramon Fried @ 2022-07-03 19:14 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Stefano Babic, Fabio Estevam, Joe Hershberger,
U-Boot Mailing List, Peng Fan
On Mon, Jun 27, 2022 at 5:44 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> Move macros and structures to header file and make some functions
> public, so that could used by other files, this is to
> prepare split platform specific config to one file.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/net/dwc_eth_qos.c | 280 +-------------------------------------
> drivers/net/dwc_eth_qos.h | 280 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 287 insertions(+), 273 deletions(-)
> create mode 100644 drivers/net/dwc_eth_qos.h
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index 6048d56ff8c..b69a9feb824 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -51,275 +51,9 @@
> #include <asm/arch/clock.h>
> #include <asm/mach-imx/sys_proto.h>
> #endif
> -#include <linux/bitops.h>
> #include <linux/delay.h>
>
> -/* Core registers */
> -
> -#define EQOS_MAC_REGS_BASE 0x000
> -struct eqos_mac_regs {
> - uint32_t configuration; /* 0x000 */
> - uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
> - uint32_t q0_tx_flow_ctrl; /* 0x070 */
> - uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
> - uint32_t rx_flow_ctrl; /* 0x090 */
> - uint32_t unused_094; /* 0x094 */
> - uint32_t txq_prty_map0; /* 0x098 */
> - uint32_t unused_09c; /* 0x09c */
> - uint32_t rxq_ctrl0; /* 0x0a0 */
> - uint32_t unused_0a4; /* 0x0a4 */
> - uint32_t rxq_ctrl2; /* 0x0a8 */
> - uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
> - uint32_t us_tic_counter; /* 0x0dc */
> - uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
> - uint32_t hw_feature0; /* 0x11c */
> - uint32_t hw_feature1; /* 0x120 */
> - uint32_t hw_feature2; /* 0x124 */
> - uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
> - uint32_t mdio_address; /* 0x200 */
> - uint32_t mdio_data; /* 0x204 */
> - uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
> - uint32_t address0_high; /* 0x300 */
> - uint32_t address0_low; /* 0x304 */
> -};
> -
> -#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
> -#define EQOS_MAC_CONFIGURATION_CST BIT(21)
> -#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
> -#define EQOS_MAC_CONFIGURATION_WD BIT(19)
> -#define EQOS_MAC_CONFIGURATION_JD BIT(17)
> -#define EQOS_MAC_CONFIGURATION_JE BIT(16)
> -#define EQOS_MAC_CONFIGURATION_PS BIT(15)
> -#define EQOS_MAC_CONFIGURATION_FES BIT(14)
> -#define EQOS_MAC_CONFIGURATION_DM BIT(13)
> -#define EQOS_MAC_CONFIGURATION_LM BIT(12)
> -#define EQOS_MAC_CONFIGURATION_TE BIT(1)
> -#define EQOS_MAC_CONFIGURATION_RE BIT(0)
> -
> -#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
> -#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
> -#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
> -
> -#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
> -
> -#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
> -#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
> -
> -#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
> -#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
> -#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
> -#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
> -#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
> -
> -#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
> -#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
> -
> -#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
> -#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
> -#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
> -#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
> -
> -#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
> -#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
> -#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
> -#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
> -
> -#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
> -#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
> -
> -#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
> -#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
> -#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
> -#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
> -#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
> -#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
> -#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
> -#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
> -#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
> -#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
> -#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
> -
> -#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
> -
> -#define EQOS_MTL_REGS_BASE 0xd00
> -struct eqos_mtl_regs {
> - uint32_t txq0_operation_mode; /* 0xd00 */
> - uint32_t unused_d04; /* 0xd04 */
> - uint32_t txq0_debug; /* 0xd08 */
> - uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
> - uint32_t txq0_quantum_weight; /* 0xd18 */
> - uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
> - uint32_t rxq0_operation_mode; /* 0xd30 */
> - uint32_t unused_d34; /* 0xd34 */
> - uint32_t rxq0_debug; /* 0xd38 */
> -};
> -
> -#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
> -#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
> -#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
> -#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
> -#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
> -#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
> -#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
> -
> -#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
> -#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
> -#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
> -
> -#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
> -#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
> -#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
> -#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
> -#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
> -#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
> -#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
> -#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
> -
> -#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
> -#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
> -#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
> -#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
> -
> -#define EQOS_DMA_REGS_BASE 0x1000
> -struct eqos_dma_regs {
> - uint32_t mode; /* 0x1000 */
> - uint32_t sysbus_mode; /* 0x1004 */
> - uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
> - uint32_t ch0_control; /* 0x1100 */
> - uint32_t ch0_tx_control; /* 0x1104 */
> - uint32_t ch0_rx_control; /* 0x1108 */
> - uint32_t unused_110c; /* 0x110c */
> - uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
> - uint32_t ch0_txdesc_list_address; /* 0x1114 */
> - uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
> - uint32_t ch0_rxdesc_list_address; /* 0x111c */
> - uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
> - uint32_t unused_1124; /* 0x1124 */
> - uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
> - uint32_t ch0_txdesc_ring_length; /* 0x112c */
> - uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
> -};
> -
> -#define EQOS_DMA_MODE_SWR BIT(0)
> -
> -#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
> -#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
> -#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
> -#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
> -#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
> -#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
> -
> -#define EQOS_DMA_CH0_CONTROL_DSL_SHIFT 18
> -#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
> -
> -#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
> -#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
> -#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
> -#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
> -
> -#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
> -#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
> -#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
> -#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
> -#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
> -
> -/* These registers are Tegra186-specific */
> -#define EQOS_TEGRA186_REGS_BASE 0x8800
> -struct eqos_tegra186_regs {
> - uint32_t sdmemcomppadctrl; /* 0x8800 */
> - uint32_t auto_cal_config; /* 0x8804 */
> - uint32_t unused_8808; /* 0x8808 */
> - uint32_t auto_cal_status; /* 0x880c */
> -};
> -
> -#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
> -
> -#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
> -#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
> -
> -#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
> -
> -/* Descriptors */
> -#define EQOS_DESCRIPTORS_TX 4
> -#define EQOS_DESCRIPTORS_RX 4
> -#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
> -#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
> -#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
> -#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
> -
> -struct eqos_desc {
> - u32 des0;
> - u32 des1;
> - u32 des2;
> - u32 des3;
> -};
> -
> -#define EQOS_DESC3_OWN BIT(31)
> -#define EQOS_DESC3_FD BIT(29)
> -#define EQOS_DESC3_LD BIT(28)
> -#define EQOS_DESC3_BUF1V BIT(24)
> -
> -#define EQOS_AXI_WIDTH_32 4
> -#define EQOS_AXI_WIDTH_64 8
> -#define EQOS_AXI_WIDTH_128 16
> -
> -struct eqos_config {
> - bool reg_access_always_ok;
> - int mdio_wait;
> - int swr_wait;
> - int config_mac;
> - int config_mac_mdio;
> - unsigned int axi_bus_width;
> - phy_interface_t (*interface)(const struct udevice *dev);
> - struct eqos_ops *ops;
> -};
> -
> -struct eqos_ops {
> - void (*eqos_inval_desc)(void *desc);
> - void (*eqos_flush_desc)(void *desc);
> - void (*eqos_inval_buffer)(void *buf, size_t size);
> - void (*eqos_flush_buffer)(void *buf, size_t size);
> - int (*eqos_probe_resources)(struct udevice *dev);
> - int (*eqos_remove_resources)(struct udevice *dev);
> - int (*eqos_stop_resets)(struct udevice *dev);
> - int (*eqos_start_resets)(struct udevice *dev);
> - int (*eqos_stop_clks)(struct udevice *dev);
> - int (*eqos_start_clks)(struct udevice *dev);
> - int (*eqos_calibrate_pads)(struct udevice *dev);
> - int (*eqos_disable_calibration)(struct udevice *dev);
> - int (*eqos_set_tx_clk_speed)(struct udevice *dev);
> - ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
> -};
> -
> -struct eqos_priv {
> - struct udevice *dev;
> - const struct eqos_config *config;
> - fdt_addr_t regs;
> - struct eqos_mac_regs *mac_regs;
> - struct eqos_mtl_regs *mtl_regs;
> - struct eqos_dma_regs *dma_regs;
> - struct eqos_tegra186_regs *tegra186_regs;
> - struct reset_ctl reset_ctl;
> - struct gpio_desc phy_reset_gpio;
> - struct clk clk_master_bus;
> - struct clk clk_rx;
> - struct clk clk_ptp_ref;
> - struct clk clk_tx;
> - struct clk clk_ck;
> - struct clk clk_slave_bus;
> - struct mii_dev *mii;
> - struct phy_device *phy;
> - u32 max_speed;
> - void *descs;
> - int tx_desc_idx, rx_desc_idx;
> - unsigned int desc_size;
> - void *tx_dma_buf;
> - void *rx_dma_buf;
> - void *rx_pkt;
> - bool started;
> - bool reg_access_ok;
> - bool clk_ck_enabled;
> -};
> +#include "dwc_eth_qos.h"
>
> /*
> * TX and RX descriptors are 16 bytes. This causes problems with the cache
> @@ -359,7 +93,7 @@ static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos,
> ((rx ? EQOS_DESCRIPTORS_TX : 0) + num) * eqos->desc_size;
> }
>
> -static void eqos_inval_desc_generic(void *desc)
> +void eqos_inval_desc_generic(void *desc)
> {
> unsigned long start = (unsigned long)desc;
> unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
> @@ -368,7 +102,7 @@ static void eqos_inval_desc_generic(void *desc)
> invalidate_dcache_range(start, end);
> }
>
> -static void eqos_flush_desc_generic(void *desc)
> +void eqos_flush_desc_generic(void *desc)
> {
> unsigned long start = (unsigned long)desc;
> unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
> @@ -377,7 +111,7 @@ static void eqos_flush_desc_generic(void *desc)
> flush_dcache_range(start, end);
> }
>
> -static void eqos_inval_buffer_tegra186(void *buf, size_t size)
> +void eqos_inval_buffer_tegra186(void *buf, size_t size)
> {
> unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
> unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
> @@ -385,7 +119,7 @@ static void eqos_inval_buffer_tegra186(void *buf, size_t size)
> invalidate_dcache_range(start, end);
> }
>
> -static void eqos_inval_buffer_generic(void *buf, size_t size)
> +void eqos_inval_buffer_generic(void *buf, size_t size)
> {
> unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
> unsigned long end = roundup((unsigned long)buf + size,
> @@ -399,7 +133,7 @@ static void eqos_flush_buffer_tegra186(void *buf, size_t size)
> flush_cache((unsigned long)buf, size);
> }
>
> -static void eqos_flush_buffer_generic(void *buf, size_t size)
> +void eqos_flush_buffer_generic(void *buf, size_t size)
> {
> unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
> unsigned long end = roundup((unsigned long)buf + size,
> @@ -1890,7 +1624,7 @@ static int eqos_remove(struct udevice *dev)
> return 0;
> }
>
> -static int eqos_null_ops(struct udevice *dev)
> +int eqos_null_ops(struct udevice *dev)
> {
> return 0;
> }
> diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
> new file mode 100644
> index 00000000000..68b367b068a
> --- /dev/null
> +++ b/drivers/net/dwc_eth_qos.h
> @@ -0,0 +1,280 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2022 NXP
> + */
> +
> +#include <phy_interface.h>
> +#include <linux/bitops.h>
> +
> +/* Core registers */
> +
> +#define EQOS_MAC_REGS_BASE 0x000
> +struct eqos_mac_regs {
> + u32 configuration; /* 0x000 */
> + u32 unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
> + u32 q0_tx_flow_ctrl; /* 0x070 */
> + u32 unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
> + u32 rx_flow_ctrl; /* 0x090 */
> + u32 unused_094; /* 0x094 */
> + u32 txq_prty_map0; /* 0x098 */
> + u32 unused_09c; /* 0x09c */
> + u32 rxq_ctrl0; /* 0x0a0 */
> + u32 unused_0a4; /* 0x0a4 */
> + u32 rxq_ctrl2; /* 0x0a8 */
> + u32 unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
> + u32 us_tic_counter; /* 0x0dc */
> + u32 unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
> + u32 hw_feature0; /* 0x11c */
> + u32 hw_feature1; /* 0x120 */
> + u32 hw_feature2; /* 0x124 */
> + u32 unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
> + u32 mdio_address; /* 0x200 */
> + u32 mdio_data; /* 0x204 */
> + u32 unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
> + u32 address0_high; /* 0x300 */
> + u32 address0_low; /* 0x304 */
> +};
> +
> +#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
> +#define EQOS_MAC_CONFIGURATION_CST BIT(21)
> +#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
> +#define EQOS_MAC_CONFIGURATION_WD BIT(19)
> +#define EQOS_MAC_CONFIGURATION_JD BIT(17)
> +#define EQOS_MAC_CONFIGURATION_JE BIT(16)
> +#define EQOS_MAC_CONFIGURATION_PS BIT(15)
> +#define EQOS_MAC_CONFIGURATION_FES BIT(14)
> +#define EQOS_MAC_CONFIGURATION_DM BIT(13)
> +#define EQOS_MAC_CONFIGURATION_LM BIT(12)
> +#define EQOS_MAC_CONFIGURATION_TE BIT(1)
> +#define EQOS_MAC_CONFIGURATION_RE BIT(0)
> +
> +#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
> +#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
> +#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
> +
> +#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
> +
> +#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
> +#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
> +
> +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
> +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
> +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
> +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
> +#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
> +
> +#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
> +#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
> +
> +#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
> +#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
> +#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
> +#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
> +
> +#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
> +#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
> +#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
> +#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
> +
> +#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
> +#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
> +
> +#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
> +#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
> +#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
> +#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
> +#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
> +#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
> +#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
> +#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
> +#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
> +#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
> +#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
> +
> +#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
> +
> +#define EQOS_MTL_REGS_BASE 0xd00
> +struct eqos_mtl_regs {
> + u32 txq0_operation_mode; /* 0xd00 */
> + u32 unused_d04; /* 0xd04 */
> + u32 txq0_debug; /* 0xd08 */
> + u32 unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
> + u32 txq0_quantum_weight; /* 0xd18 */
> + u32 unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
> + u32 rxq0_operation_mode; /* 0xd30 */
> + u32 unused_d34; /* 0xd34 */
> + u32 rxq0_debug; /* 0xd38 */
> +};
> +
> +#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
> +#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
> +#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
> +#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
> +#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
> +#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
> +#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
> +
> +#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
> +#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
> +#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
> +
> +#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
> +#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
> +#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
> +#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
> +#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
> +#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
> +#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
> +#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
> +
> +#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
> +#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
> +#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
> +#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
> +
> +#define EQOS_DMA_REGS_BASE 0x1000
> +struct eqos_dma_regs {
> + u32 mode; /* 0x1000 */
> + u32 sysbus_mode; /* 0x1004 */
> + u32 unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
> + u32 ch0_control; /* 0x1100 */
> + u32 ch0_tx_control; /* 0x1104 */
> + u32 ch0_rx_control; /* 0x1108 */
> + u32 unused_110c; /* 0x110c */
> + u32 ch0_txdesc_list_haddress; /* 0x1110 */
> + u32 ch0_txdesc_list_address; /* 0x1114 */
> + u32 ch0_rxdesc_list_haddress; /* 0x1118 */
> + u32 ch0_rxdesc_list_address; /* 0x111c */
> + u32 ch0_txdesc_tail_pointer; /* 0x1120 */
> + u32 unused_1124; /* 0x1124 */
> + u32 ch0_rxdesc_tail_pointer; /* 0x1128 */
> + u32 ch0_txdesc_ring_length; /* 0x112c */
> + u32 ch0_rxdesc_ring_length; /* 0x1130 */
> +};
> +
> +#define EQOS_DMA_MODE_SWR BIT(0)
> +
> +#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
> +#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
> +#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
> +#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
> +#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
> +#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
> +
> +#define EQOS_DMA_CH0_CONTROL_DSL_SHIFT 18
> +#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
> +
> +#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
> +#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
> +#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
> +#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
> +
> +#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
> +#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
> +#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
> +#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
> +#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
> +
> +/* These registers are Tegra186-specific */
> +#define EQOS_TEGRA186_REGS_BASE 0x8800
> +struct eqos_tegra186_regs {
> + u32 sdmemcomppadctrl; /* 0x8800 */
> + u32 auto_cal_config; /* 0x8804 */
> + u32 unused_8808; /* 0x8808 */
> + u32 auto_cal_status; /* 0x880c */
> +};
> +
> +#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
> +
> +#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
> +#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
> +
> +#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
> +
> +/* Descriptors */
> +#define EQOS_DESCRIPTORS_TX 4
> +#define EQOS_DESCRIPTORS_RX 4
> +#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
> +#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
> +#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
> +#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
> +
> +struct eqos_desc {
> + u32 des0;
> + u32 des1;
> + u32 des2;
> + u32 des3;
> +};
> +
> +#define EQOS_DESC3_OWN BIT(31)
> +#define EQOS_DESC3_FD BIT(29)
> +#define EQOS_DESC3_LD BIT(28)
> +#define EQOS_DESC3_BUF1V BIT(24)
> +
> +#define EQOS_AXI_WIDTH_32 4
> +#define EQOS_AXI_WIDTH_64 8
> +#define EQOS_AXI_WIDTH_128 16
> +
> +struct eqos_config {
> + bool reg_access_always_ok;
> + int mdio_wait;
> + int swr_wait;
> + int config_mac;
> + int config_mac_mdio;
> + unsigned int axi_bus_width;
> + phy_interface_t (*interface)(const struct udevice *dev);
> + struct eqos_ops *ops;
> +};
> +
> +struct eqos_ops {
> + void (*eqos_inval_desc)(void *desc);
> + void (*eqos_flush_desc)(void *desc);
> + void (*eqos_inval_buffer)(void *buf, size_t size);
> + void (*eqos_flush_buffer)(void *buf, size_t size);
> + int (*eqos_probe_resources)(struct udevice *dev);
> + int (*eqos_remove_resources)(struct udevice *dev);
> + int (*eqos_stop_resets)(struct udevice *dev);
> + int (*eqos_start_resets)(struct udevice *dev);
> + int (*eqos_stop_clks)(struct udevice *dev);
> + int (*eqos_start_clks)(struct udevice *dev);
> + int (*eqos_calibrate_pads)(struct udevice *dev);
> + int (*eqos_disable_calibration)(struct udevice *dev);
> + int (*eqos_set_tx_clk_speed)(struct udevice *dev);
> + ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
> +};
> +
> +struct eqos_priv {
> + struct udevice *dev;
> + const struct eqos_config *config;
> + fdt_addr_t regs;
> + struct eqos_mac_regs *mac_regs;
> + struct eqos_mtl_regs *mtl_regs;
> + struct eqos_dma_regs *dma_regs;
> + struct eqos_tegra186_regs *tegra186_regs;
> + struct reset_ctl reset_ctl;
> + struct gpio_desc phy_reset_gpio;
> + struct clk clk_master_bus;
> + struct clk clk_rx;
> + struct clk clk_ptp_ref;
> + struct clk clk_tx;
> + struct clk clk_ck;
> + struct clk clk_slave_bus;
> + struct mii_dev *mii;
> + struct phy_device *phy;
> + u32 max_speed;
> + void *descs;
> + int tx_desc_idx, rx_desc_idx;
> + unsigned int desc_size;
> + void *tx_dma_buf;
> + void *rx_dma_buf;
> + void *rx_pkt;
> + bool started;
> + bool reg_access_ok;
> + bool clk_ck_enabled;
> +};
> +
> +void eqos_inval_desc_generic(void *desc);
> +void eqos_flush_desc_generic(void *desc);
> +void eqos_inval_buffer_generic(void *buf, size_t size);
> +void eqos_flush_buffer_generic(void *buf, size_t size);
> +int eqos_null_ops(struct udevice *dev);
> --
> 2.36.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 45/49] net: dwc_eth_qos: move i.MX code out
2022-06-27 3:24 ` [PATCH V2 45/49] net: dwc_eth_qos: move i.MX code out Peng Fan (OSS)
@ 2022-07-03 19:15 ` Ramon Fried
0 siblings, 0 replies; 61+ messages in thread
From: Ramon Fried @ 2022-07-03 19:15 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Stefano Babic, Fabio Estevam, Joe Hershberger,
U-Boot Mailing List, Peng Fan
On Mon, Jun 27, 2022 at 5:44 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> Move i.MX code to a standalone file to make it easy for adding new
> platform support
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/net/Makefile | 1 +
> drivers/net/dwc_eth_qos.c | 92 --------------------------
> drivers/net/dwc_eth_qos.h | 2 +
> drivers/net/dwc_eth_qos_imx.c | 121 ++++++++++++++++++++++++++++++++++
> 4 files changed, 124 insertions(+), 92 deletions(-)
> create mode 100644 drivers/net/dwc_eth_qos_imx.c
>
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 69fb3bbbf7c..9536af11946 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -19,6 +19,7 @@ obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
> obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
> obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
> obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
> +obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
> obj-$(CONFIG_E1000) += e1000.o
> obj-$(CONFIG_E1000_SPI) += e1000_spi.o
> obj-$(CONFIG_EEPRO100) += eepro100.o
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index b69a9feb824..1f24f5cb0cf 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -506,20 +506,6 @@ static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
> #endif
> }
>
> -__weak u32 imx_get_eqos_csr_clk(void)
> -{
> - return 100 * 1000000;
> -}
> -__weak int imx_eqos_txclk_set_rate(unsigned long rate)
> -{
> - return 0;
> -}
> -
> -static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
> -{
> - return imx_get_eqos_csr_clk();
> -}
> -
> static int eqos_set_full_duplex(struct udevice *dev)
> {
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -616,38 +602,6 @@ static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
> return 0;
> }
>
> -static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
> -{
> - struct eqos_priv *eqos = dev_get_priv(dev);
> - ulong rate;
> - int ret;
> -
> - debug("%s(dev=%p):\n", __func__, dev);
> -
> - switch (eqos->phy->speed) {
> - case SPEED_1000:
> - rate = 125 * 1000 * 1000;
> - break;
> - case SPEED_100:
> - rate = 25 * 1000 * 1000;
> - break;
> - case SPEED_10:
> - rate = 2.5 * 1000 * 1000;
> - break;
> - default:
> - pr_err("invalid speed %d", eqos->phy->speed);
> - return -EINVAL;
> - }
> -
> - ret = imx_eqos_txclk_set_rate(rate);
> - if (ret < 0) {
> - pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
> - return ret;
> - }
> -
> - return 0;
> -}
> -
> static int eqos_adjust_link(struct udevice *dev)
> {
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -1468,24 +1422,6 @@ static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev)
> return PHY_INTERFACE_MODE_MII;
> }
>
> -static int eqos_probe_resources_imx(struct udevice *dev)
> -{
> - struct eqos_priv *eqos = dev_get_priv(dev);
> - phy_interface_t interface;
> -
> - debug("%s(dev=%p):\n", __func__, dev);
> -
> - interface = eqos->config->interface(dev);
> -
> - if (interface == PHY_INTERFACE_MODE_NA) {
> - pr_err("Invalid PHY interface\n");
> - return -EINVAL;
> - }
> -
> - debug("%s: OK\n", __func__);
> - return 0;
> -}
> -
> static int eqos_remove_resources_tegra186(struct udevice *dev)
> {
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -1695,34 +1631,6 @@ static const struct eqos_config __maybe_unused eqos_stm32_config = {
> .ops = &eqos_stm32_ops
> };
>
> -static struct eqos_ops eqos_imx_ops = {
> - .eqos_inval_desc = eqos_inval_desc_generic,
> - .eqos_flush_desc = eqos_flush_desc_generic,
> - .eqos_inval_buffer = eqos_inval_buffer_generic,
> - .eqos_flush_buffer = eqos_flush_buffer_generic,
> - .eqos_probe_resources = eqos_probe_resources_imx,
> - .eqos_remove_resources = eqos_null_ops,
> - .eqos_stop_resets = eqos_null_ops,
> - .eqos_start_resets = eqos_null_ops,
> - .eqos_stop_clks = eqos_null_ops,
> - .eqos_start_clks = eqos_null_ops,
> - .eqos_calibrate_pads = eqos_null_ops,
> - .eqos_disable_calibration = eqos_null_ops,
> - .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
> - .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
> -};
> -
> -struct eqos_config __maybe_unused eqos_imx_config = {
> - .reg_access_always_ok = false,
> - .mdio_wait = 10,
> - .swr_wait = 50,
> - .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
> - .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
> - .axi_bus_width = EQOS_AXI_WIDTH_64,
> - .interface = dev_read_phy_mode,
> - .ops = &eqos_imx_ops
> -};
> -
> static const struct udevice_id eqos_ids[] = {
> #if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
> {
> diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
> index 68b367b068a..ce90e1f1ce1 100644
> --- a/drivers/net/dwc_eth_qos.h
> +++ b/drivers/net/dwc_eth_qos.h
> @@ -278,3 +278,5 @@ void eqos_flush_desc_generic(void *desc);
> void eqos_inval_buffer_generic(void *buf, size_t size);
> void eqos_flush_buffer_generic(void *buf, size_t size);
> int eqos_null_ops(struct udevice *dev);
> +
> +extern struct eqos_config eqos_imx_config;
> diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
> new file mode 100644
> index 00000000000..2d1b5104af2
> --- /dev/null
> +++ b/drivers/net/dwc_eth_qos_imx.c
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2022 NXP
> + */
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <eth_phy.h>
> +#include <log.h>
> +#include <malloc.h>
> +#include <memalign.h>
> +#include <miiphy.h>
> +#include <net.h>
> +#include <netdev.h>
> +#include <phy.h>
> +#include <reset.h>
> +#include <wait_bit.h>
> +#include <asm/arch/clock.h>
> +#include <asm/cache.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/mach-imx/sys_proto.h>
> +#include <linux/delay.h>
> +
> +#include "dwc_eth_qos.h"
> +
> +__weak u32 imx_get_eqos_csr_clk(void)
> +{
> + return 100 * 1000000;
> +}
> +
> +__weak int imx_eqos_txclk_set_rate(unsigned long rate)
> +{
> + return 0;
> +}
> +
> +static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
> +{
> + return imx_get_eqos_csr_clk();
> +}
> +
> +static int eqos_probe_resources_imx(struct udevice *dev)
> +{
> + struct eqos_priv *eqos = dev_get_priv(dev);
> + phy_interface_t interface;
> +
> + debug("%s(dev=%p):\n", __func__, dev);
> +
> + interface = eqos->config->interface(dev);
> +
> + if (interface == PHY_INTERFACE_MODE_NA) {
> + pr_err("Invalid PHY interface\n");
> + return -EINVAL;
> + }
> +
> + debug("%s: OK\n", __func__);
> + return 0;
> +}
> +
> +static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
> +{
> + struct eqos_priv *eqos = dev_get_priv(dev);
> + ulong rate;
> + int ret;
> +
> + debug("%s(dev=%p):\n", __func__, dev);
> +
> + switch (eqos->phy->speed) {
> + case SPEED_1000:
> + rate = 125 * 1000 * 1000;
> + break;
> + case SPEED_100:
> + rate = 25 * 1000 * 1000;
> + break;
> + case SPEED_10:
> + rate = 2.5 * 1000 * 1000;
> + break;
> + default:
> + pr_err("invalid speed %d", eqos->phy->speed);
> + return -EINVAL;
> + }
> +
> + ret = imx_eqos_txclk_set_rate(rate);
> + if (ret < 0) {
> + pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static struct eqos_ops eqos_imx_ops = {
> + .eqos_inval_desc = eqos_inval_desc_generic,
> + .eqos_flush_desc = eqos_flush_desc_generic,
> + .eqos_inval_buffer = eqos_inval_buffer_generic,
> + .eqos_flush_buffer = eqos_flush_buffer_generic,
> + .eqos_probe_resources = eqos_probe_resources_imx,
> + .eqos_remove_resources = eqos_null_ops,
> + .eqos_stop_resets = eqos_null_ops,
> + .eqos_start_resets = eqos_null_ops,
> + .eqos_stop_clks = eqos_null_ops,
> + .eqos_start_clks = eqos_null_ops,
> + .eqos_calibrate_pads = eqos_null_ops,
> + .eqos_disable_calibration = eqos_null_ops,
> + .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
> + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
> +};
> +
> +struct eqos_config __maybe_unused eqos_imx_config = {
> + .reg_access_always_ok = false,
> + .mdio_wait = 10,
> + .swr_wait = 50,
> + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
> + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
> + .axi_bus_width = EQOS_AXI_WIDTH_64,
> + .interface = dev_read_phy_mode,
> + .ops = &eqos_imx_ops
> +};
> --
> 2.36.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 46/49] net: eqos: add function to get phy node and address
2022-06-27 3:24 ` [PATCH V2 46/49] net: eqos: add function to get phy node and address Peng Fan (OSS)
@ 2022-07-03 19:17 ` Ramon Fried
0 siblings, 0 replies; 61+ messages in thread
From: Ramon Fried @ 2022-07-03 19:17 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Stefano Babic, Fabio Estevam, Joe Hershberger,
U-Boot Mailing List, Ye Li
On Mon, Jun 27, 2022 at 5:44 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Ye Li <ye.li@nxp.com>
>
> Since new atheros PHY driver needs to access its PHY node through
> phy device, we have to assign the phy node in ethernet controller
> driver. Otherwise the PHY driver will fail to get some nodes
> and properties.
>
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/net/dwc_eth_qos.c | 23 ++++++++++++++++++++---
> drivers/net/dwc_eth_qos.h | 1 +
> 2 files changed, 21 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index 1f24f5cb0cf..a4380d17d9c 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -719,6 +719,24 @@ static int eqos_read_rom_hwaddr(struct udevice *dev)
> return !is_valid_ethaddr(pdata->enetaddr);
> }
>
> +static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev)
> +{
> + struct ofnode_phandle_args phandle_args;
> + int reg;
> +
> + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
> + &phandle_args)) {
> + debug("Failed to find phy-handle");
> + return -ENODEV;
> + }
> +
> + priv->phy_of_node = phandle_args.node;
> +
> + reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
> +
> + return reg;
> +}
> +
> static int eqos_start(struct udevice *dev)
> {
> struct eqos_priv *eqos = dev_get_priv(dev);
> @@ -767,9 +785,7 @@ static int eqos_start(struct udevice *dev)
> */
> if (!eqos->phy) {
> int addr = -1;
> -#ifdef CONFIG_DM_ETH_PHY
> - addr = eth_phy_get_addr(dev);
> -#endif
> + addr = eqos_get_phy_addr(eqos, dev);
> #ifdef DWC_NET_PHYADDR
> addr = DWC_NET_PHYADDR;
> #endif
> @@ -788,6 +804,7 @@ static int eqos_start(struct udevice *dev)
> }
> }
>
> + eqos->phy->node = eqos->phy_of_node;
> ret = phy_config(eqos->phy);
> if (ret < 0) {
> pr_err("phy_config() failed: %d", ret);
> diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
> index ce90e1f1ce1..f470189e8d4 100644
> --- a/drivers/net/dwc_eth_qos.h
> +++ b/drivers/net/dwc_eth_qos.h
> @@ -261,6 +261,7 @@ struct eqos_priv {
> struct clk clk_slave_bus;
> struct mii_dev *mii;
> struct phy_device *phy;
> + ofnode phy_of_node;
> u32 max_speed;
> void *descs;
> int tx_desc_idx, rx_desc_idx;
> --
> 2.36.0
>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 47/49] net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr
2022-06-27 3:24 ` [PATCH V2 47/49] net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr Peng Fan (OSS)
@ 2022-07-03 19:19 ` Ramon Fried
0 siblings, 0 replies; 61+ messages in thread
From: Ramon Fried @ 2022-07-03 19:19 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Stefano Babic, Fabio Estevam, Joe Hershberger,
U-Boot Mailing List, Peng Fan
intrdouce -> introduce
On Mon, Jun 27, 2022 at 5:44 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> i.MX has specific hook to get MAC address, so introduce a hook and move
> i.MX code to its own driver
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/net/dwc_eth_qos.c | 9 ++++++---
> drivers/net/dwc_eth_qos.h | 1 +
> drivers/net/dwc_eth_qos_imx.c | 12 +++++++++++-
> 3 files changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index a4380d17d9c..c1f2391d635 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -712,10 +712,13 @@ static int eqos_write_hwaddr(struct udevice *dev)
> static int eqos_read_rom_hwaddr(struct udevice *dev)
> {
> struct eth_pdata *pdata = dev_get_plat(dev);
> + struct eqos_priv *eqos = dev_get_priv(dev);
> + int ret;
> +
> + ret = eqos->config->ops->eqos_get_enetaddr(dev);
> + if (ret < 0)
> + return ret;
>
> -#ifdef CONFIG_ARCH_IMX8M
> - imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
> -#endif
> return !is_valid_ethaddr(pdata->enetaddr);
> }
>
> diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
> index f470189e8d4..b35e7742634 100644
> --- a/drivers/net/dwc_eth_qos.h
> +++ b/drivers/net/dwc_eth_qos.h
> @@ -240,6 +240,7 @@ struct eqos_ops {
> int (*eqos_calibrate_pads)(struct udevice *dev);
> int (*eqos_disable_calibration)(struct udevice *dev);
> int (*eqos_set_tx_clk_speed)(struct udevice *dev);
> + int (*eqos_get_enetaddr)(struct udevice *dev);
> ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
> };
>
> diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
> index 2d1b5104af2..42cb164ad14 100644
> --- a/drivers/net/dwc_eth_qos_imx.c
> +++ b/drivers/net/dwc_eth_qos_imx.c
> @@ -92,6 +92,15 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
> return 0;
> }
>
> +static int eqos_get_enetaddr_imx(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> +
> + imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
> +
> + return 0;
> +}
> +
> static struct eqos_ops eqos_imx_ops = {
> .eqos_inval_desc = eqos_inval_desc_generic,
> .eqos_flush_desc = eqos_flush_desc_generic,
> @@ -106,7 +115,8 @@ static struct eqos_ops eqos_imx_ops = {
> .eqos_calibrate_pads = eqos_null_ops,
> .eqos_disable_calibration = eqos_null_ops,
> .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
> - .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
> + .eqos_get_enetaddr = eqos_get_enetaddr_imx,
> + .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx,
> };
>
> struct eqos_config __maybe_unused eqos_imx_config = {
> --
> 2.36.0
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 43/49] net: dwc_eth_qos: fix build break when CLK not enabled
2022-06-27 3:24 ` [PATCH V2 43/49] net: dwc_eth_qos: fix build break when CLK not enabled Peng Fan (OSS)
@ 2022-07-03 19:21 ` Ramon Fried
0 siblings, 0 replies; 61+ messages in thread
From: Ramon Fried @ 2022-07-03 19:21 UTC (permalink / raw)
To: Peng Fan (OSS)
Cc: Stefano Babic, Fabio Estevam, Joe Hershberger,
U-Boot Mailing List, Peng Fan
On Mon, Jun 27, 2022 at 5:44 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote:
>
> From: Peng Fan <peng.fan@nxp.com>
>
> When CONFIG_CLK is not enabled, there will be buil break:
> "error: ‘eqos’ undeclared (first use in this function)"
>
> Should not guard the eqos under CONFIG_CLK macro
>
Please rephrase - the english is a bit broken
something like:
Take eqos definition out the CONFIG_CLK ifdef.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> drivers/net/dwc_eth_qos.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index 9d255cf95ff..6048d56ff8c 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -1774,11 +1774,11 @@ static int eqos_remove_resources_tegra186(struct udevice *dev)
>
> static int eqos_remove_resources_stm32(struct udevice *dev)
> {
> -#ifdef CONFIG_CLK
> struct eqos_priv *eqos = dev_get_priv(dev);
>
> debug("%s(dev=%p):\n", __func__, dev);
>
> +#ifdef CONFIG_CLK
> clk_free(&eqos->clk_tx);
> clk_free(&eqos->clk_rx);
> clk_free(&eqos->clk_master_bus);
> --
> 2.36.0
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE
2022-06-29 10:09 ` Frieder Schrempf
@ 2022-07-05 1:35 ` Peng Fan
2022-07-05 2:08 ` Peng Fan
0 siblings, 1 reply; 61+ messages in thread
From: Peng Fan @ 2022-07-05 1:35 UTC (permalink / raw)
To: Frieder Schrempf, sbabic, festevam, Ying-Chun Liu (PaulLiu),
Jagan Teki, Matteo Lisi, Marek Vasut, Olaf Mandel, Adam Ford,
Peng Fan, Tim Harvey, Teresa Remmet, Marcel Ziswiler
Cc: u-boot
On 6/29/2022 6:09 PM, Frieder Schrempf wrote:
> Am 27.06.22 um 05:24 schrieb Peng Fan (OSS):
>> From: Peng Fan <peng.fan@nxp.com>
>>
>> The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
>> set to 0x7E1000.
>>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>> common/spl/Kconfig | 1 +
>> configs/imx8mm-cl-iot-gate-optee_defconfig | 1 -
>> configs/imx8mm-cl-iot-gate_defconfig | 1 -
>> configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
>> configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
>> configs/imx8mm-mx8menlo_defconfig | 1 -
>> configs/imx8mm_beacon_defconfig | 1 -
>> configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
>> configs/imx8mm_evk_defconfig | 1 -
>> configs/imx8mm_venice_defconfig | 1 -
>> configs/phycore-imx8mm_defconfig | 1 -
>> configs/verdin-imx8mm_defconfig | 1 -
>> 12 files changed, 1 insertion(+), 11 deletions(-)
>
> Is there any reason, why you didn't include kontron-sl-mx8mm_defconfig
> in this patch?
No specific reason. I may overlook kontron-sl-mx8mm_defconfig,
but it not matter. The reason I did this patch, is a few boards
reached its size limitation, so I enlarge to avoid build break.
keep kontron-sl-mx8mm_defconfig as 0x25000 or move to 0x27000,
both are ok. If you wanna enlarge, please do a new patch,
I not wanna respin this large patchset, unless there are some
major comments.
Thanks,
Peng.
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE
2022-07-05 1:35 ` Peng Fan
@ 2022-07-05 2:08 ` Peng Fan
2022-07-05 6:40 ` Frieder Schrempf
0 siblings, 1 reply; 61+ messages in thread
From: Peng Fan @ 2022-07-05 2:08 UTC (permalink / raw)
To: Frieder Schrempf, sbabic, festevam, Ying-Chun Liu (PaulLiu),
Jagan Teki, Matteo Lisi, Marek Vasut, Olaf Mandel, Adam Ford,
Peng Fan, tharvey, t.remmet@phytec.de, Marcel Ziswiler
Cc: u-boot
On 7/5/2022 9:35 AM, Peng Fan (OSS) wrote:
>
>
> On 6/29/2022 6:09 PM, Frieder Schrempf wrote:
>> Am 27.06.22 um 05:24 schrieb Peng Fan (OSS):
>>> From: Peng Fan <peng.fan@nxp.com>
>>>
>>> The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
>>> set to 0x7E1000.
>>>
>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>> ---
>>> common/spl/Kconfig | 1 +
>>> configs/imx8mm-cl-iot-gate-optee_defconfig | 1 -
>>> configs/imx8mm-cl-iot-gate_defconfig | 1 -
>>> configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
>>> configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
>>> configs/imx8mm-mx8menlo_defconfig | 1 -
>>> configs/imx8mm_beacon_defconfig | 1 -
>>> configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
>>> configs/imx8mm_evk_defconfig | 1 -
>>> configs/imx8mm_venice_defconfig | 1 -
>>> configs/phycore-imx8mm_defconfig | 1 -
>>> configs/verdin-imx8mm_defconfig | 1 -
>>> 12 files changed, 1 insertion(+), 11 deletions(-)
>>
>> Is there any reason, why you didn't include kontron-sl-mx8mm_defconfig
>> in this patch?
>
> No specific reason. I may overlook kontron-sl-mx8mm_defconfig,
> but it not matter. The reason I did this patch, is a few boards
> reached its size limitation, so I enlarge to avoid build break.
>
> keep kontron-sl-mx8mm_defconfig as 0x25000 or move to 0x27000,
> both are ok. If you wanna enlarge, please do a new patch,
> I not wanna respin this large patchset, unless there are some
> major comments.
Just rebase the patchset based on origin/next, and also see
a few comments from Net maintainer. Will respin this patchset,
so I will include kontron-sl-mx8mm_defconfig.
Thanks,
Peng.
>
> Thanks,
> Peng.
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE
2022-07-05 2:08 ` Peng Fan
@ 2022-07-05 6:40 ` Frieder Schrempf
0 siblings, 0 replies; 61+ messages in thread
From: Frieder Schrempf @ 2022-07-05 6:40 UTC (permalink / raw)
To: Peng Fan, sbabic, festevam, Ying-Chun Liu (PaulLiu),
Jagan Teki, Matteo Lisi, Marek Vasut, Olaf Mandel, Adam Ford,
Peng Fan, tharvey, t.remmet@phytec.de, Marcel Ziswiler
Cc: u-boot
Am 05.07.22 um 04:08 schrieb Peng Fan:
>
>
> On 7/5/2022 9:35 AM, Peng Fan (OSS) wrote:
>>
>>
>> On 6/29/2022 6:09 PM, Frieder Schrempf wrote:
>>> Am 27.06.22 um 05:24 schrieb Peng Fan (OSS):
>>>> From: Peng Fan <peng.fan@nxp.com>
>>>>
>>>> The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
>>>> set to 0x7E1000.
>>>>
>>>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>>>> ---
>>>> common/spl/Kconfig | 1 +
>>>> configs/imx8mm-cl-iot-gate-optee_defconfig | 1 -
>>>> configs/imx8mm-cl-iot-gate_defconfig | 1 -
>>>> configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
>>>> configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
>>>> configs/imx8mm-mx8menlo_defconfig | 1 -
>>>> configs/imx8mm_beacon_defconfig | 1 -
>>>> configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
>>>> configs/imx8mm_evk_defconfig | 1 -
>>>> configs/imx8mm_venice_defconfig | 1 -
>>>> configs/phycore-imx8mm_defconfig | 1 -
>>>> configs/verdin-imx8mm_defconfig | 1 -
>>>> 12 files changed, 1 insertion(+), 11 deletions(-)
>>>
>>> Is there any reason, why you didn't include kontron-sl-mx8mm_defconfig
>>> in this patch?
>>
>> No specific reason. I may overlook kontron-sl-mx8mm_defconfig,
>> but it not matter. The reason I did this patch, is a few boards
>> reached its size limitation, so I enlarge to avoid build break.
>>
>> keep kontron-sl-mx8mm_defconfig as 0x25000 or move to 0x27000,
>> both are ok. If you wanna enlarge, please do a new patch,
>> I not wanna respin this large patchset, unless there are some
>> major comments.
>
> Just rebase the patchset based on origin/next, and also see
> a few comments from Net maintainer. Will respin this patchset,
> so I will include kontron-sl-mx8mm_defconfig.
Thanks a lot, Peng!
^ permalink raw reply [flat|nested] 61+ messages in thread
end of thread, other threads:[~2022-07-05 6:40 UTC | newest]
Thread overview: 61+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-27 3:24 [PATCH V2 00/49] imx: support i.MX93 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 01/49] spl: imx8mm: enlarge SPL_MAX_SIZE Peng Fan (OSS)
2022-06-29 10:09 ` Frieder Schrempf
2022-07-05 1:35 ` Peng Fan
2022-07-05 2:08 ` Peng Fan
2022-07-05 6:40 ` Frieder Schrempf
2022-06-27 3:24 ` [PATCH V2 02/49] arm: makefile: cleanup mach-imx usage Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 03/49] imx: Change USB boot device type Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 04/49] imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 05/49] imx: simplify dependency with SPL_BOOTROM_SUPPORT Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 06/49] imx: move get_boot_device to common header Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 07/49] imx: move get_boot_device to common file Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 08/49] imx: add USB2_BOOT type Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 09/49] imx: add basic i.MX9 support Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 10/49] fsl_lpuart: add " Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 11/49] gpio: pca953x: support pcal6524 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 12/49] imx: pinctrl: add pinctrl and pinfunc file for i.MX93 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 13/49] imx: imx9: Add CCM and clock API support Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 14/49] mmc: fsl_esdhc_imx: Support i.MX9 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 15/49] spl: Use SPL_FIT_IMAGE_TINY for iMX9 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 16/49] imx: imx9: Add function to initialize timer Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 17/49] imx: imx9: disable watchdog Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 18/49] imx: imx9: support romapi Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 19/49] misc: imx: S400_API: Move S400 MU and API to a common place Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 20/49] misc: s4mu: Support iMX93 with Sentinel MU Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 21/49] misc: S400_API: Update release RDC API Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 22/49] misc: S400_API: New API for FW status and chip info Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 23/49] misc: s400_api: introduce ahab_release_m33_trout Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 24/49] imx: imx9: Add TRDC driver for TRDC init Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 25/49] imx: imx9: Add AHAB boot support Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 26/49] imx: imx9: Get the chip revision through S400 API Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 27/49] misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 28/49] misc: imx8ulp: move fuse.c from imx8ulp to sentinel Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 29/49] misc: fuse: support to access fuse on i.MX93 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 30/49] misc: fuse: update the code for accessing fuse of i.MX93 Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 31/49] imx: imx9: Add gpio registers structure Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 32/49] imx: imx9: Add MIX power init Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 33/49] imx: imx9: Add M33 release prepare function Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 34/49] imx: imx9: Support booting m33 from Acore Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 35/49] imx: imx9: Support multiple env storages at runtime Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 36/49] imx: imx9: clock: Add DDR clock support Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 37/49] ddr: imx: Add i.MX9 DDR controller driver Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 38/49] ddr: imx9: enable Performance monitor counter Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 39/49] arm: dts: Add i.MX93 SoC DTSi file Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 40/49] imx: imx93_evk: Add basic board support Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 41/49] imx: imx93_evk: Set ARM clock to 1.7Ghz Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 42/49] net: fec_mxc: support i.MX93 Peng Fan (OSS)
2022-07-03 19:13 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 43/49] net: dwc_eth_qos: fix build break when CLK not enabled Peng Fan (OSS)
2022-07-03 19:21 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 44/49] net: dwc_eth_qos: public some functions Peng Fan (OSS)
2022-07-03 19:14 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 45/49] net: dwc_eth_qos: move i.MX code out Peng Fan (OSS)
2022-07-03 19:15 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 46/49] net: eqos: add function to get phy node and address Peng Fan (OSS)
2022-07-03 19:17 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 47/49] net: dwc_eth_qos: intrdouce eqos hook eqos_get_enetaddr Peng Fan (OSS)
2022-07-03 19:19 ` Ramon Fried
2022-06-27 3:24 ` [PATCH V2 48/49] board: freescale: imx93_evk: support ethernet Peng Fan (OSS)
2022-06-27 3:24 ` [PATCH V2 49/49] tools: image: support i.MX93 Peng Fan (OSS)
2022-06-27 6:45 ` [PATCH V2 00/49] imx: " Peng Fan
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.