From: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> To: <miquel.raynal@bootlin.com>, <nagasure@xilinx.com>, <vigneshr@ti.com> Cc: <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <git@amd.com>, <richard@nod.at>, <amit.kumar-mahapatra@amd.com>, Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>, <stable@vger.kernel.org> Subject: [PATCH v3 1/2] mtd: rawnand: arasan: Update NAND bus clock instead of system clock Date: Tue, 28 Jun 2022 21:18:23 +0530 [thread overview] Message-ID: <20220628154824.12222-2-amit.kumar-mahapatra@xilinx.com> (raw) In-Reply-To: <20220628154824.12222-1-amit.kumar-mahapatra@xilinx.com> In current implementation the Arasan NAND driver is updating the system clock(i.e., anand->clk) in accordance to the timing modes (i.e., SDR or NVDDR). But as per the Arasan NAND controller spec the flash clock or the NAND bus clock(i.e., nfc->bus_clk), need to be updated instead. This patch keeps the system clock unchanged and updates the NAND bus clock as per the timing modes. Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller") CC: stable@vger.kernel.org # 5.8+ Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> --- drivers/mtd/nand/raw/arasan-nand-controller.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index 53bd10738418..c5264fa223c4 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -347,17 +347,17 @@ static int anfc_select_target(struct nand_chip *chip, int target) /* Update clock frequency */ if (nfc->cur_clk != anand->clk) { - clk_disable_unprepare(nfc->controller_clk); - ret = clk_set_rate(nfc->controller_clk, anand->clk); + clk_disable_unprepare(nfc->bus_clk); + ret = clk_set_rate(nfc->bus_clk, anand->clk); if (ret) { dev_err(nfc->dev, "Failed to change clock rate\n"); return ret; } - ret = clk_prepare_enable(nfc->controller_clk); + ret = clk_prepare_enable(nfc->bus_clk); if (ret) { dev_err(nfc->dev, - "Failed to re-enable the controller clock\n"); + "Failed to re-enable the bus clock\n"); return ret; } -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> To: <miquel.raynal@bootlin.com>, <nagasure@xilinx.com>, <vigneshr@ti.com> Cc: <boris.brezillon@collabora.com>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>, <git@amd.com>, <richard@nod.at>, <amit.kumar-mahapatra@amd.com>, Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>, <stable@vger.kernel.org> Subject: [PATCH v3 1/2] mtd: rawnand: arasan: Update NAND bus clock instead of system clock Date: Tue, 28 Jun 2022 21:18:23 +0530 [thread overview] Message-ID: <20220628154824.12222-2-amit.kumar-mahapatra@xilinx.com> (raw) In-Reply-To: <20220628154824.12222-1-amit.kumar-mahapatra@xilinx.com> In current implementation the Arasan NAND driver is updating the system clock(i.e., anand->clk) in accordance to the timing modes (i.e., SDR or NVDDR). But as per the Arasan NAND controller spec the flash clock or the NAND bus clock(i.e., nfc->bus_clk), need to be updated instead. This patch keeps the system clock unchanged and updates the NAND bus clock as per the timing modes. Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller") CC: stable@vger.kernel.org # 5.8+ Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> --- drivers/mtd/nand/raw/arasan-nand-controller.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index 53bd10738418..c5264fa223c4 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -347,17 +347,17 @@ static int anfc_select_target(struct nand_chip *chip, int target) /* Update clock frequency */ if (nfc->cur_clk != anand->clk) { - clk_disable_unprepare(nfc->controller_clk); - ret = clk_set_rate(nfc->controller_clk, anand->clk); + clk_disable_unprepare(nfc->bus_clk); + ret = clk_set_rate(nfc->bus_clk, anand->clk); if (ret) { dev_err(nfc->dev, "Failed to change clock rate\n"); return ret; } - ret = clk_prepare_enable(nfc->controller_clk); + ret = clk_prepare_enable(nfc->bus_clk); if (ret) { dev_err(nfc->dev, - "Failed to re-enable the controller clock\n"); + "Failed to re-enable the bus clock\n"); return ret; } -- 2.17.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2022-06-28 15:48 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-28 15:48 [PATCH v3 0/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR Amit Kumar Mahapatra 2022-06-28 15:48 ` Amit Kumar Mahapatra 2022-06-28 15:48 ` Amit Kumar Mahapatra [this message] 2022-06-28 15:48 ` [PATCH v3 1/2] mtd: rawnand: arasan: Update NAND bus clock instead of system clock Amit Kumar Mahapatra 2022-06-29 11:38 ` Miquel Raynal 2022-06-29 11:38 ` Miquel Raynal 2022-06-28 15:48 ` [PATCH v3 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR Amit Kumar Mahapatra 2022-06-28 15:48 ` Amit Kumar Mahapatra 2022-06-29 11:38 ` Miquel Raynal 2022-06-29 11:38 ` Miquel Raynal
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