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From: Guillaume Ranquet <granquet@baylibre.com>
To: Vinod Koul <vkoul@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Daniel Vetter <daniel@ffwll.ch>,
	Chunfeng Yun <chunfeng.yun@mediatek.com>,
	CK Hu <ck.hu@mediatek.com>, Jitao shi <jitao.shi@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-mediatek@lists.infradead.org,
	dri-devel@lists.freedesktop.org,
	Pablo Sun <pablo.sun@mediatek.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Mattijs Korpershoek <mkorpershoek@baylibre.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-phy@lists.infradead.org,
	Guillaume Ranquet <granquet@baylibre.com>,
	devicetree@vger.kernel.org
Subject: [PATCH v1 05/17] drm/mediatek: hdmi: use a syscon/regmap instead of iomem
Date: Mon, 19 Sep 2022 18:56:03 +0200	[thread overview]
Message-ID: <20220919-v1-5-4844816c9808@baylibre.com> (raw)
In-Reply-To: <20220919-v1-0-4844816c9808@baylibre.com>

To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, move to a syscon.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 3196189429bc..5cd05d4fe1a9 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -172,7 +172,7 @@ struct mtk_hdmi {
 	u32 ibias_up;
 	struct regmap *sys_regmap;
 	unsigned int sys_offset;
-	void __iomem *regs;
+	struct regmap *regs;
 	enum hdmi_colorspace csp;
 	struct hdmi_audio_param aud_param;
 	bool audio_enable;
@@ -188,44 +188,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 	return container_of(b, struct mtk_hdmi, bridge);
 }
 
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
+static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val)
 {
-	return readl(hdmi->regs + offset);
+	return regmap_read(hdmi->regs, offset, val);
 }
 
 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
 {
-	writel(val, hdmi->regs + offset);
+	regmap_write(hdmi->regs, offset, val);
 }
 
 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp &= ~bits;
-	writel(tmp, reg);
+	regmap_clear_bits(hdmi->regs, offset, bits);
 }
 
 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp |= bits;
-	writel(tmp, reg);
+	regmap_set_bits(hdmi->regs, offset, bits);
 }
 
 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp = (tmp & ~mask) | (val & mask);
-	writel(tmp, reg);
+	regmap_update_bits(hdmi->regs, offset, mask, val);
 }
 
 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
@@ -474,7 +459,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG0);
+	mtk_hdmi_read(hdmi, GRL_CFG0, &val);
 	val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 
 	switch (i2s_fmt) {
@@ -566,7 +551,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG1);
+	mtk_hdmi_read(hdmi, GRL_CFG1, &val);
 	if (input_type == HDMI_AUD_INPUT_I2S &&
 	    (val & CFG1_SPDIF) == CFG1_SPDIF) {
 		val &= ~CFG1_SPDIF;
@@ -597,7 +582,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
 	if (val & MIX_CTRL_SRC_EN) {
 		val &= ~MIX_CTRL_SRC_EN;
 		mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
@@ -611,7 +596,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
 	val &= ~MIX_CTRL_SRC_EN;
 	mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 	mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
@@ -622,7 +607,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG5);
+	mtk_hdmi_read(hdmi, GRL_CFG5, &val);
 	val &= CFG5_CD_RATIO_MASK;
 
 	switch (mclk) {
@@ -1428,7 +1413,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	struct device_node *cec_np, *remote, *i2c_np;
 	struct platform_device *cec_pdev;
 	struct regmap *regmap;
-	struct resource *mem;
 	int ret;
 
 	ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1474,8 +1458,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	}
 	hdmi->sys_regmap = regmap;
 
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	hdmi->regs = devm_ioremap_resource(dev, mem);
+	hdmi->regs = syscon_node_to_regmap(dev->of_node);
 	if (IS_ERR(hdmi->regs)) {
 		ret = PTR_ERR(hdmi->regs);
 		goto put_device;

-- 
b4 0.10.0-dev

WARNING: multiple messages have this Message-ID (diff)
From: Guillaume Ranquet <granquet@baylibre.com>
To: Vinod Koul <vkoul@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	David Airlie <airlied@linux.ie>,
	 Rob Herring <robh+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Daniel Vetter <daniel@ffwll.ch>,
	 Chunfeng Yun <chunfeng.yun@mediatek.com>,
	CK Hu <ck.hu@mediatek.com>, Jitao shi <jitao.shi@mediatek.com>,
	 Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	 Kishon Vijay Abraham I <kishon@ti.com>,
	Matthias Brugger <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org,
	Guillaume Ranquet <granquet@baylibre.com>,
	Mattijs Korpershoek <mkorpershoek@baylibre.com>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-phy@lists.infradead.org, Pablo Sun <pablo.sun@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 05/17] drm/mediatek: hdmi: use a syscon/regmap instead of iomem
Date: Mon, 19 Sep 2022 18:56:03 +0200	[thread overview]
Message-ID: <20220919-v1-5-4844816c9808@baylibre.com> (raw)
In-Reply-To: <20220919-v1-0-4844816c9808@baylibre.com>

To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, move to a syscon.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 3196189429bc..5cd05d4fe1a9 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -172,7 +172,7 @@ struct mtk_hdmi {
 	u32 ibias_up;
 	struct regmap *sys_regmap;
 	unsigned int sys_offset;
-	void __iomem *regs;
+	struct regmap *regs;
 	enum hdmi_colorspace csp;
 	struct hdmi_audio_param aud_param;
 	bool audio_enable;
@@ -188,44 +188,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 	return container_of(b, struct mtk_hdmi, bridge);
 }
 
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
+static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val)
 {
-	return readl(hdmi->regs + offset);
+	return regmap_read(hdmi->regs, offset, val);
 }
 
 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
 {
-	writel(val, hdmi->regs + offset);
+	regmap_write(hdmi->regs, offset, val);
 }
 
 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp &= ~bits;
-	writel(tmp, reg);
+	regmap_clear_bits(hdmi->regs, offset, bits);
 }
 
 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp |= bits;
-	writel(tmp, reg);
+	regmap_set_bits(hdmi->regs, offset, bits);
 }
 
 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp = (tmp & ~mask) | (val & mask);
-	writel(tmp, reg);
+	regmap_update_bits(hdmi->regs, offset, mask, val);
 }
 
 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
@@ -474,7 +459,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG0);
+	mtk_hdmi_read(hdmi, GRL_CFG0, &val);
 	val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 
 	switch (i2s_fmt) {
@@ -566,7 +551,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG1);
+	mtk_hdmi_read(hdmi, GRL_CFG1, &val);
 	if (input_type == HDMI_AUD_INPUT_I2S &&
 	    (val & CFG1_SPDIF) == CFG1_SPDIF) {
 		val &= ~CFG1_SPDIF;
@@ -597,7 +582,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
 	if (val & MIX_CTRL_SRC_EN) {
 		val &= ~MIX_CTRL_SRC_EN;
 		mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
@@ -611,7 +596,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
 	val &= ~MIX_CTRL_SRC_EN;
 	mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 	mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
@@ -622,7 +607,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG5);
+	mtk_hdmi_read(hdmi, GRL_CFG5, &val);
 	val &= CFG5_CD_RATIO_MASK;
 
 	switch (mclk) {
@@ -1428,7 +1413,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	struct device_node *cec_np, *remote, *i2c_np;
 	struct platform_device *cec_pdev;
 	struct regmap *regmap;
-	struct resource *mem;
 	int ret;
 
 	ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1474,8 +1458,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	}
 	hdmi->sys_regmap = regmap;
 
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	hdmi->regs = devm_ioremap_resource(dev, mem);
+	hdmi->regs = syscon_node_to_regmap(dev->of_node);
 	if (IS_ERR(hdmi->regs)) {
 		ret = PTR_ERR(hdmi->regs);
 		goto put_device;

-- 
b4 0.10.0-dev

WARNING: multiple messages have this Message-ID (diff)
From: Guillaume Ranquet <granquet@baylibre.com>
To: Vinod Koul <vkoul@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Daniel Vetter <daniel@ffwll.ch>,
	Chunfeng Yun <chunfeng.yun@mediatek.com>,
	CK Hu <ck.hu@mediatek.com>, Jitao shi <jitao.shi@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-mediatek@lists.infradead.org,
	dri-devel@lists.freedesktop.org,
	Pablo Sun <pablo.sun@mediatek.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Mattijs Korpershoek <mkorpershoek@baylibre.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-phy@lists.infradead.org,
	Guillaume Ranquet <granquet@baylibre.com>,
	devicetree@vger.kernel.org
Subject: [PATCH v1 05/17] drm/mediatek: hdmi: use a syscon/regmap instead of iomem
Date: Mon, 19 Sep 2022 18:56:03 +0200	[thread overview]
Message-ID: <20220919-v1-5-4844816c9808@baylibre.com> (raw)
In-Reply-To: <20220919-v1-0-4844816c9808@baylibre.com>

To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, move to a syscon.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 3196189429bc..5cd05d4fe1a9 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -172,7 +172,7 @@ struct mtk_hdmi {
 	u32 ibias_up;
 	struct regmap *sys_regmap;
 	unsigned int sys_offset;
-	void __iomem *regs;
+	struct regmap *regs;
 	enum hdmi_colorspace csp;
 	struct hdmi_audio_param aud_param;
 	bool audio_enable;
@@ -188,44 +188,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 	return container_of(b, struct mtk_hdmi, bridge);
 }
 
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
+static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val)
 {
-	return readl(hdmi->regs + offset);
+	return regmap_read(hdmi->regs, offset, val);
 }
 
 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
 {
-	writel(val, hdmi->regs + offset);
+	regmap_write(hdmi->regs, offset, val);
 }
 
 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp &= ~bits;
-	writel(tmp, reg);
+	regmap_clear_bits(hdmi->regs, offset, bits);
 }
 
 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp |= bits;
-	writel(tmp, reg);
+	regmap_set_bits(hdmi->regs, offset, bits);
 }
 
 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp = (tmp & ~mask) | (val & mask);
-	writel(tmp, reg);
+	regmap_update_bits(hdmi->regs, offset, mask, val);
 }
 
 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
@@ -474,7 +459,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG0);
+	mtk_hdmi_read(hdmi, GRL_CFG0, &val);
 	val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 
 	switch (i2s_fmt) {
@@ -566,7 +551,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG1);
+	mtk_hdmi_read(hdmi, GRL_CFG1, &val);
 	if (input_type == HDMI_AUD_INPUT_I2S &&
 	    (val & CFG1_SPDIF) == CFG1_SPDIF) {
 		val &= ~CFG1_SPDIF;
@@ -597,7 +582,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
 	if (val & MIX_CTRL_SRC_EN) {
 		val &= ~MIX_CTRL_SRC_EN;
 		mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
@@ -611,7 +596,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
 	val &= ~MIX_CTRL_SRC_EN;
 	mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 	mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
@@ -622,7 +607,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG5);
+	mtk_hdmi_read(hdmi, GRL_CFG5, &val);
 	val &= CFG5_CD_RATIO_MASK;
 
 	switch (mclk) {
@@ -1428,7 +1413,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	struct device_node *cec_np, *remote, *i2c_np;
 	struct platform_device *cec_pdev;
 	struct regmap *regmap;
-	struct resource *mem;
 	int ret;
 
 	ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1474,8 +1458,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	}
 	hdmi->sys_regmap = regmap;
 
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	hdmi->regs = devm_ioremap_resource(dev, mem);
+	hdmi->regs = syscon_node_to_regmap(dev->of_node);
 	if (IS_ERR(hdmi->regs)) {
 		ret = PTR_ERR(hdmi->regs);
 		goto put_device;

-- 
b4 0.10.0-dev

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Guillaume Ranquet <granquet@baylibre.com>
To: Vinod Koul <vkoul@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Daniel Vetter <daniel@ffwll.ch>,
	Chunfeng Yun <chunfeng.yun@mediatek.com>,
	CK Hu <ck.hu@mediatek.com>, Jitao shi <jitao.shi@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-mediatek@lists.infradead.org,
	dri-devel@lists.freedesktop.org,
	Pablo Sun <pablo.sun@mediatek.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Mattijs Korpershoek <mkorpershoek@baylibre.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-phy@lists.infradead.org,
	Guillaume Ranquet <granquet@baylibre.com>,
	devicetree@vger.kernel.org
Subject: [PATCH v1 05/17] drm/mediatek: hdmi: use a syscon/regmap instead of iomem
Date: Mon, 19 Sep 2022 18:56:03 +0200	[thread overview]
Message-ID: <20220919-v1-5-4844816c9808@baylibre.com> (raw)
In-Reply-To: <20220919-v1-0-4844816c9808@baylibre.com>

To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, move to a syscon.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 3196189429bc..5cd05d4fe1a9 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -172,7 +172,7 @@ struct mtk_hdmi {
 	u32 ibias_up;
 	struct regmap *sys_regmap;
 	unsigned int sys_offset;
-	void __iomem *regs;
+	struct regmap *regs;
 	enum hdmi_colorspace csp;
 	struct hdmi_audio_param aud_param;
 	bool audio_enable;
@@ -188,44 +188,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 	return container_of(b, struct mtk_hdmi, bridge);
 }
 
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
+static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val)
 {
-	return readl(hdmi->regs + offset);
+	return regmap_read(hdmi->regs, offset, val);
 }
 
 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
 {
-	writel(val, hdmi->regs + offset);
+	regmap_write(hdmi->regs, offset, val);
 }
 
 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp &= ~bits;
-	writel(tmp, reg);
+	regmap_clear_bits(hdmi->regs, offset, bits);
 }
 
 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp |= bits;
-	writel(tmp, reg);
+	regmap_set_bits(hdmi->regs, offset, bits);
 }
 
 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
 {
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp = (tmp & ~mask) | (val & mask);
-	writel(tmp, reg);
+	regmap_update_bits(hdmi->regs, offset, mask, val);
 }
 
 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
@@ -474,7 +459,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG0);
+	mtk_hdmi_read(hdmi, GRL_CFG0, &val);
 	val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 
 	switch (i2s_fmt) {
@@ -566,7 +551,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG1);
+	mtk_hdmi_read(hdmi, GRL_CFG1, &val);
 	if (input_type == HDMI_AUD_INPUT_I2S &&
 	    (val & CFG1_SPDIF) == CFG1_SPDIF) {
 		val &= ~CFG1_SPDIF;
@@ -597,7 +582,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
 	if (val & MIX_CTRL_SRC_EN) {
 		val &= ~MIX_CTRL_SRC_EN;
 		mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
@@ -611,7 +596,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
 	val &= ~MIX_CTRL_SRC_EN;
 	mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
 	mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
@@ -622,7 +607,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG5);
+	mtk_hdmi_read(hdmi, GRL_CFG5, &val);
 	val &= CFG5_CD_RATIO_MASK;
 
 	switch (mclk) {
@@ -1428,7 +1413,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	struct device_node *cec_np, *remote, *i2c_np;
 	struct platform_device *cec_pdev;
 	struct regmap *regmap;
-	struct resource *mem;
 	int ret;
 
 	ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1474,8 +1458,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	}
 	hdmi->sys_regmap = regmap;
 
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	hdmi->regs = devm_ioremap_resource(dev, mem);
+	hdmi->regs = syscon_node_to_regmap(dev->of_node);
 	if (IS_ERR(hdmi->regs)) {
 		ret = PTR_ERR(hdmi->regs);
 		goto put_device;

-- 
b4 0.10.0-dev

-- 
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  parent reply	other threads:[~2022-09-19 17:00 UTC|newest]

Thread overview: 280+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-19 16:55 [PATCH v1 00/17] Add MT8195 HDMI support Guillaume Ranquet
2022-09-19 16:55 ` Guillaume Ranquet
2022-09-19 16:55 ` Guillaume Ranquet
2022-09-19 16:55 ` Guillaume Ranquet
2022-09-19 16:55 ` [PATCH v1 01/17] dt-bindings: clk: mediatek: Add MT8195 DPI clocks Guillaume Ranquet
2022-09-19 16:55   ` Guillaume Ranquet
2022-09-19 16:55   ` Guillaume Ranquet
2022-09-19 16:55   ` Guillaume Ranquet
2022-09-21  2:48   ` Bo-Chen Chen
2022-09-21  2:48     ` Bo-Chen Chen
2022-09-21  2:48     ` Bo-Chen Chen
2022-09-21  2:48     ` Bo-Chen Chen
2022-09-22  7:11   ` Krzysztof Kozlowski
2022-09-22  7:11     ` Krzysztof Kozlowski
2022-09-22  7:11     ` Krzysztof Kozlowski
2022-09-22  7:11     ` Krzysztof Kozlowski
2022-09-22 12:45     ` Guillaume Ranquet
2022-09-22 12:45       ` Guillaume Ranquet
2022-09-22 12:45       ` Guillaume Ranquet
2022-09-22 12:45       ` Guillaume Ranquet
2022-09-22 12:51       ` Krzysztof Kozlowski
2022-09-22 12:51         ` Krzysztof Kozlowski
2022-09-22 12:51         ` Krzysztof Kozlowski
2022-09-22 12:51         ` Krzysztof Kozlowski
2022-09-22 19:31         ` Konstantin Ryabitsev
2022-09-22 19:31           ` Konstantin Ryabitsev
2022-09-22 19:31           ` Konstantin Ryabitsev
2022-09-22 19:31           ` Konstantin Ryabitsev
2022-09-22 12:51   ` Krzysztof Kozlowski
2022-09-22 12:51     ` Krzysztof Kozlowski
2022-09-22 12:51     ` Krzysztof Kozlowski
2022-09-22 12:51     ` Krzysztof Kozlowski
2022-09-19 16:56 ` [PATCH v1 02/17] clk: mediatek: add VDOSYS1 clock Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-26  5:09   ` Chen-Yu Tsai
2022-09-26  5:09     ` Chen-Yu Tsai
2022-09-26  5:09     ` Chen-Yu Tsai
2022-09-26  5:09     ` Chen-Yu Tsai
2022-09-26  5:35     ` Chen-Yu Tsai
2022-09-26  5:35       ` Chen-Yu Tsai
2022-09-26  5:35       ` Chen-Yu Tsai
2022-09-26  5:35       ` Chen-Yu Tsai
2022-09-19 16:56 ` [PATCH v1 03/17] dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-22  7:12   ` Krzysztof Kozlowski
2022-09-22  7:12     ` Krzysztof Kozlowski
2022-09-22  7:12     ` Krzysztof Kozlowski
2022-09-22  7:12     ` Krzysztof Kozlowski
2022-09-22 12:52   ` Krzysztof Kozlowski
2022-09-22 12:52     ` Krzysztof Kozlowski
2022-09-22 12:52     ` Krzysztof Kozlowski
2022-09-22 12:52     ` Krzysztof Kozlowski
2022-09-19 16:56 ` [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-22  7:18   ` Krzysztof Kozlowski
2022-09-22  7:18     ` Krzysztof Kozlowski
2022-09-22  7:18     ` Krzysztof Kozlowski
2022-09-22  7:18     ` Krzysztof Kozlowski
2022-09-27 13:54     ` Guillaume Ranquet
2022-09-27 13:54       ` Guillaume Ranquet
2022-09-27 13:54       ` Guillaume Ranquet
2022-09-27 13:54       ` Guillaume Ranquet
2022-09-27 14:31       ` Krzysztof Kozlowski
2022-09-27 14:31         ` Krzysztof Kozlowski
2022-09-27 14:31         ` Krzysztof Kozlowski
2022-09-27 14:31         ` Krzysztof Kozlowski
2022-09-19 16:56 ` Guillaume Ranquet [this message]
2022-09-19 16:56   ` [PATCH v1 05/17] drm/mediatek: hdmi: use a syscon/regmap instead of iomem Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:18   ` AngeloGioacchino Del Regno
2022-09-20 10:18     ` AngeloGioacchino Del Regno
2022-09-20 10:18     ` AngeloGioacchino Del Regno
2022-09-20 10:18     ` AngeloGioacchino Del Regno
2022-09-27 13:06     ` Guillaume Ranquet
2022-09-27 13:06       ` Guillaume Ranquet
2022-09-27 13:06       ` Guillaume Ranquet
2022-09-27 13:06       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 06/17] dt-bindings: mediatek: set the hdmi to be compatible with syscon Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:19   ` AngeloGioacchino Del Regno
2022-09-20 10:19     ` AngeloGioacchino Del Regno
2022-09-20 10:19     ` AngeloGioacchino Del Regno
2022-09-20 10:19     ` AngeloGioacchino Del Regno
2022-09-22  7:19   ` Krzysztof Kozlowski
2022-09-22  7:19     ` Krzysztof Kozlowski
2022-09-22  7:19     ` Krzysztof Kozlowski
2022-09-22  7:19     ` Krzysztof Kozlowski
2022-09-27 14:03     ` Guillaume Ranquet
2022-09-27 14:03       ` Guillaume Ranquet
2022-09-27 14:03       ` Guillaume Ranquet
2022-09-27 14:03       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 07/17] drm/mediatek: extract common functions from the mtk hdmi driver Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:25   ` AngeloGioacchino Del Regno
2022-09-20 10:25     ` AngeloGioacchino Del Regno
2022-09-20 10:25     ` AngeloGioacchino Del Regno
2022-09-20 10:25     ` AngeloGioacchino Del Regno
2022-09-27 13:08     ` Guillaume Ranquet
2022-09-27 13:08       ` Guillaume Ranquet
2022-09-27 13:08       ` Guillaume Ranquet
2022-09-27 13:08       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 08/17] drm/mediatek: hdmi: add cec flag Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:34   ` AngeloGioacchino Del Regno
2022-09-20 10:34     ` AngeloGioacchino Del Regno
2022-09-20 10:34     ` AngeloGioacchino Del Regno
2022-09-20 10:34     ` AngeloGioacchino Del Regno
2022-09-19 16:56 ` [PATCH v1 09/17] drm/mediatek: hdmi: add connector flag Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:38   ` AngeloGioacchino Del Regno
2022-09-20 10:38     ` AngeloGioacchino Del Regno
2022-09-20 10:38     ` AngeloGioacchino Del Regno
2022-09-20 10:38     ` AngeloGioacchino Del Regno
2022-10-03 15:39     ` Guillaume Ranquet
2022-10-03 15:39       ` Guillaume Ranquet
2022-10-03 15:39       ` Guillaume Ranquet
2022-10-03 15:39       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 10/17] drm/mediatek: hdmi: add frame_colorimetry flag Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 11/17] drm/mediatek: hdmi: add mt8195 support Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 11:04   ` AngeloGioacchino Del Regno
2022-09-20 11:04     ` AngeloGioacchino Del Regno
2022-09-20 11:04     ` AngeloGioacchino Del Regno
2022-09-20 11:04     ` AngeloGioacchino Del Regno
2022-10-14 13:54     ` Guillaume Ranquet
2022-10-14 13:54       ` Guillaume Ranquet
2022-10-14 13:54       ` Guillaume Ranquet
2022-10-14 13:54       ` Guillaume Ranquet
2022-09-22  7:24   ` Krzysztof Kozlowski
2022-09-22  7:24     ` Krzysztof Kozlowski
2022-09-22  7:24     ` Krzysztof Kozlowski
2022-09-22  7:24     ` Krzysztof Kozlowski
2022-09-19 16:56 ` [PATCH v1 12/17] drm/mediatek: hdmi: mt8195: add audio support Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 11:11   ` AngeloGioacchino Del Regno
2022-09-20 11:11     ` AngeloGioacchino Del Regno
2022-09-20 11:11     ` AngeloGioacchino Del Regno
2022-09-20 11:11     ` AngeloGioacchino Del Regno
2022-09-27 13:13     ` Guillaume Ranquet
2022-09-27 13:13       ` Guillaume Ranquet
2022-09-27 13:13       ` Guillaume Ranquet
2022-09-27 13:13       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 13/17] phy: phy-mtk-hdmi: Add generic phy configure callback Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 11:41   ` AngeloGioacchino Del Regno
2022-09-20 11:41     ` AngeloGioacchino Del Regno
2022-09-20 11:41     ` AngeloGioacchino Del Regno
2022-09-20 11:41     ` AngeloGioacchino Del Regno
2022-09-19 16:56 ` [PATCH v1 14/17] phy: mediatek: add support for phy-mtk-hdmi-mt8195 Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20  7:46   ` Chunfeng Yun
2022-09-20  7:46     ` Chunfeng Yun
2022-09-20  7:46     ` Chunfeng Yun
2022-09-20  7:46     ` Chunfeng Yun
2022-09-27 13:23     ` Guillaume Ranquet
2022-09-27 13:23       ` Guillaume Ranquet
2022-09-27 13:23       ` Guillaume Ranquet
2022-09-27 13:23       ` Guillaume Ranquet
2022-09-28  2:40       ` Chunfeng Yun
2022-09-28  2:40         ` Chunfeng Yun
2022-09-28  2:40         ` Chunfeng Yun
2022-09-28  2:40         ` Chunfeng Yun
2022-09-28 12:23         ` Guillaume Ranquet
2022-09-28 12:23           ` Guillaume Ranquet
2022-09-28 12:23           ` Guillaume Ranquet
2022-09-28 12:23           ` Guillaume Ranquet
2022-09-20 12:17   ` AngeloGioacchino Del Regno
2022-09-20 12:17     ` AngeloGioacchino Del Regno
2022-09-20 12:17     ` AngeloGioacchino Del Regno
2022-09-20 12:17     ` AngeloGioacchino Del Regno
2022-09-27 13:18     ` Guillaume Ranquet
2022-09-27 13:18       ` Guillaume Ranquet
2022-09-27 13:18       ` Guillaume Ranquet
2022-09-27 13:18       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 15/17] dt-bindings: display: mediatek: dpi: Add compatible for MediaTek MT8195 Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-22  7:20   ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-26  5:24     ` Chen-Yu Tsai
2022-09-26  5:24       ` Chen-Yu Tsai
2022-09-26  5:24       ` Chen-Yu Tsai
2022-09-26  5:24       ` Chen-Yu Tsai
2022-09-26  6:38       ` Krzysztof Kozlowski
2022-09-26  6:38         ` Krzysztof Kozlowski
2022-09-26  6:38         ` Krzysztof Kozlowski
2022-09-26  6:38         ` Krzysztof Kozlowski
2022-09-19 16:56 ` [PATCH v1 16/17] drm/mediatek: dpi: Add mt8195 hdmi to DPI driver Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 12:22   ` AngeloGioacchino Del Regno
2022-09-20 12:22     ` AngeloGioacchino Del Regno
2022-09-20 12:22     ` AngeloGioacchino Del Regno
2022-09-20 12:22     ` AngeloGioacchino Del Regno
2022-09-27 13:34     ` Guillaume Ranquet
2022-09-27 13:34       ` Guillaume Ranquet
2022-09-27 13:34       ` Guillaume Ranquet
2022-09-27 13:34       ` Guillaume Ranquet
2022-09-28 13:09       ` AngeloGioacchino Del Regno
2022-09-28 13:09         ` AngeloGioacchino Del Regno
2022-09-28 13:09         ` AngeloGioacchino Del Regno
2022-09-28 13:09         ` AngeloGioacchino Del Regno
2022-09-22  7:22   ` Krzysztof Kozlowski
2022-09-22  7:22     ` Krzysztof Kozlowski
2022-09-22  7:22     ` Krzysztof Kozlowski
2022-09-22  7:22     ` Krzysztof Kozlowski
2022-09-27 13:38     ` Guillaume Ranquet
2022-09-27 13:38       ` Guillaume Ranquet
2022-09-27 13:38       ` Guillaume Ranquet
2022-09-27 13:38       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 17/17] drm/mediatek: Add mt8195-dpi support to drm_drv Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-22  7:20   ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-27 13:04     ` Guillaume Ranquet
2022-09-27 13:04       ` Guillaume Ranquet
2022-09-27 13:04       ` Guillaume Ranquet
2022-09-27 13:04       ` Guillaume Ranquet
2022-09-27 14:28       ` Krzysztof Kozlowski
2022-09-27 14:28         ` Krzysztof Kozlowski
2022-09-27 14:28         ` Krzysztof Kozlowski
2022-09-27 14:28         ` Krzysztof Kozlowski
2022-10-03 15:29         ` Guillaume Ranquet
2022-10-03 15:29           ` Guillaume Ranquet
2022-10-03 15:29           ` Guillaume Ranquet
2022-10-03 15:29           ` Guillaume Ranquet
2022-10-04 10:49           ` Krzysztof Kozlowski
2022-10-04 10:49             ` Krzysztof Kozlowski
2022-10-04 10:49             ` Krzysztof Kozlowski
2022-10-04 10:49             ` Krzysztof Kozlowski
2022-10-04 11:55             ` Guillaume Ranquet
2022-10-04 11:55               ` Guillaume Ranquet
2022-10-04 11:55               ` Guillaume Ranquet
2022-10-04 11:55               ` Guillaume Ranquet
2022-10-04 15:05               ` Krzysztof Kozlowski
2022-10-04 15:05                 ` Krzysztof Kozlowski
2022-10-04 15:05                 ` Krzysztof Kozlowski
2022-10-04 15:05                 ` Krzysztof Kozlowski
2022-10-05  9:34                 ` Guillaume Ranquet
2022-10-05  9:34                   ` Guillaume Ranquet
2022-10-05  9:34                   ` Guillaume Ranquet
2022-10-05  9:34                   ` Guillaume Ranquet
2022-10-05 14:53                   ` Krzysztof Kozlowski
2022-10-05 14:53                     ` Krzysztof Kozlowski
2022-10-05 14:53                     ` Krzysztof Kozlowski
2022-10-05 14:53                     ` Krzysztof Kozlowski

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