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From: Guillaume Ranquet <granquet@baylibre.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Vinod Koul <vkoul@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Daniel Vetter <daniel@ffwll.ch>,
	Chunfeng Yun <chunfeng.yun@mediatek.com>,
	CK Hu <ck.hu@mediatek.com>, Jitao shi <jitao.shi@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>
Cc: linux-mediatek@lists.infradead.org,
	dri-devel@lists.freedesktop.org,
	Pablo Sun <pablo.sun@mediatek.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Mattijs Korpershoek <mkorpershoek@baylibre.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-phy@lists.infradead.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings
Date: Tue, 27 Sep 2022 06:54:33 -0700	[thread overview]
Message-ID: <CABnWg9vifOaAgwr7tkELUqbQA_1f-FfMFZ9o7sjZCaneo_FUmw@mail.gmail.com> (raw)
In-Reply-To: <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org>

On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>On 19/09/2022 18:56, Guillaume Ranquet wrote:
>> Add mt8195 SoC bindings for hdmi and hdmi-ddc
>>
>> Make port1 optional for mt8195 as it only supports HDMI tx for now.
>> Requires a ddc-i2c-bus phandle.
>> Requires a power-domains phandle.
>>
>> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
>>
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> index bdaf0b51e68c..abb231a0694b 100644
>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> @@ -21,6 +21,10 @@ properties:
>>        - mediatek,mt7623-hdmi
>>        - mediatek,mt8167-hdmi
>>        - mediatek,mt8173-hdmi
>> +      - mediatek,mt8195-hdmi
>> +
>> +  clocks: true
>> +  clock-names: true
>
>????
>Why is this moved?
>
>>
>>    reg:
>>      maxItems: 1
>> @@ -28,20 +32,6 @@ properties:
>>    interrupts:
>>      maxItems: 1
>>
>> -  clocks:
>> -    items:
>> -      - description: Pixel Clock
>> -      - description: HDMI PLL
>> -      - description: Bit Clock
>> -      - description: S/PDIF Clock
>> -
>> -  clock-names:
>> -    items:
>> -      - const: pixel
>> -      - const: pll
>> -      - const: bclk
>> -      - const: spdif
>
>Clock definition with constraints should stay here. You just customize
>it per variant.
>
Clocks are different between the two hardwares, so I've tried moving everything
inside the if/else block.

Is there a better way to express this?

>> -
>>    phys:
>>      maxItems: 1
>>
>> @@ -58,6 +48,16 @@ properties:
>>      description: |
>>        phandle link and register offset to the system configuration registers.
>>
>> +  ddc-i2c-bus:
>> +    $ref: '/schemas/types.yaml#/definitions/phandle'
>
>Drop quotes
>
>> +    description: Phandle to the ddc-i2c device
>
>Isn't this property of panel?
>
It's a property used in panels and connectors.
But since this IP doesn't use a connector per say, I've added the property here.

Which doesn't sound reasonnable when I'm explaining it like this...
I'll see what I can do to fit a connector and have things look a bit
more standard.

>> +
>> +  power-domains:
>> +    description:
>> +      A phandle and PM domain specifier as defined by bindings
>> +      of the power controller specified by phandle. See
>> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
>
>No need for this text. This is standard property. You miss maxItems.
>
>
>> +
>>    ports:
>>      $ref: /schemas/graph.yaml#/properties/ports
>>
>> @@ -76,7 +76,6 @@ properties:
>>
>>      required:
>>        - port@0
>> -      - port@1
>>
>>  required:
>>    - compatible
>> @@ -86,9 +85,55 @@ required:
>>    - clock-names
>>    - phys
>>    - phy-names
>> -  - mediatek,syscon-hdmi
>>    - ports
>>
>> +allOf:
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: mediatek,mt8195-hdmi
>> +    then:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: APB
>> +            - description: HDCP
>> +            - description: HDCP 24M
>> +            - description: Split HDMI
>> +        clock-names:
>> +          items:
>> +            - const: hdmi_apb_sel
>> +            - const: hdcp_sel
>> +            - const: hdcp24_sel
>> +            - const: split_hdmi
>
>Clocks are entirely different. I am not sure there is benefit in keeping
>these devices in one bindings.
>

I agree with that, but it was requested by CK that the driver and bindings be
as common as possible.

>> +
>> +      required:
>> +        - power-domains
>> +        - ddc-i2c-bus
>
>Blank line,
>
>> +    else:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: Pixel Clock
>> +            - description: HDMI PLL
>> +            - description: Bit Clock
>> +            - description: S/PDIF Clock
>> +
>> +        clock-names:
>> +          items:
>> +            - const: pixel
>> +            - const: pll
>> +            - const: bclk
>> +            - const: spdif
>> +
>> +        ports:
>> +          required:
>> +            - port@1
>> +
>> +      required:
>> +        - mediatek,syscon-hdmi
>> +
>>  additionalProperties: false
>>
>>  examples:
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
>> new file mode 100644
>> index 000000000000..3c80bcebe6d3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
>> @@ -0,0 +1,45 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Mediatek HDMI DDC Device Tree Bindings for mt8195
>
>Drop Device Tree Bindings
>
>> +
>> +maintainers:
>> +  - CK Hu <ck.hu@mediatek.com>
>> +  - Jitao shi <jitao.shi@mediatek.com>
>> +
>> +description: |
>> +  The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
>
>Why is this different than existing ddc bindings?
>
This ddc is actually part of the MT8195 hdmi IP.

So it is a bit simpler than the mediatek,hdmi-ddc.yaml
As it has only one clock, no reg, no interrupts.

>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - mediatek,mt8195-hdmi-ddc
>> +
>> +  clocks:
>> +    maxItems: 1
>> +
>> +  clock-names:
>> +    items:
>> +      - const: ddc-i2c
>> +
>> +required:
>> +  - compatible
>> +  - clocks
>> +  - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +    hdmiddc0: ddc_i2c {
>
>No underscores in node names. Generic node names.
>
>
>Best regards,
>Krzysztof
>

WARNING: multiple messages have this Message-ID (diff)
From: Guillaume Ranquet <granquet@baylibre.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	 Matthias Brugger <matthias.bgg@gmail.com>,
	Vinod Koul <vkoul@kernel.org>,  Stephen Boyd <sboyd@kernel.org>,
	David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Daniel Vetter <daniel@ffwll.ch>,
	 Chunfeng Yun <chunfeng.yun@mediatek.com>,
	CK Hu <ck.hu@mediatek.com>,  Jitao shi <jitao.shi@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	 Michael Turquette <mturquette@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org,
	Mattijs Korpershoek <mkorpershoek@baylibre.com>,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-phy@lists.infradead.org, Pablo Sun <pablo.sun@mediatek.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings
Date: Tue, 27 Sep 2022 06:54:33 -0700	[thread overview]
Message-ID: <CABnWg9vifOaAgwr7tkELUqbQA_1f-FfMFZ9o7sjZCaneo_FUmw@mail.gmail.com> (raw)
In-Reply-To: <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org>

On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>On 19/09/2022 18:56, Guillaume Ranquet wrote:
>> Add mt8195 SoC bindings for hdmi and hdmi-ddc
>>
>> Make port1 optional for mt8195 as it only supports HDMI tx for now.
>> Requires a ddc-i2c-bus phandle.
>> Requires a power-domains phandle.
>>
>> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
>>
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> index bdaf0b51e68c..abb231a0694b 100644
>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> @@ -21,6 +21,10 @@ properties:
>>        - mediatek,mt7623-hdmi
>>        - mediatek,mt8167-hdmi
>>        - mediatek,mt8173-hdmi
>> +      - mediatek,mt8195-hdmi
>> +
>> +  clocks: true
>> +  clock-names: true
>
>????
>Why is this moved?
>
>>
>>    reg:
>>      maxItems: 1
>> @@ -28,20 +32,6 @@ properties:
>>    interrupts:
>>      maxItems: 1
>>
>> -  clocks:
>> -    items:
>> -      - description: Pixel Clock
>> -      - description: HDMI PLL
>> -      - description: Bit Clock
>> -      - description: S/PDIF Clock
>> -
>> -  clock-names:
>> -    items:
>> -      - const: pixel
>> -      - const: pll
>> -      - const: bclk
>> -      - const: spdif
>
>Clock definition with constraints should stay here. You just customize
>it per variant.
>
Clocks are different between the two hardwares, so I've tried moving everything
inside the if/else block.

Is there a better way to express this?

>> -
>>    phys:
>>      maxItems: 1
>>
>> @@ -58,6 +48,16 @@ properties:
>>      description: |
>>        phandle link and register offset to the system configuration registers.
>>
>> +  ddc-i2c-bus:
>> +    $ref: '/schemas/types.yaml#/definitions/phandle'
>
>Drop quotes
>
>> +    description: Phandle to the ddc-i2c device
>
>Isn't this property of panel?
>
It's a property used in panels and connectors.
But since this IP doesn't use a connector per say, I've added the property here.

Which doesn't sound reasonnable when I'm explaining it like this...
I'll see what I can do to fit a connector and have things look a bit
more standard.

>> +
>> +  power-domains:
>> +    description:
>> +      A phandle and PM domain specifier as defined by bindings
>> +      of the power controller specified by phandle. See
>> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
>
>No need for this text. This is standard property. You miss maxItems.
>
>
>> +
>>    ports:
>>      $ref: /schemas/graph.yaml#/properties/ports
>>
>> @@ -76,7 +76,6 @@ properties:
>>
>>      required:
>>        - port@0
>> -      - port@1
>>
>>  required:
>>    - compatible
>> @@ -86,9 +85,55 @@ required:
>>    - clock-names
>>    - phys
>>    - phy-names
>> -  - mediatek,syscon-hdmi
>>    - ports
>>
>> +allOf:
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: mediatek,mt8195-hdmi
>> +    then:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: APB
>> +            - description: HDCP
>> +            - description: HDCP 24M
>> +            - description: Split HDMI
>> +        clock-names:
>> +          items:
>> +            - const: hdmi_apb_sel
>> +            - const: hdcp_sel
>> +            - const: hdcp24_sel
>> +            - const: split_hdmi
>
>Clocks are entirely different. I am not sure there is benefit in keeping
>these devices in one bindings.
>

I agree with that, but it was requested by CK that the driver and bindings be
as common as possible.

>> +
>> +      required:
>> +        - power-domains
>> +        - ddc-i2c-bus
>
>Blank line,
>
>> +    else:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: Pixel Clock
>> +            - description: HDMI PLL
>> +            - description: Bit Clock
>> +            - description: S/PDIF Clock
>> +
>> +        clock-names:
>> +          items:
>> +            - const: pixel
>> +            - const: pll
>> +            - const: bclk
>> +            - const: spdif
>> +
>> +        ports:
>> +          required:
>> +            - port@1
>> +
>> +      required:
>> +        - mediatek,syscon-hdmi
>> +
>>  additionalProperties: false
>>
>>  examples:
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
>> new file mode 100644
>> index 000000000000..3c80bcebe6d3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
>> @@ -0,0 +1,45 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Mediatek HDMI DDC Device Tree Bindings for mt8195
>
>Drop Device Tree Bindings
>
>> +
>> +maintainers:
>> +  - CK Hu <ck.hu@mediatek.com>
>> +  - Jitao shi <jitao.shi@mediatek.com>
>> +
>> +description: |
>> +  The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
>
>Why is this different than existing ddc bindings?
>
This ddc is actually part of the MT8195 hdmi IP.

So it is a bit simpler than the mediatek,hdmi-ddc.yaml
As it has only one clock, no reg, no interrupts.

>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - mediatek,mt8195-hdmi-ddc
>> +
>> +  clocks:
>> +    maxItems: 1
>> +
>> +  clock-names:
>> +    items:
>> +      - const: ddc-i2c
>> +
>> +required:
>> +  - compatible
>> +  - clocks
>> +  - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +    hdmiddc0: ddc_i2c {
>
>No underscores in node names. Generic node names.
>
>
>Best regards,
>Krzysztof
>

WARNING: multiple messages have this Message-ID (diff)
From: Guillaume Ranquet <granquet@baylibre.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	 Matthias Brugger <matthias.bgg@gmail.com>,
	Vinod Koul <vkoul@kernel.org>,  Stephen Boyd <sboyd@kernel.org>,
	David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
	 Philipp Zabel <p.zabel@pengutronix.de>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Daniel Vetter <daniel@ffwll.ch>,
	 Chunfeng Yun <chunfeng.yun@mediatek.com>,
	CK Hu <ck.hu@mediatek.com>,  Jitao shi <jitao.shi@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	 Michael Turquette <mturquette@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>
Cc: linux-mediatek@lists.infradead.org,
	dri-devel@lists.freedesktop.org,
	 Pablo Sun <pablo.sun@mediatek.com>,
	linux-clk@vger.kernel.org,  linux-kernel@vger.kernel.org,
	Mattijs Korpershoek <mkorpershoek@baylibre.com>,
	 linux-arm-kernel@lists.infradead.org,
	linux-phy@lists.infradead.org,  devicetree@vger.kernel.org
Subject: Re: [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings
Date: Tue, 27 Sep 2022 06:54:33 -0700	[thread overview]
Message-ID: <CABnWg9vifOaAgwr7tkELUqbQA_1f-FfMFZ9o7sjZCaneo_FUmw@mail.gmail.com> (raw)
In-Reply-To: <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org>

On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>On 19/09/2022 18:56, Guillaume Ranquet wrote:
>> Add mt8195 SoC bindings for hdmi and hdmi-ddc
>>
>> Make port1 optional for mt8195 as it only supports HDMI tx for now.
>> Requires a ddc-i2c-bus phandle.
>> Requires a power-domains phandle.
>>
>> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
>>
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> index bdaf0b51e68c..abb231a0694b 100644
>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> @@ -21,6 +21,10 @@ properties:
>>        - mediatek,mt7623-hdmi
>>        - mediatek,mt8167-hdmi
>>        - mediatek,mt8173-hdmi
>> +      - mediatek,mt8195-hdmi
>> +
>> +  clocks: true
>> +  clock-names: true
>
>????
>Why is this moved?
>
>>
>>    reg:
>>      maxItems: 1
>> @@ -28,20 +32,6 @@ properties:
>>    interrupts:
>>      maxItems: 1
>>
>> -  clocks:
>> -    items:
>> -      - description: Pixel Clock
>> -      - description: HDMI PLL
>> -      - description: Bit Clock
>> -      - description: S/PDIF Clock
>> -
>> -  clock-names:
>> -    items:
>> -      - const: pixel
>> -      - const: pll
>> -      - const: bclk
>> -      - const: spdif
>
>Clock definition with constraints should stay here. You just customize
>it per variant.
>
Clocks are different between the two hardwares, so I've tried moving everything
inside the if/else block.

Is there a better way to express this?

>> -
>>    phys:
>>      maxItems: 1
>>
>> @@ -58,6 +48,16 @@ properties:
>>      description: |
>>        phandle link and register offset to the system configuration registers.
>>
>> +  ddc-i2c-bus:
>> +    $ref: '/schemas/types.yaml#/definitions/phandle'
>
>Drop quotes
>
>> +    description: Phandle to the ddc-i2c device
>
>Isn't this property of panel?
>
It's a property used in panels and connectors.
But since this IP doesn't use a connector per say, I've added the property here.

Which doesn't sound reasonnable when I'm explaining it like this...
I'll see what I can do to fit a connector and have things look a bit
more standard.

>> +
>> +  power-domains:
>> +    description:
>> +      A phandle and PM domain specifier as defined by bindings
>> +      of the power controller specified by phandle. See
>> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
>
>No need for this text. This is standard property. You miss maxItems.
>
>
>> +
>>    ports:
>>      $ref: /schemas/graph.yaml#/properties/ports
>>
>> @@ -76,7 +76,6 @@ properties:
>>
>>      required:
>>        - port@0
>> -      - port@1
>>
>>  required:
>>    - compatible
>> @@ -86,9 +85,55 @@ required:
>>    - clock-names
>>    - phys
>>    - phy-names
>> -  - mediatek,syscon-hdmi
>>    - ports
>>
>> +allOf:
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: mediatek,mt8195-hdmi
>> +    then:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: APB
>> +            - description: HDCP
>> +            - description: HDCP 24M
>> +            - description: Split HDMI
>> +        clock-names:
>> +          items:
>> +            - const: hdmi_apb_sel
>> +            - const: hdcp_sel
>> +            - const: hdcp24_sel
>> +            - const: split_hdmi
>
>Clocks are entirely different. I am not sure there is benefit in keeping
>these devices in one bindings.
>

I agree with that, but it was requested by CK that the driver and bindings be
as common as possible.

>> +
>> +      required:
>> +        - power-domains
>> +        - ddc-i2c-bus
>
>Blank line,
>
>> +    else:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: Pixel Clock
>> +            - description: HDMI PLL
>> +            - description: Bit Clock
>> +            - description: S/PDIF Clock
>> +
>> +        clock-names:
>> +          items:
>> +            - const: pixel
>> +            - const: pll
>> +            - const: bclk
>> +            - const: spdif
>> +
>> +        ports:
>> +          required:
>> +            - port@1
>> +
>> +      required:
>> +        - mediatek,syscon-hdmi
>> +
>>  additionalProperties: false
>>
>>  examples:
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
>> new file mode 100644
>> index 000000000000..3c80bcebe6d3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
>> @@ -0,0 +1,45 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Mediatek HDMI DDC Device Tree Bindings for mt8195
>
>Drop Device Tree Bindings
>
>> +
>> +maintainers:
>> +  - CK Hu <ck.hu@mediatek.com>
>> +  - Jitao shi <jitao.shi@mediatek.com>
>> +
>> +description: |
>> +  The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
>
>Why is this different than existing ddc bindings?
>
This ddc is actually part of the MT8195 hdmi IP.

So it is a bit simpler than the mediatek,hdmi-ddc.yaml
As it has only one clock, no reg, no interrupts.

>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - mediatek,mt8195-hdmi-ddc
>> +
>> +  clocks:
>> +    maxItems: 1
>> +
>> +  clock-names:
>> +    items:
>> +      - const: ddc-i2c
>> +
>> +required:
>> +  - compatible
>> +  - clocks
>> +  - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +    hdmiddc0: ddc_i2c {
>
>No underscores in node names. Generic node names.
>
>
>Best regards,
>Krzysztof
>

-- 
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linux-phy@lists.infradead.org
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WARNING: multiple messages have this Message-ID (diff)
From: Guillaume Ranquet <granquet@baylibre.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	 Matthias Brugger <matthias.bgg@gmail.com>,
	Vinod Koul <vkoul@kernel.org>,  Stephen Boyd <sboyd@kernel.org>,
	David Airlie <airlied@linux.ie>, Rob Herring <robh+dt@kernel.org>,
	 Philipp Zabel <p.zabel@pengutronix.de>,
	 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Daniel Vetter <daniel@ffwll.ch>,
	 Chunfeng Yun <chunfeng.yun@mediatek.com>,
	CK Hu <ck.hu@mediatek.com>,  Jitao shi <jitao.shi@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	 Michael Turquette <mturquette@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>
Cc: linux-mediatek@lists.infradead.org,
	dri-devel@lists.freedesktop.org,
	 Pablo Sun <pablo.sun@mediatek.com>,
	linux-clk@vger.kernel.org,  linux-kernel@vger.kernel.org,
	Mattijs Korpershoek <mkorpershoek@baylibre.com>,
	 linux-arm-kernel@lists.infradead.org,
	linux-phy@lists.infradead.org,  devicetree@vger.kernel.org
Subject: Re: [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings
Date: Tue, 27 Sep 2022 06:54:33 -0700	[thread overview]
Message-ID: <CABnWg9vifOaAgwr7tkELUqbQA_1f-FfMFZ9o7sjZCaneo_FUmw@mail.gmail.com> (raw)
In-Reply-To: <260bb17f-efc8-1287-3e03-f9b8e79a6e31@linaro.org>

On Thu, 22 Sep 2022 09:18, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>On 19/09/2022 18:56, Guillaume Ranquet wrote:
>> Add mt8195 SoC bindings for hdmi and hdmi-ddc
>>
>> Make port1 optional for mt8195 as it only supports HDMI tx for now.
>> Requires a ddc-i2c-bus phandle.
>> Requires a power-domains phandle.
>>
>> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
>>
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> index bdaf0b51e68c..abb231a0694b 100644
>> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>> @@ -21,6 +21,10 @@ properties:
>>        - mediatek,mt7623-hdmi
>>        - mediatek,mt8167-hdmi
>>        - mediatek,mt8173-hdmi
>> +      - mediatek,mt8195-hdmi
>> +
>> +  clocks: true
>> +  clock-names: true
>
>????
>Why is this moved?
>
>>
>>    reg:
>>      maxItems: 1
>> @@ -28,20 +32,6 @@ properties:
>>    interrupts:
>>      maxItems: 1
>>
>> -  clocks:
>> -    items:
>> -      - description: Pixel Clock
>> -      - description: HDMI PLL
>> -      - description: Bit Clock
>> -      - description: S/PDIF Clock
>> -
>> -  clock-names:
>> -    items:
>> -      - const: pixel
>> -      - const: pll
>> -      - const: bclk
>> -      - const: spdif
>
>Clock definition with constraints should stay here. You just customize
>it per variant.
>
Clocks are different between the two hardwares, so I've tried moving everything
inside the if/else block.

Is there a better way to express this?

>> -
>>    phys:
>>      maxItems: 1
>>
>> @@ -58,6 +48,16 @@ properties:
>>      description: |
>>        phandle link and register offset to the system configuration registers.
>>
>> +  ddc-i2c-bus:
>> +    $ref: '/schemas/types.yaml#/definitions/phandle'
>
>Drop quotes
>
>> +    description: Phandle to the ddc-i2c device
>
>Isn't this property of panel?
>
It's a property used in panels and connectors.
But since this IP doesn't use a connector per say, I've added the property here.

Which doesn't sound reasonnable when I'm explaining it like this...
I'll see what I can do to fit a connector and have things look a bit
more standard.

>> +
>> +  power-domains:
>> +    description:
>> +      A phandle and PM domain specifier as defined by bindings
>> +      of the power controller specified by phandle. See
>> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
>
>No need for this text. This is standard property. You miss maxItems.
>
>
>> +
>>    ports:
>>      $ref: /schemas/graph.yaml#/properties/ports
>>
>> @@ -76,7 +76,6 @@ properties:
>>
>>      required:
>>        - port@0
>> -      - port@1
>>
>>  required:
>>    - compatible
>> @@ -86,9 +85,55 @@ required:
>>    - clock-names
>>    - phys
>>    - phy-names
>> -  - mediatek,syscon-hdmi
>>    - ports
>>
>> +allOf:
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: mediatek,mt8195-hdmi
>> +    then:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: APB
>> +            - description: HDCP
>> +            - description: HDCP 24M
>> +            - description: Split HDMI
>> +        clock-names:
>> +          items:
>> +            - const: hdmi_apb_sel
>> +            - const: hdcp_sel
>> +            - const: hdcp24_sel
>> +            - const: split_hdmi
>
>Clocks are entirely different. I am not sure there is benefit in keeping
>these devices in one bindings.
>

I agree with that, but it was requested by CK that the driver and bindings be
as common as possible.

>> +
>> +      required:
>> +        - power-domains
>> +        - ddc-i2c-bus
>
>Blank line,
>
>> +    else:
>> +      properties:
>> +        clocks:
>> +          items:
>> +            - description: Pixel Clock
>> +            - description: HDMI PLL
>> +            - description: Bit Clock
>> +            - description: S/PDIF Clock
>> +
>> +        clock-names:
>> +          items:
>> +            - const: pixel
>> +            - const: pll
>> +            - const: bclk
>> +            - const: spdif
>> +
>> +        ports:
>> +          required:
>> +            - port@1
>> +
>> +      required:
>> +        - mediatek,syscon-hdmi
>> +
>>  additionalProperties: false
>>
>>  examples:
>> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
>> new file mode 100644
>> index 000000000000..3c80bcebe6d3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
>> @@ -0,0 +1,45 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Mediatek HDMI DDC Device Tree Bindings for mt8195
>
>Drop Device Tree Bindings
>
>> +
>> +maintainers:
>> +  - CK Hu <ck.hu@mediatek.com>
>> +  - Jitao shi <jitao.shi@mediatek.com>
>> +
>> +description: |
>> +  The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
>
>Why is this different than existing ddc bindings?
>
This ddc is actually part of the MT8195 hdmi IP.

So it is a bit simpler than the mediatek,hdmi-ddc.yaml
As it has only one clock, no reg, no interrupts.

>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - mediatek,mt8195-hdmi-ddc
>> +
>> +  clocks:
>> +    maxItems: 1
>> +
>> +  clock-names:
>> +    items:
>> +      - const: ddc-i2c
>> +
>> +required:
>> +  - compatible
>> +  - clocks
>> +  - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +    hdmiddc0: ddc_i2c {
>
>No underscores in node names. Generic node names.
>
>
>Best regards,
>Krzysztof
>

_______________________________________________
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  reply	other threads:[~2022-09-27 13:54 UTC|newest]

Thread overview: 280+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-19 16:55 [PATCH v1 00/17] Add MT8195 HDMI support Guillaume Ranquet
2022-09-19 16:55 ` Guillaume Ranquet
2022-09-19 16:55 ` Guillaume Ranquet
2022-09-19 16:55 ` Guillaume Ranquet
2022-09-19 16:55 ` [PATCH v1 01/17] dt-bindings: clk: mediatek: Add MT8195 DPI clocks Guillaume Ranquet
2022-09-19 16:55   ` Guillaume Ranquet
2022-09-19 16:55   ` Guillaume Ranquet
2022-09-19 16:55   ` Guillaume Ranquet
2022-09-21  2:48   ` Bo-Chen Chen
2022-09-21  2:48     ` Bo-Chen Chen
2022-09-21  2:48     ` Bo-Chen Chen
2022-09-21  2:48     ` Bo-Chen Chen
2022-09-22  7:11   ` Krzysztof Kozlowski
2022-09-22  7:11     ` Krzysztof Kozlowski
2022-09-22  7:11     ` Krzysztof Kozlowski
2022-09-22  7:11     ` Krzysztof Kozlowski
2022-09-22 12:45     ` Guillaume Ranquet
2022-09-22 12:45       ` Guillaume Ranquet
2022-09-22 12:45       ` Guillaume Ranquet
2022-09-22 12:45       ` Guillaume Ranquet
2022-09-22 12:51       ` Krzysztof Kozlowski
2022-09-22 12:51         ` Krzysztof Kozlowski
2022-09-22 12:51         ` Krzysztof Kozlowski
2022-09-22 12:51         ` Krzysztof Kozlowski
2022-09-22 19:31         ` Konstantin Ryabitsev
2022-09-22 19:31           ` Konstantin Ryabitsev
2022-09-22 19:31           ` Konstantin Ryabitsev
2022-09-22 19:31           ` Konstantin Ryabitsev
2022-09-22 12:51   ` Krzysztof Kozlowski
2022-09-22 12:51     ` Krzysztof Kozlowski
2022-09-22 12:51     ` Krzysztof Kozlowski
2022-09-22 12:51     ` Krzysztof Kozlowski
2022-09-19 16:56 ` [PATCH v1 02/17] clk: mediatek: add VDOSYS1 clock Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-26  5:09   ` Chen-Yu Tsai
2022-09-26  5:09     ` Chen-Yu Tsai
2022-09-26  5:09     ` Chen-Yu Tsai
2022-09-26  5:09     ` Chen-Yu Tsai
2022-09-26  5:35     ` Chen-Yu Tsai
2022-09-26  5:35       ` Chen-Yu Tsai
2022-09-26  5:35       ` Chen-Yu Tsai
2022-09-26  5:35       ` Chen-Yu Tsai
2022-09-19 16:56 ` [PATCH v1 03/17] dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-22  7:12   ` Krzysztof Kozlowski
2022-09-22  7:12     ` Krzysztof Kozlowski
2022-09-22  7:12     ` Krzysztof Kozlowski
2022-09-22  7:12     ` Krzysztof Kozlowski
2022-09-22 12:52   ` Krzysztof Kozlowski
2022-09-22 12:52     ` Krzysztof Kozlowski
2022-09-22 12:52     ` Krzysztof Kozlowski
2022-09-22 12:52     ` Krzysztof Kozlowski
2022-09-19 16:56 ` [PATCH v1 04/17] dt-bindings: display: mediatek: add MT8195 hdmi bindings Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-22  7:18   ` Krzysztof Kozlowski
2022-09-22  7:18     ` Krzysztof Kozlowski
2022-09-22  7:18     ` Krzysztof Kozlowski
2022-09-22  7:18     ` Krzysztof Kozlowski
2022-09-27 13:54     ` Guillaume Ranquet [this message]
2022-09-27 13:54       ` Guillaume Ranquet
2022-09-27 13:54       ` Guillaume Ranquet
2022-09-27 13:54       ` Guillaume Ranquet
2022-09-27 14:31       ` Krzysztof Kozlowski
2022-09-27 14:31         ` Krzysztof Kozlowski
2022-09-27 14:31         ` Krzysztof Kozlowski
2022-09-27 14:31         ` Krzysztof Kozlowski
2022-09-19 16:56 ` [PATCH v1 05/17] drm/mediatek: hdmi: use a syscon/regmap instead of iomem Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:18   ` AngeloGioacchino Del Regno
2022-09-20 10:18     ` AngeloGioacchino Del Regno
2022-09-20 10:18     ` AngeloGioacchino Del Regno
2022-09-20 10:18     ` AngeloGioacchino Del Regno
2022-09-27 13:06     ` Guillaume Ranquet
2022-09-27 13:06       ` Guillaume Ranquet
2022-09-27 13:06       ` Guillaume Ranquet
2022-09-27 13:06       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 06/17] dt-bindings: mediatek: set the hdmi to be compatible with syscon Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:19   ` AngeloGioacchino Del Regno
2022-09-20 10:19     ` AngeloGioacchino Del Regno
2022-09-20 10:19     ` AngeloGioacchino Del Regno
2022-09-20 10:19     ` AngeloGioacchino Del Regno
2022-09-22  7:19   ` Krzysztof Kozlowski
2022-09-22  7:19     ` Krzysztof Kozlowski
2022-09-22  7:19     ` Krzysztof Kozlowski
2022-09-22  7:19     ` Krzysztof Kozlowski
2022-09-27 14:03     ` Guillaume Ranquet
2022-09-27 14:03       ` Guillaume Ranquet
2022-09-27 14:03       ` Guillaume Ranquet
2022-09-27 14:03       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 07/17] drm/mediatek: extract common functions from the mtk hdmi driver Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:25   ` AngeloGioacchino Del Regno
2022-09-20 10:25     ` AngeloGioacchino Del Regno
2022-09-20 10:25     ` AngeloGioacchino Del Regno
2022-09-20 10:25     ` AngeloGioacchino Del Regno
2022-09-27 13:08     ` Guillaume Ranquet
2022-09-27 13:08       ` Guillaume Ranquet
2022-09-27 13:08       ` Guillaume Ranquet
2022-09-27 13:08       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 08/17] drm/mediatek: hdmi: add cec flag Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:34   ` AngeloGioacchino Del Regno
2022-09-20 10:34     ` AngeloGioacchino Del Regno
2022-09-20 10:34     ` AngeloGioacchino Del Regno
2022-09-20 10:34     ` AngeloGioacchino Del Regno
2022-09-19 16:56 ` [PATCH v1 09/17] drm/mediatek: hdmi: add connector flag Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 10:38   ` AngeloGioacchino Del Regno
2022-09-20 10:38     ` AngeloGioacchino Del Regno
2022-09-20 10:38     ` AngeloGioacchino Del Regno
2022-09-20 10:38     ` AngeloGioacchino Del Regno
2022-10-03 15:39     ` Guillaume Ranquet
2022-10-03 15:39       ` Guillaume Ranquet
2022-10-03 15:39       ` Guillaume Ranquet
2022-10-03 15:39       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 10/17] drm/mediatek: hdmi: add frame_colorimetry flag Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 11/17] drm/mediatek: hdmi: add mt8195 support Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 11:04   ` AngeloGioacchino Del Regno
2022-09-20 11:04     ` AngeloGioacchino Del Regno
2022-09-20 11:04     ` AngeloGioacchino Del Regno
2022-09-20 11:04     ` AngeloGioacchino Del Regno
2022-10-14 13:54     ` Guillaume Ranquet
2022-10-14 13:54       ` Guillaume Ranquet
2022-10-14 13:54       ` Guillaume Ranquet
2022-10-14 13:54       ` Guillaume Ranquet
2022-09-22  7:24   ` Krzysztof Kozlowski
2022-09-22  7:24     ` Krzysztof Kozlowski
2022-09-22  7:24     ` Krzysztof Kozlowski
2022-09-22  7:24     ` Krzysztof Kozlowski
2022-09-19 16:56 ` [PATCH v1 12/17] drm/mediatek: hdmi: mt8195: add audio support Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 11:11   ` AngeloGioacchino Del Regno
2022-09-20 11:11     ` AngeloGioacchino Del Regno
2022-09-20 11:11     ` AngeloGioacchino Del Regno
2022-09-20 11:11     ` AngeloGioacchino Del Regno
2022-09-27 13:13     ` Guillaume Ranquet
2022-09-27 13:13       ` Guillaume Ranquet
2022-09-27 13:13       ` Guillaume Ranquet
2022-09-27 13:13       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 13/17] phy: phy-mtk-hdmi: Add generic phy configure callback Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 11:41   ` AngeloGioacchino Del Regno
2022-09-20 11:41     ` AngeloGioacchino Del Regno
2022-09-20 11:41     ` AngeloGioacchino Del Regno
2022-09-20 11:41     ` AngeloGioacchino Del Regno
2022-09-19 16:56 ` [PATCH v1 14/17] phy: mediatek: add support for phy-mtk-hdmi-mt8195 Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20  7:46   ` Chunfeng Yun
2022-09-20  7:46     ` Chunfeng Yun
2022-09-20  7:46     ` Chunfeng Yun
2022-09-20  7:46     ` Chunfeng Yun
2022-09-27 13:23     ` Guillaume Ranquet
2022-09-27 13:23       ` Guillaume Ranquet
2022-09-27 13:23       ` Guillaume Ranquet
2022-09-27 13:23       ` Guillaume Ranquet
2022-09-28  2:40       ` Chunfeng Yun
2022-09-28  2:40         ` Chunfeng Yun
2022-09-28  2:40         ` Chunfeng Yun
2022-09-28  2:40         ` Chunfeng Yun
2022-09-28 12:23         ` Guillaume Ranquet
2022-09-28 12:23           ` Guillaume Ranquet
2022-09-28 12:23           ` Guillaume Ranquet
2022-09-28 12:23           ` Guillaume Ranquet
2022-09-20 12:17   ` AngeloGioacchino Del Regno
2022-09-20 12:17     ` AngeloGioacchino Del Regno
2022-09-20 12:17     ` AngeloGioacchino Del Regno
2022-09-20 12:17     ` AngeloGioacchino Del Regno
2022-09-27 13:18     ` Guillaume Ranquet
2022-09-27 13:18       ` Guillaume Ranquet
2022-09-27 13:18       ` Guillaume Ranquet
2022-09-27 13:18       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 15/17] dt-bindings: display: mediatek: dpi: Add compatible for MediaTek MT8195 Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-22  7:20   ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-26  5:24     ` Chen-Yu Tsai
2022-09-26  5:24       ` Chen-Yu Tsai
2022-09-26  5:24       ` Chen-Yu Tsai
2022-09-26  5:24       ` Chen-Yu Tsai
2022-09-26  6:38       ` Krzysztof Kozlowski
2022-09-26  6:38         ` Krzysztof Kozlowski
2022-09-26  6:38         ` Krzysztof Kozlowski
2022-09-26  6:38         ` Krzysztof Kozlowski
2022-09-19 16:56 ` [PATCH v1 16/17] drm/mediatek: dpi: Add mt8195 hdmi to DPI driver Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-20 12:22   ` AngeloGioacchino Del Regno
2022-09-20 12:22     ` AngeloGioacchino Del Regno
2022-09-20 12:22     ` AngeloGioacchino Del Regno
2022-09-20 12:22     ` AngeloGioacchino Del Regno
2022-09-27 13:34     ` Guillaume Ranquet
2022-09-27 13:34       ` Guillaume Ranquet
2022-09-27 13:34       ` Guillaume Ranquet
2022-09-27 13:34       ` Guillaume Ranquet
2022-09-28 13:09       ` AngeloGioacchino Del Regno
2022-09-28 13:09         ` AngeloGioacchino Del Regno
2022-09-28 13:09         ` AngeloGioacchino Del Regno
2022-09-28 13:09         ` AngeloGioacchino Del Regno
2022-09-22  7:22   ` Krzysztof Kozlowski
2022-09-22  7:22     ` Krzysztof Kozlowski
2022-09-22  7:22     ` Krzysztof Kozlowski
2022-09-22  7:22     ` Krzysztof Kozlowski
2022-09-27 13:38     ` Guillaume Ranquet
2022-09-27 13:38       ` Guillaume Ranquet
2022-09-27 13:38       ` Guillaume Ranquet
2022-09-27 13:38       ` Guillaume Ranquet
2022-09-19 16:56 ` [PATCH v1 17/17] drm/mediatek: Add mt8195-dpi support to drm_drv Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-19 16:56   ` Guillaume Ranquet
2022-09-22  7:20   ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-22  7:20     ` Krzysztof Kozlowski
2022-09-27 13:04     ` Guillaume Ranquet
2022-09-27 13:04       ` Guillaume Ranquet
2022-09-27 13:04       ` Guillaume Ranquet
2022-09-27 13:04       ` Guillaume Ranquet
2022-09-27 14:28       ` Krzysztof Kozlowski
2022-09-27 14:28         ` Krzysztof Kozlowski
2022-09-27 14:28         ` Krzysztof Kozlowski
2022-09-27 14:28         ` Krzysztof Kozlowski
2022-10-03 15:29         ` Guillaume Ranquet
2022-10-03 15:29           ` Guillaume Ranquet
2022-10-03 15:29           ` Guillaume Ranquet
2022-10-03 15:29           ` Guillaume Ranquet
2022-10-04 10:49           ` Krzysztof Kozlowski
2022-10-04 10:49             ` Krzysztof Kozlowski
2022-10-04 10:49             ` Krzysztof Kozlowski
2022-10-04 10:49             ` Krzysztof Kozlowski
2022-10-04 11:55             ` Guillaume Ranquet
2022-10-04 11:55               ` Guillaume Ranquet
2022-10-04 11:55               ` Guillaume Ranquet
2022-10-04 11:55               ` Guillaume Ranquet
2022-10-04 15:05               ` Krzysztof Kozlowski
2022-10-04 15:05                 ` Krzysztof Kozlowski
2022-10-04 15:05                 ` Krzysztof Kozlowski
2022-10-04 15:05                 ` Krzysztof Kozlowski
2022-10-05  9:34                 ` Guillaume Ranquet
2022-10-05  9:34                   ` Guillaume Ranquet
2022-10-05  9:34                   ` Guillaume Ranquet
2022-10-05  9:34                   ` Guillaume Ranquet
2022-10-05 14:53                   ` Krzysztof Kozlowski
2022-10-05 14:53                     ` Krzysztof Kozlowski
2022-10-05 14:53                     ` Krzysztof Kozlowski
2022-10-05 14:53                     ` Krzysztof Kozlowski

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