From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
bin.meng@windriver.com, richard.henderson@linaro.org,
lzw194868@alibaba-inc.com,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: [RFC PATCH 1/3] tcg/riscv: Fix base regsiter for qemu_ld/st
Date: Thu, 20 Oct 2022 18:41:52 +0800 [thread overview]
Message-ID: <20221020104154.4276-2-zhiwei_liu@linux.alibaba.com> (raw)
In-Reply-To: <20221020104154.4276-1-zhiwei_liu@linux.alibaba.com>
When guest base is zero, we should use addr_regl as base regiser instead of
the initial register TCG_REG_TMP0.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
tcg/riscv/tcg-target.c.inc | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 81a83e45b1..32f4bc7bfc 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1185,6 +1185,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
}
if (guest_base != 0) {
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ } else {
+ base = addr_regl;
}
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
#endif
@@ -1257,6 +1259,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
}
if (guest_base != 0) {
tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+ } else {
+ base = addr_regl;
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
#endif
--
2.25.1
next prev parent reply other threads:[~2022-10-20 11:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 10:41 [RFC PATCH 0/3] Fix some TCG RISC-V backend bugs LIU Zhiwei
2022-10-20 10:41 ` LIU Zhiwei [this message]
2022-10-20 11:18 ` [RFC PATCH 1/3] tcg/riscv: Fix base regsiter for qemu_ld/st Richard Henderson
2022-10-20 11:42 ` LIU Zhiwei
2022-10-20 12:01 ` Richard Henderson
2022-10-20 11:26 ` Philippe Mathieu-Daudé
2022-10-20 11:44 ` LIU Zhiwei
2022-10-20 10:41 ` [RFC PATCH 2/3] tcg/riscv: Fix tcg_out_opc_imm when imm exceeds LIU Zhiwei
2022-10-20 11:22 ` Richard Henderson
2022-10-20 12:42 ` LIU Zhiwei
2022-10-21 2:57 ` LIU Zhiwei
2022-10-21 4:29 ` Richard Henderson
2022-10-20 10:41 ` [RFC PATCH 3/3] tcg/riscv: Remove a wrong optimization for addsub2 LIU Zhiwei
2022-10-20 11:31 ` Richard Henderson
2022-10-20 12:39 ` LIU Zhiwei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221020104154.4276-2-zhiwei_liu@linux.alibaba.com \
--to=zhiwei_liu@linux.alibaba.com \
--cc=Alistair.Francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=lzw194868@alibaba-inc.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.