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From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
	bin.meng@windriver.com, richard.henderson@linaro.org,
	lzw194868@alibaba-inc.com,
	LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: [RFC PATCH 3/3] tcg/riscv: Remove a wrong optimization for addsub2
Date: Thu, 20 Oct 2022 18:41:54 +0800	[thread overview]
Message-ID: <20221020104154.4276-4-zhiwei_liu@linux.alibaba.com> (raw)
In-Reply-To: <20221020104154.4276-1-zhiwei_liu@linux.alibaba.com>

It's not clear what it is doing here. And it's wrong because bl and
al are both register, so we can't add them by an ADDI instruction.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
 tcg/riscv/tcg-target.c.inc | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index bfdf2bea69..a07fd0864f 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -705,9 +705,6 @@ static void tcg_out_addsub2(TCGContext *s,
                 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
                                 rl, al);
             }
-        } else if (rl == al && rl == bl) {
-            tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
-            tcg_out_opc_reg(s, opc_addi, rl, al, bl);
         } else {
             tcg_out_opc_reg(s, opc_add, rl, al, bl);
             tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
-- 
2.25.1



  parent reply	other threads:[~2022-10-20 11:13 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-20 10:41 [RFC PATCH 0/3] Fix some TCG RISC-V backend bugs LIU Zhiwei
2022-10-20 10:41 ` [RFC PATCH 1/3] tcg/riscv: Fix base regsiter for qemu_ld/st LIU Zhiwei
2022-10-20 11:18   ` Richard Henderson
2022-10-20 11:42     ` LIU Zhiwei
2022-10-20 12:01       ` Richard Henderson
2022-10-20 11:26   ` Philippe Mathieu-Daudé
2022-10-20 11:44     ` LIU Zhiwei
2022-10-20 10:41 ` [RFC PATCH 2/3] tcg/riscv: Fix tcg_out_opc_imm when imm exceeds LIU Zhiwei
2022-10-20 11:22   ` Richard Henderson
2022-10-20 12:42     ` LIU Zhiwei
2022-10-21  2:57     ` LIU Zhiwei
2022-10-21  4:29       ` Richard Henderson
2022-10-20 10:41 ` LIU Zhiwei [this message]
2022-10-20 11:31   ` [RFC PATCH 3/3] tcg/riscv: Remove a wrong optimization for addsub2 Richard Henderson
2022-10-20 12:39     ` LIU Zhiwei

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