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From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
	bin.meng@windriver.com, lzw194868@alibaba-inc.com
Subject: Re: [RFC PATCH 2/3] tcg/riscv: Fix tcg_out_opc_imm when imm exceeds
Date: Thu, 20 Oct 2022 21:22:41 +1000	[thread overview]
Message-ID: <49246207-2202-0239-65f5-1f0b44d8bd64@linaro.org> (raw)
In-Reply-To: <20221020104154.4276-3-zhiwei_liu@linux.alibaba.com>

On 10/20/22 20:41, LIU Zhiwei wrote:
> TYPE-I immediate can only represent a signed 12-bit value. If immediate
> exceed, mov it to an register.
> 
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
>   tcg/riscv/tcg-target.c.inc | 28 +++++++++++++++++++++++-----
>   1 file changed, 23 insertions(+), 5 deletions(-)
> 
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 32f4bc7bfc..bfdf2bea69 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -668,7 +668,12 @@ static void tcg_out_addsub2(TCGContext *s,
>       if (!cbh) {
>           tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
>       } else if (bh != 0 || ah == rl) {
> -        tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
> +        if (bh == sextract(bh, 0, 12)) {
> +            tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
> +        } else {
> +            tcg_out_movi(s, TCG_TYPE_TL, th, (is_sub ? -bh : bh));
> +            tcg_out_opc_reg(s, opc_add, th, ah, th);
> +        }

This value is currently constrained by 'M': +/- 0xfff.
You're suggesting that the fix should be to use 'I', which is signed 12-bit.

But this fix is definitely in the wrong place.


r~


  reply	other threads:[~2022-10-20 13:38 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-20 10:41 [RFC PATCH 0/3] Fix some TCG RISC-V backend bugs LIU Zhiwei
2022-10-20 10:41 ` [RFC PATCH 1/3] tcg/riscv: Fix base regsiter for qemu_ld/st LIU Zhiwei
2022-10-20 11:18   ` Richard Henderson
2022-10-20 11:42     ` LIU Zhiwei
2022-10-20 12:01       ` Richard Henderson
2022-10-20 11:26   ` Philippe Mathieu-Daudé
2022-10-20 11:44     ` LIU Zhiwei
2022-10-20 10:41 ` [RFC PATCH 2/3] tcg/riscv: Fix tcg_out_opc_imm when imm exceeds LIU Zhiwei
2022-10-20 11:22   ` Richard Henderson [this message]
2022-10-20 12:42     ` LIU Zhiwei
2022-10-21  2:57     ` LIU Zhiwei
2022-10-21  4:29       ` Richard Henderson
2022-10-20 10:41 ` [RFC PATCH 3/3] tcg/riscv: Remove a wrong optimization for addsub2 LIU Zhiwei
2022-10-20 11:31   ` Richard Henderson
2022-10-20 12:39     ` LIU Zhiwei

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