[PATCH 0/2] Re-introduce parent clock-rate set for fixed-factor clock

[Aradhya Bhatia <a-bhatia1@ti.com>]

Hi all,

The support for configuring CLK_SET_RATE_PARENT flag for a few specific
clocks was only used by the legacy Allwinner A10 sunxi clock, and the
reason its compatible was dropped was that the code supporting the
legacy sunxi platforms was removed (as the below-mentioned patch set
highlights) and no other fixed factor clock needed to do the same.

https://lore.kernel.org/lkml/20220531051742.43273-1-samuel@sholland.org/T/


The current patch series adds "ti,k3-am62-oldi-clk-div" (TI's display
subsystem (DSS) clock for the 1st videoport (vp0) on the AM625 SoC) as
a fixed factor clock and further, it also re-introduces the same support
to set the CLK_SET_RATE_PARENT flag.

Based on the clock-set request from DSS (equivalent to pixel frequency),
this clock asks its parent for a serial clock (with 7 times the pixel
frequrncy), which is required for the generation of serial LVDS signals.
This clock thus requires the CLK_SET_RATE_PARENT flag to be set, in
order to propagate the set clock-rate request to its parent clock.

Aradhya Bhatia (2):
  dt-bindings: clock: fixed-factor: Add TI AM62 SoC OLDI clock
  clk: fixed-factor: Re-introduce support for clocks to set parent
    clock-rate

 .../devicetree/bindings/clock/fixed-factor-clock.yaml |  1 +
 drivers/clk/clk-fixed-factor.c                        | 11 ++++++++++-
 2 files changed, 11 insertions(+), 1 deletion(-)

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2.39.0