* [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL
@ 2023-01-07 21:57 Simon Glass
2023-01-07 21:57 ` [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64 Simon Glass
2023-01-08 2:40 ` [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL Simon Glass
0 siblings, 2 replies; 6+ messages in thread
From: Simon Glass @ 2023-01-07 21:57 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass
The current approach is a bit of a hack and only works for the tpm
subsystem. Add a Kconfig so that crc8 can be enabled in SPL for other
purposes.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Add an SPL dependency in the Kconfig
lib/Kconfig | 18 ++++++++++++++++++
lib/Makefile | 3 ++-
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/lib/Kconfig b/lib/Kconfig
index def36f275ce..36d3cf99c3c 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -422,6 +422,7 @@ config TPM
config SPL_TPM
bool "Trusted Platform Module (TPM) Support in SPL"
depends on SPL_DM
+ imply SPL_CRC8
help
This enables support for TPMs which can be used to provide security
features for your board. The TPM can be connected via LPC or I2C
@@ -617,6 +618,23 @@ config SPL_MD5
security applications, but it can be useful for providing a quick
checksum of a block of data.
+config CRC8
+ def_bool y
+ help
+ Enables CRC8 support in U-Boot. This is normally required. CRC8 is
+ a simple and fast checksumming algorithm which does a bytewise
+ checksum with feedback to produce an 8-bit result. The code is small
+ and it does not require a lookup table (unlike CRC32).
+
+config SPL_CRC8
+ bool "Support CRC8 in SPL"
+ depends on SPL
+ help
+ Enables CRC8 support in SPL. This is not normally required. CRC8 is
+ a simple and fast checksumming algorithm which does a bytewise
+ checksum with feedback to produce an 8-bit result. The code is small
+ and it does not require a lookup table (unlike CRC32).
+
config CRC32
def_bool y
help
diff --git a/lib/Makefile b/lib/Makefile
index d77b33e7f48..a282e40258c 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -57,12 +57,13 @@ endif
obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm-common.o
ifeq ($(CONFIG_$(SPL_TPL_)TPM),y)
-obj-y += crc8.o
obj-$(CONFIG_TPM) += tpm_api.o
obj-$(CONFIG_TPM_V1) += tpm-v1.o
obj-$(CONFIG_TPM_V2) += tpm-v2.o
endif
+obj-$(CONFIG_$(SPL_TPL_)CRC8) += crc8.o
+
obj-y += crypto/
obj-$(CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE) += acpi/
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64
2023-01-07 21:57 [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL Simon Glass
@ 2023-01-07 21:57 ` Simon Glass
2023-01-08 15:48 ` Simon Glass
2023-02-11 23:29 ` Andrew Abbott
2023-01-08 2:40 ` [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL Simon Glass
1 sibling, 2 replies; 6+ messages in thread
From: Simon Glass @ 2023-01-07 21:57 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Kever Yang, Philipp Tomsich, huang lin
This board is useful for benchmarking overall U-Boot performance. Enable
the bootstage feature so we get a report.
Since this returns to the boot rom before finishing executing
board_init_r() in SPL, add a few bootstage calls so that we can collect
timing from TPL.
For the stash region, use a portion of SRAM, 64KB below the stack top.
This allows the TPL image to be up to nearly 120KB (it is typically about
64KB). SPL normally runs from SDRAM at 0, so can use the same stash
region.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Drop unwanted debugging
arch/arm/mach-rockchip/tpl.c | 16 +++++++++++++---
configs/rockpro64-rk3399_defconfig | 8 ++++++++
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index ed46a9ad286..fdd0c592b3e 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -4,6 +4,7 @@
*/
#include <common.h>
+#include <bootstage.h>
#include <debug_uart.h>
#include <dm.h>
#include <hang.h>
@@ -70,15 +71,15 @@ void board_init_f(ulong dummy)
U_BOOT_TIME ")\n");
#endif
#endif
+ /* Init secure timer */
+ rockchip_stimer_init();
+
ret = spl_early_init();
if (ret) {
debug("spl_early_init() failed: %d\n", ret);
hang();
}
- /* Init secure timer */
- rockchip_stimer_init();
-
/* Init ARM arch timer */
if (IS_ENABLED(CONFIG_SYS_ARCH_TIMER))
timer_init();
@@ -93,6 +94,15 @@ void board_init_f(ulong dummy)
int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
+#ifdef CONFIG_BOOTSTAGE_STASH
+ int ret;
+
+ bootstage_mark_name(BOOTSTAGE_ID_END_TPL, "end tpl");
+ ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
+ CONFIG_BOOTSTAGE_STASH_SIZE);
+ if (ret)
+ debug("Failed to stash bootstage: err=%d\n", ret);
+#endif
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
return 0;
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index 5b8d678f6bb..2f1ae156bd4 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x3F8000
CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_ROCKPRO64_RK3399=y
+CONFIG_BOOTSTAGE_STASH_ADDR=0xff8e0000
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -17,6 +18,12 @@ CONFIG_SYS_LOAD_ADDR=0x800800
CONFIG_DEBUG_UART=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
+CONFIG_BOOTSTAGE=y
+CONFIG_SPL_BOOTSTAGE=y
+CONFIG_TPL_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10
+CONFIG_BOOTSTAGE_STASH=y
CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -40,6 +47,7 @@ CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_SPI_FLASH=y
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL
2023-01-07 21:57 [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL Simon Glass
2023-01-07 21:57 ` [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64 Simon Glass
@ 2023-01-08 2:40 ` Simon Glass
1 sibling, 0 replies; 6+ messages in thread
From: Simon Glass @ 2023-01-08 2:40 UTC (permalink / raw)
To: U-Boot Mailing List
On Sat, 7 Jan 2023 at 14:57, Simon Glass <sjg@chromium.org> wrote:
>
> The current approach is a bit of a hack and only works for the tpm
> subsystem. Add a Kconfig so that crc8 can be enabled in SPL for other
> purposes.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Add an SPL dependency in the Kconfig
>
> lib/Kconfig | 18 ++++++++++++++++++
> lib/Makefile | 3 ++-
> 2 files changed, 20 insertions(+), 1 deletion(-)
Applied to u-boot-dm/next
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64
2023-01-07 21:57 ` [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64 Simon Glass
@ 2023-01-08 15:48 ` Simon Glass
2023-02-11 23:29 ` Andrew Abbott
1 sibling, 0 replies; 6+ messages in thread
From: Simon Glass @ 2023-01-08 15:48 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Jeffy Chen, Kever Yang, Philipp Tomsich, huang lin
On Sat, 7 Jan 2023 at 14:57, Simon Glass <sjg@chromium.org> wrote:
>
> This board is useful for benchmarking overall U-Boot performance. Enable
> the bootstage feature so we get a report.
>
> Since this returns to the boot rom before finishing executing
> board_init_r() in SPL, add a few bootstage calls so that we can collect
> timing from TPL.
>
> For the stash region, use a portion of SRAM, 64KB below the stack top.
> This allows the TPL image to be up to nearly 120KB (it is typically about
> 64KB). SPL normally runs from SDRAM at 0, so can use the same stash
> region.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Drop unwanted debugging
>
> arch/arm/mach-rockchip/tpl.c | 16 +++++++++++++---
> configs/rockpro64-rk3399_defconfig | 8 ++++++++
> 2 files changed, 21 insertions(+), 3 deletions(-)
>
Applied to u-boot-dm/next
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64
2023-01-07 21:57 ` [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64 Simon Glass
2023-01-08 15:48 ` Simon Glass
@ 2023-02-11 23:29 ` Andrew Abbott
2023-02-14 0:01 ` Simon Glass
1 sibling, 1 reply; 6+ messages in thread
From: Andrew Abbott @ 2023-02-11 23:29 UTC (permalink / raw)
To: u-boot; +Cc: sjg
On Sun, Jan 8, 2023, at 08:57, Simon Glass wrote:
> This board is useful for benchmarking overall U-Boot performance. Enable
> the bootstage feature so we get a report.
>
> Since this returns to the boot rom before finishing executing
> board_init_r() in SPL, add a few bootstage calls so that we can collect
> timing from TPL.
>
> For the stash region, use a portion of SRAM, 64KB below the stack top.
> This allows the TPL image to be up to nearly 120KB (it is typically about
> 64KB). SPL normally runs from SDRAM at 0, so can use the same stash
> region.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
> index 5b8d678f6bb..2f1ae156bd4 100644
> --- a/configs/rockpro64-rk3399_defconfig
> +++ b/configs/rockpro64-rk3399_defconfig
> @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x3F8000
> CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
> CONFIG_ROCKCHIP_RK3399=y
> CONFIG_TARGET_ROCKPRO64_RK3399=y
> +CONFIG_BOOTSTAGE_STASH_ADDR=0xff8e0000
> CONFIG_DEBUG_UART_BASE=0xFF1A0000
> CONFIG_DEBUG_UART_CLOCK=24000000
> CONFIG_SPL_SPI_FLASH_SUPPORT=y
> @@ -17,6 +18,12 @@ CONFIG_SYS_LOAD_ADDR=0x800800
> CONFIG_DEBUG_UART=y
> CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
> +CONFIG_BOOTSTAGE=y
Building from master commit a1e6b529e57c622e862e93fa6da03d9504565089 and copying u-boot-rockchip.bin to an SD card and booting from that on a RockPRO64 v2.1, I don't get past this:
(dirty because building on NixOS applies some patches)
>U-Boot TPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00)
>Channel 0: LPDDR4, 50MHz
>BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
>Channel 1: LPDDR4, 50MHz
>BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
>256B stride
>lpddr4_set_rate: change freq to 800MHz 1, 0
>Trying to boot from BOOTROM
>Returning to boot ROM...
>
>U-Boot SPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00 +0000)
>Trying to boot from MMC2
I bisected down to this patch. If I disable CONFIG_BOOTSTATE, I can boot. Is there something I need to do to successfully boot with bootstate enabled?
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64
2023-02-11 23:29 ` Andrew Abbott
@ 2023-02-14 0:01 ` Simon Glass
0 siblings, 0 replies; 6+ messages in thread
From: Simon Glass @ 2023-02-14 0:01 UTC (permalink / raw)
To: Andrew Abbott; +Cc: u-boot
Hi Andrew,
On Sat, 11 Feb 2023 at 16:29, Andrew Abbott <andrew@mirx.dev> wrote:
>
> On Sun, Jan 8, 2023, at 08:57, Simon Glass wrote:
> > This board is useful for benchmarking overall U-Boot performance. Enable
> > the bootstage feature so we get a report.
> >
> > Since this returns to the boot rom before finishing executing
> > board_init_r() in SPL, add a few bootstage calls so that we can collect
> > timing from TPL.
> >
> > For the stash region, use a portion of SRAM, 64KB below the stack top.
> > This allows the TPL image to be up to nearly 120KB (it is typically about
> > 64KB). SPL normally runs from SDRAM at 0, so can use the same stash
> > region.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
>
> > diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
> > index 5b8d678f6bb..2f1ae156bd4 100644
> > --- a/configs/rockpro64-rk3399_defconfig
> > +++ b/configs/rockpro64-rk3399_defconfig
> > @@ -9,6 +9,7 @@ CONFIG_ENV_OFFSET=0x3F8000
> > CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
> > CONFIG_ROCKCHIP_RK3399=y
> > CONFIG_TARGET_ROCKPRO64_RK3399=y
> > +CONFIG_BOOTSTAGE_STASH_ADDR=0xff8e0000
> > CONFIG_DEBUG_UART_BASE=0xFF1A0000
> > CONFIG_DEBUG_UART_CLOCK=24000000
> > CONFIG_SPL_SPI_FLASH_SUPPORT=y
> > @@ -17,6 +18,12 @@ CONFIG_SYS_LOAD_ADDR=0x800800
> > CONFIG_DEBUG_UART=y
> > CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> > CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
> > +CONFIG_BOOTSTAGE=y
>
> Building from master commit a1e6b529e57c622e862e93fa6da03d9504565089 and copying u-boot-rockchip.bin to an SD card and booting from that on a RockPRO64 v2.1, I don't get past this:
> (dirty because building on NixOS applies some patches)
>
> >U-Boot TPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00)
> >Channel 0: LPDDR4, 50MHz
> >BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
> >Channel 1: LPDDR4, 50MHz
> >BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
> >256B stride
> >lpddr4_set_rate: change freq to 800MHz 1, 0
> >Trying to boot from BOOTROM
> >Returning to boot ROM...
> >
> >U-Boot SPL 2023.04-rc1-00483-ga1e6b529e5-dirty (Jan 01 1980 - 00:00:00 +0000)
> >Trying to boot from MMC2
>
> I bisected down to this patch. If I disable CONFIG_BOOTSTATE, I can boot. Is there something I need to do to successfully boot with bootstate enabled?
I'm not sure what happened here, but there may have been some timer
changes that went in at the same time. I will take a look.
Regards,
Sim on
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-02-14 0:01 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-07 21:57 [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL Simon Glass
2023-01-07 21:57 ` [PATCH v2 13/14] rockchip: Enable bootstage on rockpro64 Simon Glass
2023-01-08 15:48 ` Simon Glass
2023-02-11 23:29 ` Andrew Abbott
2023-02-14 0:01 ` Simon Glass
2023-01-08 2:40 ` [PATCH v2 03/14] tpm: Add a proper Kconfig option for crc8 in SPL Simon Glass
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