From: Andrew Jones <ajones@ventanamicro.com> To: Atish Patra <atishp@rivosinc.com> Cc: linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sergey Matyukevich <sergey.matyukevich@syntacore.com>, Eric Lin <eric.lin@sifive.com>, Will Deacon <will@kernel.org> Subject: Re: [PATCH v2 10/11] RISC-V: KVM: Implement perf support without sampling Date: Mon, 23 Jan 2023 08:23:27 +0100 [thread overview] Message-ID: <20230123072327.4k4ai6mwfy4uc6qq@orel> (raw) In-Reply-To: <20230113114502.hiebgkujduwcmsuk@orel> On Fri, Jan 13, 2023 at 12:45:02PM +0100, Andrew Jones wrote: > On Thu, Dec 15, 2022 at 09:00:45AM -0800, Atish Patra wrote: ... > > + /* Start the counters that have been configured and requested by the guest */ > > + for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { > > + pmc_index = i + ctr_base; > > + if (!test_bit(pmc_index, kvpmu->pmc_in_use)) > > + continue; > > + pmc = &kvpmu->pmc[pmc_index]; > > + if (flag & SBI_PMU_START_FLAG_SET_INIT_VALUE) > > + pmc->counter_val = ival; > > + if (pmc->perf_event) { > > + if (unlikely(pmc->started)) { > > + sbiret = SBI_ERR_ALREADY_STARTED; > > + continue; > > + } > > + perf_event_period(pmc->perf_event, pmu_get_sample_period(pmc)); > > + perf_event_enable(pmc->perf_event); > > + pmc->started = true; > > + } else { > > + kvm_debug("Can not start counter due to invalid confiugartion\n"); > ^ Cannot ^ configuration > > > + sbiret = SBI_ERR_INVALID_PARAM; > > + } > > + } > > Possibly a spec oversight is that we continue to try and start counters, > even when we've seen errors. The problem with implementing that is that > if we have both errors we only return the last one. I.e. one counter > was already started and another counter resulted in invalid-param, we > only return invalid-param. We also don't say anything about the number > of failures / successes. I think we should bail on the first error and > even stop counters that we started. Callers can then try again after > correcting their input without potentially getting already-started errors. > We'd need to change the spec to do that though. > Thinking about this some more, the spec doesn't prohibit implementations from bailing on the first error, so we can do that. But maybe we don't need to stop the counters we started. We can leave it to the driver to sort out what got configured/started and what didn't when it gets an error. Thanks, drew
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com> To: Atish Patra <atishp@rivosinc.com> Cc: linux-kernel@vger.kernel.org, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sergey Matyukevich <sergey.matyukevich@syntacore.com>, Eric Lin <eric.lin@sifive.com>, Will Deacon <will@kernel.org> Subject: Re: [PATCH v2 10/11] RISC-V: KVM: Implement perf support without sampling Date: Mon, 23 Jan 2023 08:23:27 +0100 [thread overview] Message-ID: <20230123072327.4k4ai6mwfy4uc6qq@orel> (raw) In-Reply-To: <20230113114502.hiebgkujduwcmsuk@orel> On Fri, Jan 13, 2023 at 12:45:02PM +0100, Andrew Jones wrote: > On Thu, Dec 15, 2022 at 09:00:45AM -0800, Atish Patra wrote: ... > > + /* Start the counters that have been configured and requested by the guest */ > > + for_each_set_bit(i, &ctr_mask, RISCV_MAX_COUNTERS) { > > + pmc_index = i + ctr_base; > > + if (!test_bit(pmc_index, kvpmu->pmc_in_use)) > > + continue; > > + pmc = &kvpmu->pmc[pmc_index]; > > + if (flag & SBI_PMU_START_FLAG_SET_INIT_VALUE) > > + pmc->counter_val = ival; > > + if (pmc->perf_event) { > > + if (unlikely(pmc->started)) { > > + sbiret = SBI_ERR_ALREADY_STARTED; > > + continue; > > + } > > + perf_event_period(pmc->perf_event, pmu_get_sample_period(pmc)); > > + perf_event_enable(pmc->perf_event); > > + pmc->started = true; > > + } else { > > + kvm_debug("Can not start counter due to invalid confiugartion\n"); > ^ Cannot ^ configuration > > > + sbiret = SBI_ERR_INVALID_PARAM; > > + } > > + } > > Possibly a spec oversight is that we continue to try and start counters, > even when we've seen errors. The problem with implementing that is that > if we have both errors we only return the last one. I.e. one counter > was already started and another counter resulted in invalid-param, we > only return invalid-param. We also don't say anything about the number > of failures / successes. I think we should bail on the first error and > even stop counters that we started. Callers can then try again after > correcting their input without potentially getting already-started errors. > We'd need to change the spec to do that though. > Thinking about this some more, the spec doesn't prohibit implementations from bailing on the first error, so we can do that. But maybe we don't need to stop the counters we started. We can leave it to the driver to sort out what got configured/started and what didn't when it gets an error. Thanks, drew _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-23 7:24 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-15 17:00 [PATCH v2 00/11] KVM perf support Atish Patra 2022-12-15 17:00 ` Atish Patra 2022-12-15 17:00 ` [PATCH v2 01/11] RISC-V: Define helper functions expose hpm counter width and count Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 10:06 ` Andrew Jones 2023-01-12 10:06 ` Andrew Jones 2023-01-12 18:18 ` Atish Kumar Patra 2023-01-12 18:18 ` Atish Kumar Patra 2023-01-13 7:22 ` Andrew Jones 2023-01-13 7:22 ` Andrew Jones 2023-01-24 20:41 ` Atish Patra 2023-01-24 20:41 ` Atish Patra 2022-12-15 17:00 ` [PATCH v2 02/11] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 10:21 ` Andrew Jones 2023-01-12 10:21 ` Andrew Jones 2023-01-12 18:19 ` Atish Kumar Patra 2023-01-12 18:19 ` Atish Kumar Patra 2022-12-15 17:00 ` [PATCH v2 03/11] RISC-V: KVM: Return correct code for hsm stop function Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 10:28 ` Andrew Jones 2023-01-12 10:28 ` Andrew Jones 2023-01-12 18:25 ` Atish Kumar Patra 2023-01-12 18:25 ` Atish Kumar Patra 2023-01-13 7:25 ` Andrew Jones 2023-01-13 7:25 ` Andrew Jones 2022-12-15 17:00 ` [PATCH v2 04/11] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 11:04 ` Andrew Jones 2023-01-12 11:04 ` Andrew Jones 2023-01-12 18:47 ` Atish Kumar Patra 2023-01-12 18:47 ` Atish Kumar Patra 2023-01-13 7:42 ` Andrew Jones 2023-01-13 7:42 ` Andrew Jones 2022-12-15 17:00 ` [PATCH v2 05/11] RISC-V: KVM: Improve privilege mode filtering for perf Atish Patra 2022-12-15 17:00 ` Atish Patra 2022-12-15 20:17 ` Conor Dooley 2022-12-15 20:17 ` Conor Dooley 2022-12-15 21:10 ` Atish Kumar Patra 2022-12-15 21:10 ` Atish Kumar Patra 2022-12-15 17:00 ` [PATCH v2 06/11] RISC-V: KVM: Add skeleton support " Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 15:10 ` Andrew Jones 2023-01-12 15:10 ` Andrew Jones 2023-01-12 18:09 ` Atish Kumar Patra 2023-01-12 18:09 ` Atish Kumar Patra 2022-12-15 17:00 ` [PATCH v2 07/11] RISC-V: KVM: Add SBI PMU extension support Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 15:29 ` Andrew Jones 2023-01-12 15:29 ` Andrew Jones 2023-01-12 18:04 ` Atish Kumar Patra 2023-01-12 18:04 ` Atish Kumar Patra 2022-12-15 17:00 ` [PATCH v2 08/11] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 15:47 ` Andrew Jones 2023-01-12 15:47 ` Andrew Jones 2022-12-15 17:00 ` [PATCH v2 09/11] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-13 11:47 ` Andrew Jones 2023-01-13 11:47 ` Andrew Jones 2022-12-15 17:00 ` [PATCH v2 10/11] RISC-V: KVM: Implement perf support without sampling Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-13 11:45 ` Andrew Jones 2023-01-13 11:45 ` Andrew Jones 2023-01-23 7:23 ` Andrew Jones [this message] 2023-01-23 7:23 ` Andrew Jones 2023-01-26 0:50 ` Atish Patra 2023-01-26 0:50 ` Atish Patra 2022-12-15 17:00 ` [PATCH v2 11/11] RISC-V: KVM: Implement firmware events Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-13 12:08 ` Andrew Jones 2023-01-13 12:08 ` Andrew Jones 2023-01-26 3:08 ` Atish Patra 2023-01-26 3:08 ` Atish Patra
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