From: Atish Kumar Patra <atishp@rivosinc.com> To: Conor Dooley <conor@kernel.org> Cc: linux-kernel@vger.kernel.org, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sergey Matyukevich <sergey.matyukevich@syntacore.com>, Eric Lin <eric.lin@sifive.com>, Will Deacon <will@kernel.org> Subject: Re: [PATCH v2 05/11] RISC-V: KVM: Improve privilege mode filtering for perf Date: Thu, 15 Dec 2022 13:10:33 -0800 [thread overview] Message-ID: <CAHBxVyHFutEuKF=CHFA+7xrpcVEj+72L0PGvh6Hry=4SUW8tug@mail.gmail.com> (raw) In-Reply-To: <Y5uA8CEoTKzIGoSy@dizzy> On Thu, Dec 15, 2022 at 12:18 PM Conor Dooley <conor@kernel.org> wrote: > > Hey Atish, > > On Thu, Dec 15, 2022 at 09:00:40AM -0800, Atish Patra wrote: > > RISC-V: KVM: Improve privilege mode filtering for perf > > I almost marked this as "not applicable" in patchwork as I was mislead > by the $subject. I know our perf driver is a real mixed bag, but should > it not be something more like: > "perf: RISC-V: Improve privilege mode filtering for KVM"? Sure. I will change it in the next version. > It was only when I noticed that the rest of the series had been marked > as "Handled Elsewhere" that I realised that this must not be a KVM patch > ;) > > Thanks, > Conor > > > Currently, the host driver doesn't have any method to identify if the > > requested perf event is from kvm or bare metal. As KVM runs in HS > > mode, there are no separate hypervisor privilege mode to distinguish > > between the attributes for guest/host. > > > > Improve the privilege mode filtering by using the event specific > > config1 field. > > > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > --- > > drivers/perf/riscv_pmu_sbi.c | 27 ++++++++++++++++++++++----- > > include/linux/perf/riscv_pmu.h | 2 ++ > > 2 files changed, 24 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > > index 65d4aa4..df795b7 100644 > > --- a/drivers/perf/riscv_pmu_sbi.c > > +++ b/drivers/perf/riscv_pmu_sbi.c > > @@ -298,6 +298,27 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr) > > } > > EXPORT_SYMBOL(riscv_pmu_get_hpm_info); > > > > +static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) > > +{ > > + unsigned long cflags = 0; > > + bool guest_events = false; > > + > > + if (event->attr.config1 & RISCV_KVM_PMU_CONFIG1_GUEST_EVENTS) > > + guest_events = true; > > + if (event->attr.exclude_kernel) > > + cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VSINH : SBI_PMU_CFG_FLAG_SET_SINH; > > + if (event->attr.exclude_user) > > + cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VUINH : SBI_PMU_CFG_FLAG_SET_UINH; > > + if (guest_events && event->attr.exclude_hv) > > + cflags |= SBI_PMU_CFG_FLAG_SET_SINH; > > + if (event->attr.exclude_host) > > + cflags |= SBI_PMU_CFG_FLAG_SET_UINH | SBI_PMU_CFG_FLAG_SET_SINH; > > + if (event->attr.exclude_guest) > > + cflags |= SBI_PMU_CFG_FLAG_SET_VSINH | SBI_PMU_CFG_FLAG_SET_VUINH; > > + > > + return cflags; > > +} > > + > > static int pmu_sbi_ctr_get_idx(struct perf_event *event) > > { > > struct hw_perf_event *hwc = &event->hw; > > @@ -308,11 +329,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) > > uint64_t cbase = 0; > > unsigned long cflags = 0; > > > > - if (event->attr.exclude_kernel) > > - cflags |= SBI_PMU_CFG_FLAG_SET_SINH; > > - if (event->attr.exclude_user) > > - cflags |= SBI_PMU_CFG_FLAG_SET_UINH; > > - > > + cflags = pmu_sbi_get_filter_flags(event); > > /* retrieve the available counter index */ > > #if defined(CONFIG_32BIT) > > ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, > > diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h > > index a1c3f77..1c42146 100644 > > --- a/include/linux/perf/riscv_pmu.h > > +++ b/include/linux/perf/riscv_pmu.h > > @@ -26,6 +26,8 @@ > > > > #define RISCV_PMU_STOP_FLAG_RESET 1 > > > > +#define RISCV_KVM_PMU_CONFIG1_GUEST_EVENTS 0x1 > > + > > struct cpu_hw_events { > > /* currently enabled events */ > > int n_events; > > -- > > 2.25.1 > > > >
WARNING: multiple messages have this Message-ID (diff)
From: Atish Kumar Patra <atishp@rivosinc.com> To: Conor Dooley <conor@kernel.org> Cc: linux-kernel@vger.kernel.org, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sergey Matyukevich <sergey.matyukevich@syntacore.com>, Eric Lin <eric.lin@sifive.com>, Will Deacon <will@kernel.org> Subject: Re: [PATCH v2 05/11] RISC-V: KVM: Improve privilege mode filtering for perf Date: Thu, 15 Dec 2022 13:10:33 -0800 [thread overview] Message-ID: <CAHBxVyHFutEuKF=CHFA+7xrpcVEj+72L0PGvh6Hry=4SUW8tug@mail.gmail.com> (raw) In-Reply-To: <Y5uA8CEoTKzIGoSy@dizzy> On Thu, Dec 15, 2022 at 12:18 PM Conor Dooley <conor@kernel.org> wrote: > > Hey Atish, > > On Thu, Dec 15, 2022 at 09:00:40AM -0800, Atish Patra wrote: > > RISC-V: KVM: Improve privilege mode filtering for perf > > I almost marked this as "not applicable" in patchwork as I was mislead > by the $subject. I know our perf driver is a real mixed bag, but should > it not be something more like: > "perf: RISC-V: Improve privilege mode filtering for KVM"? Sure. I will change it in the next version. > It was only when I noticed that the rest of the series had been marked > as "Handled Elsewhere" that I realised that this must not be a KVM patch > ;) > > Thanks, > Conor > > > Currently, the host driver doesn't have any method to identify if the > > requested perf event is from kvm or bare metal. As KVM runs in HS > > mode, there are no separate hypervisor privilege mode to distinguish > > between the attributes for guest/host. > > > > Improve the privilege mode filtering by using the event specific > > config1 field. > > > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > --- > > drivers/perf/riscv_pmu_sbi.c | 27 ++++++++++++++++++++++----- > > include/linux/perf/riscv_pmu.h | 2 ++ > > 2 files changed, 24 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > > index 65d4aa4..df795b7 100644 > > --- a/drivers/perf/riscv_pmu_sbi.c > > +++ b/drivers/perf/riscv_pmu_sbi.c > > @@ -298,6 +298,27 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr) > > } > > EXPORT_SYMBOL(riscv_pmu_get_hpm_info); > > > > +static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) > > +{ > > + unsigned long cflags = 0; > > + bool guest_events = false; > > + > > + if (event->attr.config1 & RISCV_KVM_PMU_CONFIG1_GUEST_EVENTS) > > + guest_events = true; > > + if (event->attr.exclude_kernel) > > + cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VSINH : SBI_PMU_CFG_FLAG_SET_SINH; > > + if (event->attr.exclude_user) > > + cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VUINH : SBI_PMU_CFG_FLAG_SET_UINH; > > + if (guest_events && event->attr.exclude_hv) > > + cflags |= SBI_PMU_CFG_FLAG_SET_SINH; > > + if (event->attr.exclude_host) > > + cflags |= SBI_PMU_CFG_FLAG_SET_UINH | SBI_PMU_CFG_FLAG_SET_SINH; > > + if (event->attr.exclude_guest) > > + cflags |= SBI_PMU_CFG_FLAG_SET_VSINH | SBI_PMU_CFG_FLAG_SET_VUINH; > > + > > + return cflags; > > +} > > + > > static int pmu_sbi_ctr_get_idx(struct perf_event *event) > > { > > struct hw_perf_event *hwc = &event->hw; > > @@ -308,11 +329,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) > > uint64_t cbase = 0; > > unsigned long cflags = 0; > > > > - if (event->attr.exclude_kernel) > > - cflags |= SBI_PMU_CFG_FLAG_SET_SINH; > > - if (event->attr.exclude_user) > > - cflags |= SBI_PMU_CFG_FLAG_SET_UINH; > > - > > + cflags = pmu_sbi_get_filter_flags(event); > > /* retrieve the available counter index */ > > #if defined(CONFIG_32BIT) > > ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, > > diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h > > index a1c3f77..1c42146 100644 > > --- a/include/linux/perf/riscv_pmu.h > > +++ b/include/linux/perf/riscv_pmu.h > > @@ -26,6 +26,8 @@ > > > > #define RISCV_PMU_STOP_FLAG_RESET 1 > > > > +#define RISCV_KVM_PMU_CONFIG1_GUEST_EVENTS 0x1 > > + > > struct cpu_hw_events { > > /* currently enabled events */ > > int n_events; > > -- > > 2.25.1 > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-12-15 21:11 UTC|newest] Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-15 17:00 [PATCH v2 00/11] KVM perf support Atish Patra 2022-12-15 17:00 ` Atish Patra 2022-12-15 17:00 ` [PATCH v2 01/11] RISC-V: Define helper functions expose hpm counter width and count Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 10:06 ` Andrew Jones 2023-01-12 10:06 ` Andrew Jones 2023-01-12 18:18 ` Atish Kumar Patra 2023-01-12 18:18 ` Atish Kumar Patra 2023-01-13 7:22 ` Andrew Jones 2023-01-13 7:22 ` Andrew Jones 2023-01-24 20:41 ` Atish Patra 2023-01-24 20:41 ` Atish Patra 2022-12-15 17:00 ` [PATCH v2 02/11] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 10:21 ` Andrew Jones 2023-01-12 10:21 ` Andrew Jones 2023-01-12 18:19 ` Atish Kumar Patra 2023-01-12 18:19 ` Atish Kumar Patra 2022-12-15 17:00 ` [PATCH v2 03/11] RISC-V: KVM: Return correct code for hsm stop function Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 10:28 ` Andrew Jones 2023-01-12 10:28 ` Andrew Jones 2023-01-12 18:25 ` Atish Kumar Patra 2023-01-12 18:25 ` Atish Kumar Patra 2023-01-13 7:25 ` Andrew Jones 2023-01-13 7:25 ` Andrew Jones 2022-12-15 17:00 ` [PATCH v2 04/11] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 11:04 ` Andrew Jones 2023-01-12 11:04 ` Andrew Jones 2023-01-12 18:47 ` Atish Kumar Patra 2023-01-12 18:47 ` Atish Kumar Patra 2023-01-13 7:42 ` Andrew Jones 2023-01-13 7:42 ` Andrew Jones 2022-12-15 17:00 ` [PATCH v2 05/11] RISC-V: KVM: Improve privilege mode filtering for perf Atish Patra 2022-12-15 17:00 ` Atish Patra 2022-12-15 20:17 ` Conor Dooley 2022-12-15 20:17 ` Conor Dooley 2022-12-15 21:10 ` Atish Kumar Patra [this message] 2022-12-15 21:10 ` Atish Kumar Patra 2022-12-15 17:00 ` [PATCH v2 06/11] RISC-V: KVM: Add skeleton support " Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 15:10 ` Andrew Jones 2023-01-12 15:10 ` Andrew Jones 2023-01-12 18:09 ` Atish Kumar Patra 2023-01-12 18:09 ` Atish Kumar Patra 2022-12-15 17:00 ` [PATCH v2 07/11] RISC-V: KVM: Add SBI PMU extension support Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 15:29 ` Andrew Jones 2023-01-12 15:29 ` Andrew Jones 2023-01-12 18:04 ` Atish Kumar Patra 2023-01-12 18:04 ` Atish Kumar Patra 2022-12-15 17:00 ` [PATCH v2 08/11] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-12 15:47 ` Andrew Jones 2023-01-12 15:47 ` Andrew Jones 2022-12-15 17:00 ` [PATCH v2 09/11] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-13 11:47 ` Andrew Jones 2023-01-13 11:47 ` Andrew Jones 2022-12-15 17:00 ` [PATCH v2 10/11] RISC-V: KVM: Implement perf support without sampling Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-13 11:45 ` Andrew Jones 2023-01-13 11:45 ` Andrew Jones 2023-01-23 7:23 ` Andrew Jones 2023-01-23 7:23 ` Andrew Jones 2023-01-26 0:50 ` Atish Patra 2023-01-26 0:50 ` Atish Patra 2022-12-15 17:00 ` [PATCH v2 11/11] RISC-V: KVM: Implement firmware events Atish Patra 2022-12-15 17:00 ` Atish Patra 2023-01-13 12:08 ` Andrew Jones 2023-01-13 12:08 ` Andrew Jones 2023-01-26 3:08 ` Atish Patra 2023-01-26 3:08 ` Atish Patra
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