All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v3 1/2] arm64: dts: imx8mm: Deduplicate PCIe clock-names property
@ 2023-01-16 10:14 Marek Vasut
  2023-01-16 10:14 ` [PATCH v3 2/2] arm64: dts: imx8mq: " Marek Vasut
                   ` (2 more replies)
  0 siblings, 3 replies; 7+ messages in thread
From: Marek Vasut @ 2023-01-16 10:14 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Marek Vasut, Alexander Stein, Fabio Estevam, Peng Fan,
	Richard Zhu, Shawn Guo, NXP Linux Team

Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
---
V2: - Add RB from Alex
    - Fix venice build
    - Add default pcie clock entry into dtsi
V3: - Drop clocks altogether from imx8mm-innocomm-wb15.dtsi imx8mm-phyboard-polis-rdk.dts imx8mm-verdin.dtsi
      as they are identical to imx8mm.dtsi
---
 arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi  | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi               | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi     | 3 ---
 arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 3 ---
 arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts   | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi     | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi     | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi     | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts      | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts      | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts      | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts      | 5 ++---
 arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi            | 4 ----
 arch/arm64/boot/dts/freescale/imx8mm.dtsi                   | 4 ++++
 15 files changed, 26 insertions(+), 43 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
index 169f047fbca50..bc531175ff765 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
@@ -241,9 +241,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk_gated>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
index 9889319d4f045..b1f2beb40a98f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
@@ -905,9 +905,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcieclk 0>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index e0b604ac0da4f..0ce3005d578d2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -360,9 +360,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
index 44e87b1568e79..299752aa82772 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
@@ -210,9 +210,6 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>,
-		 <&clk IMX8MM_CLK_PCIE1_AUX>;
-	clock-names = "pcie", "pcie_bus", "pcie_aux";
 	fsl,max-link-speed = <1>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
index 4a3df2b77b0be..266129b4a70d9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
@@ -175,9 +175,6 @@ &pcie0 {
 	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 				 <&clk IMX8MM_SYS_PLL2_250M>;
 	assigned-clock-rates = <10000000>, <250000000>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&clk IMX8MM_CLK_PCIE1_PHY>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie>;
 	reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
index a0aeac6199299..156d793a0c972 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
@@ -79,9 +79,8 @@ &pcie_phy {
 
 &pcie0 {
 	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		<&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 				<&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
index c557dbf4dcd60..0ce60ad9c7d50 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
@@ -120,9 +120,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
index 41d0de6a7027b..570992a52b759 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
@@ -142,9 +142,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
index 7761d5671cb13..1800c6a4b1fc6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
@@ -162,9 +162,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
index 64b366e83fa14..df3b2c93d2d58 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -702,9 +702,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
index e8bc1fccc47be..c33ec6826d324 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
@@ -623,9 +623,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
index acc2ba8e00a88..363020a08c9b8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
@@ -557,9 +557,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
index eceed9816f5dc..93088fa1c3b9c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
@@ -618,9 +618,8 @@ &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
+		 <&clk IMX8MM_CLK_PCIE1_AUX>;
 	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
 			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
 	assigned-clock-rates = <10000000>, <250000000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 7e8b3b0fa3066..5b2493bb8dd93 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -657,10 +657,6 @@ &pcie0 {
 	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
 				 <&clk IMX8MM_SYS_PLL2_250M>;
 	assigned-clock-rates = <10000000>, <250000000>;
-	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MM_CLK_PCIE1_AUX>,
-		 <&clk IMX8MM_CLK_PCIE1_PHY>;
-	clock-names = "pcie", "pcie_aux", "pcie_bus";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
 	/* PCIE_1_RESET# (SODIMM 244) */
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 04cf2c3c9928b..31f4548f85cfa 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1302,6 +1302,10 @@ pcie0: pcie@33800000 {
 					<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 			fsl,max-link-speed = <2>;
 			linux,pci-domain = <0>;
+			clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+				 <&clk IMX8MM_CLK_PCIE1_PHY>,
+				 <&clk IMX8MM_CLK_PCIE1_AUX>;
+			clock-names = "pcie", "pcie_bus", "pcie_aux";
 			power-domains = <&pgc_pcie>;
 			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
 				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
-- 
2.39.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH v3 2/2] arm64: dts: imx8mq: Deduplicate PCIe clock-names property
  2023-01-16 10:14 [PATCH v3 1/2] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
@ 2023-01-16 10:14 ` Marek Vasut
  2023-01-17  4:00   ` Hongxing Zhu
  2023-01-17  3:35 ` [PATCH v3 1/2] arm64: dts: imx8mm: " Hongxing Zhu
  2023-01-26  6:50 ` Shawn Guo
  2 siblings, 1 reply; 7+ messages in thread
From: Marek Vasut @ 2023-01-16 10:14 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Marek Vasut, Alexander Stein, Fabio Estevam, Peng Fan,
	Richard Zhu, Shawn Guo, NXP Linux Team

Move the PCIe clock-names property from various DTs into SoC dtsi to
reduce duplication. In case of a couple of boards, reorder the clock
so they match the order in yaml DT bindings.

Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mq.dtsi, imx8mq-tqma8mq-mba8mx.dts
Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
---
V2: - Add RB from Alex
    - Add default pcie clock entry into dtsi
    - Fix the Ultra board
V3: Rebase on latest next-20230116
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts           | 10 ++++------
 .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts   | 10 ++++------
 arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts   |  5 ++---
 .../arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 10 ++++------
 arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi    | 10 ++++------
 arch/arm64/boot/dts/freescale/imx8mq.dtsi              | 10 ++++++++++
 6 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 78937910f4039..7507548cdb16b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -356,10 +356,9 @@ &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	vph-supply = <&vgen5_reg>;
 	status = "okay";
 };
@@ -369,10 +368,9 @@ &pcie1 {
 	pinctrl-0 = <&pinctrl_pcie1>;
 	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	vpcie-supply = <&reg_pcie1>;
 	vph-supply = <&vgen5_reg>;
 	status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
index a91c136797f60..6376417e918c2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -245,20 +245,18 @@ &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	status = "okay";
 };
 
 /* Intel Ethernet Controller I210/I211 */
 &pcie1 {
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie1_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	fsl,max-link-speed = <1>;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
index 055031bba8c4b..200268660518d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
@@ -197,10 +197,9 @@ &pcie1 {
 	pinctrl-0 = <&pinctrl_pcie1>;
 	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie1_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
index d7660eab68b94..344cfdaeb1d59 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
@@ -105,10 +105,9 @@ &led2 {
 &pcie0 {
 	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
+		 <&pcie0_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	epdev_on-supply = <&reg_vcc_3v3>;
 	hard-wired = <1>;
 	status = "okay";
@@ -120,10 +119,9 @@ &pcie0 {
  */
 &pcie1 {
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
+		 <&pcie1_refclk>,
 		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	epdev_on-supply = <&reg_vcc_3v3>;
 	hard-wired = <1>;
 	status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
index 4e05120c62d41..74a7a589a3296 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
@@ -551,10 +551,9 @@ &pcie0 {
 	pinctrl-0 = <&pinctrl_pcie0>;
 	reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-	         <&clk IMX8MQ_CLK_PCIE1_AUX>,
+	         <&pcie0_refclk>,
 	         <&clk IMX8MQ_CLK_PCIE1_PHY>,
-	         <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	         <&clk IMX8MQ_CLK_PCIE1_AUX>;
 	vph-supply = <&vgen5_reg>;
 	status = "okay";
 };
@@ -564,10 +563,9 @@ &pcie1 {
 	pinctrl-0 = <&pinctrl_pcie1>;
 	reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
 	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-	         <&clk IMX8MQ_CLK_PCIE2_AUX>,
+	         <&pcie1_refclk>,
 	         <&clk IMX8MQ_CLK_PCIE2_PHY>,
-	         <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	         <&clk IMX8MQ_CLK_PCIE2_AUX>;
 	vph-supply = <&vgen5_reg>;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index faed28e3ffa17..98fbba4c99a99 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1542,6 +1542,11 @@ pcie0: pcie@33800000 {
 			                <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 			fsl,max-link-speed = <2>;
 			linux,pci-domain = <0>;
+			clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+				 <&clk IMX8MQ_CLK_PCIE1_PHY>,
+				 <&clk IMX8MQ_CLK_PCIE1_PHY>,
+				 <&clk IMX8MQ_CLK_PCIE1_AUX>;
+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
 			power-domains = <&pgc_pcie>;
 			resets = <&src IMX8MQ_RESET_PCIEPHY>,
 			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
@@ -1579,6 +1584,11 @@ pcie1: pcie@33c00000 {
 					<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			fsl,max-link-speed = <2>;
 			linux,pci-domain = <1>;
+			clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+				 <&clk IMX8MQ_CLK_PCIE2_PHY>,
+				 <&clk IMX8MQ_CLK_PCIE2_PHY>,
+				 <&clk IMX8MQ_CLK_PCIE2_AUX>;
+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
 			power-domains = <&pgc_pcie>;
 			resets = <&src IMX8MQ_RESET_PCIEPHY2>,
 			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
-- 
2.39.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 7+ messages in thread
* RE: [PATCH v3 1/2] arm64: dts: imx8mm: Deduplicate PCIe clock-names property
  2023-01-16 10:14 [PATCH v3 1/2] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
  2023-01-16 10:14 ` [PATCH v3 2/2] arm64: dts: imx8mq: " Marek Vasut
@ 2023-01-17  3:35 ` Hongxing Zhu
  2023-01-26  6:50 ` Shawn Guo
  2 siblings, 0 replies; 7+ messages in thread
From: Hongxing Zhu @ 2023-01-17  3:35 UTC (permalink / raw)
  To: Marek Vasut, linux-arm-kernel
  Cc: Alexander Stein, Fabio Estevam, Peng Fan, Shawn Guo, dl-linux-imx

Hi Marek:

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: 2023年1月16日 18:14
> To: linux-arm-kernel@lists.infradead.org
> Cc: Marek Vasut <marex@denx.de>; Alexander Stein
> <alexander.stein@ew.tq-group.com>; Fabio Estevam <festevam@denx.de>;
> Peng Fan <peng.fan@nxp.com>; Hongxing Zhu <hongxing.zhu@nxp.com>;
> Shawn Guo <shawnguo@kernel.org>; dl-linux-imx <linux-imx@nxp.com>
> Subject: [PATCH v3 1/2] arm64: dts: imx8mm: Deduplicate PCIe clock-names
> property
> 
> Move the PCIe clock-names property from various DTs into SoC dtsi to reduce
> duplication. In case of a couple of boards, reorder the clock so they match the
> order in yaml DT bindings.
> 
> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> #
> imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts
> Signed-off-by: Marek Vasut <marex@denx.de>
Thanks for your patch.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>

Best Regards
Richard Zhu
> ---
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: linux-arm-kernel@lists.infradead.org
> ---
> V2: - Add RB from Alex
>     - Fix venice build
>     - Add default pcie clock entry into dtsi
> V3: - Drop clocks altogether from imx8mm-innocomm-wb15.dtsi
> imx8mm-phyboard-polis-rdk.dts imx8mm-verdin.dtsi
>       as they are identical to imx8mm.dtsi
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi  | 5 ++---
> arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi               | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi     | 3 ---
>  arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts | 3 ---
>  arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts   | 5
> ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi     | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi     | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi     | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts      | 5 ++---
>  arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi            | 4 ----
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi                   | 4 ++++
>  15 files changed, 26 insertions(+), 43 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> index 169f047fbca50..bc531175ff765 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
> @@ -241,9 +241,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk_gated>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk_gated>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> index 9889319d4f045..b1f2beb40a98f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts
> @@ -905,9 +905,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcieclk 0>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 0>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index e0b604ac0da4f..0ce3005d578d2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -360,9 +360,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> index 44e87b1568e79..299752aa82772 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi
> @@ -210,9 +210,6 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_PHY>,
> -		 <&clk IMX8MM_CLK_PCIE1_AUX>;
> -	clock-names = "pcie", "pcie_bus", "pcie_aux";
>  	fsl,max-link-speed = <1>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk
> IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> index 4a3df2b77b0be..266129b4a70d9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts
> @@ -175,9 +175,6 @@ &pcie0 {
>  	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
>  				 <&clk IMX8MM_SYS_PLL2_250M>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&clk IMX8MM_CLK_PCIE1_PHY>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie>;
>  	reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> index a0aeac6199299..156d793a0c972 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
> @@ -79,9 +79,8 @@ &pcie_phy {
> 
>  &pcie0 {
>  	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		<&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  				<&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> index c557dbf4dcd60..0ce60ad9c7d50 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
> @@ -120,9 +120,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> index 41d0de6a7027b..570992a52b759 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
> @@ -142,9 +142,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> index 7761d5671cb13..1800c6a4b1fc6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
> @@ -162,9 +162,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> index 64b366e83fa14..df3b2c93d2d58 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> @@ -702,9 +702,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> index e8bc1fccc47be..c33ec6826d324 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
> @@ -623,9 +623,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> index acc2ba8e00a88..363020a08c9b8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
> @@ -557,9 +557,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> index eceed9816f5dc..93088fa1c3b9c 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
> @@ -618,9 +618,8 @@ &pcie0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk
> IMX8MM_CLK_PCIE1_AUX>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
> +	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
> +		 <&clk IMX8MM_CLK_PCIE1_AUX>;
>  	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
>  			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
>  	assigned-clock-rates = <10000000>, <250000000>; diff --git
> a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> index 7e8b3b0fa3066..5b2493bb8dd93 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
> @@ -657,10 +657,6 @@ &pcie0 {
>  	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
>  				 <&clk IMX8MM_SYS_PLL2_250M>;
>  	assigned-clock-rates = <10000000>, <250000000>;
> -	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MM_CLK_PCIE1_AUX>,
> -		 <&clk IMX8MM_CLK_PCIE1_PHY>;
> -	clock-names = "pcie", "pcie_aux", "pcie_bus";
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	/* PCIE_1_RESET# (SODIMM 244) */
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 04cf2c3c9928b..31f4548f85cfa 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1302,6 +1302,10 @@ pcie0: pcie@33800000 {
>  					<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
>  			fsl,max-link-speed = <2>;
>  			linux,pci-domain = <0>;
> +			clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
> +				 <&clk IMX8MM_CLK_PCIE1_PHY>,
> +				 <&clk IMX8MM_CLK_PCIE1_AUX>;
> +			clock-names = "pcie", "pcie_bus", "pcie_aux";
>  			power-domains = <&pgc_pcie>;
>  			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
>  				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
> --
> 2.39.0

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 7+ messages in thread
* RE: [PATCH v3 2/2] arm64: dts: imx8mq: Deduplicate PCIe clock-names property
  2023-01-16 10:14 ` [PATCH v3 2/2] arm64: dts: imx8mq: " Marek Vasut
@ 2023-01-17  4:00   ` Hongxing Zhu
  2023-01-17 12:31     ` Marek Vasut
  0 siblings, 1 reply; 7+ messages in thread
From: Hongxing Zhu @ 2023-01-17  4:00 UTC (permalink / raw)
  To: Marek Vasut, linux-arm-kernel
  Cc: Alexander Stein, Fabio Estevam, Peng Fan, Shawn Guo, dl-linux-imx

Hi Marek:
Thanks for your patches.

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: 2023年1月16日 18:14
> To: linux-arm-kernel@lists.infradead.org
> Cc: Marek Vasut <marex@denx.de>; Alexander Stein
> <alexander.stein@ew.tq-group.com>; Fabio Estevam <festevam@denx.de>;
> Peng Fan <peng.fan@nxp.com>; Hongxing Zhu <hongxing.zhu@nxp.com>;
> Shawn Guo <shawnguo@kernel.org>; dl-linux-imx <linux-imx@nxp.com>
> Subject: [PATCH v3 2/2] arm64: dts: imx8mq: Deduplicate PCIe clock-names
> property
> 
> Move the PCIe clock-names property from various DTs into SoC dtsi to reduce
> duplication. In case of a couple of boards, reorder the clock so they match the
> order in yaml DT bindings.
> 
> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> #
> imx8mq.dtsi, imx8mq-tqma8mq-mba8mx.dts
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> To: linux-arm-kernel@lists.infradead.org
> ---
> V2: - Add RB from Alex
>     - Add default pcie clock entry into dtsi
>     - Fix the Ultra board
> V3: Rebase on latest next-20230116
> ---
>  arch/arm64/boot/dts/freescale/imx8mq-evk.dts           | 10 ++++------
>  .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts   | 10 ++++------
>  arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts   |  5 ++---
>  .../arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 10 ++++------
>  arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi    | 10 ++++------
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi              | 10
> ++++++++++
>  6 files changed, 28 insertions(+), 27 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index 78937910f4039..7507548cdb16b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -356,10 +356,9 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	vph-supply = <&vgen5_reg>;
>  	status = "okay";
>  };
> @@ -369,10 +368,9 @@ &pcie1 {
>  	pinctrl-0 = <&pinctrl_pcie1>;
>  	reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	vpcie-supply = <&reg_pcie1>;
>  	vph-supply = <&vgen5_reg>;
>  	status = "okay";
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> index a91c136797f60..6376417e918c2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
> @@ -245,20 +245,18 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	status = "okay";
>  };
> 
>  /* Intel Ethernet Controller I210/I211 */
>  &pcie1 {
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie1_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	fsl,max-link-speed = <1>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> index 055031bba8c4b..200268660518d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
> @@ -197,10 +197,9 @@ &pcie1 {
>  	pinctrl-0 = <&pinctrl_pcie1>;
>  	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie1_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	status = "okay";
>  };
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> index d7660eab68b94..344cfdaeb1d59 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
> @@ -105,10 +105,9 @@ &led2 {
>  &pcie0 {
>  	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +		 <&pcie0_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -		 <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	epdev_on-supply = <&reg_vcc_3v3>;
>  	hard-wired = <1>;
>  	status = "okay";
> @@ -120,10 +119,9 @@ &pcie0 {
>   */
>  &pcie1 {
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +		 <&pcie1_refclk>,
>  		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -		 <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +		 <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	epdev_on-supply = <&reg_vcc_3v3>;
>  	hard-wired = <1>;
>  	status = "okay";
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
> index 4e05120c62d41..74a7a589a3296 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
> @@ -551,10 +551,9 @@ &pcie0 {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> -	         <&clk IMX8MQ_CLK_PCIE1_AUX>,
> +	         <&pcie0_refclk>,
>  	         <&clk IMX8MQ_CLK_PCIE1_PHY>,
> -	         <&pcie0_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +	         <&clk IMX8MQ_CLK_PCIE1_AUX>;
>  	vph-supply = <&vgen5_reg>;
>  	status = "okay";
>  };
> @@ -564,10 +563,9 @@ &pcie1 {
>  	pinctrl-0 = <&pinctrl_pcie1>;
>  	reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
>  	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> -	         <&clk IMX8MQ_CLK_PCIE2_AUX>,
> +	         <&pcie1_refclk>,
>  	         <&clk IMX8MQ_CLK_PCIE2_PHY>,
> -	         <&pcie1_refclk>;
> -	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> +	         <&clk IMX8MQ_CLK_PCIE2_AUX>;
>  	vph-supply = <&vgen5_reg>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index faed28e3ffa17..98fbba4c99a99 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1542,6 +1542,11 @@ pcie0: pcie@33800000 {
>  			                <0 0 0 4 &gic GIC_SPI 122
> IRQ_TYPE_LEVEL_HIGH>;
>  			fsl,max-link-speed = <2>;
>  			linux,pci-domain = <0>;
> +			clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> +				 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> +				 <&clk IMX8MQ_CLK_PCIE1_PHY>,
Why there are two PHY clocks?
Do you want to define IMX8MQ_CLK_PCIE1_PHY clock as "pcie_bus" clock here,
 and then change "pcie_bus" clock to "pcie0_refclk" in the evk board dts later?

How about to set the "pcie_bus" clock as " pcie#_refclk " directly in i.MX8MQ
 dtsi file?
Thus, it can avoid more duplicated codes in boards dts files further.

> +				 <&clk IMX8MQ_CLK_PCIE1_AUX>;
> +			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
>  			power-domains = <&pgc_pcie>;
>  			resets = <&src IMX8MQ_RESET_PCIEPHY>,
>  			         <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, @@
> -1579,6 +1584,11 @@ pcie1: pcie@33c00000 {
>  					<0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>  			fsl,max-link-speed = <2>;
>  			linux,pci-domain = <1>;
> +			clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> +				 <&clk IMX8MQ_CLK_PCIE2_PHY>,
> +				 <&clk IMX8MQ_CLK_PCIE2_PHY>,
Same to above.

Best Regards
Richard Zhu

> +				 <&clk IMX8MQ_CLK_PCIE2_AUX>;
> +			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
>  			power-domains = <&pgc_pcie>;
>  			resets = <&src IMX8MQ_RESET_PCIEPHY2>,
>  			         <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
> --
> 2.39.0

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/2] arm64: dts: imx8mq: Deduplicate PCIe clock-names property
  2023-01-17  4:00   ` Hongxing Zhu
@ 2023-01-17 12:31     ` Marek Vasut
  2023-01-18  1:48       ` Hongxing Zhu
  0 siblings, 1 reply; 7+ messages in thread
From: Marek Vasut @ 2023-01-17 12:31 UTC (permalink / raw)
  To: Hongxing Zhu, linux-arm-kernel
  Cc: Alexander Stein, Fabio Estevam, Peng Fan, Shawn Guo, dl-linux-imx

On 1/17/23 05:00, Hongxing Zhu wrote:

Hi,

[...]

>> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> index faed28e3ffa17..98fbba4c99a99 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
>> @@ -1542,6 +1542,11 @@ pcie0: pcie@33800000 {
>>   			                <0 0 0 4 &gic GIC_SPI 122
>> IRQ_TYPE_LEVEL_HIGH>;
>>   			fsl,max-link-speed = <2>;
>>   			linux,pci-domain = <0>;
>> +			clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
>> +				 <&clk IMX8MQ_CLK_PCIE1_PHY>,
>> +				 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> Why there are two PHY clocks?
> Do you want to define IMX8MQ_CLK_PCIE1_PHY clock as "pcie_bus" clock here,
>   and then change "pcie_bus" clock to "pcie0_refclk" in the evk board dts later?

Yes

> How about to set the "pcie_bus" clock as " pcie#_refclk " directly in i.MX8MQ
>   dtsi file?
> Thus, it can avoid more duplicated codes in boards dts files further.

I can do that, but is that really the right approach ?

Consider a board which supplies 'pcie_bus' from some I2C PCIe clock 
generator, such board would now have a useless /pcie#-clock {} node in 
DT , right ?

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 7+ messages in thread
* RE: [PATCH v3 2/2] arm64: dts: imx8mq: Deduplicate PCIe clock-names property
  2023-01-17 12:31     ` Marek Vasut
@ 2023-01-18  1:48       ` Hongxing Zhu
  0 siblings, 0 replies; 7+ messages in thread
From: Hongxing Zhu @ 2023-01-18  1:48 UTC (permalink / raw)
  To: Marek Vasut, linux-arm-kernel
  Cc: Alexander Stein, Fabio Estevam, Peng Fan, Shawn Guo, dl-linux-imx

Hi:

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: 2023年1月17日 20:32
> To: Hongxing Zhu <hongxing.zhu@nxp.com>;
> linux-arm-kernel@lists.infradead.org
> Cc: Alexander Stein <alexander.stein@ew.tq-group.com>; Fabio Estevam
> <festevam@denx.de>; Peng Fan <peng.fan@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v3 2/2] arm64: dts: imx8mq: Deduplicate PCIe
> clock-names property
> 
> On 1/17/23 05:00, Hongxing Zhu wrote:
> 
> Hi,
> 
> [...]
> 
> >> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> >> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> >> index faed28e3ffa17..98fbba4c99a99 100644
> >> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> >> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> >> @@ -1542,6 +1542,11 @@ pcie0: pcie@33800000 {
> >>   			                <0 0 0 4 &gic GIC_SPI 122
> IRQ_TYPE_LEVEL_HIGH>;
> >>   			fsl,max-link-speed = <2>;
> >>   			linux,pci-domain = <0>;
> >> +			clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> >> +				 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> >> +				 <&clk IMX8MQ_CLK_PCIE1_PHY>,
> > Why there are two PHY clocks?
> > Do you want to define IMX8MQ_CLK_PCIE1_PHY clock as "pcie_bus" clock
> here,
> >   and then change "pcie_bus" clock to "pcie0_refclk" in the evk board dts
> later?
> 
> Yes
> 
> > How about to set the "pcie_bus" clock as " pcie#_refclk " directly in i.MX8MQ
> >   dtsi file?
> > Thus, it can avoid more duplicated codes in boards dts files further.
> 
> I can do that, but is that really the right approach ?
> 
> Consider a board which supplies 'pcie_bus' from some I2C PCIe clock generator,
> such board would now have a useless /pcie#-clock {} node in DT , right ?
You're right.
I only consider the fixed external PCIe clock generator design contained on
 i.MX8MQ EVK board.
I'm fine with this patch-set, thanks.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>

Best Regards
Richard Zhu
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH v3 1/2] arm64: dts: imx8mm: Deduplicate PCIe clock-names property
  2023-01-16 10:14 [PATCH v3 1/2] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
  2023-01-16 10:14 ` [PATCH v3 2/2] arm64: dts: imx8mq: " Marek Vasut
  2023-01-17  3:35 ` [PATCH v3 1/2] arm64: dts: imx8mm: " Hongxing Zhu
@ 2023-01-26  6:50 ` Shawn Guo
  2 siblings, 0 replies; 7+ messages in thread
From: Shawn Guo @ 2023-01-26  6:50 UTC (permalink / raw)
  To: Marek Vasut
  Cc: linux-arm-kernel, Alexander Stein, Fabio Estevam, Peng Fan,
	Richard Zhu, NXP Linux Team

On Mon, Jan 16, 2023 at 11:14:21AM +0100, Marek Vasut wrote:
> Move the PCIe clock-names property from various DTs into SoC dtsi to
> reduce duplication. In case of a couple of boards, reorder the clock
> so they match the order in yaml DT bindings.
> 
> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mm.dtsi, imx8mm-tqma8mqml-mba8mx.dts
> Signed-off-by: Marek Vasut <marex@denx.de>

Applied both, thanks!

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-01-26  6:51 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-16 10:14 [PATCH v3 1/2] arm64: dts: imx8mm: Deduplicate PCIe clock-names property Marek Vasut
2023-01-16 10:14 ` [PATCH v3 2/2] arm64: dts: imx8mq: " Marek Vasut
2023-01-17  4:00   ` Hongxing Zhu
2023-01-17 12:31     ` Marek Vasut
2023-01-18  1:48       ` Hongxing Zhu
2023-01-17  3:35 ` [PATCH v3 1/2] arm64: dts: imx8mm: " Hongxing Zhu
2023-01-26  6:50 ` Shawn Guo

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.