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* [PATCH v3 0/6] Introduce STM32 system bus
@ 2023-01-27 16:40 ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.

For every peripheral, the bus checks the firewall registers to see
if the peripheral is configured as non-secure. If the peripheral
is configured as secure, the node is marked populated, so the
device won't be probed.

This is useful as a firewall configuration sanity check and avoid
platform crashes in case peripherals are incorrectly configured.

The STM32 System Bus implements the feature-domain-controller
bindings. It is used by peripherals to reference a domain
controller, in this case the firewall feature domain.
The bus uses the ID referenced by the feature-domains property to
know where to look in the firewall to get the security configuration
for the peripheral. This allows a device tree description rather
than a hardcoded peripheral table in the bus driver.

On STM32MP13/15 platforms, the firewall bus is represented by the
ETZPC node, which is responsible for the securing / MCU isolating
the capable peripherals.

STM32MP13/15 device trees are updated in this series to implement
the bus. All peripherals that are securable or MCU isolation capable
by the ETZPC are connected to the bus.

Changes in V2:
	- Corrected YAMLS errors highlighted by Rob's robot
	- Re-ordered Signed-off-by tags in two patches

Changes in V3:
	- Document feature-domains property in YAML documentation for
	concerned periperals under the System Bus
	- Fix STM32 System Bus YAML documentation
	- Remove STM32 System bus bindings that were currently used
	as helpers for device tree
	- Correct few errors in driver
	- Add missing peripherals under the System Bus that were in
	SoC variation device tree files
	- Fix node names

Gatien Chevallier (5):
  dt-bindings: treewide: add feature-domains description in binding
    files
  dt-bindings: bus: add STM32 System Bus
  bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards

Oleksii Moisieiev (1):
  dt-bindings: Document common device controller bindings

 .../devicetree/bindings/bus/st,sys-bus.yaml   |  127 +
 .../bindings/crypto/st,stm32-hash.yaml        |    5 +
 .../devicetree/bindings/dma/st,stm32-dma.yaml |    5 +
 .../bindings/dma/st,stm32-dmamux.yaml         |    5 +
 .../feature-domain-controller.yaml            |   84 +
 .../devicetree/bindings/i2c/st,stm32-i2c.yaml |    5 +
 .../bindings/iio/adc/st,stm32-adc.yaml        |    5 +
 .../bindings/iio/adc/st,stm32-dfsdm-adc.yaml  |    5 +
 .../bindings/iio/dac/st,stm32-dac.yaml        |    5 +
 .../bindings/media/st,stm32-cec.yaml          |    5 +
 .../bindings/media/st,stm32-dcmi.yaml         |    5 +
 .../memory-controllers/st,stm32-fmc2-ebi.yaml |    5 +
 .../bindings/mfd/st,stm32-lptimer.yaml        |    5 +
 .../bindings/mfd/st,stm32-timers.yaml         |    6 +
 .../devicetree/bindings/mmc/arm,pl18x.yaml    |    5 +
 .../devicetree/bindings/net/stm32-dwmac.yaml  |    5 +
 .../bindings/phy/phy-stm32-usbphyc.yaml       |    5 +
 .../bindings/regulator/st,stm32-vrefbuf.yaml  |    5 +
 .../devicetree/bindings/rng/st,stm32-rng.yaml |    5 +
 .../bindings/serial/st,stm32-uart.yaml        |    5 +
 .../bindings/sound/st,stm32-i2s.yaml          |    5 +
 .../bindings/sound/st,stm32-sai.yaml          |    5 +
 .../bindings/sound/st,stm32-spdifrx.yaml      |    5 +
 .../bindings/spi/st,stm32-qspi.yaml           |    5 +
 .../devicetree/bindings/spi/st,stm32-spi.yaml |    5 +
 .../devicetree/bindings/usb/dwc2.yaml         |    5 +
 MAINTAINERS                                   |    6 +
 arch/arm/boot/dts/stm32mp131.dtsi             |  407 +--
 arch/arm/boot/dts/stm32mp133.dtsi             |   51 +-
 arch/arm/boot/dts/stm32mp13xc.dtsi            |   19 +-
 arch/arm/boot/dts/stm32mp13xf.dtsi            |   18 +-
 arch/arm/boot/dts/stm32mp151.dtsi             | 2722 +++++++++--------
 arch/arm/boot/dts/stm32mp153.dtsi             |   52 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi            |   19 +-
 drivers/bus/Kconfig                           |    9 +
 drivers/bus/Makefile                          |    1 +
 drivers/bus/stm32_sys_bus.c                   |  168 +
 37 files changed, 2208 insertions(+), 1596 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
 create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
 create mode 100644 drivers/bus/stm32_sys_bus.c

-- 
2.35.3


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* [PATCH v3 0/6] Introduce STM32 system bus
@ 2023-01-27 16:40 ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.

For every peripheral, the bus checks the firewall registers to see
if the peripheral is configured as non-secure. If the peripheral
is configured as secure, the node is marked populated, so the
device won't be probed.

This is useful as a firewall configuration sanity check and avoid
platform crashes in case peripherals are incorrectly configured.

The STM32 System Bus implements the feature-domain-controller
bindings. It is used by peripherals to reference a domain
controller, in this case the firewall feature domain.
The bus uses the ID referenced by the feature-domains property to
know where to look in the firewall to get the security configuration
for the peripheral. This allows a device tree description rather
than a hardcoded peripheral table in the bus driver.

On STM32MP13/15 platforms, the firewall bus is represented by the
ETZPC node, which is responsible for the securing / MCU isolating
the capable peripherals.

STM32MP13/15 device trees are updated in this series to implement
the bus. All peripherals that are securable or MCU isolation capable
by the ETZPC are connected to the bus.

Changes in V2:
	- Corrected YAMLS errors highlighted by Rob's robot
	- Re-ordered Signed-off-by tags in two patches

Changes in V3:
	- Document feature-domains property in YAML documentation for
	concerned periperals under the System Bus
	- Fix STM32 System Bus YAML documentation
	- Remove STM32 System bus bindings that were currently used
	as helpers for device tree
	- Correct few errors in driver
	- Add missing peripherals under the System Bus that were in
	SoC variation device tree files
	- Fix node names

Gatien Chevallier (5):
  dt-bindings: treewide: add feature-domains description in binding
    files
  dt-bindings: bus: add STM32 System Bus
  bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards

Oleksii Moisieiev (1):
  dt-bindings: Document common device controller bindings

 .../devicetree/bindings/bus/st,sys-bus.yaml   |  127 +
 .../bindings/crypto/st,stm32-hash.yaml        |    5 +
 .../devicetree/bindings/dma/st,stm32-dma.yaml |    5 +
 .../bindings/dma/st,stm32-dmamux.yaml         |    5 +
 .../feature-domain-controller.yaml            |   84 +
 .../devicetree/bindings/i2c/st,stm32-i2c.yaml |    5 +
 .../bindings/iio/adc/st,stm32-adc.yaml        |    5 +
 .../bindings/iio/adc/st,stm32-dfsdm-adc.yaml  |    5 +
 .../bindings/iio/dac/st,stm32-dac.yaml        |    5 +
 .../bindings/media/st,stm32-cec.yaml          |    5 +
 .../bindings/media/st,stm32-dcmi.yaml         |    5 +
 .../memory-controllers/st,stm32-fmc2-ebi.yaml |    5 +
 .../bindings/mfd/st,stm32-lptimer.yaml        |    5 +
 .../bindings/mfd/st,stm32-timers.yaml         |    6 +
 .../devicetree/bindings/mmc/arm,pl18x.yaml    |    5 +
 .../devicetree/bindings/net/stm32-dwmac.yaml  |    5 +
 .../bindings/phy/phy-stm32-usbphyc.yaml       |    5 +
 .../bindings/regulator/st,stm32-vrefbuf.yaml  |    5 +
 .../devicetree/bindings/rng/st,stm32-rng.yaml |    5 +
 .../bindings/serial/st,stm32-uart.yaml        |    5 +
 .../bindings/sound/st,stm32-i2s.yaml          |    5 +
 .../bindings/sound/st,stm32-sai.yaml          |    5 +
 .../bindings/sound/st,stm32-spdifrx.yaml      |    5 +
 .../bindings/spi/st,stm32-qspi.yaml           |    5 +
 .../devicetree/bindings/spi/st,stm32-spi.yaml |    5 +
 .../devicetree/bindings/usb/dwc2.yaml         |    5 +
 MAINTAINERS                                   |    6 +
 arch/arm/boot/dts/stm32mp131.dtsi             |  407 +--
 arch/arm/boot/dts/stm32mp133.dtsi             |   51 +-
 arch/arm/boot/dts/stm32mp13xc.dtsi            |   19 +-
 arch/arm/boot/dts/stm32mp13xf.dtsi            |   18 +-
 arch/arm/boot/dts/stm32mp151.dtsi             | 2722 +++++++++--------
 arch/arm/boot/dts/stm32mp153.dtsi             |   52 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi            |   19 +-
 drivers/bus/Kconfig                           |    9 +
 drivers/bus/Makefile                          |    1 +
 drivers/bus/stm32_sys_bus.c                   |  168 +
 37 files changed, 2208 insertions(+), 1596 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
 create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
 create mode 100644 drivers/bus/stm32_sys_bus.c

-- 
2.35.3


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* [PATCH v3 0/6] Introduce STM32 system bus
@ 2023-01-27 16:40 ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, Gatien Chevallier, linux-iio, netdev,
	linux-usb, linux-mmc, linux-kernel, linux-spi, linux-phy,
	linux-crypto, linux-serial, dmaengine, linux-media, linux-stm32,
	linux-arm-kernel, linux-i2c

Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.

For every peripheral, the bus checks the firewall registers to see
if the peripheral is configured as non-secure. If the peripheral
is configured as secure, the node is marked populated, so the
device won't be probed.

This is useful as a firewall configuration sanity check and avoid
platform crashes in case peripherals are incorrectly configured.

The STM32 System Bus implements the feature-domain-controller
bindings. It is used by peripherals to reference a domain
controller, in this case the firewall feature domain.
The bus uses the ID referenced by the feature-domains property to
know where to look in the firewall to get the security configuration
for the peripheral. This allows a device tree description rather
than a hardcoded peripheral table in the bus driver.

On STM32MP13/15 platforms, the firewall bus is represented by the
ETZPC node, which is responsible for the securing / MCU isolating
the capable peripherals.

STM32MP13/15 device trees are updated in this series to implement
the bus. All peripherals that are securable or MCU isolation capable
by the ETZPC are connected to the bus.

Changes in V2:
	- Corrected YAMLS errors highlighted by Rob's robot
	- Re-ordered Signed-off-by tags in two patches

Changes in V3:
	- Document feature-domains property in YAML documentation for
	concerned periperals under the System Bus
	- Fix STM32 System Bus YAML documentation
	- Remove STM32 System bus bindings that were currently used
	as helpers for device tree
	- Correct few errors in driver
	- Add missing peripherals under the System Bus that were in
	SoC variation device tree files
	- Fix node names

Gatien Chevallier (5):
  dt-bindings: treewide: add feature-domains description in binding
    files
  dt-bindings: bus: add STM32 System Bus
  bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards

Oleksii Moisieiev (1):
  dt-bindings: Document common device controller bindings

 .../devicetree/bindings/bus/st,sys-bus.yaml   |  127 +
 .../bindings/crypto/st,stm32-hash.yaml        |    5 +
 .../devicetree/bindings/dma/st,stm32-dma.yaml |    5 +
 .../bindings/dma/st,stm32-dmamux.yaml         |    5 +
 .../feature-domain-controller.yaml            |   84 +
 .../devicetree/bindings/i2c/st,stm32-i2c.yaml |    5 +
 .../bindings/iio/adc/st,stm32-adc.yaml        |    5 +
 .../bindings/iio/adc/st,stm32-dfsdm-adc.yaml  |    5 +
 .../bindings/iio/dac/st,stm32-dac.yaml        |    5 +
 .../bindings/media/st,stm32-cec.yaml          |    5 +
 .../bindings/media/st,stm32-dcmi.yaml         |    5 +
 .../memory-controllers/st,stm32-fmc2-ebi.yaml |    5 +
 .../bindings/mfd/st,stm32-lptimer.yaml        |    5 +
 .../bindings/mfd/st,stm32-timers.yaml         |    6 +
 .../devicetree/bindings/mmc/arm,pl18x.yaml    |    5 +
 .../devicetree/bindings/net/stm32-dwmac.yaml  |    5 +
 .../bindings/phy/phy-stm32-usbphyc.yaml       |    5 +
 .../bindings/regulator/st,stm32-vrefbuf.yaml  |    5 +
 .../devicetree/bindings/rng/st,stm32-rng.yaml |    5 +
 .../bindings/serial/st,stm32-uart.yaml        |    5 +
 .../bindings/sound/st,stm32-i2s.yaml          |    5 +
 .../bindings/sound/st,stm32-sai.yaml          |    5 +
 .../bindings/sound/st,stm32-spdifrx.yaml      |    5 +
 .../bindings/spi/st,stm32-qspi.yaml           |    5 +
 .../devicetree/bindings/spi/st,stm32-spi.yaml |    5 +
 .../devicetree/bindings/usb/dwc2.yaml         |    5 +
 MAINTAINERS                                   |    6 +
 arch/arm/boot/dts/stm32mp131.dtsi             |  407 +--
 arch/arm/boot/dts/stm32mp133.dtsi             |   51 +-
 arch/arm/boot/dts/stm32mp13xc.dtsi            |   19 +-
 arch/arm/boot/dts/stm32mp13xf.dtsi            |   18 +-
 arch/arm/boot/dts/stm32mp151.dtsi             | 2722 +++++++++--------
 arch/arm/boot/dts/stm32mp153.dtsi             |   52 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi            |   19 +-
 drivers/bus/Kconfig                           |    9 +
 drivers/bus/Makefile                          |    1 +
 drivers/bus/stm32_sys_bus.c                   |  168 +
 37 files changed, 2208 insertions(+), 1596 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
 create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
 create mode 100644 drivers/bus/stm32_sys_bus.c

-- 
2.35.3


^ permalink raw reply	[flat|nested] 93+ messages in thread

* [PATCH v3 0/6] Introduce STM32 system bus
@ 2023-01-27 16:40 ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.

For every peripheral, the bus checks the firewall registers to see
if the peripheral is configured as non-secure. If the peripheral
is configured as secure, the node is marked populated, so the
device won't be probed.

This is useful as a firewall configuration sanity check and avoid
platform crashes in case peripherals are incorrectly configured.

The STM32 System Bus implements the feature-domain-controller
bindings. It is used by peripherals to reference a domain
controller, in this case the firewall feature domain.
The bus uses the ID referenced by the feature-domains property to
know where to look in the firewall to get the security configuration
for the peripheral. This allows a device tree description rather
than a hardcoded peripheral table in the bus driver.

On STM32MP13/15 platforms, the firewall bus is represented by the
ETZPC node, which is responsible for the securing / MCU isolating
the capable peripherals.

STM32MP13/15 device trees are updated in this series to implement
the bus. All peripherals that are securable or MCU isolation capable
by the ETZPC are connected to the bus.

Changes in V2:
	- Corrected YAMLS errors highlighted by Rob's robot
	- Re-ordered Signed-off-by tags in two patches

Changes in V3:
	- Document feature-domains property in YAML documentation for
	concerned periperals under the System Bus
	- Fix STM32 System Bus YAML documentation
	- Remove STM32 System bus bindings that were currently used
	as helpers for device tree
	- Correct few errors in driver
	- Add missing peripherals under the System Bus that were in
	SoC variation device tree files
	- Fix node names

Gatien Chevallier (5):
  dt-bindings: treewide: add feature-domains description in binding
    files
  dt-bindings: bus: add STM32 System Bus
  bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
  ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards

Oleksii Moisieiev (1):
  dt-bindings: Document common device controller bindings

 .../devicetree/bindings/bus/st,sys-bus.yaml   |  127 +
 .../bindings/crypto/st,stm32-hash.yaml        |    5 +
 .../devicetree/bindings/dma/st,stm32-dma.yaml |    5 +
 .../bindings/dma/st,stm32-dmamux.yaml         |    5 +
 .../feature-domain-controller.yaml            |   84 +
 .../devicetree/bindings/i2c/st,stm32-i2c.yaml |    5 +
 .../bindings/iio/adc/st,stm32-adc.yaml        |    5 +
 .../bindings/iio/adc/st,stm32-dfsdm-adc.yaml  |    5 +
 .../bindings/iio/dac/st,stm32-dac.yaml        |    5 +
 .../bindings/media/st,stm32-cec.yaml          |    5 +
 .../bindings/media/st,stm32-dcmi.yaml         |    5 +
 .../memory-controllers/st,stm32-fmc2-ebi.yaml |    5 +
 .../bindings/mfd/st,stm32-lptimer.yaml        |    5 +
 .../bindings/mfd/st,stm32-timers.yaml         |    6 +
 .../devicetree/bindings/mmc/arm,pl18x.yaml    |    5 +
 .../devicetree/bindings/net/stm32-dwmac.yaml  |    5 +
 .../bindings/phy/phy-stm32-usbphyc.yaml       |    5 +
 .../bindings/regulator/st,stm32-vrefbuf.yaml  |    5 +
 .../devicetree/bindings/rng/st,stm32-rng.yaml |    5 +
 .../bindings/serial/st,stm32-uart.yaml        |    5 +
 .../bindings/sound/st,stm32-i2s.yaml          |    5 +
 .../bindings/sound/st,stm32-sai.yaml          |    5 +
 .../bindings/sound/st,stm32-spdifrx.yaml      |    5 +
 .../bindings/spi/st,stm32-qspi.yaml           |    5 +
 .../devicetree/bindings/spi/st,stm32-spi.yaml |    5 +
 .../devicetree/bindings/usb/dwc2.yaml         |    5 +
 MAINTAINERS                                   |    6 +
 arch/arm/boot/dts/stm32mp131.dtsi             |  407 +--
 arch/arm/boot/dts/stm32mp133.dtsi             |   51 +-
 arch/arm/boot/dts/stm32mp13xc.dtsi            |   19 +-
 arch/arm/boot/dts/stm32mp13xf.dtsi            |   18 +-
 arch/arm/boot/dts/stm32mp151.dtsi             | 2722 +++++++++--------
 arch/arm/boot/dts/stm32mp153.dtsi             |   52 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi            |   19 +-
 drivers/bus/Kconfig                           |    9 +
 drivers/bus/Makefile                          |    1 +
 drivers/bus/stm32_sys_bus.c                   |  168 +
 37 files changed, 2208 insertions(+), 1596 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
 create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
 create mode 100644 drivers/bus/stm32_sys_bus.c

-- 
2.35.3


^ permalink raw reply	[flat|nested] 93+ messages in thread

* [PATCH v3 1/6] dt-bindings: Document common device controller bindings
  2023-01-27 16:40 ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-27 16:40   ` Gatien Chevallier
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Oleksii Moisieiev

From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>

Introducing of the common device controller bindings for the controller
provider and consumer devices. Those bindings are intended to allow
divided system on chip into muliple domains, that can be used to
configure hardware permissions.

Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
---

No change since V1. I'm letting this patch for dependency with bindings to
avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
appropriate thread.

Depends-on: https://lore.kernel.org/lkml/c869d2751125181a55bc8a88c96e3a892b42f37a.1668070216.git.oleksii_moisieiev@epam.com/

 .../feature-domain-controller.yaml            | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml

diff --git a/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
new file mode 100644
index 000000000000..90a7c38c833c
--- /dev/null
+++ b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/feature-controllers/feature-domain-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Domain Controller bindings
+
+maintainers:
+  - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
+
+description: |+
+  Common Feature Domains Controller bindings properties
+
+  Domain controllers allow to divided system on chip into multiple feature
+  domains that can be used to select by who hardware blocks could be accessed.
+  A feature domain could be a cluster of CPUs (or coprocessors), a range of
+  addresses or a group of hardware blocks.
+
+  This device tree bindings can be used to bind feature domain consumer devices
+  with their feature domains provided by feature-domains controllers.
+  Feature omain controller provider can be represened by any node in the
+  device tree and can provide one or more configuration parameters, needed to
+  control parameters of the consumer device. A consumer node can refer to the
+  provider by phandle and a set of phandle arguments, specified by
+  '#feature-domain-cells' property in the device controller provider node.
+
+  Device controllers are typically used to set the permissions of the hardware
+  block. The contents of the feature-domains configuration properties are
+  defined by the binding for the individual feature-domains controller device.
+
+  Each node can be a consumer for the several providers. The first
+  configuration of 'feature-domains' or the one named 'default' is applied
+  before probing the device itself.
+
+# always select the core schema
+select: true
+
+properties:
+  '#feature-domain-cells':
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of cells in a feature-domains controller specifier;
+      Can be any value as specified by device tree binding documentation
+      of a particular provider.
+
+  feature-domain-controller:
+    description:
+      Indicates that the node is feature-domain-controller provider.
+
+  feature-domain-names:
+    $ref: '/schemas/types.yaml#/definitions/string-array'
+    description:
+      A list of feature-domains names, sorted in the same order as
+      feature-domains entries. Consumer drivers will use feature-domain-names
+      to match with existing feature-domains entries.
+
+  feature-domains:
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+    description:
+      A list of feature-domains controller specifiers, as defined by the
+      bindings of the feature-domain-controller provider.
+
+additionalProperties: true
+
+examples:
+  - |
+    ctrl0: ctrl@100 {
+        feature-domain-controller;
+        reg = <0x100 0x10>;
+        #feature-domain-cells = <2>;
+    };
+
+    ctrl1: ctrl@110 {
+        feature-domain-controller;
+        reg = <0x110 0x10>;
+        #feature-domain-cells = <3>;
+    };
+
+    foo@0 {
+        reg = <0x0 0x1>;
+        feature-domains = <&ctrl0 1 2>, <&ctrl1 3 4 5>;
+        feature-domain-names = "default", "unbind";
+    };
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 1/6] dt-bindings: Document common device controller bindings
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Oleksii Moisieiev

From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>

Introducing of the common device controller bindings for the controller
provider and consumer devices. Those bindings are intended to allow
divided system on chip into muliple domains, that can be used to
configure hardware permissions.

Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
---

No change since V1. I'm letting this patch for dependency with bindings to
avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
appropriate thread.

Depends-on: https://lore.kernel.org/lkml/c869d2751125181a55bc8a88c96e3a892b42f37a.1668070216.git.oleksii_moisieiev@epam.com/

 .../feature-domain-controller.yaml            | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml

diff --git a/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
new file mode 100644
index 000000000000..90a7c38c833c
--- /dev/null
+++ b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/feature-controllers/feature-domain-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Domain Controller bindings
+
+maintainers:
+  - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
+
+description: |+
+  Common Feature Domains Controller bindings properties
+
+  Domain controllers allow to divided system on chip into multiple feature
+  domains that can be used to select by who hardware blocks could be accessed.
+  A feature domain could be a cluster of CPUs (or coprocessors), a range of
+  addresses or a group of hardware blocks.
+
+  This device tree bindings can be used to bind feature domain consumer devices
+  with their feature domains provided by feature-domains controllers.
+  Feature omain controller provider can be represened by any node in the
+  device tree and can provide one or more configuration parameters, needed to
+  control parameters of the consumer device. A consumer node can refer to the
+  provider by phandle and a set of phandle arguments, specified by
+  '#feature-domain-cells' property in the device controller provider node.
+
+  Device controllers are typically used to set the permissions of the hardware
+  block. The contents of the feature-domains configuration properties are
+  defined by the binding for the individual feature-domains controller device.
+
+  Each node can be a consumer for the several providers. The first
+  configuration of 'feature-domains' or the one named 'default' is applied
+  before probing the device itself.
+
+# always select the core schema
+select: true
+
+properties:
+  '#feature-domain-cells':
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of cells in a feature-domains controller specifier;
+      Can be any value as specified by device tree binding documentation
+      of a particular provider.
+
+  feature-domain-controller:
+    description:
+      Indicates that the node is feature-domain-controller provider.
+
+  feature-domain-names:
+    $ref: '/schemas/types.yaml#/definitions/string-array'
+    description:
+      A list of feature-domains names, sorted in the same order as
+      feature-domains entries. Consumer drivers will use feature-domain-names
+      to match with existing feature-domains entries.
+
+  feature-domains:
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+    description:
+      A list of feature-domains controller specifiers, as defined by the
+      bindings of the feature-domain-controller provider.
+
+additionalProperties: true
+
+examples:
+  - |
+    ctrl0: ctrl@100 {
+        feature-domain-controller;
+        reg = <0x100 0x10>;
+        #feature-domain-cells = <2>;
+    };
+
+    ctrl1: ctrl@110 {
+        feature-domain-controller;
+        reg = <0x110 0x10>;
+        #feature-domain-cells = <3>;
+    };
+
+    foo@0 {
+        reg = <0x0 0x1>;
+        feature-domains = <&ctrl0 1 2>, <&ctrl1 3 4 5>;
+        feature-domain-names = "default", "unbind";
+    };
-- 
2.35.3


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 1/6] dt-bindings: Document common device controller bindings
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Oleksii Moisieiev

From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>

Introducing of the common device controller bindings for the controller
provider and consumer devices. Those bindings are intended to allow
divided system on chip into muliple domains, that can be used to
configure hardware permissions.

Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
---

No change since V1. I'm letting this patch for dependency with bindings to
avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
appropriate thread.

Depends-on: https://lore.kernel.org/lkml/c869d2751125181a55bc8a88c96e3a892b42f37a.1668070216.git.oleksii_moisieiev@epam.com/

 .../feature-domain-controller.yaml            | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml

diff --git a/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
new file mode 100644
index 000000000000..90a7c38c833c
--- /dev/null
+++ b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/feature-controllers/feature-domain-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Domain Controller bindings
+
+maintainers:
+  - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
+
+description: |+
+  Common Feature Domains Controller bindings properties
+
+  Domain controllers allow to divided system on chip into multiple feature
+  domains that can be used to select by who hardware blocks could be accessed.
+  A feature domain could be a cluster of CPUs (or coprocessors), a range of
+  addresses or a group of hardware blocks.
+
+  This device tree bindings can be used to bind feature domain consumer devices
+  with their feature domains provided by feature-domains controllers.
+  Feature omain controller provider can be represened by any node in the
+  device tree and can provide one or more configuration parameters, needed to
+  control parameters of the consumer device. A consumer node can refer to the
+  provider by phandle and a set of phandle arguments, specified by
+  '#feature-domain-cells' property in the device controller provider node.
+
+  Device controllers are typically used to set the permissions of the hardware
+  block. The contents of the feature-domains configuration properties are
+  defined by the binding for the individual feature-domains controller device.
+
+  Each node can be a consumer for the several providers. The first
+  configuration of 'feature-domains' or the one named 'default' is applied
+  before probing the device itself.
+
+# always select the core schema
+select: true
+
+properties:
+  '#feature-domain-cells':
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of cells in a feature-domains controller specifier;
+      Can be any value as specified by device tree binding documentation
+      of a particular provider.
+
+  feature-domain-controller:
+    description:
+      Indicates that the node is feature-domain-controller provider.
+
+  feature-domain-names:
+    $ref: '/schemas/types.yaml#/definitions/string-array'
+    description:
+      A list of feature-domains names, sorted in the same order as
+      feature-domains entries. Consumer drivers will use feature-domain-names
+      to match with existing feature-domains entries.
+
+  feature-domains:
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+    description:
+      A list of feature-domains controller specifiers, as defined by the
+      bindings of the feature-domain-controller provider.
+
+additionalProperties: true
+
+examples:
+  - |
+    ctrl0: ctrl@100 {
+        feature-domain-controller;
+        reg = <0x100 0x10>;
+        #feature-domain-cells = <2>;
+    };
+
+    ctrl1: ctrl@110 {
+        feature-domain-controller;
+        reg = <0x110 0x10>;
+        #feature-domain-cells = <3>;
+    };
+
+    foo@0 {
+        reg = <0x0 0x1>;
+        feature-domains = <&ctrl0 1 2>, <&ctrl1 3 4 5>;
+        feature-domain-names = "default", "unbind";
+    };
-- 
2.35.3


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 1/6] dt-bindings: Document common device controller bindings
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-phy, Oleksii Moisieiev,
	linux-crypto, linux-serial, dmaengine, linux-media, linux-stm32,
	linux-arm-kernel, linux-i2c

From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>

Introducing of the common device controller bindings for the controller
provider and consumer devices. Those bindings are intended to allow
divided system on chip into muliple domains, that can be used to
configure hardware permissions.

Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
---

No change since V1. I'm letting this patch for dependency with bindings to
avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
appropriate thread.

Depends-on: https://lore.kernel.org/lkml/c869d2751125181a55bc8a88c96e3a892b42f37a.1668070216.git.oleksii_moisieiev@epam.com/

 .../feature-domain-controller.yaml            | 84 +++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml

diff --git a/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
new file mode 100644
index 000000000000..90a7c38c833c
--- /dev/null
+++ b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/feature-controllers/feature-domain-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Domain Controller bindings
+
+maintainers:
+  - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
+
+description: |+
+  Common Feature Domains Controller bindings properties
+
+  Domain controllers allow to divided system on chip into multiple feature
+  domains that can be used to select by who hardware blocks could be accessed.
+  A feature domain could be a cluster of CPUs (or coprocessors), a range of
+  addresses or a group of hardware blocks.
+
+  This device tree bindings can be used to bind feature domain consumer devices
+  with their feature domains provided by feature-domains controllers.
+  Feature omain controller provider can be represened by any node in the
+  device tree and can provide one or more configuration parameters, needed to
+  control parameters of the consumer device. A consumer node can refer to the
+  provider by phandle and a set of phandle arguments, specified by
+  '#feature-domain-cells' property in the device controller provider node.
+
+  Device controllers are typically used to set the permissions of the hardware
+  block. The contents of the feature-domains configuration properties are
+  defined by the binding for the individual feature-domains controller device.
+
+  Each node can be a consumer for the several providers. The first
+  configuration of 'feature-domains' or the one named 'default' is applied
+  before probing the device itself.
+
+# always select the core schema
+select: true
+
+properties:
+  '#feature-domain-cells':
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Number of cells in a feature-domains controller specifier;
+      Can be any value as specified by device tree binding documentation
+      of a particular provider.
+
+  feature-domain-controller:
+    description:
+      Indicates that the node is feature-domain-controller provider.
+
+  feature-domain-names:
+    $ref: '/schemas/types.yaml#/definitions/string-array'
+    description:
+      A list of feature-domains names, sorted in the same order as
+      feature-domains entries. Consumer drivers will use feature-domain-names
+      to match with existing feature-domains entries.
+
+  feature-domains:
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+    description:
+      A list of feature-domains controller specifiers, as defined by the
+      bindings of the feature-domain-controller provider.
+
+additionalProperties: true
+
+examples:
+  - |
+    ctrl0: ctrl@100 {
+        feature-domain-controller;
+        reg = <0x100 0x10>;
+        #feature-domain-cells = <2>;
+    };
+
+    ctrl1: ctrl@110 {
+        feature-domain-controller;
+        reg = <0x110 0x10>;
+        #feature-domain-cells = <3>;
+    };
+
+    foo@0 {
+        reg = <0x0 0x1>;
+        feature-domains = <&ctrl0 1 2>, <&ctrl1 3 4 5>;
+        feature-domain-names = "default", "unbind";
+    };
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
  2023-01-27 16:40 ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-27 16:40   ` Gatien Chevallier
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

feature-domains is an optional property that allows a peripheral to
refer to one or more feature domain controller(s).

Description of this property is added to all peripheral binding files of
the peripheral under the STM32 System Bus. It allows an accurate
representation of the hardware, where various peripherals are connected
to this firewall bus. The firewall can then check the peripheral accesses
before allowing it to probe.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

Patch not present in V1 and V2.

 Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 5 +++++
 Documentation/devicetree/bindings/dma/st,stm32-dma.yaml     | 5 +++++
 Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml  | 5 +++++
 Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml     | 5 +++++
 Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 5 +++++
 .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml     | 5 +++++
 Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 5 +++++
 Documentation/devicetree/bindings/media/st,stm32-cec.yaml   | 5 +++++
 Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml  | 5 +++++
 .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml      | 5 +++++
 Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 5 +++++
 Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml  | 6 ++++++
 Documentation/devicetree/bindings/mmc/arm,pl18x.yaml        | 5 +++++
 Documentation/devicetree/bindings/net/stm32-dwmac.yaml      | 5 +++++
 .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml          | 5 +++++
 .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml     | 5 +++++
 Documentation/devicetree/bindings/rng/st,stm32-rng.yaml     | 5 +++++
 Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 5 +++++
 Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml   | 5 +++++
 Documentation/devicetree/bindings/sound/st,stm32-sai.yaml   | 5 +++++
 .../devicetree/bindings/sound/st,stm32-spdifrx.yaml         | 5 +++++
 Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml    | 5 +++++
 Documentation/devicetree/bindings/spi/st,stm32-spi.yaml     | 5 +++++
 Documentation/devicetree/bindings/usb/dwc2.yaml             | 5 +++++
 24 files changed, 121 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
index 4ccb335e8063..cb2ad7d5fdb5 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
@@ -41,6 +41,11 @@ properties:
     maximum: 2
     default: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
index 158c791d7caa..3df6c3c998bc 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
@@ -82,6 +82,11 @@ properties:
     description: if defined, it indicates that the controller
       supports memory-to-memory transfer
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
index 3e0b82d277ca..73a06651ec94 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
@@ -28,6 +28,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
index bf396e9466aa..126576200e1f 100644
--- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
@@ -99,6 +99,11 @@ properties:
 
   wakeup-source: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
index 1c340c95df16..c68b7b0e1903 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
@@ -93,6 +93,11 @@ properties:
   '#size-cells':
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 allOf:
   - if:
       properties:
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index 1970503389aa..d01f60765e48 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -59,6 +59,11 @@ properties:
       If not, SPI CLKOUT frequency will not be accurate.
     maximum: 20000000
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
index 0f1bf1110122..f6fe58d2f9b8 100644
--- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
@@ -45,6 +45,11 @@ properties:
   '#size-cells':
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 additionalProperties: false
 
 required:
diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
index 7f545a587a39..719f4f38afcf 100644
--- a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
+++ b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
@@ -29,6 +29,11 @@ properties:
       - const: cec
       - const: hdmi-cec
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
index 6b3e413cedb2..49001646663b 100644
--- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
+++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
@@ -36,6 +36,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   port:
     $ref: /schemas/graph.yaml#/$defs/port-base
     unevaluatedProperties: false
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
index e76ba767dfd2..565e7d2fe164 100644
--- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
@@ -45,6 +45,11 @@ properties:
       Reflects the memory layout with four integer values per bank. Format:
       <bank-number> 0 <address of the bank> <size>
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 patternProperties:
   "^.*@[0-4],[a-f0-9]+$":
     type: object
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
index 27329c5dc38e..9649c672c9a5 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
@@ -44,6 +44,11 @@ properties:
 
   wakeup-source: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   pwm:
     type: object
     additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
index f84e09a5743b..897e805fde49 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
@@ -67,6 +67,12 @@ properties:
   "#size-cells":
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
+
   pwm:
     type: object
     additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
index 1c96da04f0e5..43c546d1a0cd 100644
--- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
+++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
@@ -78,6 +78,11 @@ properties:
           - const: rx
           - const: tx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   power-domains: true
 
   resets:
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index 5c93167b3b41..d39b2efd186a 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -93,6 +93,11 @@ properties:
       select RCC clock instead of ETH_REF_CLK.
     type: boolean
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - clocks
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 5b4c915cc9e5..9bd81cde2fa9 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -55,6 +55,11 @@ properties:
     description: number of clock cells for ck_usbo_48m consumer
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 #Required child nodes:
 
 patternProperties:
diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
index c1bf1f90490a..77ac6409ee60 100644
--- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
+++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
@@ -30,6 +30,11 @@ properties:
   vdda-supply:
     description: phandle to the vdda input analog voltage.
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
index 187b172d0cca..9f75537e11d0 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
@@ -30,6 +30,11 @@ properties:
     type: boolean
     description: If set enable the clock detection management
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 85876c668f6d..f528f284e448 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -77,6 +77,11 @@ properties:
     enum: [1, 2, 4, 8, 12, 14, 16]
     default: 8
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 allOf:
   - $ref: rs485.yaml#
   - $ref: serial.yaml#
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
index a040d4d31412..aee8b09ec264 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
@@ -61,6 +61,11 @@ properties:
     description: Configure the I2S device as MCLK clock provider.
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
index 56d206f97a96..f16fd41eed02 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
@@ -48,6 +48,11 @@ properties:
   clock-names:
     maxItems: 3
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
index bc48151b9adb..8b1da025565c 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
@@ -50,6 +50,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
index 1eb17f7a4d86..ef75e9aed120 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
@@ -46,6 +46,11 @@ properties:
       - const: tx
       - const: rx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
index 1cda15f91cc3..6bda605b2ecb 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
@@ -59,6 +59,11 @@ properties:
       - const: rx
       - const: tx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 patternProperties:
   "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
     type: object
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 371ba93f3ce5..f5092a2846b4 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -168,6 +168,11 @@ properties:
 
   tpl-support: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 dependencies:
   port: [ usb-role-switch ]
   role-switch-default-mode: [ usb-role-switch ]
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

feature-domains is an optional property that allows a peripheral to
refer to one or more feature domain controller(s).

Description of this property is added to all peripheral binding files of
the peripheral under the STM32 System Bus. It allows an accurate
representation of the hardware, where various peripherals are connected
to this firewall bus. The firewall can then check the peripheral accesses
before allowing it to probe.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

Patch not present in V1 and V2.

 Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 5 +++++
 Documentation/devicetree/bindings/dma/st,stm32-dma.yaml     | 5 +++++
 Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml  | 5 +++++
 Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml     | 5 +++++
 Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 5 +++++
 .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml     | 5 +++++
 Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 5 +++++
 Documentation/devicetree/bindings/media/st,stm32-cec.yaml   | 5 +++++
 Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml  | 5 +++++
 .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml      | 5 +++++
 Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 5 +++++
 Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml  | 6 ++++++
 Documentation/devicetree/bindings/mmc/arm,pl18x.yaml        | 5 +++++
 Documentation/devicetree/bindings/net/stm32-dwmac.yaml      | 5 +++++
 .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml          | 5 +++++
 .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml     | 5 +++++
 Documentation/devicetree/bindings/rng/st,stm32-rng.yaml     | 5 +++++
 Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 5 +++++
 Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml   | 5 +++++
 Documentation/devicetree/bindings/sound/st,stm32-sai.yaml   | 5 +++++
 .../devicetree/bindings/sound/st,stm32-spdifrx.yaml         | 5 +++++
 Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml    | 5 +++++
 Documentation/devicetree/bindings/spi/st,stm32-spi.yaml     | 5 +++++
 Documentation/devicetree/bindings/usb/dwc2.yaml             | 5 +++++
 24 files changed, 121 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
index 4ccb335e8063..cb2ad7d5fdb5 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
@@ -41,6 +41,11 @@ properties:
     maximum: 2
     default: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
index 158c791d7caa..3df6c3c998bc 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
@@ -82,6 +82,11 @@ properties:
     description: if defined, it indicates that the controller
       supports memory-to-memory transfer
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
index 3e0b82d277ca..73a06651ec94 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
@@ -28,6 +28,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
index bf396e9466aa..126576200e1f 100644
--- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
@@ -99,6 +99,11 @@ properties:
 
   wakeup-source: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
index 1c340c95df16..c68b7b0e1903 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
@@ -93,6 +93,11 @@ properties:
   '#size-cells':
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 allOf:
   - if:
       properties:
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index 1970503389aa..d01f60765e48 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -59,6 +59,11 @@ properties:
       If not, SPI CLKOUT frequency will not be accurate.
     maximum: 20000000
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
index 0f1bf1110122..f6fe58d2f9b8 100644
--- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
@@ -45,6 +45,11 @@ properties:
   '#size-cells':
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 additionalProperties: false
 
 required:
diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
index 7f545a587a39..719f4f38afcf 100644
--- a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
+++ b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
@@ -29,6 +29,11 @@ properties:
       - const: cec
       - const: hdmi-cec
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
index 6b3e413cedb2..49001646663b 100644
--- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
+++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
@@ -36,6 +36,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   port:
     $ref: /schemas/graph.yaml#/$defs/port-base
     unevaluatedProperties: false
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
index e76ba767dfd2..565e7d2fe164 100644
--- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
@@ -45,6 +45,11 @@ properties:
       Reflects the memory layout with four integer values per bank. Format:
       <bank-number> 0 <address of the bank> <size>
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 patternProperties:
   "^.*@[0-4],[a-f0-9]+$":
     type: object
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
index 27329c5dc38e..9649c672c9a5 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
@@ -44,6 +44,11 @@ properties:
 
   wakeup-source: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   pwm:
     type: object
     additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
index f84e09a5743b..897e805fde49 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
@@ -67,6 +67,12 @@ properties:
   "#size-cells":
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
+
   pwm:
     type: object
     additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
index 1c96da04f0e5..43c546d1a0cd 100644
--- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
+++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
@@ -78,6 +78,11 @@ properties:
           - const: rx
           - const: tx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   power-domains: true
 
   resets:
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index 5c93167b3b41..d39b2efd186a 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -93,6 +93,11 @@ properties:
       select RCC clock instead of ETH_REF_CLK.
     type: boolean
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - clocks
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 5b4c915cc9e5..9bd81cde2fa9 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -55,6 +55,11 @@ properties:
     description: number of clock cells for ck_usbo_48m consumer
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 #Required child nodes:
 
 patternProperties:
diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
index c1bf1f90490a..77ac6409ee60 100644
--- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
+++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
@@ -30,6 +30,11 @@ properties:
   vdda-supply:
     description: phandle to the vdda input analog voltage.
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
index 187b172d0cca..9f75537e11d0 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
@@ -30,6 +30,11 @@ properties:
     type: boolean
     description: If set enable the clock detection management
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 85876c668f6d..f528f284e448 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -77,6 +77,11 @@ properties:
     enum: [1, 2, 4, 8, 12, 14, 16]
     default: 8
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 allOf:
   - $ref: rs485.yaml#
   - $ref: serial.yaml#
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
index a040d4d31412..aee8b09ec264 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
@@ -61,6 +61,11 @@ properties:
     description: Configure the I2S device as MCLK clock provider.
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
index 56d206f97a96..f16fd41eed02 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
@@ -48,6 +48,11 @@ properties:
   clock-names:
     maxItems: 3
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
index bc48151b9adb..8b1da025565c 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
@@ -50,6 +50,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
index 1eb17f7a4d86..ef75e9aed120 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
@@ -46,6 +46,11 @@ properties:
       - const: tx
       - const: rx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
index 1cda15f91cc3..6bda605b2ecb 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
@@ -59,6 +59,11 @@ properties:
       - const: rx
       - const: tx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 patternProperties:
   "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
     type: object
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 371ba93f3ce5..f5092a2846b4 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -168,6 +168,11 @@ properties:
 
   tpl-support: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 dependencies:
   port: [ usb-role-switch ]
   role-switch-default-mode: [ usb-role-switch ]
-- 
2.35.3


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

feature-domains is an optional property that allows a peripheral to
refer to one or more feature domain controller(s).

Description of this property is added to all peripheral binding files of
the peripheral under the STM32 System Bus. It allows an accurate
representation of the hardware, where various peripherals are connected
to this firewall bus. The firewall can then check the peripheral accesses
before allowing it to probe.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

Patch not present in V1 and V2.

 Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 5 +++++
 Documentation/devicetree/bindings/dma/st,stm32-dma.yaml     | 5 +++++
 Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml  | 5 +++++
 Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml     | 5 +++++
 Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 5 +++++
 .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml     | 5 +++++
 Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 5 +++++
 Documentation/devicetree/bindings/media/st,stm32-cec.yaml   | 5 +++++
 Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml  | 5 +++++
 .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml      | 5 +++++
 Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 5 +++++
 Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml  | 6 ++++++
 Documentation/devicetree/bindings/mmc/arm,pl18x.yaml        | 5 +++++
 Documentation/devicetree/bindings/net/stm32-dwmac.yaml      | 5 +++++
 .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml          | 5 +++++
 .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml     | 5 +++++
 Documentation/devicetree/bindings/rng/st,stm32-rng.yaml     | 5 +++++
 Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 5 +++++
 Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml   | 5 +++++
 Documentation/devicetree/bindings/sound/st,stm32-sai.yaml   | 5 +++++
 .../devicetree/bindings/sound/st,stm32-spdifrx.yaml         | 5 +++++
 Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml    | 5 +++++
 Documentation/devicetree/bindings/spi/st,stm32-spi.yaml     | 5 +++++
 Documentation/devicetree/bindings/usb/dwc2.yaml             | 5 +++++
 24 files changed, 121 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
index 4ccb335e8063..cb2ad7d5fdb5 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
@@ -41,6 +41,11 @@ properties:
     maximum: 2
     default: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
index 158c791d7caa..3df6c3c998bc 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
@@ -82,6 +82,11 @@ properties:
     description: if defined, it indicates that the controller
       supports memory-to-memory transfer
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
index 3e0b82d277ca..73a06651ec94 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
@@ -28,6 +28,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
index bf396e9466aa..126576200e1f 100644
--- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
@@ -99,6 +99,11 @@ properties:
 
   wakeup-source: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
index 1c340c95df16..c68b7b0e1903 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
@@ -93,6 +93,11 @@ properties:
   '#size-cells':
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 allOf:
   - if:
       properties:
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index 1970503389aa..d01f60765e48 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -59,6 +59,11 @@ properties:
       If not, SPI CLKOUT frequency will not be accurate.
     maximum: 20000000
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
index 0f1bf1110122..f6fe58d2f9b8 100644
--- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
@@ -45,6 +45,11 @@ properties:
   '#size-cells':
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 additionalProperties: false
 
 required:
diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
index 7f545a587a39..719f4f38afcf 100644
--- a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
+++ b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
@@ -29,6 +29,11 @@ properties:
       - const: cec
       - const: hdmi-cec
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
index 6b3e413cedb2..49001646663b 100644
--- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
+++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
@@ -36,6 +36,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   port:
     $ref: /schemas/graph.yaml#/$defs/port-base
     unevaluatedProperties: false
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
index e76ba767dfd2..565e7d2fe164 100644
--- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
@@ -45,6 +45,11 @@ properties:
       Reflects the memory layout with four integer values per bank. Format:
       <bank-number> 0 <address of the bank> <size>
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 patternProperties:
   "^.*@[0-4],[a-f0-9]+$":
     type: object
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
index 27329c5dc38e..9649c672c9a5 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
@@ -44,6 +44,11 @@ properties:
 
   wakeup-source: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   pwm:
     type: object
     additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
index f84e09a5743b..897e805fde49 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
@@ -67,6 +67,12 @@ properties:
   "#size-cells":
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
+
   pwm:
     type: object
     additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
index 1c96da04f0e5..43c546d1a0cd 100644
--- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
+++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
@@ -78,6 +78,11 @@ properties:
           - const: rx
           - const: tx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   power-domains: true
 
   resets:
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index 5c93167b3b41..d39b2efd186a 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -93,6 +93,11 @@ properties:
       select RCC clock instead of ETH_REF_CLK.
     type: boolean
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - clocks
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 5b4c915cc9e5..9bd81cde2fa9 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -55,6 +55,11 @@ properties:
     description: number of clock cells for ck_usbo_48m consumer
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 #Required child nodes:
 
 patternProperties:
diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
index c1bf1f90490a..77ac6409ee60 100644
--- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
+++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
@@ -30,6 +30,11 @@ properties:
   vdda-supply:
     description: phandle to the vdda input analog voltage.
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
index 187b172d0cca..9f75537e11d0 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
@@ -30,6 +30,11 @@ properties:
     type: boolean
     description: If set enable the clock detection management
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 85876c668f6d..f528f284e448 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -77,6 +77,11 @@ properties:
     enum: [1, 2, 4, 8, 12, 14, 16]
     default: 8
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 allOf:
   - $ref: rs485.yaml#
   - $ref: serial.yaml#
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
index a040d4d31412..aee8b09ec264 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
@@ -61,6 +61,11 @@ properties:
     description: Configure the I2S device as MCLK clock provider.
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
index 56d206f97a96..f16fd41eed02 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
@@ -48,6 +48,11 @@ properties:
   clock-names:
     maxItems: 3
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
index bc48151b9adb..8b1da025565c 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
@@ -50,6 +50,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
index 1eb17f7a4d86..ef75e9aed120 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
@@ -46,6 +46,11 @@ properties:
       - const: tx
       - const: rx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
index 1cda15f91cc3..6bda605b2ecb 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
@@ -59,6 +59,11 @@ properties:
       - const: rx
       - const: tx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 patternProperties:
   "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
     type: object
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 371ba93f3ce5..f5092a2846b4 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -168,6 +168,11 @@ properties:
 
   tpl-support: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 dependencies:
   port: [ usb-role-switch ]
   role-switch-default-mode: [ usb-role-switch ]
-- 
2.35.3


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, Gatien Chevallier, linux-iio, netdev,
	linux-usb, linux-mmc, linux-kernel, linux-spi, linux-phy,
	linux-crypto, linux-serial, dmaengine, linux-media, linux-stm32,
	linux-arm-kernel, linux-i2c

feature-domains is an optional property that allows a peripheral to
refer to one or more feature domain controller(s).

Description of this property is added to all peripheral binding files of
the peripheral under the STM32 System Bus. It allows an accurate
representation of the hardware, where various peripherals are connected
to this firewall bus. The firewall can then check the peripheral accesses
before allowing it to probe.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

Patch not present in V1 and V2.

 Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 5 +++++
 Documentation/devicetree/bindings/dma/st,stm32-dma.yaml     | 5 +++++
 Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml  | 5 +++++
 Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml     | 5 +++++
 Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 5 +++++
 .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml     | 5 +++++
 Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 5 +++++
 Documentation/devicetree/bindings/media/st,stm32-cec.yaml   | 5 +++++
 Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml  | 5 +++++
 .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml      | 5 +++++
 Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 5 +++++
 Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml  | 6 ++++++
 Documentation/devicetree/bindings/mmc/arm,pl18x.yaml        | 5 +++++
 Documentation/devicetree/bindings/net/stm32-dwmac.yaml      | 5 +++++
 .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml          | 5 +++++
 .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml     | 5 +++++
 Documentation/devicetree/bindings/rng/st,stm32-rng.yaml     | 5 +++++
 Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 5 +++++
 Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml   | 5 +++++
 Documentation/devicetree/bindings/sound/st,stm32-sai.yaml   | 5 +++++
 .../devicetree/bindings/sound/st,stm32-spdifrx.yaml         | 5 +++++
 Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml    | 5 +++++
 Documentation/devicetree/bindings/spi/st,stm32-spi.yaml     | 5 +++++
 Documentation/devicetree/bindings/usb/dwc2.yaml             | 5 +++++
 24 files changed, 121 insertions(+)

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
index 4ccb335e8063..cb2ad7d5fdb5 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
@@ -41,6 +41,11 @@ properties:
     maximum: 2
     default: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
index 158c791d7caa..3df6c3c998bc 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
@@ -82,6 +82,11 @@ properties:
     description: if defined, it indicates that the controller
       supports memory-to-memory transfer
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
index 3e0b82d277ca..73a06651ec94 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
@@ -28,6 +28,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
index bf396e9466aa..126576200e1f 100644
--- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
@@ -99,6 +99,11 @@ properties:
 
   wakeup-source: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
index 1c340c95df16..c68b7b0e1903 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
@@ -93,6 +93,11 @@ properties:
   '#size-cells':
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 allOf:
   - if:
       properties:
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index 1970503389aa..d01f60765e48 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -59,6 +59,11 @@ properties:
       If not, SPI CLKOUT frequency will not be accurate.
     maximum: 20000000
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
index 0f1bf1110122..f6fe58d2f9b8 100644
--- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
@@ -45,6 +45,11 @@ properties:
   '#size-cells':
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 additionalProperties: false
 
 required:
diff --git a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
index 7f545a587a39..719f4f38afcf 100644
--- a/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
+++ b/Documentation/devicetree/bindings/media/st,stm32-cec.yaml
@@ -29,6 +29,11 @@ properties:
       - const: cec
       - const: hdmi-cec
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
index 6b3e413cedb2..49001646663b 100644
--- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
+++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
@@ -36,6 +36,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   port:
     $ref: /schemas/graph.yaml#/$defs/port-base
     unevaluatedProperties: false
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
index e76ba767dfd2..565e7d2fe164 100644
--- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
@@ -45,6 +45,11 @@ properties:
       Reflects the memory layout with four integer values per bank. Format:
       <bank-number> 0 <address of the bank> <size>
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 patternProperties:
   "^.*@[0-4],[a-f0-9]+$":
     type: object
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
index 27329c5dc38e..9649c672c9a5 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
@@ -44,6 +44,11 @@ properties:
 
   wakeup-source: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   pwm:
     type: object
     additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
index f84e09a5743b..897e805fde49 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
@@ -67,6 +67,12 @@ properties:
   "#size-cells":
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
+
   pwm:
     type: object
     additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
index 1c96da04f0e5..43c546d1a0cd 100644
--- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
+++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
@@ -78,6 +78,11 @@ properties:
           - const: rx
           - const: tx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
   power-domains: true
 
   resets:
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index 5c93167b3b41..d39b2efd186a 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -93,6 +93,11 @@ properties:
       select RCC clock instead of ETH_REF_CLK.
     type: boolean
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - clocks
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 5b4c915cc9e5..9bd81cde2fa9 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -55,6 +55,11 @@ properties:
     description: number of clock cells for ck_usbo_48m consumer
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 #Required child nodes:
 
 patternProperties:
diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
index c1bf1f90490a..77ac6409ee60 100644
--- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
+++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
@@ -30,6 +30,11 @@ properties:
   vdda-supply:
     description: phandle to the vdda input analog voltage.
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
index 187b172d0cca..9f75537e11d0 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
@@ -30,6 +30,11 @@ properties:
     type: boolean
     description: If set enable the clock detection management
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 85876c668f6d..f528f284e448 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -77,6 +77,11 @@ properties:
     enum: [1, 2, 4, 8, 12, 14, 16]
     default: 8
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 allOf:
   - $ref: rs485.yaml#
   - $ref: serial.yaml#
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
index a040d4d31412..aee8b09ec264 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
@@ -61,6 +61,11 @@ properties:
     description: Configure the I2S device as MCLK clock provider.
     const: 0
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
index 56d206f97a96..f16fd41eed02 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
@@ -48,6 +48,11 @@ properties:
   clock-names:
     maxItems: 3
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
index bc48151b9adb..8b1da025565c 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
@@ -50,6 +50,11 @@ properties:
   resets:
     maxItems: 1
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
index 1eb17f7a4d86..ef75e9aed120 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
@@ -46,6 +46,11 @@ properties:
       - const: tx
       - const: rx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
index 1cda15f91cc3..6bda605b2ecb 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
@@ -59,6 +59,11 @@ properties:
       - const: rx
       - const: tx
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 patternProperties:
   "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
     type: object
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 371ba93f3ce5..f5092a2846b4 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -168,6 +168,11 @@ properties:
 
   tpl-support: true
 
+  feature-domains:
+    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+    minItems: 1
+    maxItems: 3
+
 dependencies:
   port: [ usb-role-switch ]
   role-switch-default-mode: [ usb-role-switch ]
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
  2023-01-27 16:40 ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-27 16:40   ` Gatien Chevallier
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier, Loic PALLARDY

Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---

Changes in V2: 
	- Corrected errors highlighted by Rob's robot
	- Re-ordered Signed-off-by tags
	
Changes in V3:
	- Correct #feature-domain-cells
	- Declare 1 as minimum number of arguments for feature-domains property
	in bus subnodes and 3 as maximum.
	- Change example to be a real usecase.

 .../devicetree/bindings/bus/st,sys-bus.yaml   | 127 ++++++++++++++++++
 1 file changed, 127 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml

diff --git a/Documentation/devicetree/bindings/bus/st,sys-bus.yaml b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
new file mode 100644
index 000000000000..c1510784b79b
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,sys-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 System Bus
+
+description: |
+  The STM32 System Bus is an internal bus to which some internal peripherals
+  are connected. STM32 System Bus integrates a firewall controlling access to each
+  device. This bus prevents non-accessible devices to be probed.
+
+  To see which peripherals are securable, please check the SoC reference manual.
+
+maintainers:
+  - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+allOf:
+  - $ref: /schemas/feature-controllers/feature-domain-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - st,stm32mp13-sys-bus
+      - st,stm32mp15-sys-bus
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  "#feature-domain-cells":
+    const: 1
+
+  ranges: true
+
+  feature-domain-controller: true
+
+patternProperties:
+  "^.*@[0-9a-f]+$":
+    description: Devices attached to system bus
+    type: object
+    properties:
+      feature-domains:
+        $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+        minItems: 1
+        maxItems: 3
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - feature-domain-controller
+  - "#feature-domain-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    // In this example, the rng1 device refers to etzpc as its domain controller.
+    // Same goes for fmc.
+    // Access rights are verified before creating devices.
+
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/stm32mp1-clks.h>
+    #include <dt-bindings/reset/stm32mp1-resets.h>
+
+    etzpc: bus@5c007000 {
+        compatible = "st,stm32mp15-sys-bus";
+        reg = <0x5c007000 0x400>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        feature-domain-controller;
+        #feature-domain-cells = <1>;
+
+        rng1: rng@54003000 {
+          compatible = "st,stm32-rng";
+          reg = <0x54003000 0x400>;
+          clocks = <&rcc RNG1_K>;
+          resets = <&rcc RNG1_R>;
+          feature-domains = <&etzpc 7>;
+          status = "disabled";
+        };
+
+        fmc: memory-controller@58002000 {
+          #address-cells = <2>;
+          #size-cells = <1>;
+          compatible = "st,stm32mp1-fmc2-ebi";
+          reg = <0x58002000 0x1000>;
+          clocks = <&rcc FMC_K>;
+          resets = <&rcc FMC_R>;
+          feature-domains = <&etzpc 91>;
+          status = "disabled";
+
+          ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+                   <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+                   <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+                   <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+                   <4 0 0x80000000 0x10000000>; /* NAND */
+
+          nand-controller@4,0 {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            compatible = "st,stm32mp1-fmc2-nfc";
+            reg = <4 0x00000000 0x1000>,
+                  <4 0x08010000 0x1000>,
+                  <4 0x08020000 0x1000>,
+                  <4 0x01000000 0x1000>,
+                  <4 0x09010000 0x1000>,
+                  <4 0x09020000 0x1000>;
+            interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+            dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+                   <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+                   <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+            dma-names = "tx", "rx", "ecc";
+            status = "disabled";
+          };
+        };
+    };
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier, Loic PALLARDY

Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---

Changes in V2: 
	- Corrected errors highlighted by Rob's robot
	- Re-ordered Signed-off-by tags
	
Changes in V3:
	- Correct #feature-domain-cells
	- Declare 1 as minimum number of arguments for feature-domains property
	in bus subnodes and 3 as maximum.
	- Change example to be a real usecase.

 .../devicetree/bindings/bus/st,sys-bus.yaml   | 127 ++++++++++++++++++
 1 file changed, 127 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml

diff --git a/Documentation/devicetree/bindings/bus/st,sys-bus.yaml b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
new file mode 100644
index 000000000000..c1510784b79b
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,sys-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 System Bus
+
+description: |
+  The STM32 System Bus is an internal bus to which some internal peripherals
+  are connected. STM32 System Bus integrates a firewall controlling access to each
+  device. This bus prevents non-accessible devices to be probed.
+
+  To see which peripherals are securable, please check the SoC reference manual.
+
+maintainers:
+  - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+allOf:
+  - $ref: /schemas/feature-controllers/feature-domain-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - st,stm32mp13-sys-bus
+      - st,stm32mp15-sys-bus
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  "#feature-domain-cells":
+    const: 1
+
+  ranges: true
+
+  feature-domain-controller: true
+
+patternProperties:
+  "^.*@[0-9a-f]+$":
+    description: Devices attached to system bus
+    type: object
+    properties:
+      feature-domains:
+        $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+        minItems: 1
+        maxItems: 3
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - feature-domain-controller
+  - "#feature-domain-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    // In this example, the rng1 device refers to etzpc as its domain controller.
+    // Same goes for fmc.
+    // Access rights are verified before creating devices.
+
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/stm32mp1-clks.h>
+    #include <dt-bindings/reset/stm32mp1-resets.h>
+
+    etzpc: bus@5c007000 {
+        compatible = "st,stm32mp15-sys-bus";
+        reg = <0x5c007000 0x400>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        feature-domain-controller;
+        #feature-domain-cells = <1>;
+
+        rng1: rng@54003000 {
+          compatible = "st,stm32-rng";
+          reg = <0x54003000 0x400>;
+          clocks = <&rcc RNG1_K>;
+          resets = <&rcc RNG1_R>;
+          feature-domains = <&etzpc 7>;
+          status = "disabled";
+        };
+
+        fmc: memory-controller@58002000 {
+          #address-cells = <2>;
+          #size-cells = <1>;
+          compatible = "st,stm32mp1-fmc2-ebi";
+          reg = <0x58002000 0x1000>;
+          clocks = <&rcc FMC_K>;
+          resets = <&rcc FMC_R>;
+          feature-domains = <&etzpc 91>;
+          status = "disabled";
+
+          ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+                   <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+                   <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+                   <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+                   <4 0 0x80000000 0x10000000>; /* NAND */
+
+          nand-controller@4,0 {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            compatible = "st,stm32mp1-fmc2-nfc";
+            reg = <4 0x00000000 0x1000>,
+                  <4 0x08010000 0x1000>,
+                  <4 0x08020000 0x1000>,
+                  <4 0x01000000 0x1000>,
+                  <4 0x09010000 0x1000>,
+                  <4 0x09020000 0x1000>;
+            interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+            dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+                   <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+                   <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+            dma-names = "tx", "rx", "ecc";
+            status = "disabled";
+          };
+        };
+    };
-- 
2.35.3


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier, Loic PALLARDY

Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---

Changes in V2: 
	- Corrected errors highlighted by Rob's robot
	- Re-ordered Signed-off-by tags
	
Changes in V3:
	- Correct #feature-domain-cells
	- Declare 1 as minimum number of arguments for feature-domains property
	in bus subnodes and 3 as maximum.
	- Change example to be a real usecase.

 .../devicetree/bindings/bus/st,sys-bus.yaml   | 127 ++++++++++++++++++
 1 file changed, 127 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml

diff --git a/Documentation/devicetree/bindings/bus/st,sys-bus.yaml b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
new file mode 100644
index 000000000000..c1510784b79b
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,sys-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 System Bus
+
+description: |
+  The STM32 System Bus is an internal bus to which some internal peripherals
+  are connected. STM32 System Bus integrates a firewall controlling access to each
+  device. This bus prevents non-accessible devices to be probed.
+
+  To see which peripherals are securable, please check the SoC reference manual.
+
+maintainers:
+  - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+allOf:
+  - $ref: /schemas/feature-controllers/feature-domain-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - st,stm32mp13-sys-bus
+      - st,stm32mp15-sys-bus
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  "#feature-domain-cells":
+    const: 1
+
+  ranges: true
+
+  feature-domain-controller: true
+
+patternProperties:
+  "^.*@[0-9a-f]+$":
+    description: Devices attached to system bus
+    type: object
+    properties:
+      feature-domains:
+        $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+        minItems: 1
+        maxItems: 3
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - feature-domain-controller
+  - "#feature-domain-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    // In this example, the rng1 device refers to etzpc as its domain controller.
+    // Same goes for fmc.
+    // Access rights are verified before creating devices.
+
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/stm32mp1-clks.h>
+    #include <dt-bindings/reset/stm32mp1-resets.h>
+
+    etzpc: bus@5c007000 {
+        compatible = "st,stm32mp15-sys-bus";
+        reg = <0x5c007000 0x400>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        feature-domain-controller;
+        #feature-domain-cells = <1>;
+
+        rng1: rng@54003000 {
+          compatible = "st,stm32-rng";
+          reg = <0x54003000 0x400>;
+          clocks = <&rcc RNG1_K>;
+          resets = <&rcc RNG1_R>;
+          feature-domains = <&etzpc 7>;
+          status = "disabled";
+        };
+
+        fmc: memory-controller@58002000 {
+          #address-cells = <2>;
+          #size-cells = <1>;
+          compatible = "st,stm32mp1-fmc2-ebi";
+          reg = <0x58002000 0x1000>;
+          clocks = <&rcc FMC_K>;
+          resets = <&rcc FMC_R>;
+          feature-domains = <&etzpc 91>;
+          status = "disabled";
+
+          ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+                   <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+                   <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+                   <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+                   <4 0 0x80000000 0x10000000>; /* NAND */
+
+          nand-controller@4,0 {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            compatible = "st,stm32mp1-fmc2-nfc";
+            reg = <4 0x00000000 0x1000>,
+                  <4 0x08010000 0x1000>,
+                  <4 0x08020000 0x1000>,
+                  <4 0x01000000 0x1000>,
+                  <4 0x09010000 0x1000>,
+                  <4 0x09020000 0x1000>;
+            interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+            dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+                   <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+                   <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+            dma-names = "tx", "rx", "ecc";
+            status = "disabled";
+          };
+        };
+    };
-- 
2.35.3


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, Gatien Chevallier, Loic PALLARDY,
	linux-iio, netdev, linux-usb, linux-mmc, linux-kernel, linux-spi,
	linux-phy, linux-crypto, linux-serial, dmaengine, linux-media,
	linux-stm32, linux-arm-kernel, linux-i2c

Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---

Changes in V2: 
	- Corrected errors highlighted by Rob's robot
	- Re-ordered Signed-off-by tags
	
Changes in V3:
	- Correct #feature-domain-cells
	- Declare 1 as minimum number of arguments for feature-domains property
	in bus subnodes and 3 as maximum.
	- Change example to be a real usecase.

 .../devicetree/bindings/bus/st,sys-bus.yaml   | 127 ++++++++++++++++++
 1 file changed, 127 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml

diff --git a/Documentation/devicetree/bindings/bus/st,sys-bus.yaml b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
new file mode 100644
index 000000000000..c1510784b79b
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,sys-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 System Bus
+
+description: |
+  The STM32 System Bus is an internal bus to which some internal peripherals
+  are connected. STM32 System Bus integrates a firewall controlling access to each
+  device. This bus prevents non-accessible devices to be probed.
+
+  To see which peripherals are securable, please check the SoC reference manual.
+
+maintainers:
+  - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+allOf:
+  - $ref: /schemas/feature-controllers/feature-domain-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - st,stm32mp13-sys-bus
+      - st,stm32mp15-sys-bus
+
+  reg:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  "#feature-domain-cells":
+    const: 1
+
+  ranges: true
+
+  feature-domain-controller: true
+
+patternProperties:
+  "^.*@[0-9a-f]+$":
+    description: Devices attached to system bus
+    type: object
+    properties:
+      feature-domains:
+        $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+        minItems: 1
+        maxItems: 3
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - feature-domain-controller
+  - "#feature-domain-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    // In this example, the rng1 device refers to etzpc as its domain controller.
+    // Same goes for fmc.
+    // Access rights are verified before creating devices.
+
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/stm32mp1-clks.h>
+    #include <dt-bindings/reset/stm32mp1-resets.h>
+
+    etzpc: bus@5c007000 {
+        compatible = "st,stm32mp15-sys-bus";
+        reg = <0x5c007000 0x400>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        feature-domain-controller;
+        #feature-domain-cells = <1>;
+
+        rng1: rng@54003000 {
+          compatible = "st,stm32-rng";
+          reg = <0x54003000 0x400>;
+          clocks = <&rcc RNG1_K>;
+          resets = <&rcc RNG1_R>;
+          feature-domains = <&etzpc 7>;
+          status = "disabled";
+        };
+
+        fmc: memory-controller@58002000 {
+          #address-cells = <2>;
+          #size-cells = <1>;
+          compatible = "st,stm32mp1-fmc2-ebi";
+          reg = <0x58002000 0x1000>;
+          clocks = <&rcc FMC_K>;
+          resets = <&rcc FMC_R>;
+          feature-domains = <&etzpc 91>;
+          status = "disabled";
+
+          ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+                   <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+                   <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+                   <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+                   <4 0 0x80000000 0x10000000>; /* NAND */
+
+          nand-controller@4,0 {
+            #address-cells = <1>;
+            #size-cells = <0>;
+            compatible = "st,stm32mp1-fmc2-nfc";
+            reg = <4 0x00000000 0x1000>,
+                  <4 0x08010000 0x1000>,
+                  <4 0x08020000 0x1000>,
+                  <4 0x01000000 0x1000>,
+                  <4 0x09010000 0x1000>,
+                  <4 0x09020000 0x1000>;
+            interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+            dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+                   <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+                   <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+            dma-names = "tx", "rx", "ecc";
+            status = "disabled";
+          };
+        };
+    };
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
  2023-01-27 16:40 ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-27 16:40   ` Gatien Chevallier
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier, Loic PALLARDY

This driver is checking the access rights of the different
peripherals connected to the system bus. If access is denied,
the associated device tree node is skipped so the platform bus
does not probe it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---

No changes in V2.

Changes in V3:
	- Remove useless sys_bus_get_access and unused map_table fields in
	stm32_sys_bus_match_data structure
	- Use devm_platform_ioremap_resource() helper
	- Clean check on of_device_get_match_data() and remove unused local
	variables in stm32_sys_bus_probe().

 MAINTAINERS                 |   6 ++
 drivers/bus/Kconfig         |   9 ++
 drivers/bus/Makefile        |   1 +
 drivers/bus/stm32_sys_bus.c | 168 ++++++++++++++++++++++++++++++++++++
 4 files changed, 184 insertions(+)
 create mode 100644 drivers/bus/stm32_sys_bus.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 5b74014994f5..aafe32aa1925 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19782,6 +19782,12 @@ L:	linux-spi@vger.kernel.org
 S:	Maintained
 F:	drivers/spi/spi-stm32.c
 
+ST STM32 SYS BUS DRIVER
+M:	Gatien Chevallier <gatien.chevallier@foss.st.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/bus/st,sys-bus.yaml
+F:	drivers/bus/stm32_sys_bus.c
+
 ST STPDDC60 DRIVER
 M:	Daniel Nilsson <daniel.nilsson@flex.com>
 L:	linux-hwmon@vger.kernel.org
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 7bfe998f3514..3f7bc1f67916 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -163,6 +163,15 @@ config QCOM_SSC_BLOCK_BUS
 	  i2c/spi/uart controllers, a hexagon core, and a clock controller
 	  which provides clocks for the above.
 
+config STM32_SYS_BUS
+	bool "STM32 System bus controller"
+	depends on ARCH_STM32 || COMPILE_TEST
+	default MACH_STM32MP157 || MACH_STM32MP13
+	help
+	  Say y to enable device access right verification before device probing.
+	  If access not granted, device won't be probed and an error message will
+	  provide the reason.
+
 config SUN50I_DE2_BUS
 	bool "Allwinner A64 DE2 Bus Driver"
 	  default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index d90eed189a65..b15fdc42d0be 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT)	+= omap_l3_smx.o omap_l3_noc.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 obj-$(CONFIG_QCOM_EBI2)		+= qcom-ebi2.o
 obj-$(CONFIG_QCOM_SSC_BLOCK_BUS)	+= qcom-ssc-block-bus.o
+obj-$(CONFIG_STM32_SYS_BUS)	+= stm32_sys_bus.o
 obj-$(CONFIG_SUN50I_DE2_BUS)	+= sun50i-de2.o
 obj-$(CONFIG_SUNXI_RSB)		+= sunxi-rsb.o
 obj-$(CONFIG_OF)		+= simple-pm-bus.o
diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
new file mode 100644
index 000000000000..c12926466bae
--- /dev/null
+++ b/drivers/bus/stm32_sys_bus.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+/* ETZPC peripheral as firewall bus */
+/* ETZPC registers */
+#define ETZPC_DECPROT			0x10
+
+/* ETZPC miscellaneous */
+#define ETZPC_PROT_MASK			GENMASK(1, 0)
+#define ETZPC_PROT_A7NS			0x3
+#define ETZPC_DECPROT_SHIFT		1
+
+#define IDS_PER_DECPROT_REGS		16
+#define STM32MP15_ETZPC_ENTRIES		96
+#define STM32MP13_ETZPC_ENTRIES		64
+
+struct sys_bus_data;
+
+struct stm32_sys_bus_match_data {
+	unsigned int max_entries;
+};
+
+struct sys_bus_data {
+	const struct stm32_sys_bus_match_data *pconf;
+	void __iomem *sys_bus_base;
+	struct device *dev;
+};
+
+static int stm32_sys_bus_get_periph_id(struct sys_bus_data *pdata, struct device_node *np, u32 *id)
+{
+	int err;
+	u32 feature_domain_cell[2];
+	u32 id_bus;
+
+	/* Get reg from device node */
+	err = of_property_read_u32_array(np, "feature-domains", feature_domain_cell, 2);
+	if (err) {
+		dev_err(pdata->dev, "Unable to find feature-domains property\n");
+		return -ENODEV;
+	}
+
+	id_bus = feature_domain_cell[1];
+
+	if (id_bus >= pdata->pconf->max_entries) {
+		dev_err(pdata->dev, "Invalid sys bus ID for %s\n", np->full_name);
+		return -EINVAL;
+	}
+
+	*id = id_bus;
+
+	return 0;
+}
+
+static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
+{
+	int err;
+	u32 offset, reg_offset, sec_val, id;
+
+	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
+	if (err)
+		return err;
+
+	/* Check access configuration, 16 peripherals per register */
+	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
+
+	/* Verify peripheral is non-secure and attributed to cortex A7 */
+	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+	if (sec_val != ETZPC_PROT_A7NS) {
+		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
+			reg_offset, sec_val);
+		return -EACCES;
+	}
+
+	return 0;
+}
+
+static void stm32_sys_bus_populate(struct sys_bus_data *pdata)
+{
+	struct device *parent;
+	struct device_node *child;
+
+	parent = pdata->dev;
+
+	dev_dbg(parent, "Populating %s system bus\n", pdata->dev->driver->name);
+
+	for_each_available_child_of_node(dev_of_node(parent), child) {
+		if (stm32_etzpc_get_access(pdata, child)) {
+			/*
+			 * Peripheral access not allowed.
+			 * Mark the node as populated so platform bus won't probe it
+			 */
+			of_node_set_flag(child, OF_POPULATED);
+			dev_dbg(parent, "%s: Peripheral will not be probed\n",
+				child->full_name);
+		}
+	}
+}
+
+static int stm32_sys_bus_probe(struct platform_device *pdev)
+{
+	struct sys_bus_data *pdata;
+	void __iomem *mmio;
+	struct device_node *np = pdev->dev.of_node;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	mmio = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(mmio))
+		return PTR_ERR(mmio);
+
+	pdata->sys_bus_base = mmio;
+	pdata->pconf = of_device_get_match_data(&pdev->dev);
+	pdata->dev = &pdev->dev;
+
+	platform_set_drvdata(pdev, pdata);
+
+	stm32_sys_bus_populate(pdata);
+
+	/* Populate all available nodes */
+	return of_platform_populate(np, NULL, NULL, &pdev->dev);
+}
+
+static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {
+	.max_entries = STM32MP15_ETZPC_ENTRIES,
+};
+
+static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
+	.max_entries = STM32MP13_ETZPC_ENTRIES,
+};
+
+static const struct of_device_id stm32_sys_bus_of_match[] = {
+	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
+	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },
+	{}
+};
+MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
+
+static struct platform_driver stm32_sys_bus_driver = {
+	.probe  = stm32_sys_bus_probe,
+	.driver = {
+		.name = "stm32-sys-bus",
+		.of_match_table = stm32_sys_bus_of_match,
+	},
+};
+
+static int __init stm32_sys_bus_init(void)
+{
+	return platform_driver_register(&stm32_sys_bus_driver);
+}
+arch_initcall(stm32_sys_bus_init);
+
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier, Loic PALLARDY

This driver is checking the access rights of the different
peripherals connected to the system bus. If access is denied,
the associated device tree node is skipped so the platform bus
does not probe it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---

No changes in V2.

Changes in V3:
	- Remove useless sys_bus_get_access and unused map_table fields in
	stm32_sys_bus_match_data structure
	- Use devm_platform_ioremap_resource() helper
	- Clean check on of_device_get_match_data() and remove unused local
	variables in stm32_sys_bus_probe().

 MAINTAINERS                 |   6 ++
 drivers/bus/Kconfig         |   9 ++
 drivers/bus/Makefile        |   1 +
 drivers/bus/stm32_sys_bus.c | 168 ++++++++++++++++++++++++++++++++++++
 4 files changed, 184 insertions(+)
 create mode 100644 drivers/bus/stm32_sys_bus.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 5b74014994f5..aafe32aa1925 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19782,6 +19782,12 @@ L:	linux-spi@vger.kernel.org
 S:	Maintained
 F:	drivers/spi/spi-stm32.c
 
+ST STM32 SYS BUS DRIVER
+M:	Gatien Chevallier <gatien.chevallier@foss.st.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/bus/st,sys-bus.yaml
+F:	drivers/bus/stm32_sys_bus.c
+
 ST STPDDC60 DRIVER
 M:	Daniel Nilsson <daniel.nilsson@flex.com>
 L:	linux-hwmon@vger.kernel.org
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 7bfe998f3514..3f7bc1f67916 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -163,6 +163,15 @@ config QCOM_SSC_BLOCK_BUS
 	  i2c/spi/uart controllers, a hexagon core, and a clock controller
 	  which provides clocks for the above.
 
+config STM32_SYS_BUS
+	bool "STM32 System bus controller"
+	depends on ARCH_STM32 || COMPILE_TEST
+	default MACH_STM32MP157 || MACH_STM32MP13
+	help
+	  Say y to enable device access right verification before device probing.
+	  If access not granted, device won't be probed and an error message will
+	  provide the reason.
+
 config SUN50I_DE2_BUS
 	bool "Allwinner A64 DE2 Bus Driver"
 	  default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index d90eed189a65..b15fdc42d0be 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT)	+= omap_l3_smx.o omap_l3_noc.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 obj-$(CONFIG_QCOM_EBI2)		+= qcom-ebi2.o
 obj-$(CONFIG_QCOM_SSC_BLOCK_BUS)	+= qcom-ssc-block-bus.o
+obj-$(CONFIG_STM32_SYS_BUS)	+= stm32_sys_bus.o
 obj-$(CONFIG_SUN50I_DE2_BUS)	+= sun50i-de2.o
 obj-$(CONFIG_SUNXI_RSB)		+= sunxi-rsb.o
 obj-$(CONFIG_OF)		+= simple-pm-bus.o
diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
new file mode 100644
index 000000000000..c12926466bae
--- /dev/null
+++ b/drivers/bus/stm32_sys_bus.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+/* ETZPC peripheral as firewall bus */
+/* ETZPC registers */
+#define ETZPC_DECPROT			0x10
+
+/* ETZPC miscellaneous */
+#define ETZPC_PROT_MASK			GENMASK(1, 0)
+#define ETZPC_PROT_A7NS			0x3
+#define ETZPC_DECPROT_SHIFT		1
+
+#define IDS_PER_DECPROT_REGS		16
+#define STM32MP15_ETZPC_ENTRIES		96
+#define STM32MP13_ETZPC_ENTRIES		64
+
+struct sys_bus_data;
+
+struct stm32_sys_bus_match_data {
+	unsigned int max_entries;
+};
+
+struct sys_bus_data {
+	const struct stm32_sys_bus_match_data *pconf;
+	void __iomem *sys_bus_base;
+	struct device *dev;
+};
+
+static int stm32_sys_bus_get_periph_id(struct sys_bus_data *pdata, struct device_node *np, u32 *id)
+{
+	int err;
+	u32 feature_domain_cell[2];
+	u32 id_bus;
+
+	/* Get reg from device node */
+	err = of_property_read_u32_array(np, "feature-domains", feature_domain_cell, 2);
+	if (err) {
+		dev_err(pdata->dev, "Unable to find feature-domains property\n");
+		return -ENODEV;
+	}
+
+	id_bus = feature_domain_cell[1];
+
+	if (id_bus >= pdata->pconf->max_entries) {
+		dev_err(pdata->dev, "Invalid sys bus ID for %s\n", np->full_name);
+		return -EINVAL;
+	}
+
+	*id = id_bus;
+
+	return 0;
+}
+
+static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
+{
+	int err;
+	u32 offset, reg_offset, sec_val, id;
+
+	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
+	if (err)
+		return err;
+
+	/* Check access configuration, 16 peripherals per register */
+	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
+
+	/* Verify peripheral is non-secure and attributed to cortex A7 */
+	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+	if (sec_val != ETZPC_PROT_A7NS) {
+		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
+			reg_offset, sec_val);
+		return -EACCES;
+	}
+
+	return 0;
+}
+
+static void stm32_sys_bus_populate(struct sys_bus_data *pdata)
+{
+	struct device *parent;
+	struct device_node *child;
+
+	parent = pdata->dev;
+
+	dev_dbg(parent, "Populating %s system bus\n", pdata->dev->driver->name);
+
+	for_each_available_child_of_node(dev_of_node(parent), child) {
+		if (stm32_etzpc_get_access(pdata, child)) {
+			/*
+			 * Peripheral access not allowed.
+			 * Mark the node as populated so platform bus won't probe it
+			 */
+			of_node_set_flag(child, OF_POPULATED);
+			dev_dbg(parent, "%s: Peripheral will not be probed\n",
+				child->full_name);
+		}
+	}
+}
+
+static int stm32_sys_bus_probe(struct platform_device *pdev)
+{
+	struct sys_bus_data *pdata;
+	void __iomem *mmio;
+	struct device_node *np = pdev->dev.of_node;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	mmio = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(mmio))
+		return PTR_ERR(mmio);
+
+	pdata->sys_bus_base = mmio;
+	pdata->pconf = of_device_get_match_data(&pdev->dev);
+	pdata->dev = &pdev->dev;
+
+	platform_set_drvdata(pdev, pdata);
+
+	stm32_sys_bus_populate(pdata);
+
+	/* Populate all available nodes */
+	return of_platform_populate(np, NULL, NULL, &pdev->dev);
+}
+
+static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {
+	.max_entries = STM32MP15_ETZPC_ENTRIES,
+};
+
+static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
+	.max_entries = STM32MP13_ETZPC_ENTRIES,
+};
+
+static const struct of_device_id stm32_sys_bus_of_match[] = {
+	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
+	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },
+	{}
+};
+MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
+
+static struct platform_driver stm32_sys_bus_driver = {
+	.probe  = stm32_sys_bus_probe,
+	.driver = {
+		.name = "stm32-sys-bus",
+		.of_match_table = stm32_sys_bus_of_match,
+	},
+};
+
+static int __init stm32_sys_bus_init(void)
+{
+	return platform_driver_register(&stm32_sys_bus_driver);
+}
+arch_initcall(stm32_sys_bus_init);
+
-- 
2.35.3


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier, Loic PALLARDY

This driver is checking the access rights of the different
peripherals connected to the system bus. If access is denied,
the associated device tree node is skipped so the platform bus
does not probe it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---

No changes in V2.

Changes in V3:
	- Remove useless sys_bus_get_access and unused map_table fields in
	stm32_sys_bus_match_data structure
	- Use devm_platform_ioremap_resource() helper
	- Clean check on of_device_get_match_data() and remove unused local
	variables in stm32_sys_bus_probe().

 MAINTAINERS                 |   6 ++
 drivers/bus/Kconfig         |   9 ++
 drivers/bus/Makefile        |   1 +
 drivers/bus/stm32_sys_bus.c | 168 ++++++++++++++++++++++++++++++++++++
 4 files changed, 184 insertions(+)
 create mode 100644 drivers/bus/stm32_sys_bus.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 5b74014994f5..aafe32aa1925 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19782,6 +19782,12 @@ L:	linux-spi@vger.kernel.org
 S:	Maintained
 F:	drivers/spi/spi-stm32.c
 
+ST STM32 SYS BUS DRIVER
+M:	Gatien Chevallier <gatien.chevallier@foss.st.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/bus/st,sys-bus.yaml
+F:	drivers/bus/stm32_sys_bus.c
+
 ST STPDDC60 DRIVER
 M:	Daniel Nilsson <daniel.nilsson@flex.com>
 L:	linux-hwmon@vger.kernel.org
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 7bfe998f3514..3f7bc1f67916 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -163,6 +163,15 @@ config QCOM_SSC_BLOCK_BUS
 	  i2c/spi/uart controllers, a hexagon core, and a clock controller
 	  which provides clocks for the above.
 
+config STM32_SYS_BUS
+	bool "STM32 System bus controller"
+	depends on ARCH_STM32 || COMPILE_TEST
+	default MACH_STM32MP157 || MACH_STM32MP13
+	help
+	  Say y to enable device access right verification before device probing.
+	  If access not granted, device won't be probed and an error message will
+	  provide the reason.
+
 config SUN50I_DE2_BUS
 	bool "Allwinner A64 DE2 Bus Driver"
 	  default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index d90eed189a65..b15fdc42d0be 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT)	+= omap_l3_smx.o omap_l3_noc.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 obj-$(CONFIG_QCOM_EBI2)		+= qcom-ebi2.o
 obj-$(CONFIG_QCOM_SSC_BLOCK_BUS)	+= qcom-ssc-block-bus.o
+obj-$(CONFIG_STM32_SYS_BUS)	+= stm32_sys_bus.o
 obj-$(CONFIG_SUN50I_DE2_BUS)	+= sun50i-de2.o
 obj-$(CONFIG_SUNXI_RSB)		+= sunxi-rsb.o
 obj-$(CONFIG_OF)		+= simple-pm-bus.o
diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
new file mode 100644
index 000000000000..c12926466bae
--- /dev/null
+++ b/drivers/bus/stm32_sys_bus.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+/* ETZPC peripheral as firewall bus */
+/* ETZPC registers */
+#define ETZPC_DECPROT			0x10
+
+/* ETZPC miscellaneous */
+#define ETZPC_PROT_MASK			GENMASK(1, 0)
+#define ETZPC_PROT_A7NS			0x3
+#define ETZPC_DECPROT_SHIFT		1
+
+#define IDS_PER_DECPROT_REGS		16
+#define STM32MP15_ETZPC_ENTRIES		96
+#define STM32MP13_ETZPC_ENTRIES		64
+
+struct sys_bus_data;
+
+struct stm32_sys_bus_match_data {
+	unsigned int max_entries;
+};
+
+struct sys_bus_data {
+	const struct stm32_sys_bus_match_data *pconf;
+	void __iomem *sys_bus_base;
+	struct device *dev;
+};
+
+static int stm32_sys_bus_get_periph_id(struct sys_bus_data *pdata, struct device_node *np, u32 *id)
+{
+	int err;
+	u32 feature_domain_cell[2];
+	u32 id_bus;
+
+	/* Get reg from device node */
+	err = of_property_read_u32_array(np, "feature-domains", feature_domain_cell, 2);
+	if (err) {
+		dev_err(pdata->dev, "Unable to find feature-domains property\n");
+		return -ENODEV;
+	}
+
+	id_bus = feature_domain_cell[1];
+
+	if (id_bus >= pdata->pconf->max_entries) {
+		dev_err(pdata->dev, "Invalid sys bus ID for %s\n", np->full_name);
+		return -EINVAL;
+	}
+
+	*id = id_bus;
+
+	return 0;
+}
+
+static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
+{
+	int err;
+	u32 offset, reg_offset, sec_val, id;
+
+	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
+	if (err)
+		return err;
+
+	/* Check access configuration, 16 peripherals per register */
+	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
+
+	/* Verify peripheral is non-secure and attributed to cortex A7 */
+	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+	if (sec_val != ETZPC_PROT_A7NS) {
+		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
+			reg_offset, sec_val);
+		return -EACCES;
+	}
+
+	return 0;
+}
+
+static void stm32_sys_bus_populate(struct sys_bus_data *pdata)
+{
+	struct device *parent;
+	struct device_node *child;
+
+	parent = pdata->dev;
+
+	dev_dbg(parent, "Populating %s system bus\n", pdata->dev->driver->name);
+
+	for_each_available_child_of_node(dev_of_node(parent), child) {
+		if (stm32_etzpc_get_access(pdata, child)) {
+			/*
+			 * Peripheral access not allowed.
+			 * Mark the node as populated so platform bus won't probe it
+			 */
+			of_node_set_flag(child, OF_POPULATED);
+			dev_dbg(parent, "%s: Peripheral will not be probed\n",
+				child->full_name);
+		}
+	}
+}
+
+static int stm32_sys_bus_probe(struct platform_device *pdev)
+{
+	struct sys_bus_data *pdata;
+	void __iomem *mmio;
+	struct device_node *np = pdev->dev.of_node;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	mmio = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(mmio))
+		return PTR_ERR(mmio);
+
+	pdata->sys_bus_base = mmio;
+	pdata->pconf = of_device_get_match_data(&pdev->dev);
+	pdata->dev = &pdev->dev;
+
+	platform_set_drvdata(pdev, pdata);
+
+	stm32_sys_bus_populate(pdata);
+
+	/* Populate all available nodes */
+	return of_platform_populate(np, NULL, NULL, &pdev->dev);
+}
+
+static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {
+	.max_entries = STM32MP15_ETZPC_ENTRIES,
+};
+
+static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
+	.max_entries = STM32MP13_ETZPC_ENTRIES,
+};
+
+static const struct of_device_id stm32_sys_bus_of_match[] = {
+	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
+	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },
+	{}
+};
+MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
+
+static struct platform_driver stm32_sys_bus_driver = {
+	.probe  = stm32_sys_bus_probe,
+	.driver = {
+		.name = "stm32-sys-bus",
+		.of_match_table = stm32_sys_bus_of_match,
+	},
+};
+
+static int __init stm32_sys_bus_init(void)
+{
+	return platform_driver_register(&stm32_sys_bus_driver);
+}
+arch_initcall(stm32_sys_bus_init);
+
-- 
2.35.3


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, Gatien Chevallier, Loic PALLARDY,
	linux-iio, netdev, linux-usb, linux-mmc, linux-kernel, linux-spi,
	linux-phy, linux-crypto, linux-serial, dmaengine, linux-media,
	linux-stm32, linux-arm-kernel, linux-i2c

This driver is checking the access rights of the different
peripherals connected to the system bus. If access is denied,
the associated device tree node is skipped so the platform bus
does not probe it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---

No changes in V2.

Changes in V3:
	- Remove useless sys_bus_get_access and unused map_table fields in
	stm32_sys_bus_match_data structure
	- Use devm_platform_ioremap_resource() helper
	- Clean check on of_device_get_match_data() and remove unused local
	variables in stm32_sys_bus_probe().

 MAINTAINERS                 |   6 ++
 drivers/bus/Kconfig         |   9 ++
 drivers/bus/Makefile        |   1 +
 drivers/bus/stm32_sys_bus.c | 168 ++++++++++++++++++++++++++++++++++++
 4 files changed, 184 insertions(+)
 create mode 100644 drivers/bus/stm32_sys_bus.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 5b74014994f5..aafe32aa1925 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19782,6 +19782,12 @@ L:	linux-spi@vger.kernel.org
 S:	Maintained
 F:	drivers/spi/spi-stm32.c
 
+ST STM32 SYS BUS DRIVER
+M:	Gatien Chevallier <gatien.chevallier@foss.st.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/bus/st,sys-bus.yaml
+F:	drivers/bus/stm32_sys_bus.c
+
 ST STPDDC60 DRIVER
 M:	Daniel Nilsson <daniel.nilsson@flex.com>
 L:	linux-hwmon@vger.kernel.org
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 7bfe998f3514..3f7bc1f67916 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -163,6 +163,15 @@ config QCOM_SSC_BLOCK_BUS
 	  i2c/spi/uart controllers, a hexagon core, and a clock controller
 	  which provides clocks for the above.
 
+config STM32_SYS_BUS
+	bool "STM32 System bus controller"
+	depends on ARCH_STM32 || COMPILE_TEST
+	default MACH_STM32MP157 || MACH_STM32MP13
+	help
+	  Say y to enable device access right verification before device probing.
+	  If access not granted, device won't be probed and an error message will
+	  provide the reason.
+
 config SUN50I_DE2_BUS
 	bool "Allwinner A64 DE2 Bus Driver"
 	  default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index d90eed189a65..b15fdc42d0be 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT)	+= omap_l3_smx.o omap_l3_noc.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 obj-$(CONFIG_QCOM_EBI2)		+= qcom-ebi2.o
 obj-$(CONFIG_QCOM_SSC_BLOCK_BUS)	+= qcom-ssc-block-bus.o
+obj-$(CONFIG_STM32_SYS_BUS)	+= stm32_sys_bus.o
 obj-$(CONFIG_SUN50I_DE2_BUS)	+= sun50i-de2.o
 obj-$(CONFIG_SUNXI_RSB)		+= sunxi-rsb.o
 obj-$(CONFIG_OF)		+= simple-pm-bus.o
diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
new file mode 100644
index 000000000000..c12926466bae
--- /dev/null
+++ b/drivers/bus/stm32_sys_bus.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+/* ETZPC peripheral as firewall bus */
+/* ETZPC registers */
+#define ETZPC_DECPROT			0x10
+
+/* ETZPC miscellaneous */
+#define ETZPC_PROT_MASK			GENMASK(1, 0)
+#define ETZPC_PROT_A7NS			0x3
+#define ETZPC_DECPROT_SHIFT		1
+
+#define IDS_PER_DECPROT_REGS		16
+#define STM32MP15_ETZPC_ENTRIES		96
+#define STM32MP13_ETZPC_ENTRIES		64
+
+struct sys_bus_data;
+
+struct stm32_sys_bus_match_data {
+	unsigned int max_entries;
+};
+
+struct sys_bus_data {
+	const struct stm32_sys_bus_match_data *pconf;
+	void __iomem *sys_bus_base;
+	struct device *dev;
+};
+
+static int stm32_sys_bus_get_periph_id(struct sys_bus_data *pdata, struct device_node *np, u32 *id)
+{
+	int err;
+	u32 feature_domain_cell[2];
+	u32 id_bus;
+
+	/* Get reg from device node */
+	err = of_property_read_u32_array(np, "feature-domains", feature_domain_cell, 2);
+	if (err) {
+		dev_err(pdata->dev, "Unable to find feature-domains property\n");
+		return -ENODEV;
+	}
+
+	id_bus = feature_domain_cell[1];
+
+	if (id_bus >= pdata->pconf->max_entries) {
+		dev_err(pdata->dev, "Invalid sys bus ID for %s\n", np->full_name);
+		return -EINVAL;
+	}
+
+	*id = id_bus;
+
+	return 0;
+}
+
+static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
+{
+	int err;
+	u32 offset, reg_offset, sec_val, id;
+
+	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
+	if (err)
+		return err;
+
+	/* Check access configuration, 16 peripherals per register */
+	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
+
+	/* Verify peripheral is non-secure and attributed to cortex A7 */
+	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+	if (sec_val != ETZPC_PROT_A7NS) {
+		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
+			reg_offset, sec_val);
+		return -EACCES;
+	}
+
+	return 0;
+}
+
+static void stm32_sys_bus_populate(struct sys_bus_data *pdata)
+{
+	struct device *parent;
+	struct device_node *child;
+
+	parent = pdata->dev;
+
+	dev_dbg(parent, "Populating %s system bus\n", pdata->dev->driver->name);
+
+	for_each_available_child_of_node(dev_of_node(parent), child) {
+		if (stm32_etzpc_get_access(pdata, child)) {
+			/*
+			 * Peripheral access not allowed.
+			 * Mark the node as populated so platform bus won't probe it
+			 */
+			of_node_set_flag(child, OF_POPULATED);
+			dev_dbg(parent, "%s: Peripheral will not be probed\n",
+				child->full_name);
+		}
+	}
+}
+
+static int stm32_sys_bus_probe(struct platform_device *pdev)
+{
+	struct sys_bus_data *pdata;
+	void __iomem *mmio;
+	struct device_node *np = pdev->dev.of_node;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
+
+	mmio = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(mmio))
+		return PTR_ERR(mmio);
+
+	pdata->sys_bus_base = mmio;
+	pdata->pconf = of_device_get_match_data(&pdev->dev);
+	pdata->dev = &pdev->dev;
+
+	platform_set_drvdata(pdev, pdata);
+
+	stm32_sys_bus_populate(pdata);
+
+	/* Populate all available nodes */
+	return of_platform_populate(np, NULL, NULL, &pdev->dev);
+}
+
+static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {
+	.max_entries = STM32MP15_ETZPC_ENTRIES,
+};
+
+static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
+	.max_entries = STM32MP13_ETZPC_ENTRIES,
+};
+
+static const struct of_device_id stm32_sys_bus_of_match[] = {
+	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
+	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },
+	{}
+};
+MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
+
+static struct platform_driver stm32_sys_bus_driver = {
+	.probe  = stm32_sys_bus_probe,
+	.driver = {
+		.name = "stm32-sys-bus",
+		.of_match_table = stm32_sys_bus_of_match,
+	},
+};
+
+static int __init stm32_sys_bus_init(void)
+{
+	return platform_driver_register(&stm32_sys_bus_driver);
+}
+arch_initcall(stm32_sys_bus_init);
+
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 5/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
  2023-01-27 16:40 ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-27 16:40   ` Gatien Chevallier
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

The STM32 System Bus is an internal bus on which devices are connected.
ETZPC is a peripheral overseeing the firewall bus that configures
and control access to the peripherals connected on it.

For more information on which peripheral is securable, please read
the STM32MP15 reference manual.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

No changes in V2.

Changes in V3:
	-Use appriopriate node name: bus

 arch/arm/boot/dts/stm32mp151.dtsi  | 2722 ++++++++++++++--------------
 arch/arm/boot/dts/stm32mp153.dtsi  |   52 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi |   19 +-
 3 files changed, 1434 insertions(+), 1359 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index 5491b6c4dec2..5dab96e7c2ba 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -122,1526 +122,1600 @@ soc {
 		interrupt-parent = <&intc>;
 		ranges;
 
-		timers2: timer@40000000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40000000 0x400>;
-			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM2_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 18 0x400 0x1>,
-			       <&dmamux1 19 0x400 0x1>,
-			       <&dmamux1 20 0x400 0x1>,
-			       <&dmamux1 21 0x400 0x1>,
-			       <&dmamux1 22 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+		ipcc: mailbox@4c001000 {
+			compatible = "st,stm32mp1-ipcc";
+			#mbox-cells = <1>;
+			reg = <0x4c001000 0x400>;
+			st,proc-id = <0>;
+			interrupts-extended =
+				<&exti 61 1>,
+				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "rx", "tx";
+			clocks = <&rcc IPCC>;
+			wakeup-source;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@1 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <1>;
-				status = "disabled";
-			};
-
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		rcc: rcc@50000000 {
+			compatible = "st,stm32mp1-rcc", "syscon";
+			reg = <0x50000000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
-		timers3: timer@40001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40001000 0x400>;
-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM3_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 23 0x400 0x1>,
-			       <&dmamux1 24 0x400 0x1>,
-			       <&dmamux1 25 0x400 0x1>,
-			       <&dmamux1 26 0x400 0x1>,
-			       <&dmamux1 27 0x400 0x1>,
-			       <&dmamux1 28 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
-			status = "disabled";
+		pwr_regulators: pwr@50001000 {
+			compatible = "st,stm32mp1,pwr-reg";
+			reg = <0x50001000 0x10>;
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+			reg11: reg11 {
+				regulator-name = "reg11";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
 			};
 
-			timer@2 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <2>;
-				status = "disabled";
+			reg18: reg18 {
+				regulator-name = "reg18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
 			};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
+			usb33: usb33 {
+				regulator-name = "usb33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
 			};
 		};
 
-		timers4: timer@40002000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40002000 0x400>;
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM4_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 29 0x400 0x1>,
-			       <&dmamux1 30 0x400 0x1>,
-			       <&dmamux1 31 0x400 0x1>,
-			       <&dmamux1 32 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4";
-			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
+		pwr_mcu: pwr_mcu@50001014 {
+			compatible = "st,stm32mp151-pwr-mcu", "syscon";
+			reg = <0x50001014 0x4>;
+		};
 
-			timer@3 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <3>;
-				status = "disabled";
-			};
+		exti: interrupt-controller@5000d000 {
+			compatible = "st,stm32mp1-exti", "syscon";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x5000d000 0x400>;
+		};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		syscfg: syscon@50020000 {
+			compatible = "st,stm32mp157-syscfg", "syscon";
+			reg = <0x50020000 0x400>;
+			clocks = <&rcc SYSCFG>;
 		};
 
-		timers5: timer@40003000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40003000 0x400>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM5_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 55 0x400 0x1>,
-			       <&dmamux1 56 0x400 0x1>,
-			       <&dmamux1 57 0x400 0x1>,
-			       <&dmamux1 58 0x400 0x1>,
-			       <&dmamux1 59 0x400 0x1>,
-			       <&dmamux1 60 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+		dts: thermal@50028000 {
+			compatible = "st,stm32-thermal";
+			reg = <0x50028000 0x100>;
+			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc TMPSENS>;
+			clock-names = "pclk";
+			#thermal-sensor-cells = <0>;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@4 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <4>;
-				status = "disabled";
-			};
-
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		mdma1: dma-controller@58000000 {
+			compatible = "st,stm32h7-mdma";
+			reg = <0x58000000 0x1000>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc MDMA>;
+			resets = <&rcc MDMA_R>;
+			#dma-cells = <5>;
+			dma-channels = <32>;
+			dma-requests = <48>;
 		};
 
-		timers6: timer@40004000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40004000 0x400>;
-			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM6_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 69 0x400 0x1>;
-			dma-names = "up";
+		sdmmc1: mmc@58005000 {
+			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+			arm,primecell-periphid = <0x00253180>;
+			reg = <0x58005000 0x1000>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SDMMC1_K>;
+			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC1_R>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
 			status = "disabled";
-
-			timer@5 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <5>;
-				status = "disabled";
-			};
 		};
 
-		timers7: timer@40005000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40005000 0x400>;
-			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM7_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 70 0x400 0x1>;
-			dma-names = "up";
+		sdmmc2: mmc@58007000 {
+			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+			arm,primecell-periphid = <0x00253180>;
+			reg = <0x58007000 0x1000>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SDMMC2_K>;
+			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC2_R>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
 			status = "disabled";
-
-			timer@6 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <6>;
-				status = "disabled";
-			};
 		};
 
-		timers12: timer@40006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40006000 0x400>;
-			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM12_K>;
-			clock-names = "int";
+		crc1: crc@58009000 {
+			compatible = "st,stm32f7-crc";
+			reg = <0x58009000 0x400>;
+			clocks = <&rcc CRC1>;
 			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@11 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <11>;
-				status = "disabled";
-			};
 		};
 
-		timers13: timer@40007000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40007000 0x400>;
-			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM13_K>;
-			clock-names = "int";
+		usbh_ohci: usb@5800c000 {
+			compatible = "generic-ohci";
+			reg = <0x5800c000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@12 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <12>;
-				status = "disabled";
-			};
+		usbh_ehci: usb@5800d000 {
+			compatible = "generic-ehci";
+			reg = <0x5800d000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			companion = <&usbh_ohci>;
+			status = "disabled";
 		};
 
-		timers14: timer@40008000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40008000 0x400>;
-			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM14_K>;
-			clock-names = "int";
+		ltdc: display-controller@5a001000 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x5a001000 0x400>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LTDC_PX>;
+			clock-names = "lcd";
+			resets = <&rcc LTDC_R>;
 			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
 			};
+		};
 
-			timer@13 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <13>;
-				status = "disabled";
-			};
+		iwdg2: watchdog@5a002000 {
+			compatible = "st,stm32mp1-iwdg";
+			reg = <0x5a002000 0x400>;
+			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
+			clock-names = "pclk", "lsi";
+			status = "disabled";
 		};
 
-		lptimer1: timer@40009000 {
+		usbphyc: usbphyc@5a006000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x40009000 0x400>;
-			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM1_K>;
-			clock-names = "mux";
-			wakeup-source;
+			#clock-cells = <0>;
+			compatible = "st,stm32mp1-usbphyc";
+			reg = <0x5a006000 0x1000>;
+			clocks = <&rcc USBPHY_K>;
+			resets = <&rcc USBPHY_R>;
+			vdda1v1-supply = <&reg11>;
+			vdda1v8-supply = <&reg18>;
 			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			trigger@0 {
-				compatible = "st,stm32-lptimer-trigger";
+			usbphyc_port0: usb-phy@0 {
+				#phy-cells = <0>;
 				reg = <0>;
-				status = "disabled";
 			};
 
-			counter {
-				compatible = "st,stm32-lptimer-counter";
-				status = "disabled";
+			usbphyc_port1: usb-phy@1 {
+				#phy-cells = <1>;
+				reg = <1>;
 			};
 		};
 
-		spi2: spi@4000b000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x4000b000 0x400>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI2_K>;
-			resets = <&rcc SPI2_R>;
-			dmas = <&dmamux1 39 0x400 0x05>,
-			       <&dmamux1 40 0x400 0x05>;
-			dma-names = "rx", "tx";
+		rtc: rtc@5c004000 {
+			compatible = "st,stm32mp1-rtc";
+			reg = <0x5c004000 0x400>;
+			clocks = <&rcc RTCAPB>, <&rcc RTC>;
+			clock-names = "pclk", "rtc_ck";
+			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
-		i2s2: audio-controller@4000b000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x4000b000 0x400>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 39 0x400 0x01>,
-			       <&dmamux1 40 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
+		bsec: efuse@5c005000 {
+			compatible = "st,stm32mp15-bsec";
+			reg = <0x5c005000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ts_cal1: calib@5c {
+				reg = <0x5c 0x2>;
+			};
+			ts_cal2: calib@5e {
+				reg = <0x5e 0x2>;
+			};
 		};
 
-		spi3: spi@4000c000 {
+		etzpc: bus@5c007000 {
+			compatible = "st,stm32mp15-sys-bus";
+			reg = <0x5c007000 0x400>;
 			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x4000c000 0x400>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI3_K>;
-			resets = <&rcc SPI3_R>;
-			dmas = <&dmamux1 61 0x400 0x05>,
-			       <&dmamux1 62 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			#size-cells = <1>;
+			feature-domain-controller;
+			#feature-domain-cells = <1>;
+			ranges;
 
-		i2s3: audio-controller@4000c000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x4000c000 0x400>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 61 0x400 0x01>,
-			       <&dmamux1 62 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers2: timer@40000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40000000 0x400>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM2_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 18 0x400 0x1>,
+				       <&dmamux1 19 0x400 0x1>,
+				       <&dmamux1 20 0x400 0x1>,
+				       <&dmamux1 21 0x400 0x1>,
+				       <&dmamux1 22 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+				feature-domains = <&etzpc 16>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		spdifrx: audio-controller@4000d000 {
-			compatible = "st,stm32h7-spdifrx";
-			#sound-dai-cells = <0>;
-			reg = <0x4000d000 0x400>;
-			clocks = <&rcc SPDIF_K>;
-			clock-names = "kclk";
-			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 93 0x400 0x01>,
-			       <&dmamux1 94 0x400 0x01>;
-			dma-names = "rx", "rx-ctrl";
-			status = "disabled";
-		};
+				timer@1 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <1>;
+					status = "disabled";
+				};
 
-		usart2: serial@4000e000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x4000e000 0x400>;
-			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART2_K>;
-			wakeup-source;
-			dmas = <&dmamux1 43 0x400 0x15>,
-			       <&dmamux1 44 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		usart3: serial@4000f000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x4000f000 0x400>;
-			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART3_K>;
-			wakeup-source;
-			dmas = <&dmamux1 45 0x400 0x15>,
-			       <&dmamux1 46 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers3: timer@40001000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40001000 0x400>;
+				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM3_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 23 0x400 0x1>,
+				       <&dmamux1 24 0x400 0x1>,
+				       <&dmamux1 25 0x400 0x1>,
+				       <&dmamux1 26 0x400 0x1>,
+				       <&dmamux1 27 0x400 0x1>,
+				       <&dmamux1 28 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+				feature-domains = <&etzpc 17>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		uart4: serial@40010000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40010000 0x400>;
-			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART4_K>;
-			wakeup-source;
-			dmas = <&dmamux1 63 0x400 0x15>,
-			       <&dmamux1 64 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				timer@2 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <2>;
+					status = "disabled";
+				};
 
-		uart5: serial@40011000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40011000 0x400>;
-			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART5_K>;
-			wakeup-source;
-			dmas = <&dmamux1 65 0x400 0x15>,
-			       <&dmamux1 66 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		i2c1: i2c@40012000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40012000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C1_K>;
-			resets = <&rcc I2C1_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x1>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+			timers4: timer@40002000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40002000 0x400>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM4_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 29 0x400 0x1>,
+				       <&dmamux1 30 0x400 0x1>,
+				       <&dmamux1 31 0x400 0x1>,
+				       <&dmamux1 32 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4";
+				feature-domains = <&etzpc 18>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		i2c2: i2c@40013000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40013000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C2_K>;
-			resets = <&rcc I2C2_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x2>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+				timer@3 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <3>;
+					status = "disabled";
+				};
 
-		i2c3: i2c@40014000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40014000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C3_K>;
-			resets = <&rcc I2C3_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x4>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		i2c5: i2c@40015000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40015000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C5_K>;
-			resets = <&rcc I2C5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x10>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+			timers5: timer@40003000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40003000 0x400>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM5_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 55 0x400 0x1>,
+				       <&dmamux1 56 0x400 0x1>,
+				       <&dmamux1 57 0x400 0x1>,
+				       <&dmamux1 58 0x400 0x1>,
+				       <&dmamux1 59 0x400 0x1>,
+				       <&dmamux1 60 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+				feature-domains = <&etzpc 19>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		cec: cec@40016000 {
-			compatible = "st,stm32-cec";
-			reg = <0x40016000 0x400>;
-			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CEC_K>, <&rcc CEC>;
-			clock-names = "cec", "hdmi-cec";
-			status = "disabled";
-		};
+				timer@4 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <4>;
+					status = "disabled";
+				};
 
-		dac: dac@40017000 {
-			compatible = "st,stm32h7-dac-core";
-			reg = <0x40017000 0x400>;
-			clocks = <&rcc DAC12>;
-			clock-names = "pclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-			dac1: dac@1 {
-				compatible = "st,stm32-dac";
-				#io-channel-cells = <1>;
-				reg = <1>;
-				status = "disabled";
+			timers6: timer@40004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40004000 0x400>;
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM6_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 69 0x400 0x1>;
+				dma-names = "up";
+				feature-domains = <&etzpc 20>;
+				status = "disabled";
+
+				timer@5 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <5>;
+					status = "disabled";
+				};
 			};
 
-			dac2: dac@2 {
-				compatible = "st,stm32-dac";
-				#io-channel-cells = <1>;
-				reg = <2>;
-				status = "disabled";
+			timers7: timer@40005000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40005000 0x400>;
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM7_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 70 0x400 0x1>;
+				dma-names = "up";
+				feature-domains = <&etzpc 21>;
+				status = "disabled";
+
+				timer@6 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <6>;
+					status = "disabled";
+				};
 			};
-		};
 
-		uart7: serial@40018000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40018000 0x400>;
-			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART7_K>;
-			wakeup-source;
-			dmas = <&dmamux1 79 0x400 0x15>,
-			       <&dmamux1 80 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers12: timer@40006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40006000 0x400>;
+				interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM12_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 22>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		uart8: serial@40019000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40019000 0x400>;
-			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART8_K>;
-			wakeup-source;
-			dmas = <&dmamux1 81 0x400 0x15>,
-			       <&dmamux1 82 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				timer@11 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <11>;
+					status = "disabled";
+				};
+			};
 
-		timers1: timer@44000000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44000000 0x400>;
-			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "brk", "up", "trg-com", "cc";
-			clocks = <&rcc TIM1_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 11 0x400 0x1>,
-			       <&dmamux1 12 0x400 0x1>,
-			       <&dmamux1 13 0x400 0x1>,
-			       <&dmamux1 14 0x400 0x1>,
-			       <&dmamux1 15 0x400 0x1>,
-			       <&dmamux1 16 0x400 0x1>,
-			       <&dmamux1 17 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4",
-				    "up", "trig", "com";
-			status = "disabled";
+			timers13: timer@40007000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40007000 0x400>;
+				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM13_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 23>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+				timer@12 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <12>;
+					status = "disabled";
+				};
 			};
 
-			timer@0 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <0>;
-				status = "disabled";
-			};
+			timers14: timer@40008000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40008000 0x400>;
+				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM14_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 24>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
+				timer@13 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <13>;
+					status = "disabled";
+				};
 			};
-		};
 
-		timers8: timer@44001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44001000 0x400>;
-			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "brk", "up", "trg-com", "cc";
-			clocks = <&rcc TIM8_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 47 0x400 0x1>,
-			       <&dmamux1 48 0x400 0x1>,
-			       <&dmamux1 49 0x400 0x1>,
-			       <&dmamux1 50 0x400 0x1>,
-			       <&dmamux1 51 0x400 0x1>,
-			       <&dmamux1 52 0x400 0x1>,
-			       <&dmamux1 53 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4",
-				    "up", "trig", "com";
-			status = "disabled";
+			lptimer1: timer@40009000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x40009000 0x400>;
+				interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM1_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 25>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+				trigger@0 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <0>;
+					status = "disabled";
+				};
+
+				counter {
+					compatible = "st,stm32-lptimer-counter";
+					status = "disabled";
+				};
 			};
 
-			timer@7 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <7>;
+			i2s2: audio-controller@4000b000 {
+				compatible = "st,stm32h7-i2s";
+				#sound-dai-cells = <0>;
+				reg = <0x4000b000 0x400>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 39 0x400 0x01>,
+				       <&dmamux1 40 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 27>;
 				status = "disabled";
 			};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
+			spi2: spi@4000b000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x4000b000 0x400>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI2_K>;
+				resets = <&rcc SPI2_R>;
+				dmas = <&dmamux1 39 0x400 0x05>,
+				       <&dmamux1 40 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 27>;
 				status = "disabled";
 			};
-		};
-
-		usart6: serial@44003000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x44003000 0x400>;
-			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART6_K>;
-			wakeup-source;
-			dmas = <&dmamux1 71 0x400 0x15>,
-			       <&dmamux1 72 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi1: spi@44004000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44004000 0x400>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI1_K>;
-			resets = <&rcc SPI1_R>;
-			dmas = <&dmamux1 37 0x400 0x05>,
-			       <&dmamux1 38 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2s1: audio-controller@44004000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x44004000 0x400>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 37 0x400 0x01>,
-			       <&dmamux1 38 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi4: spi@44005000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44005000 0x400>;
-			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI4_K>;
-			resets = <&rcc SPI4_R>;
-			dmas = <&dmamux1 83 0x400 0x05>,
-			       <&dmamux1 84 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		timers15: timer@44006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44006000 0x400>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM15_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 105 0x400 0x1>,
-			       <&dmamux1 106 0x400 0x1>,
-			       <&dmamux1 107 0x400 0x1>,
-			       <&dmamux1 108 0x400 0x1>;
-			dma-names = "ch1", "up", "trig", "com";
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			i2s3: audio-controller@4000c000 {
+				compatible = "st,stm32h7-i2s";
+				#sound-dai-cells = <0>;
+				reg = <0x4000c000 0x400>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 61 0x400 0x01>,
+				       <&dmamux1 62 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 28>;
 				status = "disabled";
 			};
 
-			timer@14 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <14>;
+			spi3: spi@4000c000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x4000c000 0x400>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI3_K>;
+				resets = <&rcc SPI3_R>;
+				dmas = <&dmamux1 61 0x400 0x05>,
+				       <&dmamux1 62 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 28>;
 				status = "disabled";
 			};
-		};
-
-		timers16: timer@44007000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44007000 0x400>;
-			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM16_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 109 0x400 0x1>,
-			       <&dmamux1 110 0x400 0x1>;
-			dma-names = "ch1", "up";
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			spdifrx: audio-controller@4000d000 {
+				compatible = "st,stm32h7-spdifrx";
+				#sound-dai-cells = <0>;
+				reg = <0x4000d000 0x400>;
+				clocks = <&rcc SPDIF_K>;
+				clock-names = "kclk";
+				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 93 0x400 0x01>,
+				       <&dmamux1 94 0x400 0x01>;
+				dma-names = "rx", "rx-ctrl";
+				feature-domains = <&etzpc 29>;
+				status = "disabled";
+			};
+
+			usart2: serial@4000e000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x4000e000 0x400>;
+				interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART2_K>;
+				wakeup-source;
+				dmas = <&dmamux1 43 0x400 0x15>,
+				       <&dmamux1 44 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 30>;
+				status = "disabled";
+			};
+
+			usart3: serial@4000f000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x4000f000 0x400>;
+				interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART3_K>;
+				wakeup-source;
+				dmas = <&dmamux1 45 0x400 0x15>,
+				       <&dmamux1 46 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 31>;
+				status = "disabled";
+			};
+
+			uart4: serial@40010000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40010000 0x400>;
+				interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART4_K>;
+				wakeup-source;
+				dmas = <&dmamux1 63 0x400 0x15>,
+				       <&dmamux1 64 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 32>;
+				status = "disabled";
+			};
+
+			uart5: serial@40011000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40011000 0x400>;
+				interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART5_K>;
+				wakeup-source;
+				dmas = <&dmamux1 65 0x400 0x15>,
+				       <&dmamux1 66 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 33>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@40012000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40012000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C1_K>;
+				resets = <&rcc I2C1_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x1>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 34>;
 				status = "disabled";
 			};
-			timer@15 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <15>;
+
+			i2c2: i2c@40013000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40013000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C2_K>;
+				resets = <&rcc I2C2_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x2>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 35>;
 				status = "disabled";
 			};
-		};
 
-		timers17: timer@44008000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44008000 0x400>;
-			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM17_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 111 0x400 0x1>,
-			       <&dmamux1 112 0x400 0x1>;
-			dma-names = "ch1", "up";
-			status = "disabled";
+			i2c3: i2c@40014000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40014000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C3_K>;
+				resets = <&rcc I2C3_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x4>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 36>;
+				status = "disabled";
+			};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			i2c5: i2c@40015000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40015000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C5_K>;
+				resets = <&rcc I2C5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x10>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 37>;
 				status = "disabled";
 			};
 
-			timer@16 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <16>;
+			cec: cec@40016000 {
+				compatible = "st,stm32-cec";
+				reg = <0x40016000 0x400>;
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CEC_K>, <&rcc CEC>;
+				clock-names = "cec", "hdmi-cec";
+				feature-domains = <&etzpc 38>;
 				status = "disabled";
 			};
-		};
 
-		spi5: spi@44009000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44009000 0x400>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI5_K>;
-			resets = <&rcc SPI5_R>;
-			dmas = <&dmamux1 85 0x400 0x05>,
-			       <&dmamux1 86 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			dac: dac@40017000 {
+				compatible = "st,stm32h7-dac-core";
+				reg = <0x40017000 0x400>;
+				clocks = <&rcc DAC12>;
+				clock-names = "pclk";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 39>;
+				status = "disabled";
 
-		sai1: sai@4400a000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400a000 0x400>;
-			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
-			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI1_R>;
-			status = "disabled";
+				dac1: dac@1 {
+					compatible = "st,stm32-dac";
+					#io-channel-cells = <1>;
+					reg = <1>;
+					status = "disabled";
+				};
 
-			sai1a: audio-controller@4400a004 {
-				#sound-dai-cells = <0>;
+				dac2: dac@2 {
+					compatible = "st,stm32-dac";
+					#io-channel-cells = <1>;
+					reg = <2>;
+					status = "disabled";
+				};
+			};
 
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x4 0x20>;
-				clocks = <&rcc SAI1_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 87 0x400 0x01>;
+			uart7: serial@40018000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40018000 0x400>;
+				interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART7_K>;
+				wakeup-source;
+				dmas = <&dmamux1 79 0x400 0x15>,
+				       <&dmamux1 80 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 40>;
 				status = "disabled";
 			};
 
-			sai1b: audio-controller@4400a024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI1_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 88 0x400 0x01>;
+			uart8: serial@40019000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40019000 0x400>;
+				interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART8_K>;
+				wakeup-source;
+				dmas = <&dmamux1 81 0x400 0x15>,
+				       <&dmamux1 82 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 41>;
 				status = "disabled";
 			};
-		};
 
-		sai2: sai@4400b000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400b000 0x400>;
-			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
-			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI2_R>;
-			status = "disabled";
+			timers1: timer@44000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44000000 0x400>;
+				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "brk", "up", "trg-com", "cc";
+				clocks = <&rcc TIM1_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 11 0x400 0x1>,
+				       <&dmamux1 12 0x400 0x1>,
+				       <&dmamux1 13 0x400 0x1>,
+				       <&dmamux1 14 0x400 0x1>,
+				       <&dmamux1 15 0x400 0x1>,
+				       <&dmamux1 16 0x400 0x1>,
+				       <&dmamux1 17 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4",
+					    "up", "trig", "com";
+				feature-domains = <&etzpc 48>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			sai2a: audio-controller@4400b004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x4 0x20>;
-				clocks = <&rcc SAI2_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 89 0x400 0x01>;
-				status = "disabled";
-			};
+				timer@0 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <0>;
+					status = "disabled";
+				};
 
-			sai2b: audio-controller@4400b024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI2_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 90 0x400 0x01>;
-				status = "disabled";
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
 			};
-		};
 
-		sai3: sai@4400c000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400c000 0x400>;
-			reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
-			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI3_R>;
-			status = "disabled";
+			timers8: timer@44001000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44001000 0x400>;
+				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "brk", "up", "trg-com", "cc";
+				clocks = <&rcc TIM8_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 47 0x400 0x1>,
+				       <&dmamux1 48 0x400 0x1>,
+				       <&dmamux1 49 0x400 0x1>,
+				       <&dmamux1 50 0x400 0x1>,
+				       <&dmamux1 51 0x400 0x1>,
+				       <&dmamux1 52 0x400 0x1>,
+				       <&dmamux1 53 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4",
+					    "up", "trig", "com";
+				feature-domains = <&etzpc 49>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			sai3a: audio-controller@4400c004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x04 0x20>;
-				clocks = <&rcc SAI3_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 113 0x400 0x01>;
+				timer@7 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <7>;
+					status = "disabled";
+				};
+
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
+
+			usart6: serial@44003000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x44003000 0x400>;
+				interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART6_K>;
+				wakeup-source;
+				dmas = <&dmamux1 71 0x400 0x15>,
+				<&dmamux1 72 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 51>;
 				status = "disabled";
 			};
 
-			sai3b: audio-controller@4400c024 {
+			i2s1: audio-controller@44004000 {
+				compatible = "st,stm32h7-i2s";
 				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI3_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 114 0x400 0x01>;
+				reg = <0x44004000 0x400>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 37 0x400 0x01>,
+				<&dmamux1 38 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 52>;
 				status = "disabled";
 			};
-		};
-
-		dfsdm: dfsdm@4400d000 {
-			compatible = "st,stm32mp1-dfsdm";
-			reg = <0x4400d000 0x800>;
-			clocks = <&rcc DFSDM_K>;
-			clock-names = "dfsdm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
 
-			dfsdm0: filter@0 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <0>;
-				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 101 0x400 0x01>;
-				dma-names = "rx";
+			spi1: spi@44004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44004000 0x400>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI1_K>;
+				resets = <&rcc SPI1_R>;
+				dmas = <&dmamux1 37 0x400 0x05>,
+				<&dmamux1 38 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 52>;
 				status = "disabled";
 			};
 
-			dfsdm1: filter@1 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <1>;
-				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 102 0x400 0x01>;
-				dma-names = "rx";
+			spi4: spi@44005000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44005000 0x400>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI4_K>;
+				resets = <&rcc SPI4_R>;
+				dmas = <&dmamux1 83 0x400 0x05>,
+				<&dmamux1 84 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 53>;
 				status = "disabled";
 			};
 
-			dfsdm2: filter@2 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <2>;
-				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 103 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers15: timer@44006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44006000 0x400>;
+				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM15_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 105 0x400 0x1>,
+				       <&dmamux1 106 0x400 0x1>,
+				       <&dmamux1 107 0x400 0x1>,
+				       <&dmamux1 108 0x400 0x1>;
+				dma-names = "ch1", "up", "trig", "com";
+				feature-domains = <&etzpc 54>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+
+				timer@14 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <14>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm3: filter@3 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <3>;
-				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 104 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers16: timer@44007000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44007000 0x400>;
+				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM16_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 109 0x400 0x1>,
+				<&dmamux1 110 0x400 0x1>;
+				dma-names = "ch1", "up";
+				feature-domains = <&etzpc 55>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+				timer@15 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <15>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm4: filter@4 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <4>;
-				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 91 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers17: timer@44008000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44008000 0x400>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM17_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 111 0x400 0x1>,
+				<&dmamux1 112 0x400 0x1>;
+				dma-names = "ch1", "up";
+				feature-domains = <&etzpc 56>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+
+				timer@16 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <16>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm5: filter@5 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <5>;
-				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 92 0x400 0x01>;
-				dma-names = "rx";
+			spi5: spi@44009000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44009000 0x400>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI5_K>;
+				resets = <&rcc SPI5_R>;
+				dmas = <&dmamux1 85 0x400 0x05>,
+				<&dmamux1 86 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 57>;
 				status = "disabled";
 			};
-		};
 
-		dma1: dma-controller@48000000 {
-			compatible = "st,stm32-dma";
-			reg = <0x48000000 0x400>;
-			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc DMA1>;
-			resets = <&rcc DMA1_R>;
-			#dma-cells = <4>;
-			st,mem2mem;
-			dma-requests = <8>;
-		};
+			sai1: sai@4400a000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400a000 0x400>;
+				reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI1_R>;
+				feature-domains = <&etzpc 58>;
+				status = "disabled";
+
+				sai1a: audio-controller@4400a004 {
+					#sound-dai-cells = <0>;
+
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					clocks = <&rcc SAI1_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 87 0x400 0x01>;
+					status = "disabled";
+				};
 
-		dma2: dma-controller@48001000 {
-			compatible = "st,stm32-dma";
-			reg = <0x48001000 0x400>;
-			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc DMA2>;
-			resets = <&rcc DMA2_R>;
-			#dma-cells = <4>;
-			st,mem2mem;
-			dma-requests = <8>;
-		};
+				sai1b: audio-controller@4400a024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI1_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 88 0x400 0x01>;
+					status = "disabled";
+				};
+			};
 
-		dmamux1: dma-router@48002000 {
-			compatible = "st,stm32h7-dmamux";
-			reg = <0x48002000 0x40>;
-			#dma-cells = <3>;
-			dma-requests = <128>;
-			dma-masters = <&dma1 &dma2>;
-			dma-channels = <16>;
-			clocks = <&rcc DMAMUX>;
-			resets = <&rcc DMAMUX_R>;
-		};
+			sai2: sai@4400b000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400b000 0x400>;
+				reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI2_R>;
+				feature-domains = <&etzpc 59>;
+				status = "disabled";
+
+				sai2a: audio-controller@4400b004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					clocks = <&rcc SAI2_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 89 0x400 0x01>;
+					status = "disabled";
+				};
 
-		adc: adc@48003000 {
-			compatible = "st,stm32mp1-adc-core";
-			reg = <0x48003000 0x400>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			st,syscfg = <&syscfg>;
-			#interrupt-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
+				sai2b: audio-controller@4400b024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI2_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 90 0x400 0x01>;
+					status = "disabled";
+				};
+			};
 
-			adc1: adc@0 {
-				compatible = "st,stm32mp1-adc";
-				#io-channel-cells = <1>;
-				reg = <0x0>;
-				interrupt-parent = <&adc>;
-				interrupts = <0>;
-				dmas = <&dmamux1 9 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			sai3: sai@4400c000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400c000 0x400>;
+				reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI3_R>;
+				feature-domains = <&etzpc 60>;
+				status = "disabled";
+
+				sai3a: audio-controller@4400c004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x04 0x20>;
+					clocks = <&rcc SAI3_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 113 0x400 0x01>;
+					status = "disabled";
+				};
+
+				sai3b: audio-controller@4400c024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI3_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 114 0x400 0x01>;
+					status = "disabled";
+				};
 			};
 
-			adc2: adc@100 {
-				compatible = "st,stm32mp1-adc";
-				#io-channel-cells = <1>;
-				reg = <0x100>;
-				interrupt-parent = <&adc>;
-				interrupts = <1>;
-				dmas = <&dmamux1 10 0x400 0x01>;
-				dma-names = "rx";
+			dfsdm: dfsdm@4400d000 {
+				compatible = "st,stm32mp1-dfsdm";
+				reg = <0x4400d000 0x800>;
+				clocks = <&rcc DFSDM_K>;
+				clock-names = "dfsdm";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 61>;
 				status = "disabled";
-			};
-		};
 
-		sdmmc3: mmc@48004000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x48004000 0x400>;
-			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC3_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC3_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
+				dfsdm0: filter@0 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <0>;
+					interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 101 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		usbotg_hs: usb-otg@49000000 {
-			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-			reg = <0x49000000 0x10000>;
-			clocks = <&rcc USBO_K>;
-			clock-names = "otg";
-			resets = <&rcc USBO_R>;
-			reset-names = "dwc2";
-			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-			g-rx-fifo-size = <512>;
-			g-np-tx-fifo-size = <32>;
-			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-			dr_mode = "otg";
-			otg-rev = <0x200>;
-			usb33d-supply = <&usb33>;
-			status = "disabled";
-		};
+				dfsdm1: filter@1 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <1>;
+					interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 102 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		ipcc: mailbox@4c001000 {
-			compatible = "st,stm32mp1-ipcc";
-			#mbox-cells = <1>;
-			reg = <0x4c001000 0x400>;
-			st,proc-id = <0>;
-			interrupts-extended =
-				<&exti 61 1>,
-				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "rx", "tx";
-			clocks = <&rcc IPCC>;
-			wakeup-source;
-			status = "disabled";
-		};
-
-		dcmi: dcmi@4c006000 {
-			compatible = "st,stm32-dcmi";
-			reg = <0x4c006000 0x400>;
-			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc CAMITF_R>;
-			clocks = <&rcc DCMI>;
-			clock-names = "mclk";
-			dmas = <&dmamux1 75 0x400 0x01>;
-			dma-names = "tx";
-			status = "disabled";
-		};
+				dfsdm2: filter@2 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <2>;
+					interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 103 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		rcc: rcc@50000000 {
-			compatible = "st,stm32mp1-rcc", "syscon";
-			reg = <0x50000000 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
+				dfsdm3: filter@3 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <3>;
+					interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 104 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		pwr_regulators: pwr@50001000 {
-			compatible = "st,stm32mp1,pwr-reg";
-			reg = <0x50001000 0x10>;
+				dfsdm4: filter@4 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <4>;
+					interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 91 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-			reg11: reg11 {
-				regulator-name = "reg11";
-				regulator-min-microvolt = <1100000>;
-				regulator-max-microvolt = <1100000>;
+				dfsdm5: filter@5 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <5>;
+					interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 92 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 			};
 
-			reg18: reg18 {
-				regulator-name = "reg18";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-			};
+			dma1: dma-controller@48000000 {
+				compatible = "st,stm32-dma";
+				reg = <0x48000000 0x400>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc DMA1>;
+				resets = <&rcc DMA1_R>;
+				#dma-cells = <4>;
+				st,mem2mem;
+				dma-requests = <8>;
+				feature-domains = <&etzpc 88>;
+			};
+
+			dma2: dma-controller@48001000 {
+				compatible = "st,stm32-dma";
+				reg = <0x48001000 0x400>;
+				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc DMA2>;
+				resets = <&rcc DMA2_R>;
+				#dma-cells = <4>;
+				st,mem2mem;
+				dma-requests = <8>;
+				feature-domains = <&etzpc 89>;
+			};
+
+			dmamux1: dma-router@48002000 {
+				compatible = "st,stm32h7-dmamux";
+				reg = <0x48002000 0x40>;
+				#dma-cells = <3>;
+				dma-requests = <128>;
+				dma-masters = <&dma1 &dma2>;
+				dma-channels = <16>;
+				clocks = <&rcc DMAMUX>;
+				resets = <&rcc DMAMUX_R>;
+				feature-domains = <&etzpc 90>;
+			};
+
+			adc: adc@48003000 {
+				compatible = "st,stm32mp1-adc-core";
+				reg = <0x48003000 0x400>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+				clock-names = "bus", "adc";
+				interrupt-controller;
+				st,syscfg = <&syscfg>;
+				#interrupt-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 72>;
+				status = "disabled";
+
+				adc1: adc@0 {
+					compatible = "st,stm32mp1-adc";
+					#io-channel-cells = <1>;
+					reg = <0x0>;
+					interrupt-parent = <&adc>;
+					interrupts = <0>;
+					dmas = <&dmamux1 9 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-			usb33: usb33 {
-				regulator-name = "usb33";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
+				adc2: adc@100 {
+					compatible = "st,stm32mp1-adc";
+					#io-channel-cells = <1>;
+					reg = <0x100>;
+					interrupt-parent = <&adc>;
+					interrupts = <1>;
+					dmas = <&dmamux1 10 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 			};
-		};
 
-		pwr_mcu: pwr_mcu@50001014 {
-			compatible = "st,stm32mp151-pwr-mcu", "syscon";
-			reg = <0x50001014 0x4>;
-		};
+			sdmmc3: mmc@48004000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x00253180>;
+				reg = <0x48004000 0x400>;
+				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC3_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC3_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <120000000>;
+				feature-domains = <&etzpc 86>;
+				status = "disabled";
+			};
+
+			usbotg_hs: usb-otg@49000000 {
+				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+				reg = <0x49000000 0x10000>;
+				clocks = <&rcc USBO_K>;
+				clock-names = "otg";
+				resets = <&rcc USBO_R>;
+				reset-names = "dwc2";
+				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+				g-rx-fifo-size = <512>;
+				g-np-tx-fifo-size = <32>;
+				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+				dr_mode = "otg";
+				otg-rev = <0x200>;
+				usb33d-supply = <&usb33>;
+				feature-domains = <&etzpc 85>;
+				status = "disabled";
+			};
+
+			dcmi: dcmi@4c006000 {
+				compatible = "st,stm32-dcmi";
+				reg = <0x4c006000 0x400>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc CAMITF_R>;
+				clocks = <&rcc DCMI>;
+				clock-names = "mclk";
+				dmas = <&dmamux1 75 0x400 0x01>;
+				dma-names = "tx";
+				feature-domains = <&etzpc 70>;
+				status = "disabled";
+			};
+
+			lptimer2: timer@50021000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x50021000 0x400>;
+				interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM2_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 64>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		exti: interrupt-controller@5000d000 {
-			compatible = "st,stm32mp1-exti", "syscon";
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			reg = <0x5000d000 0x400>;
-		};
+				trigger@1 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <1>;
+					status = "disabled";
+				};
 
-		syscfg: syscon@50020000 {
-			compatible = "st,stm32mp157-syscfg", "syscon";
-			reg = <0x50020000 0x400>;
-			clocks = <&rcc SYSCFG>;
-		};
+				counter {
+					compatible = "st,stm32-lptimer-counter";
+					status = "disabled";
+				};
+			};
 
-		lptimer2: timer@50021000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x50021000 0x400>;
-			interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM2_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
+			lptimer3: timer@50022000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x50022000 0x400>;
+				interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM3_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 65>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
+				trigger@2 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <2>;
+					status = "disabled";
+				};
 			};
 
-			trigger@1 {
-				compatible = "st,stm32-lptimer-trigger";
-				reg = <1>;
+			lptimer4: timer@50023000 {
+				compatible = "st,stm32-lptimer";
+				reg = <0x50023000 0x400>;
+				interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM4_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 66>;
 				status = "disabled";
-			};
 
-			counter {
-				compatible = "st,stm32-lptimer-counter";
-				status = "disabled";
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 			};
-		};
-
-		lptimer3: timer@50022000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x50022000 0x400>;
-			interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM3_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
+			lptimer5: timer@50024000 {
+				compatible = "st,stm32-lptimer";
+				reg = <0x50024000 0x400>;
+				interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM5_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 67>;
 				status = "disabled";
-			};
 
-			trigger@2 {
-				compatible = "st,stm32-lptimer-trigger";
-				reg = <2>;
-				status = "disabled";
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 			};
-		};
 
-		lptimer4: timer@50023000 {
-			compatible = "st,stm32-lptimer";
-			reg = <0x50023000 0x400>;
-			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM4_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
+			vrefbuf: vrefbuf@50025000 {
+				compatible = "st,stm32-vrefbuf";
+				reg = <0x50025000 0x8>;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <2500000>;
+				clocks = <&rcc VREF>;
+				feature-domains = <&etzpc 69>;
 				status = "disabled";
 			};
-		};
 
-		lptimer5: timer@50024000 {
-			compatible = "st,stm32-lptimer";
-			reg = <0x50024000 0x400>;
-			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM5_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
+			sai4: sai@50027000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x50027000 0x400>;
+				reg = <0x50027000 0x4>, <0x500273f0 0x10>;
+				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI4_R>;
+				feature-domains = <&etzpc 68>;
+				status = "disabled";
+
+				sai4a: audio-controller@50027004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x04 0x20>;
+					clocks = <&rcc SAI4_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 99 0x400 0x01>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
+				sai4b: audio-controller@50027024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI4_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 100 0x400 0x01>;
+					status = "disabled";
+				};
 			};
-		};
 
-		vrefbuf: vrefbuf@50025000 {
-			compatible = "st,stm32-vrefbuf";
-			reg = <0x50025000 0x8>;
-			regulator-min-microvolt = <1500000>;
-			regulator-max-microvolt = <2500000>;
-			clocks = <&rcc VREF>;
-			status = "disabled";
-		};
-
-		sai4: sai@50027000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x50027000 0x400>;
-			reg = <0x50027000 0x4>, <0x500273f0 0x10>;
-			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI4_R>;
-			status = "disabled";
+			hash1: hash@54002000 {
+				compatible = "st,stm32f756-hash";
+				reg = <0x54002000 0x400>;
+				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc HASH1>;
+				resets = <&rcc HASH1_R>;
+				dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
+				dma-names = "in";
+				dma-maxburst = <2>;
+				feature-domains = <&etzpc 8>;
+				status = "disabled";
+			};
+
+			rng1: rng@54003000 {
+				compatible = "st,stm32-rng";
+				reg = <0x54003000 0x400>;
+				clocks = <&rcc RNG1_K>;
+				resets = <&rcc RNG1_R>;
+				feature-domains = <&etzpc 7>;
+				status = "disabled";
+			};
+
+			fmc: memory-controller@58002000 {
+				#address-cells = <2>;
+				#size-cells = <1>;
+				compatible = "st,stm32mp1-fmc2-ebi";
+				reg = <0x58002000 0x1000>;
+				clocks = <&rcc FMC_K>;
+				resets = <&rcc FMC_R>;
+				feature-domains = <&etzpc 91>;
+				status = "disabled";
+
+				ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+					 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+					 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+					 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+					 <4 0 0x80000000 0x10000000>; /* NAND */
+
+				nand-controller@4,0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "st,stm32mp1-fmc2-nfc";
+					reg = <4 0x00000000 0x1000>,
+					      <4 0x08010000 0x1000>,
+					      <4 0x08020000 0x1000>,
+					      <4 0x01000000 0x1000>,
+					      <4 0x09010000 0x1000>,
+					      <4 0x09020000 0x1000>;
+					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+					       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+					       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+					dma-names = "tx", "rx", "ecc";
+					status = "disabled";
+				};
+			};
 
-			sai4a: audio-controller@50027004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x04 0x20>;
-				clocks = <&rcc SAI4_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 99 0x400 0x01>;
-				status = "disabled";
+			qspi: spi@58003000 {
+				compatible = "st,stm32f469-qspi";
+				reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+				reg-names = "qspi", "qspi_mm";
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
+				       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
+				dma-names = "tx", "rx";
+				clocks = <&rcc QSPI_K>;
+				resets = <&rcc QSPI_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 92>;
+				status = "disabled";
+			};
+
+			ethernet0: ethernet@5800a000 {
+				compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+				reg = <0x5800a000 0x2000>;
+				reg-names = "stmmaceth";
+				interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "macirq";
+				clock-names = "stmmaceth",
+					      "mac-clk-tx",
+					      "mac-clk-rx",
+					      "eth-ck",
+					      "ptp_ref",
+					      "ethstp";
+				clocks = <&rcc ETHMAC>,
+					 <&rcc ETHTX>,
+					 <&rcc ETHRX>,
+					 <&rcc ETHCK_K>,
+					 <&rcc ETHPTP_K>,
+					 <&rcc ETHSTP>;
+				st,syscon = <&syscfg 0x4>;
+				snps,mixed-burst;
+				snps,pbl = <2>;
+				snps,en-tx-lpi-clockgating;
+				snps,axi-config = <&stmmac_axi_config_0>;
+				snps,tso;
+				feature-domains = <&etzpc 94>;
+				status = "disabled";
+
+				stmmac_axi_config_0: stmmac-axi-config {
+					snps,wr_osr_lmt = <0x7>;
+					snps,rd_osr_lmt = <0x7>;
+					snps,blen = <0 0 0 0 16 8 4>;
+				};
 			};
 
-			sai4b: audio-controller@50027024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI4_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 100 0x400 0x01>;
+			usart1: serial@5c000000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x5c000000 0x400>;
+				interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART1_K>;
+				wakeup-source;
+				feature-domains = <&etzpc 3>;
 				status = "disabled";
 			};
-		};
 
-		dts: thermal@50028000 {
-			compatible = "st,stm32-thermal";
-			reg = <0x50028000 0x100>;
-			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc TMPSENS>;
-			clock-names = "pclk";
-			#thermal-sensor-cells = <0>;
-			status = "disabled";
-		};
-
-		hash1: hash@54002000 {
-			compatible = "st,stm32f756-hash";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc HASH1>;
-			resets = <&rcc HASH1_R>;
-			dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
-			dma-names = "in";
-			dma-maxburst = <2>;
-			status = "disabled";
-		};
-
-		rng1: rng@54003000 {
-			compatible = "st,stm32-rng";
-			reg = <0x54003000 0x400>;
-			clocks = <&rcc RNG1_K>;
-			resets = <&rcc RNG1_R>;
-			status = "disabled";
-		};
-
-		mdma1: dma-controller@58000000 {
-			compatible = "st,stm32h7-mdma";
-			reg = <0x58000000 0x1000>;
-			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc MDMA>;
-			resets = <&rcc MDMA_R>;
-			#dma-cells = <5>;
-			dma-channels = <32>;
-			dma-requests = <48>;
-		};
-
-		fmc: memory-controller@58002000 {
-			#address-cells = <2>;
-			#size-cells = <1>;
-			compatible = "st,stm32mp1-fmc2-ebi";
-			reg = <0x58002000 0x1000>;
-			clocks = <&rcc FMC_K>;
-			resets = <&rcc FMC_R>;
-			status = "disabled";
-
-			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
-				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
-				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
-				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
-				 <4 0 0x80000000 0x10000000>; /* NAND */
-
-			nand-controller@4,0 {
+			spi6: spi@5c001000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "st,stm32mp1-fmc2-nfc";
-				reg = <4 0x00000000 0x1000>,
-				      <4 0x08010000 0x1000>,
-				      <4 0x08020000 0x1000>,
-				      <4 0x01000000 0x1000>,
-				      <4 0x09010000 0x1000>,
-				      <4 0x09020000 0x1000>;
-				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
-				       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
-				       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
-				dma-names = "tx", "rx", "ecc";
+				compatible = "st,stm32h7-spi";
+				reg = <0x5c001000 0x400>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI6_K>;
+				resets = <&rcc SPI6_R>;
+				dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
+				       <&mdma1 35 0x0 0x40002 0x0 0x0>;
+				feature-domains = <&etzpc 4>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			i2c4: i2c@5c002000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x5c002000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C4_K>;
+				resets = <&rcc I2C4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x8>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 5>;
 				status = "disabled";
 			};
-		};
-
-		qspi: spi@58003000 {
-			compatible = "st,stm32f469-qspi";
-			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
-			reg-names = "qspi", "qspi_mm";
-			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
-			       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
-			dma-names = "tx", "rx";
-			clocks = <&rcc QSPI_K>;
-			resets = <&rcc QSPI_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		sdmmc1: mmc@58005000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x58005000 0x1000>;
-			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC1_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC1_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
-
-		sdmmc2: mmc@58007000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x58007000 0x1000>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC2_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC2_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
-
-		crc1: crc@58009000 {
-			compatible = "st,stm32f7-crc";
-			reg = <0x58009000 0x400>;
-			clocks = <&rcc CRC1>;
-			status = "disabled";
-		};
-
-		ethernet0: ethernet@5800a000 {
-			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
-			reg = <0x5800a000 0x2000>;
-			reg-names = "stmmaceth";
-			interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
-			clock-names = "stmmaceth",
-				      "mac-clk-tx",
-				      "mac-clk-rx",
-				      "eth-ck",
-				      "ptp_ref",
-				      "ethstp";
-			clocks = <&rcc ETHMAC>,
-				 <&rcc ETHTX>,
-				 <&rcc ETHRX>,
-				 <&rcc ETHCK_K>,
-				 <&rcc ETHPTP_K>,
-				 <&rcc ETHSTP>;
-			st,syscon = <&syscfg 0x4>;
-			snps,mixed-burst;
-			snps,pbl = <2>;
-			snps,en-tx-lpi-clockgating;
-			snps,axi-config = <&stmmac_axi_config_0>;
-			snps,tso;
-			status = "disabled";
-
-			stmmac_axi_config_0: stmmac-axi-config {
-				snps,wr_osr_lmt = <0x7>;
-				snps,rd_osr_lmt = <0x7>;
-				snps,blen = <0 0 0 0 16 8 4>;
-			};
-		};
 
-		usbh_ohci: usb@5800c000 {
-			compatible = "generic-ohci";
-			reg = <0x5800c000 0x1000>;
-			clocks = <&usbphyc>, <&rcc USBH>;
-			resets = <&rcc USBH_R>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		usbh_ehci: usb@5800d000 {
-			compatible = "generic-ehci";
-			reg = <0x5800d000 0x1000>;
-			clocks = <&usbphyc>, <&rcc USBH>;
-			resets = <&rcc USBH_R>;
-			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			companion = <&usbh_ohci>;
-			status = "disabled";
-		};
-
-		ltdc: display-controller@5a001000 {
-			compatible = "st,stm32-ltdc";
-			reg = <0x5a001000 0x400>;
-			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LTDC_PX>;
-			clock-names = "lcd";
-			resets = <&rcc LTDC_R>;
-			status = "disabled";
-
-			port {
+			i2c6: i2c@5c009000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x5c009000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C6_K>;
+				resets = <&rcc I2C6_R>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x20>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 12>;
+				status = "disabled";
 			};
-		};
-
-		iwdg2: watchdog@5a002000 {
-			compatible = "st,stm32mp1-iwdg";
-			reg = <0x5a002000 0x400>;
-			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
-			clock-names = "pclk", "lsi";
-			status = "disabled";
-		};
-
-		usbphyc: usbphyc@5a006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#clock-cells = <0>;
-			compatible = "st,stm32mp1-usbphyc";
-			reg = <0x5a006000 0x1000>;
-			clocks = <&rcc USBPHY_K>;
-			resets = <&rcc USBPHY_R>;
-			vdda1v1-supply = <&reg11>;
-			vdda1v8-supply = <&reg18>;
-			status = "disabled";
-
-			usbphyc_port0: usb-phy@0 {
-				#phy-cells = <0>;
-				reg = <0>;
-			};
-
-			usbphyc_port1: usb-phy@1 {
-				#phy-cells = <1>;
-				reg = <1>;
-			};
-		};
-
-		usart1: serial@5c000000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x5c000000 0x400>;
-			interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART1_K>;
-			wakeup-source;
-			status = "disabled";
-		};
-
-		spi6: spi@5c001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x5c001000 0x400>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI6_K>;
-			resets = <&rcc SPI6_R>;
-			dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
-			       <&mdma1 35 0x0 0x40002 0x0 0x0>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2c4: i2c@5c002000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x5c002000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C4_K>;
-			resets = <&rcc I2C4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x8>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		rtc: rtc@5c004000 {
-			compatible = "st,stm32mp1-rtc";
-			reg = <0x5c004000 0x400>;
-			clocks = <&rcc RTCAPB>, <&rcc RTC>;
-			clock-names = "pclk", "rtc_ck";
-			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		bsec: efuse@5c005000 {
-			compatible = "st,stm32mp15-bsec";
-			reg = <0x5c005000 0x400>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ts_cal1: calib@5c {
-				reg = <0x5c 0x2>;
-			};
-			ts_cal2: calib@5e {
-				reg = <0x5e 0x2>;
-			};
-		};
 
-		i2c6: i2c@5c009000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x5c009000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C6_K>;
-			resets = <&rcc I2C6_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x20>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
 		};
 
 		tamp: tamp@5c00a000 {
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi
index 486084e0b80b..82073dd85f18 100644
--- a/arch/arm/boot/dts/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/stm32mp153.dtsi
@@ -28,32 +28,34 @@ timer {
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+};
 
-	soc {
-		m_can1: can@4400e000 {
-			compatible = "bosch,m_can";
-			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
-			reg-names = "m_can", "message_ram";
-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "int0", "int1";
-			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-			clock-names = "hclk", "cclk";
-			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
-			status = "disabled";
-		};
+&etzpc {
+	m_can1: can@4400e000 {
+		compatible = "bosch,m_can";
+		reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+		reg-names = "m_can", "message_ram";
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "int0", "int1";
+		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+		clock-names = "hclk", "cclk";
+		bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+		feature-domains = <&etzpc 62>;
+		status = "disabled";
+	};
 
-		m_can2: can@4400f000 {
-			compatible = "bosch,m_can";
-			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
-			reg-names = "m_can", "message_ram";
-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "int0", "int1";
-			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-			clock-names = "hclk", "cclk";
-			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
-			status = "disabled";
-		};
+	m_can2: can@4400f000 {
+		compatible = "bosch,m_can";
+		reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+		reg-names = "m_can", "message_ram";
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "int0", "int1";
+		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+		clock-names = "hclk", "cclk";
+		bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+		feature-domains = <&etzpc 62>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi
index b06a55a2fa18..55524a8d3093 100644
--- a/arch/arm/boot/dts/stm32mp15xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xc.dtsi
@@ -4,15 +4,14 @@
  * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp1: cryp@54001000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54001000 0x400>;
-			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp1: cryp@54001000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54001000 0x400>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		feature-domains = <&etzpc 9>;
+		status = "disabled";
 	};
 };
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 5/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

The STM32 System Bus is an internal bus on which devices are connected.
ETZPC is a peripheral overseeing the firewall bus that configures
and control access to the peripherals connected on it.

For more information on which peripheral is securable, please read
the STM32MP15 reference manual.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

No changes in V2.

Changes in V3:
	-Use appriopriate node name: bus

 arch/arm/boot/dts/stm32mp151.dtsi  | 2722 ++++++++++++++--------------
 arch/arm/boot/dts/stm32mp153.dtsi  |   52 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi |   19 +-
 3 files changed, 1434 insertions(+), 1359 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index 5491b6c4dec2..5dab96e7c2ba 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -122,1526 +122,1600 @@ soc {
 		interrupt-parent = <&intc>;
 		ranges;
 
-		timers2: timer@40000000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40000000 0x400>;
-			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM2_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 18 0x400 0x1>,
-			       <&dmamux1 19 0x400 0x1>,
-			       <&dmamux1 20 0x400 0x1>,
-			       <&dmamux1 21 0x400 0x1>,
-			       <&dmamux1 22 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+		ipcc: mailbox@4c001000 {
+			compatible = "st,stm32mp1-ipcc";
+			#mbox-cells = <1>;
+			reg = <0x4c001000 0x400>;
+			st,proc-id = <0>;
+			interrupts-extended =
+				<&exti 61 1>,
+				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "rx", "tx";
+			clocks = <&rcc IPCC>;
+			wakeup-source;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@1 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <1>;
-				status = "disabled";
-			};
-
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		rcc: rcc@50000000 {
+			compatible = "st,stm32mp1-rcc", "syscon";
+			reg = <0x50000000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
-		timers3: timer@40001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40001000 0x400>;
-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM3_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 23 0x400 0x1>,
-			       <&dmamux1 24 0x400 0x1>,
-			       <&dmamux1 25 0x400 0x1>,
-			       <&dmamux1 26 0x400 0x1>,
-			       <&dmamux1 27 0x400 0x1>,
-			       <&dmamux1 28 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
-			status = "disabled";
+		pwr_regulators: pwr@50001000 {
+			compatible = "st,stm32mp1,pwr-reg";
+			reg = <0x50001000 0x10>;
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+			reg11: reg11 {
+				regulator-name = "reg11";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
 			};
 
-			timer@2 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <2>;
-				status = "disabled";
+			reg18: reg18 {
+				regulator-name = "reg18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
 			};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
+			usb33: usb33 {
+				regulator-name = "usb33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
 			};
 		};
 
-		timers4: timer@40002000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40002000 0x400>;
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM4_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 29 0x400 0x1>,
-			       <&dmamux1 30 0x400 0x1>,
-			       <&dmamux1 31 0x400 0x1>,
-			       <&dmamux1 32 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4";
-			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
+		pwr_mcu: pwr_mcu@50001014 {
+			compatible = "st,stm32mp151-pwr-mcu", "syscon";
+			reg = <0x50001014 0x4>;
+		};
 
-			timer@3 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <3>;
-				status = "disabled";
-			};
+		exti: interrupt-controller@5000d000 {
+			compatible = "st,stm32mp1-exti", "syscon";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x5000d000 0x400>;
+		};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		syscfg: syscon@50020000 {
+			compatible = "st,stm32mp157-syscfg", "syscon";
+			reg = <0x50020000 0x400>;
+			clocks = <&rcc SYSCFG>;
 		};
 
-		timers5: timer@40003000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40003000 0x400>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM5_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 55 0x400 0x1>,
-			       <&dmamux1 56 0x400 0x1>,
-			       <&dmamux1 57 0x400 0x1>,
-			       <&dmamux1 58 0x400 0x1>,
-			       <&dmamux1 59 0x400 0x1>,
-			       <&dmamux1 60 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+		dts: thermal@50028000 {
+			compatible = "st,stm32-thermal";
+			reg = <0x50028000 0x100>;
+			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc TMPSENS>;
+			clock-names = "pclk";
+			#thermal-sensor-cells = <0>;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@4 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <4>;
-				status = "disabled";
-			};
-
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		mdma1: dma-controller@58000000 {
+			compatible = "st,stm32h7-mdma";
+			reg = <0x58000000 0x1000>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc MDMA>;
+			resets = <&rcc MDMA_R>;
+			#dma-cells = <5>;
+			dma-channels = <32>;
+			dma-requests = <48>;
 		};
 
-		timers6: timer@40004000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40004000 0x400>;
-			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM6_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 69 0x400 0x1>;
-			dma-names = "up";
+		sdmmc1: mmc@58005000 {
+			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+			arm,primecell-periphid = <0x00253180>;
+			reg = <0x58005000 0x1000>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SDMMC1_K>;
+			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC1_R>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
 			status = "disabled";
-
-			timer@5 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <5>;
-				status = "disabled";
-			};
 		};
 
-		timers7: timer@40005000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40005000 0x400>;
-			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM7_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 70 0x400 0x1>;
-			dma-names = "up";
+		sdmmc2: mmc@58007000 {
+			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+			arm,primecell-periphid = <0x00253180>;
+			reg = <0x58007000 0x1000>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SDMMC2_K>;
+			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC2_R>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
 			status = "disabled";
-
-			timer@6 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <6>;
-				status = "disabled";
-			};
 		};
 
-		timers12: timer@40006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40006000 0x400>;
-			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM12_K>;
-			clock-names = "int";
+		crc1: crc@58009000 {
+			compatible = "st,stm32f7-crc";
+			reg = <0x58009000 0x400>;
+			clocks = <&rcc CRC1>;
 			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@11 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <11>;
-				status = "disabled";
-			};
 		};
 
-		timers13: timer@40007000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40007000 0x400>;
-			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM13_K>;
-			clock-names = "int";
+		usbh_ohci: usb@5800c000 {
+			compatible = "generic-ohci";
+			reg = <0x5800c000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@12 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <12>;
-				status = "disabled";
-			};
+		usbh_ehci: usb@5800d000 {
+			compatible = "generic-ehci";
+			reg = <0x5800d000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			companion = <&usbh_ohci>;
+			status = "disabled";
 		};
 
-		timers14: timer@40008000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40008000 0x400>;
-			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM14_K>;
-			clock-names = "int";
+		ltdc: display-controller@5a001000 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x5a001000 0x400>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LTDC_PX>;
+			clock-names = "lcd";
+			resets = <&rcc LTDC_R>;
 			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
 			};
+		};
 
-			timer@13 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <13>;
-				status = "disabled";
-			};
+		iwdg2: watchdog@5a002000 {
+			compatible = "st,stm32mp1-iwdg";
+			reg = <0x5a002000 0x400>;
+			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
+			clock-names = "pclk", "lsi";
+			status = "disabled";
 		};
 
-		lptimer1: timer@40009000 {
+		usbphyc: usbphyc@5a006000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x40009000 0x400>;
-			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM1_K>;
-			clock-names = "mux";
-			wakeup-source;
+			#clock-cells = <0>;
+			compatible = "st,stm32mp1-usbphyc";
+			reg = <0x5a006000 0x1000>;
+			clocks = <&rcc USBPHY_K>;
+			resets = <&rcc USBPHY_R>;
+			vdda1v1-supply = <&reg11>;
+			vdda1v8-supply = <&reg18>;
 			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			trigger@0 {
-				compatible = "st,stm32-lptimer-trigger";
+			usbphyc_port0: usb-phy@0 {
+				#phy-cells = <0>;
 				reg = <0>;
-				status = "disabled";
 			};
 
-			counter {
-				compatible = "st,stm32-lptimer-counter";
-				status = "disabled";
+			usbphyc_port1: usb-phy@1 {
+				#phy-cells = <1>;
+				reg = <1>;
 			};
 		};
 
-		spi2: spi@4000b000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x4000b000 0x400>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI2_K>;
-			resets = <&rcc SPI2_R>;
-			dmas = <&dmamux1 39 0x400 0x05>,
-			       <&dmamux1 40 0x400 0x05>;
-			dma-names = "rx", "tx";
+		rtc: rtc@5c004000 {
+			compatible = "st,stm32mp1-rtc";
+			reg = <0x5c004000 0x400>;
+			clocks = <&rcc RTCAPB>, <&rcc RTC>;
+			clock-names = "pclk", "rtc_ck";
+			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
-		i2s2: audio-controller@4000b000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x4000b000 0x400>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 39 0x400 0x01>,
-			       <&dmamux1 40 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
+		bsec: efuse@5c005000 {
+			compatible = "st,stm32mp15-bsec";
+			reg = <0x5c005000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ts_cal1: calib@5c {
+				reg = <0x5c 0x2>;
+			};
+			ts_cal2: calib@5e {
+				reg = <0x5e 0x2>;
+			};
 		};
 
-		spi3: spi@4000c000 {
+		etzpc: bus@5c007000 {
+			compatible = "st,stm32mp15-sys-bus";
+			reg = <0x5c007000 0x400>;
 			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x4000c000 0x400>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI3_K>;
-			resets = <&rcc SPI3_R>;
-			dmas = <&dmamux1 61 0x400 0x05>,
-			       <&dmamux1 62 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			#size-cells = <1>;
+			feature-domain-controller;
+			#feature-domain-cells = <1>;
+			ranges;
 
-		i2s3: audio-controller@4000c000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x4000c000 0x400>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 61 0x400 0x01>,
-			       <&dmamux1 62 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers2: timer@40000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40000000 0x400>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM2_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 18 0x400 0x1>,
+				       <&dmamux1 19 0x400 0x1>,
+				       <&dmamux1 20 0x400 0x1>,
+				       <&dmamux1 21 0x400 0x1>,
+				       <&dmamux1 22 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+				feature-domains = <&etzpc 16>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		spdifrx: audio-controller@4000d000 {
-			compatible = "st,stm32h7-spdifrx";
-			#sound-dai-cells = <0>;
-			reg = <0x4000d000 0x400>;
-			clocks = <&rcc SPDIF_K>;
-			clock-names = "kclk";
-			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 93 0x400 0x01>,
-			       <&dmamux1 94 0x400 0x01>;
-			dma-names = "rx", "rx-ctrl";
-			status = "disabled";
-		};
+				timer@1 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <1>;
+					status = "disabled";
+				};
 
-		usart2: serial@4000e000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x4000e000 0x400>;
-			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART2_K>;
-			wakeup-source;
-			dmas = <&dmamux1 43 0x400 0x15>,
-			       <&dmamux1 44 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		usart3: serial@4000f000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x4000f000 0x400>;
-			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART3_K>;
-			wakeup-source;
-			dmas = <&dmamux1 45 0x400 0x15>,
-			       <&dmamux1 46 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers3: timer@40001000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40001000 0x400>;
+				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM3_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 23 0x400 0x1>,
+				       <&dmamux1 24 0x400 0x1>,
+				       <&dmamux1 25 0x400 0x1>,
+				       <&dmamux1 26 0x400 0x1>,
+				       <&dmamux1 27 0x400 0x1>,
+				       <&dmamux1 28 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+				feature-domains = <&etzpc 17>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		uart4: serial@40010000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40010000 0x400>;
-			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART4_K>;
-			wakeup-source;
-			dmas = <&dmamux1 63 0x400 0x15>,
-			       <&dmamux1 64 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				timer@2 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <2>;
+					status = "disabled";
+				};
 
-		uart5: serial@40011000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40011000 0x400>;
-			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART5_K>;
-			wakeup-source;
-			dmas = <&dmamux1 65 0x400 0x15>,
-			       <&dmamux1 66 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		i2c1: i2c@40012000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40012000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C1_K>;
-			resets = <&rcc I2C1_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x1>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+			timers4: timer@40002000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40002000 0x400>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM4_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 29 0x400 0x1>,
+				       <&dmamux1 30 0x400 0x1>,
+				       <&dmamux1 31 0x400 0x1>,
+				       <&dmamux1 32 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4";
+				feature-domains = <&etzpc 18>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		i2c2: i2c@40013000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40013000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C2_K>;
-			resets = <&rcc I2C2_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x2>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+				timer@3 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <3>;
+					status = "disabled";
+				};
 
-		i2c3: i2c@40014000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40014000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C3_K>;
-			resets = <&rcc I2C3_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x4>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		i2c5: i2c@40015000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40015000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C5_K>;
-			resets = <&rcc I2C5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x10>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+			timers5: timer@40003000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40003000 0x400>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM5_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 55 0x400 0x1>,
+				       <&dmamux1 56 0x400 0x1>,
+				       <&dmamux1 57 0x400 0x1>,
+				       <&dmamux1 58 0x400 0x1>,
+				       <&dmamux1 59 0x400 0x1>,
+				       <&dmamux1 60 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+				feature-domains = <&etzpc 19>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		cec: cec@40016000 {
-			compatible = "st,stm32-cec";
-			reg = <0x40016000 0x400>;
-			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CEC_K>, <&rcc CEC>;
-			clock-names = "cec", "hdmi-cec";
-			status = "disabled";
-		};
+				timer@4 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <4>;
+					status = "disabled";
+				};
 
-		dac: dac@40017000 {
-			compatible = "st,stm32h7-dac-core";
-			reg = <0x40017000 0x400>;
-			clocks = <&rcc DAC12>;
-			clock-names = "pclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-			dac1: dac@1 {
-				compatible = "st,stm32-dac";
-				#io-channel-cells = <1>;
-				reg = <1>;
-				status = "disabled";
+			timers6: timer@40004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40004000 0x400>;
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM6_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 69 0x400 0x1>;
+				dma-names = "up";
+				feature-domains = <&etzpc 20>;
+				status = "disabled";
+
+				timer@5 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <5>;
+					status = "disabled";
+				};
 			};
 
-			dac2: dac@2 {
-				compatible = "st,stm32-dac";
-				#io-channel-cells = <1>;
-				reg = <2>;
-				status = "disabled";
+			timers7: timer@40005000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40005000 0x400>;
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM7_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 70 0x400 0x1>;
+				dma-names = "up";
+				feature-domains = <&etzpc 21>;
+				status = "disabled";
+
+				timer@6 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <6>;
+					status = "disabled";
+				};
 			};
-		};
 
-		uart7: serial@40018000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40018000 0x400>;
-			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART7_K>;
-			wakeup-source;
-			dmas = <&dmamux1 79 0x400 0x15>,
-			       <&dmamux1 80 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers12: timer@40006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40006000 0x400>;
+				interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM12_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 22>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		uart8: serial@40019000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40019000 0x400>;
-			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART8_K>;
-			wakeup-source;
-			dmas = <&dmamux1 81 0x400 0x15>,
-			       <&dmamux1 82 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				timer@11 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <11>;
+					status = "disabled";
+				};
+			};
 
-		timers1: timer@44000000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44000000 0x400>;
-			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "brk", "up", "trg-com", "cc";
-			clocks = <&rcc TIM1_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 11 0x400 0x1>,
-			       <&dmamux1 12 0x400 0x1>,
-			       <&dmamux1 13 0x400 0x1>,
-			       <&dmamux1 14 0x400 0x1>,
-			       <&dmamux1 15 0x400 0x1>,
-			       <&dmamux1 16 0x400 0x1>,
-			       <&dmamux1 17 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4",
-				    "up", "trig", "com";
-			status = "disabled";
+			timers13: timer@40007000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40007000 0x400>;
+				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM13_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 23>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+				timer@12 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <12>;
+					status = "disabled";
+				};
 			};
 
-			timer@0 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <0>;
-				status = "disabled";
-			};
+			timers14: timer@40008000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40008000 0x400>;
+				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM14_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 24>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
+				timer@13 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <13>;
+					status = "disabled";
+				};
 			};
-		};
 
-		timers8: timer@44001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44001000 0x400>;
-			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "brk", "up", "trg-com", "cc";
-			clocks = <&rcc TIM8_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 47 0x400 0x1>,
-			       <&dmamux1 48 0x400 0x1>,
-			       <&dmamux1 49 0x400 0x1>,
-			       <&dmamux1 50 0x400 0x1>,
-			       <&dmamux1 51 0x400 0x1>,
-			       <&dmamux1 52 0x400 0x1>,
-			       <&dmamux1 53 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4",
-				    "up", "trig", "com";
-			status = "disabled";
+			lptimer1: timer@40009000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x40009000 0x400>;
+				interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM1_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 25>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+				trigger@0 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <0>;
+					status = "disabled";
+				};
+
+				counter {
+					compatible = "st,stm32-lptimer-counter";
+					status = "disabled";
+				};
 			};
 
-			timer@7 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <7>;
+			i2s2: audio-controller@4000b000 {
+				compatible = "st,stm32h7-i2s";
+				#sound-dai-cells = <0>;
+				reg = <0x4000b000 0x400>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 39 0x400 0x01>,
+				       <&dmamux1 40 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 27>;
 				status = "disabled";
 			};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
+			spi2: spi@4000b000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x4000b000 0x400>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI2_K>;
+				resets = <&rcc SPI2_R>;
+				dmas = <&dmamux1 39 0x400 0x05>,
+				       <&dmamux1 40 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 27>;
 				status = "disabled";
 			};
-		};
-
-		usart6: serial@44003000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x44003000 0x400>;
-			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART6_K>;
-			wakeup-source;
-			dmas = <&dmamux1 71 0x400 0x15>,
-			       <&dmamux1 72 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi1: spi@44004000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44004000 0x400>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI1_K>;
-			resets = <&rcc SPI1_R>;
-			dmas = <&dmamux1 37 0x400 0x05>,
-			       <&dmamux1 38 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2s1: audio-controller@44004000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x44004000 0x400>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 37 0x400 0x01>,
-			       <&dmamux1 38 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi4: spi@44005000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44005000 0x400>;
-			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI4_K>;
-			resets = <&rcc SPI4_R>;
-			dmas = <&dmamux1 83 0x400 0x05>,
-			       <&dmamux1 84 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		timers15: timer@44006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44006000 0x400>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM15_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 105 0x400 0x1>,
-			       <&dmamux1 106 0x400 0x1>,
-			       <&dmamux1 107 0x400 0x1>,
-			       <&dmamux1 108 0x400 0x1>;
-			dma-names = "ch1", "up", "trig", "com";
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			i2s3: audio-controller@4000c000 {
+				compatible = "st,stm32h7-i2s";
+				#sound-dai-cells = <0>;
+				reg = <0x4000c000 0x400>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 61 0x400 0x01>,
+				       <&dmamux1 62 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 28>;
 				status = "disabled";
 			};
 
-			timer@14 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <14>;
+			spi3: spi@4000c000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x4000c000 0x400>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI3_K>;
+				resets = <&rcc SPI3_R>;
+				dmas = <&dmamux1 61 0x400 0x05>,
+				       <&dmamux1 62 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 28>;
 				status = "disabled";
 			};
-		};
-
-		timers16: timer@44007000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44007000 0x400>;
-			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM16_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 109 0x400 0x1>,
-			       <&dmamux1 110 0x400 0x1>;
-			dma-names = "ch1", "up";
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			spdifrx: audio-controller@4000d000 {
+				compatible = "st,stm32h7-spdifrx";
+				#sound-dai-cells = <0>;
+				reg = <0x4000d000 0x400>;
+				clocks = <&rcc SPDIF_K>;
+				clock-names = "kclk";
+				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 93 0x400 0x01>,
+				       <&dmamux1 94 0x400 0x01>;
+				dma-names = "rx", "rx-ctrl";
+				feature-domains = <&etzpc 29>;
+				status = "disabled";
+			};
+
+			usart2: serial@4000e000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x4000e000 0x400>;
+				interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART2_K>;
+				wakeup-source;
+				dmas = <&dmamux1 43 0x400 0x15>,
+				       <&dmamux1 44 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 30>;
+				status = "disabled";
+			};
+
+			usart3: serial@4000f000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x4000f000 0x400>;
+				interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART3_K>;
+				wakeup-source;
+				dmas = <&dmamux1 45 0x400 0x15>,
+				       <&dmamux1 46 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 31>;
+				status = "disabled";
+			};
+
+			uart4: serial@40010000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40010000 0x400>;
+				interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART4_K>;
+				wakeup-source;
+				dmas = <&dmamux1 63 0x400 0x15>,
+				       <&dmamux1 64 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 32>;
+				status = "disabled";
+			};
+
+			uart5: serial@40011000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40011000 0x400>;
+				interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART5_K>;
+				wakeup-source;
+				dmas = <&dmamux1 65 0x400 0x15>,
+				       <&dmamux1 66 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 33>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@40012000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40012000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C1_K>;
+				resets = <&rcc I2C1_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x1>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 34>;
 				status = "disabled";
 			};
-			timer@15 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <15>;
+
+			i2c2: i2c@40013000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40013000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C2_K>;
+				resets = <&rcc I2C2_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x2>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 35>;
 				status = "disabled";
 			};
-		};
 
-		timers17: timer@44008000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44008000 0x400>;
-			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM17_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 111 0x400 0x1>,
-			       <&dmamux1 112 0x400 0x1>;
-			dma-names = "ch1", "up";
-			status = "disabled";
+			i2c3: i2c@40014000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40014000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C3_K>;
+				resets = <&rcc I2C3_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x4>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 36>;
+				status = "disabled";
+			};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			i2c5: i2c@40015000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40015000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C5_K>;
+				resets = <&rcc I2C5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x10>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 37>;
 				status = "disabled";
 			};
 
-			timer@16 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <16>;
+			cec: cec@40016000 {
+				compatible = "st,stm32-cec";
+				reg = <0x40016000 0x400>;
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CEC_K>, <&rcc CEC>;
+				clock-names = "cec", "hdmi-cec";
+				feature-domains = <&etzpc 38>;
 				status = "disabled";
 			};
-		};
 
-		spi5: spi@44009000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44009000 0x400>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI5_K>;
-			resets = <&rcc SPI5_R>;
-			dmas = <&dmamux1 85 0x400 0x05>,
-			       <&dmamux1 86 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			dac: dac@40017000 {
+				compatible = "st,stm32h7-dac-core";
+				reg = <0x40017000 0x400>;
+				clocks = <&rcc DAC12>;
+				clock-names = "pclk";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 39>;
+				status = "disabled";
 
-		sai1: sai@4400a000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400a000 0x400>;
-			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
-			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI1_R>;
-			status = "disabled";
+				dac1: dac@1 {
+					compatible = "st,stm32-dac";
+					#io-channel-cells = <1>;
+					reg = <1>;
+					status = "disabled";
+				};
 
-			sai1a: audio-controller@4400a004 {
-				#sound-dai-cells = <0>;
+				dac2: dac@2 {
+					compatible = "st,stm32-dac";
+					#io-channel-cells = <1>;
+					reg = <2>;
+					status = "disabled";
+				};
+			};
 
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x4 0x20>;
-				clocks = <&rcc SAI1_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 87 0x400 0x01>;
+			uart7: serial@40018000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40018000 0x400>;
+				interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART7_K>;
+				wakeup-source;
+				dmas = <&dmamux1 79 0x400 0x15>,
+				       <&dmamux1 80 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 40>;
 				status = "disabled";
 			};
 
-			sai1b: audio-controller@4400a024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI1_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 88 0x400 0x01>;
+			uart8: serial@40019000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40019000 0x400>;
+				interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART8_K>;
+				wakeup-source;
+				dmas = <&dmamux1 81 0x400 0x15>,
+				       <&dmamux1 82 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 41>;
 				status = "disabled";
 			};
-		};
 
-		sai2: sai@4400b000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400b000 0x400>;
-			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
-			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI2_R>;
-			status = "disabled";
+			timers1: timer@44000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44000000 0x400>;
+				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "brk", "up", "trg-com", "cc";
+				clocks = <&rcc TIM1_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 11 0x400 0x1>,
+				       <&dmamux1 12 0x400 0x1>,
+				       <&dmamux1 13 0x400 0x1>,
+				       <&dmamux1 14 0x400 0x1>,
+				       <&dmamux1 15 0x400 0x1>,
+				       <&dmamux1 16 0x400 0x1>,
+				       <&dmamux1 17 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4",
+					    "up", "trig", "com";
+				feature-domains = <&etzpc 48>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			sai2a: audio-controller@4400b004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x4 0x20>;
-				clocks = <&rcc SAI2_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 89 0x400 0x01>;
-				status = "disabled";
-			};
+				timer@0 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <0>;
+					status = "disabled";
+				};
 
-			sai2b: audio-controller@4400b024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI2_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 90 0x400 0x01>;
-				status = "disabled";
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
 			};
-		};
 
-		sai3: sai@4400c000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400c000 0x400>;
-			reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
-			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI3_R>;
-			status = "disabled";
+			timers8: timer@44001000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44001000 0x400>;
+				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "brk", "up", "trg-com", "cc";
+				clocks = <&rcc TIM8_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 47 0x400 0x1>,
+				       <&dmamux1 48 0x400 0x1>,
+				       <&dmamux1 49 0x400 0x1>,
+				       <&dmamux1 50 0x400 0x1>,
+				       <&dmamux1 51 0x400 0x1>,
+				       <&dmamux1 52 0x400 0x1>,
+				       <&dmamux1 53 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4",
+					    "up", "trig", "com";
+				feature-domains = <&etzpc 49>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			sai3a: audio-controller@4400c004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x04 0x20>;
-				clocks = <&rcc SAI3_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 113 0x400 0x01>;
+				timer@7 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <7>;
+					status = "disabled";
+				};
+
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
+
+			usart6: serial@44003000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x44003000 0x400>;
+				interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART6_K>;
+				wakeup-source;
+				dmas = <&dmamux1 71 0x400 0x15>,
+				<&dmamux1 72 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 51>;
 				status = "disabled";
 			};
 
-			sai3b: audio-controller@4400c024 {
+			i2s1: audio-controller@44004000 {
+				compatible = "st,stm32h7-i2s";
 				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI3_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 114 0x400 0x01>;
+				reg = <0x44004000 0x400>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 37 0x400 0x01>,
+				<&dmamux1 38 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 52>;
 				status = "disabled";
 			};
-		};
-
-		dfsdm: dfsdm@4400d000 {
-			compatible = "st,stm32mp1-dfsdm";
-			reg = <0x4400d000 0x800>;
-			clocks = <&rcc DFSDM_K>;
-			clock-names = "dfsdm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
 
-			dfsdm0: filter@0 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <0>;
-				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 101 0x400 0x01>;
-				dma-names = "rx";
+			spi1: spi@44004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44004000 0x400>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI1_K>;
+				resets = <&rcc SPI1_R>;
+				dmas = <&dmamux1 37 0x400 0x05>,
+				<&dmamux1 38 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 52>;
 				status = "disabled";
 			};
 
-			dfsdm1: filter@1 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <1>;
-				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 102 0x400 0x01>;
-				dma-names = "rx";
+			spi4: spi@44005000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44005000 0x400>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI4_K>;
+				resets = <&rcc SPI4_R>;
+				dmas = <&dmamux1 83 0x400 0x05>,
+				<&dmamux1 84 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 53>;
 				status = "disabled";
 			};
 
-			dfsdm2: filter@2 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <2>;
-				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 103 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers15: timer@44006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44006000 0x400>;
+				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM15_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 105 0x400 0x1>,
+				       <&dmamux1 106 0x400 0x1>,
+				       <&dmamux1 107 0x400 0x1>,
+				       <&dmamux1 108 0x400 0x1>;
+				dma-names = "ch1", "up", "trig", "com";
+				feature-domains = <&etzpc 54>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+
+				timer@14 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <14>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm3: filter@3 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <3>;
-				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 104 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers16: timer@44007000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44007000 0x400>;
+				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM16_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 109 0x400 0x1>,
+				<&dmamux1 110 0x400 0x1>;
+				dma-names = "ch1", "up";
+				feature-domains = <&etzpc 55>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+				timer@15 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <15>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm4: filter@4 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <4>;
-				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 91 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers17: timer@44008000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44008000 0x400>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM17_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 111 0x400 0x1>,
+				<&dmamux1 112 0x400 0x1>;
+				dma-names = "ch1", "up";
+				feature-domains = <&etzpc 56>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+
+				timer@16 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <16>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm5: filter@5 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <5>;
-				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 92 0x400 0x01>;
-				dma-names = "rx";
+			spi5: spi@44009000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44009000 0x400>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI5_K>;
+				resets = <&rcc SPI5_R>;
+				dmas = <&dmamux1 85 0x400 0x05>,
+				<&dmamux1 86 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 57>;
 				status = "disabled";
 			};
-		};
 
-		dma1: dma-controller@48000000 {
-			compatible = "st,stm32-dma";
-			reg = <0x48000000 0x400>;
-			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc DMA1>;
-			resets = <&rcc DMA1_R>;
-			#dma-cells = <4>;
-			st,mem2mem;
-			dma-requests = <8>;
-		};
+			sai1: sai@4400a000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400a000 0x400>;
+				reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI1_R>;
+				feature-domains = <&etzpc 58>;
+				status = "disabled";
+
+				sai1a: audio-controller@4400a004 {
+					#sound-dai-cells = <0>;
+
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					clocks = <&rcc SAI1_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 87 0x400 0x01>;
+					status = "disabled";
+				};
 
-		dma2: dma-controller@48001000 {
-			compatible = "st,stm32-dma";
-			reg = <0x48001000 0x400>;
-			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc DMA2>;
-			resets = <&rcc DMA2_R>;
-			#dma-cells = <4>;
-			st,mem2mem;
-			dma-requests = <8>;
-		};
+				sai1b: audio-controller@4400a024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI1_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 88 0x400 0x01>;
+					status = "disabled";
+				};
+			};
 
-		dmamux1: dma-router@48002000 {
-			compatible = "st,stm32h7-dmamux";
-			reg = <0x48002000 0x40>;
-			#dma-cells = <3>;
-			dma-requests = <128>;
-			dma-masters = <&dma1 &dma2>;
-			dma-channels = <16>;
-			clocks = <&rcc DMAMUX>;
-			resets = <&rcc DMAMUX_R>;
-		};
+			sai2: sai@4400b000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400b000 0x400>;
+				reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI2_R>;
+				feature-domains = <&etzpc 59>;
+				status = "disabled";
+
+				sai2a: audio-controller@4400b004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					clocks = <&rcc SAI2_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 89 0x400 0x01>;
+					status = "disabled";
+				};
 
-		adc: adc@48003000 {
-			compatible = "st,stm32mp1-adc-core";
-			reg = <0x48003000 0x400>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			st,syscfg = <&syscfg>;
-			#interrupt-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
+				sai2b: audio-controller@4400b024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI2_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 90 0x400 0x01>;
+					status = "disabled";
+				};
+			};
 
-			adc1: adc@0 {
-				compatible = "st,stm32mp1-adc";
-				#io-channel-cells = <1>;
-				reg = <0x0>;
-				interrupt-parent = <&adc>;
-				interrupts = <0>;
-				dmas = <&dmamux1 9 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			sai3: sai@4400c000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400c000 0x400>;
+				reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI3_R>;
+				feature-domains = <&etzpc 60>;
+				status = "disabled";
+
+				sai3a: audio-controller@4400c004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x04 0x20>;
+					clocks = <&rcc SAI3_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 113 0x400 0x01>;
+					status = "disabled";
+				};
+
+				sai3b: audio-controller@4400c024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI3_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 114 0x400 0x01>;
+					status = "disabled";
+				};
 			};
 
-			adc2: adc@100 {
-				compatible = "st,stm32mp1-adc";
-				#io-channel-cells = <1>;
-				reg = <0x100>;
-				interrupt-parent = <&adc>;
-				interrupts = <1>;
-				dmas = <&dmamux1 10 0x400 0x01>;
-				dma-names = "rx";
+			dfsdm: dfsdm@4400d000 {
+				compatible = "st,stm32mp1-dfsdm";
+				reg = <0x4400d000 0x800>;
+				clocks = <&rcc DFSDM_K>;
+				clock-names = "dfsdm";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 61>;
 				status = "disabled";
-			};
-		};
 
-		sdmmc3: mmc@48004000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x48004000 0x400>;
-			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC3_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC3_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
+				dfsdm0: filter@0 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <0>;
+					interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 101 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		usbotg_hs: usb-otg@49000000 {
-			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-			reg = <0x49000000 0x10000>;
-			clocks = <&rcc USBO_K>;
-			clock-names = "otg";
-			resets = <&rcc USBO_R>;
-			reset-names = "dwc2";
-			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-			g-rx-fifo-size = <512>;
-			g-np-tx-fifo-size = <32>;
-			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-			dr_mode = "otg";
-			otg-rev = <0x200>;
-			usb33d-supply = <&usb33>;
-			status = "disabled";
-		};
+				dfsdm1: filter@1 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <1>;
+					interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 102 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		ipcc: mailbox@4c001000 {
-			compatible = "st,stm32mp1-ipcc";
-			#mbox-cells = <1>;
-			reg = <0x4c001000 0x400>;
-			st,proc-id = <0>;
-			interrupts-extended =
-				<&exti 61 1>,
-				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "rx", "tx";
-			clocks = <&rcc IPCC>;
-			wakeup-source;
-			status = "disabled";
-		};
-
-		dcmi: dcmi@4c006000 {
-			compatible = "st,stm32-dcmi";
-			reg = <0x4c006000 0x400>;
-			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc CAMITF_R>;
-			clocks = <&rcc DCMI>;
-			clock-names = "mclk";
-			dmas = <&dmamux1 75 0x400 0x01>;
-			dma-names = "tx";
-			status = "disabled";
-		};
+				dfsdm2: filter@2 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <2>;
+					interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 103 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		rcc: rcc@50000000 {
-			compatible = "st,stm32mp1-rcc", "syscon";
-			reg = <0x50000000 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
+				dfsdm3: filter@3 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <3>;
+					interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 104 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		pwr_regulators: pwr@50001000 {
-			compatible = "st,stm32mp1,pwr-reg";
-			reg = <0x50001000 0x10>;
+				dfsdm4: filter@4 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <4>;
+					interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 91 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-			reg11: reg11 {
-				regulator-name = "reg11";
-				regulator-min-microvolt = <1100000>;
-				regulator-max-microvolt = <1100000>;
+				dfsdm5: filter@5 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <5>;
+					interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 92 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 			};
 
-			reg18: reg18 {
-				regulator-name = "reg18";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-			};
+			dma1: dma-controller@48000000 {
+				compatible = "st,stm32-dma";
+				reg = <0x48000000 0x400>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc DMA1>;
+				resets = <&rcc DMA1_R>;
+				#dma-cells = <4>;
+				st,mem2mem;
+				dma-requests = <8>;
+				feature-domains = <&etzpc 88>;
+			};
+
+			dma2: dma-controller@48001000 {
+				compatible = "st,stm32-dma";
+				reg = <0x48001000 0x400>;
+				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc DMA2>;
+				resets = <&rcc DMA2_R>;
+				#dma-cells = <4>;
+				st,mem2mem;
+				dma-requests = <8>;
+				feature-domains = <&etzpc 89>;
+			};
+
+			dmamux1: dma-router@48002000 {
+				compatible = "st,stm32h7-dmamux";
+				reg = <0x48002000 0x40>;
+				#dma-cells = <3>;
+				dma-requests = <128>;
+				dma-masters = <&dma1 &dma2>;
+				dma-channels = <16>;
+				clocks = <&rcc DMAMUX>;
+				resets = <&rcc DMAMUX_R>;
+				feature-domains = <&etzpc 90>;
+			};
+
+			adc: adc@48003000 {
+				compatible = "st,stm32mp1-adc-core";
+				reg = <0x48003000 0x400>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+				clock-names = "bus", "adc";
+				interrupt-controller;
+				st,syscfg = <&syscfg>;
+				#interrupt-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 72>;
+				status = "disabled";
+
+				adc1: adc@0 {
+					compatible = "st,stm32mp1-adc";
+					#io-channel-cells = <1>;
+					reg = <0x0>;
+					interrupt-parent = <&adc>;
+					interrupts = <0>;
+					dmas = <&dmamux1 9 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-			usb33: usb33 {
-				regulator-name = "usb33";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
+				adc2: adc@100 {
+					compatible = "st,stm32mp1-adc";
+					#io-channel-cells = <1>;
+					reg = <0x100>;
+					interrupt-parent = <&adc>;
+					interrupts = <1>;
+					dmas = <&dmamux1 10 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 			};
-		};
 
-		pwr_mcu: pwr_mcu@50001014 {
-			compatible = "st,stm32mp151-pwr-mcu", "syscon";
-			reg = <0x50001014 0x4>;
-		};
+			sdmmc3: mmc@48004000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x00253180>;
+				reg = <0x48004000 0x400>;
+				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC3_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC3_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <120000000>;
+				feature-domains = <&etzpc 86>;
+				status = "disabled";
+			};
+
+			usbotg_hs: usb-otg@49000000 {
+				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+				reg = <0x49000000 0x10000>;
+				clocks = <&rcc USBO_K>;
+				clock-names = "otg";
+				resets = <&rcc USBO_R>;
+				reset-names = "dwc2";
+				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+				g-rx-fifo-size = <512>;
+				g-np-tx-fifo-size = <32>;
+				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+				dr_mode = "otg";
+				otg-rev = <0x200>;
+				usb33d-supply = <&usb33>;
+				feature-domains = <&etzpc 85>;
+				status = "disabled";
+			};
+
+			dcmi: dcmi@4c006000 {
+				compatible = "st,stm32-dcmi";
+				reg = <0x4c006000 0x400>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc CAMITF_R>;
+				clocks = <&rcc DCMI>;
+				clock-names = "mclk";
+				dmas = <&dmamux1 75 0x400 0x01>;
+				dma-names = "tx";
+				feature-domains = <&etzpc 70>;
+				status = "disabled";
+			};
+
+			lptimer2: timer@50021000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x50021000 0x400>;
+				interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM2_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 64>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		exti: interrupt-controller@5000d000 {
-			compatible = "st,stm32mp1-exti", "syscon";
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			reg = <0x5000d000 0x400>;
-		};
+				trigger@1 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <1>;
+					status = "disabled";
+				};
 
-		syscfg: syscon@50020000 {
-			compatible = "st,stm32mp157-syscfg", "syscon";
-			reg = <0x50020000 0x400>;
-			clocks = <&rcc SYSCFG>;
-		};
+				counter {
+					compatible = "st,stm32-lptimer-counter";
+					status = "disabled";
+				};
+			};
 
-		lptimer2: timer@50021000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x50021000 0x400>;
-			interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM2_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
+			lptimer3: timer@50022000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x50022000 0x400>;
+				interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM3_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 65>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
+				trigger@2 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <2>;
+					status = "disabled";
+				};
 			};
 
-			trigger@1 {
-				compatible = "st,stm32-lptimer-trigger";
-				reg = <1>;
+			lptimer4: timer@50023000 {
+				compatible = "st,stm32-lptimer";
+				reg = <0x50023000 0x400>;
+				interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM4_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 66>;
 				status = "disabled";
-			};
 
-			counter {
-				compatible = "st,stm32-lptimer-counter";
-				status = "disabled";
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 			};
-		};
-
-		lptimer3: timer@50022000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x50022000 0x400>;
-			interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM3_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
+			lptimer5: timer@50024000 {
+				compatible = "st,stm32-lptimer";
+				reg = <0x50024000 0x400>;
+				interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM5_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 67>;
 				status = "disabled";
-			};
 
-			trigger@2 {
-				compatible = "st,stm32-lptimer-trigger";
-				reg = <2>;
-				status = "disabled";
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 			};
-		};
 
-		lptimer4: timer@50023000 {
-			compatible = "st,stm32-lptimer";
-			reg = <0x50023000 0x400>;
-			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM4_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
+			vrefbuf: vrefbuf@50025000 {
+				compatible = "st,stm32-vrefbuf";
+				reg = <0x50025000 0x8>;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <2500000>;
+				clocks = <&rcc VREF>;
+				feature-domains = <&etzpc 69>;
 				status = "disabled";
 			};
-		};
 
-		lptimer5: timer@50024000 {
-			compatible = "st,stm32-lptimer";
-			reg = <0x50024000 0x400>;
-			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM5_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
+			sai4: sai@50027000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x50027000 0x400>;
+				reg = <0x50027000 0x4>, <0x500273f0 0x10>;
+				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI4_R>;
+				feature-domains = <&etzpc 68>;
+				status = "disabled";
+
+				sai4a: audio-controller@50027004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x04 0x20>;
+					clocks = <&rcc SAI4_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 99 0x400 0x01>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
+				sai4b: audio-controller@50027024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI4_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 100 0x400 0x01>;
+					status = "disabled";
+				};
 			};
-		};
 
-		vrefbuf: vrefbuf@50025000 {
-			compatible = "st,stm32-vrefbuf";
-			reg = <0x50025000 0x8>;
-			regulator-min-microvolt = <1500000>;
-			regulator-max-microvolt = <2500000>;
-			clocks = <&rcc VREF>;
-			status = "disabled";
-		};
-
-		sai4: sai@50027000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x50027000 0x400>;
-			reg = <0x50027000 0x4>, <0x500273f0 0x10>;
-			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI4_R>;
-			status = "disabled";
+			hash1: hash@54002000 {
+				compatible = "st,stm32f756-hash";
+				reg = <0x54002000 0x400>;
+				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc HASH1>;
+				resets = <&rcc HASH1_R>;
+				dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
+				dma-names = "in";
+				dma-maxburst = <2>;
+				feature-domains = <&etzpc 8>;
+				status = "disabled";
+			};
+
+			rng1: rng@54003000 {
+				compatible = "st,stm32-rng";
+				reg = <0x54003000 0x400>;
+				clocks = <&rcc RNG1_K>;
+				resets = <&rcc RNG1_R>;
+				feature-domains = <&etzpc 7>;
+				status = "disabled";
+			};
+
+			fmc: memory-controller@58002000 {
+				#address-cells = <2>;
+				#size-cells = <1>;
+				compatible = "st,stm32mp1-fmc2-ebi";
+				reg = <0x58002000 0x1000>;
+				clocks = <&rcc FMC_K>;
+				resets = <&rcc FMC_R>;
+				feature-domains = <&etzpc 91>;
+				status = "disabled";
+
+				ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+					 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+					 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+					 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+					 <4 0 0x80000000 0x10000000>; /* NAND */
+
+				nand-controller@4,0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "st,stm32mp1-fmc2-nfc";
+					reg = <4 0x00000000 0x1000>,
+					      <4 0x08010000 0x1000>,
+					      <4 0x08020000 0x1000>,
+					      <4 0x01000000 0x1000>,
+					      <4 0x09010000 0x1000>,
+					      <4 0x09020000 0x1000>;
+					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+					       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+					       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+					dma-names = "tx", "rx", "ecc";
+					status = "disabled";
+				};
+			};
 
-			sai4a: audio-controller@50027004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x04 0x20>;
-				clocks = <&rcc SAI4_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 99 0x400 0x01>;
-				status = "disabled";
+			qspi: spi@58003000 {
+				compatible = "st,stm32f469-qspi";
+				reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+				reg-names = "qspi", "qspi_mm";
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
+				       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
+				dma-names = "tx", "rx";
+				clocks = <&rcc QSPI_K>;
+				resets = <&rcc QSPI_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 92>;
+				status = "disabled";
+			};
+
+			ethernet0: ethernet@5800a000 {
+				compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+				reg = <0x5800a000 0x2000>;
+				reg-names = "stmmaceth";
+				interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "macirq";
+				clock-names = "stmmaceth",
+					      "mac-clk-tx",
+					      "mac-clk-rx",
+					      "eth-ck",
+					      "ptp_ref",
+					      "ethstp";
+				clocks = <&rcc ETHMAC>,
+					 <&rcc ETHTX>,
+					 <&rcc ETHRX>,
+					 <&rcc ETHCK_K>,
+					 <&rcc ETHPTP_K>,
+					 <&rcc ETHSTP>;
+				st,syscon = <&syscfg 0x4>;
+				snps,mixed-burst;
+				snps,pbl = <2>;
+				snps,en-tx-lpi-clockgating;
+				snps,axi-config = <&stmmac_axi_config_0>;
+				snps,tso;
+				feature-domains = <&etzpc 94>;
+				status = "disabled";
+
+				stmmac_axi_config_0: stmmac-axi-config {
+					snps,wr_osr_lmt = <0x7>;
+					snps,rd_osr_lmt = <0x7>;
+					snps,blen = <0 0 0 0 16 8 4>;
+				};
 			};
 
-			sai4b: audio-controller@50027024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI4_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 100 0x400 0x01>;
+			usart1: serial@5c000000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x5c000000 0x400>;
+				interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART1_K>;
+				wakeup-source;
+				feature-domains = <&etzpc 3>;
 				status = "disabled";
 			};
-		};
 
-		dts: thermal@50028000 {
-			compatible = "st,stm32-thermal";
-			reg = <0x50028000 0x100>;
-			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc TMPSENS>;
-			clock-names = "pclk";
-			#thermal-sensor-cells = <0>;
-			status = "disabled";
-		};
-
-		hash1: hash@54002000 {
-			compatible = "st,stm32f756-hash";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc HASH1>;
-			resets = <&rcc HASH1_R>;
-			dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
-			dma-names = "in";
-			dma-maxburst = <2>;
-			status = "disabled";
-		};
-
-		rng1: rng@54003000 {
-			compatible = "st,stm32-rng";
-			reg = <0x54003000 0x400>;
-			clocks = <&rcc RNG1_K>;
-			resets = <&rcc RNG1_R>;
-			status = "disabled";
-		};
-
-		mdma1: dma-controller@58000000 {
-			compatible = "st,stm32h7-mdma";
-			reg = <0x58000000 0x1000>;
-			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc MDMA>;
-			resets = <&rcc MDMA_R>;
-			#dma-cells = <5>;
-			dma-channels = <32>;
-			dma-requests = <48>;
-		};
-
-		fmc: memory-controller@58002000 {
-			#address-cells = <2>;
-			#size-cells = <1>;
-			compatible = "st,stm32mp1-fmc2-ebi";
-			reg = <0x58002000 0x1000>;
-			clocks = <&rcc FMC_K>;
-			resets = <&rcc FMC_R>;
-			status = "disabled";
-
-			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
-				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
-				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
-				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
-				 <4 0 0x80000000 0x10000000>; /* NAND */
-
-			nand-controller@4,0 {
+			spi6: spi@5c001000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "st,stm32mp1-fmc2-nfc";
-				reg = <4 0x00000000 0x1000>,
-				      <4 0x08010000 0x1000>,
-				      <4 0x08020000 0x1000>,
-				      <4 0x01000000 0x1000>,
-				      <4 0x09010000 0x1000>,
-				      <4 0x09020000 0x1000>;
-				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
-				       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
-				       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
-				dma-names = "tx", "rx", "ecc";
+				compatible = "st,stm32h7-spi";
+				reg = <0x5c001000 0x400>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI6_K>;
+				resets = <&rcc SPI6_R>;
+				dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
+				       <&mdma1 35 0x0 0x40002 0x0 0x0>;
+				feature-domains = <&etzpc 4>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			i2c4: i2c@5c002000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x5c002000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C4_K>;
+				resets = <&rcc I2C4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x8>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 5>;
 				status = "disabled";
 			};
-		};
-
-		qspi: spi@58003000 {
-			compatible = "st,stm32f469-qspi";
-			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
-			reg-names = "qspi", "qspi_mm";
-			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
-			       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
-			dma-names = "tx", "rx";
-			clocks = <&rcc QSPI_K>;
-			resets = <&rcc QSPI_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		sdmmc1: mmc@58005000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x58005000 0x1000>;
-			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC1_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC1_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
-
-		sdmmc2: mmc@58007000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x58007000 0x1000>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC2_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC2_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
-
-		crc1: crc@58009000 {
-			compatible = "st,stm32f7-crc";
-			reg = <0x58009000 0x400>;
-			clocks = <&rcc CRC1>;
-			status = "disabled";
-		};
-
-		ethernet0: ethernet@5800a000 {
-			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
-			reg = <0x5800a000 0x2000>;
-			reg-names = "stmmaceth";
-			interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
-			clock-names = "stmmaceth",
-				      "mac-clk-tx",
-				      "mac-clk-rx",
-				      "eth-ck",
-				      "ptp_ref",
-				      "ethstp";
-			clocks = <&rcc ETHMAC>,
-				 <&rcc ETHTX>,
-				 <&rcc ETHRX>,
-				 <&rcc ETHCK_K>,
-				 <&rcc ETHPTP_K>,
-				 <&rcc ETHSTP>;
-			st,syscon = <&syscfg 0x4>;
-			snps,mixed-burst;
-			snps,pbl = <2>;
-			snps,en-tx-lpi-clockgating;
-			snps,axi-config = <&stmmac_axi_config_0>;
-			snps,tso;
-			status = "disabled";
-
-			stmmac_axi_config_0: stmmac-axi-config {
-				snps,wr_osr_lmt = <0x7>;
-				snps,rd_osr_lmt = <0x7>;
-				snps,blen = <0 0 0 0 16 8 4>;
-			};
-		};
 
-		usbh_ohci: usb@5800c000 {
-			compatible = "generic-ohci";
-			reg = <0x5800c000 0x1000>;
-			clocks = <&usbphyc>, <&rcc USBH>;
-			resets = <&rcc USBH_R>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		usbh_ehci: usb@5800d000 {
-			compatible = "generic-ehci";
-			reg = <0x5800d000 0x1000>;
-			clocks = <&usbphyc>, <&rcc USBH>;
-			resets = <&rcc USBH_R>;
-			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			companion = <&usbh_ohci>;
-			status = "disabled";
-		};
-
-		ltdc: display-controller@5a001000 {
-			compatible = "st,stm32-ltdc";
-			reg = <0x5a001000 0x400>;
-			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LTDC_PX>;
-			clock-names = "lcd";
-			resets = <&rcc LTDC_R>;
-			status = "disabled";
-
-			port {
+			i2c6: i2c@5c009000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x5c009000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C6_K>;
+				resets = <&rcc I2C6_R>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x20>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 12>;
+				status = "disabled";
 			};
-		};
-
-		iwdg2: watchdog@5a002000 {
-			compatible = "st,stm32mp1-iwdg";
-			reg = <0x5a002000 0x400>;
-			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
-			clock-names = "pclk", "lsi";
-			status = "disabled";
-		};
-
-		usbphyc: usbphyc@5a006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#clock-cells = <0>;
-			compatible = "st,stm32mp1-usbphyc";
-			reg = <0x5a006000 0x1000>;
-			clocks = <&rcc USBPHY_K>;
-			resets = <&rcc USBPHY_R>;
-			vdda1v1-supply = <&reg11>;
-			vdda1v8-supply = <&reg18>;
-			status = "disabled";
-
-			usbphyc_port0: usb-phy@0 {
-				#phy-cells = <0>;
-				reg = <0>;
-			};
-
-			usbphyc_port1: usb-phy@1 {
-				#phy-cells = <1>;
-				reg = <1>;
-			};
-		};
-
-		usart1: serial@5c000000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x5c000000 0x400>;
-			interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART1_K>;
-			wakeup-source;
-			status = "disabled";
-		};
-
-		spi6: spi@5c001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x5c001000 0x400>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI6_K>;
-			resets = <&rcc SPI6_R>;
-			dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
-			       <&mdma1 35 0x0 0x40002 0x0 0x0>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2c4: i2c@5c002000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x5c002000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C4_K>;
-			resets = <&rcc I2C4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x8>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		rtc: rtc@5c004000 {
-			compatible = "st,stm32mp1-rtc";
-			reg = <0x5c004000 0x400>;
-			clocks = <&rcc RTCAPB>, <&rcc RTC>;
-			clock-names = "pclk", "rtc_ck";
-			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		bsec: efuse@5c005000 {
-			compatible = "st,stm32mp15-bsec";
-			reg = <0x5c005000 0x400>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ts_cal1: calib@5c {
-				reg = <0x5c 0x2>;
-			};
-			ts_cal2: calib@5e {
-				reg = <0x5e 0x2>;
-			};
-		};
 
-		i2c6: i2c@5c009000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x5c009000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C6_K>;
-			resets = <&rcc I2C6_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x20>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
 		};
 
 		tamp: tamp@5c00a000 {
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi
index 486084e0b80b..82073dd85f18 100644
--- a/arch/arm/boot/dts/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/stm32mp153.dtsi
@@ -28,32 +28,34 @@ timer {
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+};
 
-	soc {
-		m_can1: can@4400e000 {
-			compatible = "bosch,m_can";
-			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
-			reg-names = "m_can", "message_ram";
-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "int0", "int1";
-			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-			clock-names = "hclk", "cclk";
-			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
-			status = "disabled";
-		};
+&etzpc {
+	m_can1: can@4400e000 {
+		compatible = "bosch,m_can";
+		reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+		reg-names = "m_can", "message_ram";
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "int0", "int1";
+		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+		clock-names = "hclk", "cclk";
+		bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+		feature-domains = <&etzpc 62>;
+		status = "disabled";
+	};
 
-		m_can2: can@4400f000 {
-			compatible = "bosch,m_can";
-			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
-			reg-names = "m_can", "message_ram";
-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "int0", "int1";
-			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-			clock-names = "hclk", "cclk";
-			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
-			status = "disabled";
-		};
+	m_can2: can@4400f000 {
+		compatible = "bosch,m_can";
+		reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+		reg-names = "m_can", "message_ram";
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "int0", "int1";
+		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+		clock-names = "hclk", "cclk";
+		bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+		feature-domains = <&etzpc 62>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi
index b06a55a2fa18..55524a8d3093 100644
--- a/arch/arm/boot/dts/stm32mp15xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xc.dtsi
@@ -4,15 +4,14 @@
  * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp1: cryp@54001000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54001000 0x400>;
-			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp1: cryp@54001000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54001000 0x400>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		feature-domains = <&etzpc 9>;
+		status = "disabled";
 	};
 };
-- 
2.35.3


-- 
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 5/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

The STM32 System Bus is an internal bus on which devices are connected.
ETZPC is a peripheral overseeing the firewall bus that configures
and control access to the peripherals connected on it.

For more information on which peripheral is securable, please read
the STM32MP15 reference manual.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

No changes in V2.

Changes in V3:
	-Use appriopriate node name: bus

 arch/arm/boot/dts/stm32mp151.dtsi  | 2722 ++++++++++++++--------------
 arch/arm/boot/dts/stm32mp153.dtsi  |   52 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi |   19 +-
 3 files changed, 1434 insertions(+), 1359 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index 5491b6c4dec2..5dab96e7c2ba 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -122,1526 +122,1600 @@ soc {
 		interrupt-parent = <&intc>;
 		ranges;
 
-		timers2: timer@40000000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40000000 0x400>;
-			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM2_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 18 0x400 0x1>,
-			       <&dmamux1 19 0x400 0x1>,
-			       <&dmamux1 20 0x400 0x1>,
-			       <&dmamux1 21 0x400 0x1>,
-			       <&dmamux1 22 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+		ipcc: mailbox@4c001000 {
+			compatible = "st,stm32mp1-ipcc";
+			#mbox-cells = <1>;
+			reg = <0x4c001000 0x400>;
+			st,proc-id = <0>;
+			interrupts-extended =
+				<&exti 61 1>,
+				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "rx", "tx";
+			clocks = <&rcc IPCC>;
+			wakeup-source;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@1 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <1>;
-				status = "disabled";
-			};
-
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		rcc: rcc@50000000 {
+			compatible = "st,stm32mp1-rcc", "syscon";
+			reg = <0x50000000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
-		timers3: timer@40001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40001000 0x400>;
-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM3_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 23 0x400 0x1>,
-			       <&dmamux1 24 0x400 0x1>,
-			       <&dmamux1 25 0x400 0x1>,
-			       <&dmamux1 26 0x400 0x1>,
-			       <&dmamux1 27 0x400 0x1>,
-			       <&dmamux1 28 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
-			status = "disabled";
+		pwr_regulators: pwr@50001000 {
+			compatible = "st,stm32mp1,pwr-reg";
+			reg = <0x50001000 0x10>;
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+			reg11: reg11 {
+				regulator-name = "reg11";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
 			};
 
-			timer@2 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <2>;
-				status = "disabled";
+			reg18: reg18 {
+				regulator-name = "reg18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
 			};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
+			usb33: usb33 {
+				regulator-name = "usb33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
 			};
 		};
 
-		timers4: timer@40002000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40002000 0x400>;
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM4_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 29 0x400 0x1>,
-			       <&dmamux1 30 0x400 0x1>,
-			       <&dmamux1 31 0x400 0x1>,
-			       <&dmamux1 32 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4";
-			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
+		pwr_mcu: pwr_mcu@50001014 {
+			compatible = "st,stm32mp151-pwr-mcu", "syscon";
+			reg = <0x50001014 0x4>;
+		};
 
-			timer@3 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <3>;
-				status = "disabled";
-			};
+		exti: interrupt-controller@5000d000 {
+			compatible = "st,stm32mp1-exti", "syscon";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x5000d000 0x400>;
+		};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		syscfg: syscon@50020000 {
+			compatible = "st,stm32mp157-syscfg", "syscon";
+			reg = <0x50020000 0x400>;
+			clocks = <&rcc SYSCFG>;
 		};
 
-		timers5: timer@40003000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40003000 0x400>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM5_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 55 0x400 0x1>,
-			       <&dmamux1 56 0x400 0x1>,
-			       <&dmamux1 57 0x400 0x1>,
-			       <&dmamux1 58 0x400 0x1>,
-			       <&dmamux1 59 0x400 0x1>,
-			       <&dmamux1 60 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+		dts: thermal@50028000 {
+			compatible = "st,stm32-thermal";
+			reg = <0x50028000 0x100>;
+			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc TMPSENS>;
+			clock-names = "pclk";
+			#thermal-sensor-cells = <0>;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@4 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <4>;
-				status = "disabled";
-			};
-
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		mdma1: dma-controller@58000000 {
+			compatible = "st,stm32h7-mdma";
+			reg = <0x58000000 0x1000>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc MDMA>;
+			resets = <&rcc MDMA_R>;
+			#dma-cells = <5>;
+			dma-channels = <32>;
+			dma-requests = <48>;
 		};
 
-		timers6: timer@40004000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40004000 0x400>;
-			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM6_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 69 0x400 0x1>;
-			dma-names = "up";
+		sdmmc1: mmc@58005000 {
+			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+			arm,primecell-periphid = <0x00253180>;
+			reg = <0x58005000 0x1000>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SDMMC1_K>;
+			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC1_R>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
 			status = "disabled";
-
-			timer@5 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <5>;
-				status = "disabled";
-			};
 		};
 
-		timers7: timer@40005000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40005000 0x400>;
-			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM7_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 70 0x400 0x1>;
-			dma-names = "up";
+		sdmmc2: mmc@58007000 {
+			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+			arm,primecell-periphid = <0x00253180>;
+			reg = <0x58007000 0x1000>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SDMMC2_K>;
+			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC2_R>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
 			status = "disabled";
-
-			timer@6 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <6>;
-				status = "disabled";
-			};
 		};
 
-		timers12: timer@40006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40006000 0x400>;
-			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM12_K>;
-			clock-names = "int";
+		crc1: crc@58009000 {
+			compatible = "st,stm32f7-crc";
+			reg = <0x58009000 0x400>;
+			clocks = <&rcc CRC1>;
 			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@11 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <11>;
-				status = "disabled";
-			};
 		};
 
-		timers13: timer@40007000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40007000 0x400>;
-			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM13_K>;
-			clock-names = "int";
+		usbh_ohci: usb@5800c000 {
+			compatible = "generic-ohci";
+			reg = <0x5800c000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@12 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <12>;
-				status = "disabled";
-			};
+		usbh_ehci: usb@5800d000 {
+			compatible = "generic-ehci";
+			reg = <0x5800d000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			companion = <&usbh_ohci>;
+			status = "disabled";
 		};
 
-		timers14: timer@40008000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40008000 0x400>;
-			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM14_K>;
-			clock-names = "int";
+		ltdc: display-controller@5a001000 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x5a001000 0x400>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LTDC_PX>;
+			clock-names = "lcd";
+			resets = <&rcc LTDC_R>;
 			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
 			};
+		};
 
-			timer@13 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <13>;
-				status = "disabled";
-			};
+		iwdg2: watchdog@5a002000 {
+			compatible = "st,stm32mp1-iwdg";
+			reg = <0x5a002000 0x400>;
+			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
+			clock-names = "pclk", "lsi";
+			status = "disabled";
 		};
 
-		lptimer1: timer@40009000 {
+		usbphyc: usbphyc@5a006000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x40009000 0x400>;
-			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM1_K>;
-			clock-names = "mux";
-			wakeup-source;
+			#clock-cells = <0>;
+			compatible = "st,stm32mp1-usbphyc";
+			reg = <0x5a006000 0x1000>;
+			clocks = <&rcc USBPHY_K>;
+			resets = <&rcc USBPHY_R>;
+			vdda1v1-supply = <&reg11>;
+			vdda1v8-supply = <&reg18>;
 			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			trigger@0 {
-				compatible = "st,stm32-lptimer-trigger";
+			usbphyc_port0: usb-phy@0 {
+				#phy-cells = <0>;
 				reg = <0>;
-				status = "disabled";
 			};
 
-			counter {
-				compatible = "st,stm32-lptimer-counter";
-				status = "disabled";
+			usbphyc_port1: usb-phy@1 {
+				#phy-cells = <1>;
+				reg = <1>;
 			};
 		};
 
-		spi2: spi@4000b000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x4000b000 0x400>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI2_K>;
-			resets = <&rcc SPI2_R>;
-			dmas = <&dmamux1 39 0x400 0x05>,
-			       <&dmamux1 40 0x400 0x05>;
-			dma-names = "rx", "tx";
+		rtc: rtc@5c004000 {
+			compatible = "st,stm32mp1-rtc";
+			reg = <0x5c004000 0x400>;
+			clocks = <&rcc RTCAPB>, <&rcc RTC>;
+			clock-names = "pclk", "rtc_ck";
+			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
-		i2s2: audio-controller@4000b000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x4000b000 0x400>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 39 0x400 0x01>,
-			       <&dmamux1 40 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
+		bsec: efuse@5c005000 {
+			compatible = "st,stm32mp15-bsec";
+			reg = <0x5c005000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ts_cal1: calib@5c {
+				reg = <0x5c 0x2>;
+			};
+			ts_cal2: calib@5e {
+				reg = <0x5e 0x2>;
+			};
 		};
 
-		spi3: spi@4000c000 {
+		etzpc: bus@5c007000 {
+			compatible = "st,stm32mp15-sys-bus";
+			reg = <0x5c007000 0x400>;
 			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x4000c000 0x400>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI3_K>;
-			resets = <&rcc SPI3_R>;
-			dmas = <&dmamux1 61 0x400 0x05>,
-			       <&dmamux1 62 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			#size-cells = <1>;
+			feature-domain-controller;
+			#feature-domain-cells = <1>;
+			ranges;
 
-		i2s3: audio-controller@4000c000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x4000c000 0x400>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 61 0x400 0x01>,
-			       <&dmamux1 62 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers2: timer@40000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40000000 0x400>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM2_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 18 0x400 0x1>,
+				       <&dmamux1 19 0x400 0x1>,
+				       <&dmamux1 20 0x400 0x1>,
+				       <&dmamux1 21 0x400 0x1>,
+				       <&dmamux1 22 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+				feature-domains = <&etzpc 16>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		spdifrx: audio-controller@4000d000 {
-			compatible = "st,stm32h7-spdifrx";
-			#sound-dai-cells = <0>;
-			reg = <0x4000d000 0x400>;
-			clocks = <&rcc SPDIF_K>;
-			clock-names = "kclk";
-			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 93 0x400 0x01>,
-			       <&dmamux1 94 0x400 0x01>;
-			dma-names = "rx", "rx-ctrl";
-			status = "disabled";
-		};
+				timer@1 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <1>;
+					status = "disabled";
+				};
 
-		usart2: serial@4000e000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x4000e000 0x400>;
-			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART2_K>;
-			wakeup-source;
-			dmas = <&dmamux1 43 0x400 0x15>,
-			       <&dmamux1 44 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		usart3: serial@4000f000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x4000f000 0x400>;
-			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART3_K>;
-			wakeup-source;
-			dmas = <&dmamux1 45 0x400 0x15>,
-			       <&dmamux1 46 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers3: timer@40001000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40001000 0x400>;
+				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM3_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 23 0x400 0x1>,
+				       <&dmamux1 24 0x400 0x1>,
+				       <&dmamux1 25 0x400 0x1>,
+				       <&dmamux1 26 0x400 0x1>,
+				       <&dmamux1 27 0x400 0x1>,
+				       <&dmamux1 28 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+				feature-domains = <&etzpc 17>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		uart4: serial@40010000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40010000 0x400>;
-			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART4_K>;
-			wakeup-source;
-			dmas = <&dmamux1 63 0x400 0x15>,
-			       <&dmamux1 64 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				timer@2 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <2>;
+					status = "disabled";
+				};
 
-		uart5: serial@40011000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40011000 0x400>;
-			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART5_K>;
-			wakeup-source;
-			dmas = <&dmamux1 65 0x400 0x15>,
-			       <&dmamux1 66 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		i2c1: i2c@40012000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40012000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C1_K>;
-			resets = <&rcc I2C1_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x1>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+			timers4: timer@40002000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40002000 0x400>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM4_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 29 0x400 0x1>,
+				       <&dmamux1 30 0x400 0x1>,
+				       <&dmamux1 31 0x400 0x1>,
+				       <&dmamux1 32 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4";
+				feature-domains = <&etzpc 18>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		i2c2: i2c@40013000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40013000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C2_K>;
-			resets = <&rcc I2C2_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x2>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+				timer@3 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <3>;
+					status = "disabled";
+				};
 
-		i2c3: i2c@40014000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40014000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C3_K>;
-			resets = <&rcc I2C3_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x4>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		i2c5: i2c@40015000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40015000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C5_K>;
-			resets = <&rcc I2C5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x10>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+			timers5: timer@40003000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40003000 0x400>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM5_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 55 0x400 0x1>,
+				       <&dmamux1 56 0x400 0x1>,
+				       <&dmamux1 57 0x400 0x1>,
+				       <&dmamux1 58 0x400 0x1>,
+				       <&dmamux1 59 0x400 0x1>,
+				       <&dmamux1 60 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+				feature-domains = <&etzpc 19>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		cec: cec@40016000 {
-			compatible = "st,stm32-cec";
-			reg = <0x40016000 0x400>;
-			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CEC_K>, <&rcc CEC>;
-			clock-names = "cec", "hdmi-cec";
-			status = "disabled";
-		};
+				timer@4 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <4>;
+					status = "disabled";
+				};
 
-		dac: dac@40017000 {
-			compatible = "st,stm32h7-dac-core";
-			reg = <0x40017000 0x400>;
-			clocks = <&rcc DAC12>;
-			clock-names = "pclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-			dac1: dac@1 {
-				compatible = "st,stm32-dac";
-				#io-channel-cells = <1>;
-				reg = <1>;
-				status = "disabled";
+			timers6: timer@40004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40004000 0x400>;
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM6_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 69 0x400 0x1>;
+				dma-names = "up";
+				feature-domains = <&etzpc 20>;
+				status = "disabled";
+
+				timer@5 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <5>;
+					status = "disabled";
+				};
 			};
 
-			dac2: dac@2 {
-				compatible = "st,stm32-dac";
-				#io-channel-cells = <1>;
-				reg = <2>;
-				status = "disabled";
+			timers7: timer@40005000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40005000 0x400>;
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM7_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 70 0x400 0x1>;
+				dma-names = "up";
+				feature-domains = <&etzpc 21>;
+				status = "disabled";
+
+				timer@6 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <6>;
+					status = "disabled";
+				};
 			};
-		};
 
-		uart7: serial@40018000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40018000 0x400>;
-			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART7_K>;
-			wakeup-source;
-			dmas = <&dmamux1 79 0x400 0x15>,
-			       <&dmamux1 80 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers12: timer@40006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40006000 0x400>;
+				interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM12_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 22>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		uart8: serial@40019000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40019000 0x400>;
-			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART8_K>;
-			wakeup-source;
-			dmas = <&dmamux1 81 0x400 0x15>,
-			       <&dmamux1 82 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				timer@11 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <11>;
+					status = "disabled";
+				};
+			};
 
-		timers1: timer@44000000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44000000 0x400>;
-			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "brk", "up", "trg-com", "cc";
-			clocks = <&rcc TIM1_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 11 0x400 0x1>,
-			       <&dmamux1 12 0x400 0x1>,
-			       <&dmamux1 13 0x400 0x1>,
-			       <&dmamux1 14 0x400 0x1>,
-			       <&dmamux1 15 0x400 0x1>,
-			       <&dmamux1 16 0x400 0x1>,
-			       <&dmamux1 17 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4",
-				    "up", "trig", "com";
-			status = "disabled";
+			timers13: timer@40007000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40007000 0x400>;
+				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM13_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 23>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+				timer@12 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <12>;
+					status = "disabled";
+				};
 			};
 
-			timer@0 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <0>;
-				status = "disabled";
-			};
+			timers14: timer@40008000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40008000 0x400>;
+				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM14_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 24>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
+				timer@13 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <13>;
+					status = "disabled";
+				};
 			};
-		};
 
-		timers8: timer@44001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44001000 0x400>;
-			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "brk", "up", "trg-com", "cc";
-			clocks = <&rcc TIM8_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 47 0x400 0x1>,
-			       <&dmamux1 48 0x400 0x1>,
-			       <&dmamux1 49 0x400 0x1>,
-			       <&dmamux1 50 0x400 0x1>,
-			       <&dmamux1 51 0x400 0x1>,
-			       <&dmamux1 52 0x400 0x1>,
-			       <&dmamux1 53 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4",
-				    "up", "trig", "com";
-			status = "disabled";
+			lptimer1: timer@40009000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x40009000 0x400>;
+				interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM1_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 25>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+				trigger@0 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <0>;
+					status = "disabled";
+				};
+
+				counter {
+					compatible = "st,stm32-lptimer-counter";
+					status = "disabled";
+				};
 			};
 
-			timer@7 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <7>;
+			i2s2: audio-controller@4000b000 {
+				compatible = "st,stm32h7-i2s";
+				#sound-dai-cells = <0>;
+				reg = <0x4000b000 0x400>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 39 0x400 0x01>,
+				       <&dmamux1 40 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 27>;
 				status = "disabled";
 			};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
+			spi2: spi@4000b000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x4000b000 0x400>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI2_K>;
+				resets = <&rcc SPI2_R>;
+				dmas = <&dmamux1 39 0x400 0x05>,
+				       <&dmamux1 40 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 27>;
 				status = "disabled";
 			};
-		};
-
-		usart6: serial@44003000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x44003000 0x400>;
-			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART6_K>;
-			wakeup-source;
-			dmas = <&dmamux1 71 0x400 0x15>,
-			       <&dmamux1 72 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi1: spi@44004000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44004000 0x400>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI1_K>;
-			resets = <&rcc SPI1_R>;
-			dmas = <&dmamux1 37 0x400 0x05>,
-			       <&dmamux1 38 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2s1: audio-controller@44004000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x44004000 0x400>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 37 0x400 0x01>,
-			       <&dmamux1 38 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi4: spi@44005000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44005000 0x400>;
-			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI4_K>;
-			resets = <&rcc SPI4_R>;
-			dmas = <&dmamux1 83 0x400 0x05>,
-			       <&dmamux1 84 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		timers15: timer@44006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44006000 0x400>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM15_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 105 0x400 0x1>,
-			       <&dmamux1 106 0x400 0x1>,
-			       <&dmamux1 107 0x400 0x1>,
-			       <&dmamux1 108 0x400 0x1>;
-			dma-names = "ch1", "up", "trig", "com";
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			i2s3: audio-controller@4000c000 {
+				compatible = "st,stm32h7-i2s";
+				#sound-dai-cells = <0>;
+				reg = <0x4000c000 0x400>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 61 0x400 0x01>,
+				       <&dmamux1 62 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 28>;
 				status = "disabled";
 			};
 
-			timer@14 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <14>;
+			spi3: spi@4000c000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x4000c000 0x400>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI3_K>;
+				resets = <&rcc SPI3_R>;
+				dmas = <&dmamux1 61 0x400 0x05>,
+				       <&dmamux1 62 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 28>;
 				status = "disabled";
 			};
-		};
-
-		timers16: timer@44007000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44007000 0x400>;
-			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM16_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 109 0x400 0x1>,
-			       <&dmamux1 110 0x400 0x1>;
-			dma-names = "ch1", "up";
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			spdifrx: audio-controller@4000d000 {
+				compatible = "st,stm32h7-spdifrx";
+				#sound-dai-cells = <0>;
+				reg = <0x4000d000 0x400>;
+				clocks = <&rcc SPDIF_K>;
+				clock-names = "kclk";
+				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 93 0x400 0x01>,
+				       <&dmamux1 94 0x400 0x01>;
+				dma-names = "rx", "rx-ctrl";
+				feature-domains = <&etzpc 29>;
+				status = "disabled";
+			};
+
+			usart2: serial@4000e000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x4000e000 0x400>;
+				interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART2_K>;
+				wakeup-source;
+				dmas = <&dmamux1 43 0x400 0x15>,
+				       <&dmamux1 44 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 30>;
+				status = "disabled";
+			};
+
+			usart3: serial@4000f000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x4000f000 0x400>;
+				interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART3_K>;
+				wakeup-source;
+				dmas = <&dmamux1 45 0x400 0x15>,
+				       <&dmamux1 46 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 31>;
+				status = "disabled";
+			};
+
+			uart4: serial@40010000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40010000 0x400>;
+				interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART4_K>;
+				wakeup-source;
+				dmas = <&dmamux1 63 0x400 0x15>,
+				       <&dmamux1 64 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 32>;
+				status = "disabled";
+			};
+
+			uart5: serial@40011000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40011000 0x400>;
+				interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART5_K>;
+				wakeup-source;
+				dmas = <&dmamux1 65 0x400 0x15>,
+				       <&dmamux1 66 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 33>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@40012000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40012000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C1_K>;
+				resets = <&rcc I2C1_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x1>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 34>;
 				status = "disabled";
 			};
-			timer@15 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <15>;
+
+			i2c2: i2c@40013000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40013000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C2_K>;
+				resets = <&rcc I2C2_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x2>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 35>;
 				status = "disabled";
 			};
-		};
 
-		timers17: timer@44008000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44008000 0x400>;
-			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM17_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 111 0x400 0x1>,
-			       <&dmamux1 112 0x400 0x1>;
-			dma-names = "ch1", "up";
-			status = "disabled";
+			i2c3: i2c@40014000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40014000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C3_K>;
+				resets = <&rcc I2C3_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x4>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 36>;
+				status = "disabled";
+			};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			i2c5: i2c@40015000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40015000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C5_K>;
+				resets = <&rcc I2C5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x10>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 37>;
 				status = "disabled";
 			};
 
-			timer@16 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <16>;
+			cec: cec@40016000 {
+				compatible = "st,stm32-cec";
+				reg = <0x40016000 0x400>;
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CEC_K>, <&rcc CEC>;
+				clock-names = "cec", "hdmi-cec";
+				feature-domains = <&etzpc 38>;
 				status = "disabled";
 			};
-		};
 
-		spi5: spi@44009000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44009000 0x400>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI5_K>;
-			resets = <&rcc SPI5_R>;
-			dmas = <&dmamux1 85 0x400 0x05>,
-			       <&dmamux1 86 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			dac: dac@40017000 {
+				compatible = "st,stm32h7-dac-core";
+				reg = <0x40017000 0x400>;
+				clocks = <&rcc DAC12>;
+				clock-names = "pclk";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 39>;
+				status = "disabled";
 
-		sai1: sai@4400a000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400a000 0x400>;
-			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
-			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI1_R>;
-			status = "disabled";
+				dac1: dac@1 {
+					compatible = "st,stm32-dac";
+					#io-channel-cells = <1>;
+					reg = <1>;
+					status = "disabled";
+				};
 
-			sai1a: audio-controller@4400a004 {
-				#sound-dai-cells = <0>;
+				dac2: dac@2 {
+					compatible = "st,stm32-dac";
+					#io-channel-cells = <1>;
+					reg = <2>;
+					status = "disabled";
+				};
+			};
 
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x4 0x20>;
-				clocks = <&rcc SAI1_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 87 0x400 0x01>;
+			uart7: serial@40018000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40018000 0x400>;
+				interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART7_K>;
+				wakeup-source;
+				dmas = <&dmamux1 79 0x400 0x15>,
+				       <&dmamux1 80 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 40>;
 				status = "disabled";
 			};
 
-			sai1b: audio-controller@4400a024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI1_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 88 0x400 0x01>;
+			uart8: serial@40019000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40019000 0x400>;
+				interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART8_K>;
+				wakeup-source;
+				dmas = <&dmamux1 81 0x400 0x15>,
+				       <&dmamux1 82 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 41>;
 				status = "disabled";
 			};
-		};
 
-		sai2: sai@4400b000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400b000 0x400>;
-			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
-			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI2_R>;
-			status = "disabled";
+			timers1: timer@44000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44000000 0x400>;
+				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "brk", "up", "trg-com", "cc";
+				clocks = <&rcc TIM1_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 11 0x400 0x1>,
+				       <&dmamux1 12 0x400 0x1>,
+				       <&dmamux1 13 0x400 0x1>,
+				       <&dmamux1 14 0x400 0x1>,
+				       <&dmamux1 15 0x400 0x1>,
+				       <&dmamux1 16 0x400 0x1>,
+				       <&dmamux1 17 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4",
+					    "up", "trig", "com";
+				feature-domains = <&etzpc 48>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			sai2a: audio-controller@4400b004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x4 0x20>;
-				clocks = <&rcc SAI2_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 89 0x400 0x01>;
-				status = "disabled";
-			};
+				timer@0 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <0>;
+					status = "disabled";
+				};
 
-			sai2b: audio-controller@4400b024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI2_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 90 0x400 0x01>;
-				status = "disabled";
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
 			};
-		};
 
-		sai3: sai@4400c000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400c000 0x400>;
-			reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
-			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI3_R>;
-			status = "disabled";
+			timers8: timer@44001000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44001000 0x400>;
+				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "brk", "up", "trg-com", "cc";
+				clocks = <&rcc TIM8_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 47 0x400 0x1>,
+				       <&dmamux1 48 0x400 0x1>,
+				       <&dmamux1 49 0x400 0x1>,
+				       <&dmamux1 50 0x400 0x1>,
+				       <&dmamux1 51 0x400 0x1>,
+				       <&dmamux1 52 0x400 0x1>,
+				       <&dmamux1 53 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4",
+					    "up", "trig", "com";
+				feature-domains = <&etzpc 49>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			sai3a: audio-controller@4400c004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x04 0x20>;
-				clocks = <&rcc SAI3_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 113 0x400 0x01>;
+				timer@7 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <7>;
+					status = "disabled";
+				};
+
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
+
+			usart6: serial@44003000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x44003000 0x400>;
+				interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART6_K>;
+				wakeup-source;
+				dmas = <&dmamux1 71 0x400 0x15>,
+				<&dmamux1 72 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 51>;
 				status = "disabled";
 			};
 
-			sai3b: audio-controller@4400c024 {
+			i2s1: audio-controller@44004000 {
+				compatible = "st,stm32h7-i2s";
 				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI3_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 114 0x400 0x01>;
+				reg = <0x44004000 0x400>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 37 0x400 0x01>,
+				<&dmamux1 38 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 52>;
 				status = "disabled";
 			};
-		};
-
-		dfsdm: dfsdm@4400d000 {
-			compatible = "st,stm32mp1-dfsdm";
-			reg = <0x4400d000 0x800>;
-			clocks = <&rcc DFSDM_K>;
-			clock-names = "dfsdm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
 
-			dfsdm0: filter@0 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <0>;
-				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 101 0x400 0x01>;
-				dma-names = "rx";
+			spi1: spi@44004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44004000 0x400>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI1_K>;
+				resets = <&rcc SPI1_R>;
+				dmas = <&dmamux1 37 0x400 0x05>,
+				<&dmamux1 38 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 52>;
 				status = "disabled";
 			};
 
-			dfsdm1: filter@1 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <1>;
-				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 102 0x400 0x01>;
-				dma-names = "rx";
+			spi4: spi@44005000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44005000 0x400>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI4_K>;
+				resets = <&rcc SPI4_R>;
+				dmas = <&dmamux1 83 0x400 0x05>,
+				<&dmamux1 84 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 53>;
 				status = "disabled";
 			};
 
-			dfsdm2: filter@2 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <2>;
-				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 103 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers15: timer@44006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44006000 0x400>;
+				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM15_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 105 0x400 0x1>,
+				       <&dmamux1 106 0x400 0x1>,
+				       <&dmamux1 107 0x400 0x1>,
+				       <&dmamux1 108 0x400 0x1>;
+				dma-names = "ch1", "up", "trig", "com";
+				feature-domains = <&etzpc 54>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+
+				timer@14 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <14>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm3: filter@3 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <3>;
-				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 104 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers16: timer@44007000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44007000 0x400>;
+				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM16_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 109 0x400 0x1>,
+				<&dmamux1 110 0x400 0x1>;
+				dma-names = "ch1", "up";
+				feature-domains = <&etzpc 55>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+				timer@15 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <15>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm4: filter@4 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <4>;
-				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 91 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers17: timer@44008000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44008000 0x400>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM17_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 111 0x400 0x1>,
+				<&dmamux1 112 0x400 0x1>;
+				dma-names = "ch1", "up";
+				feature-domains = <&etzpc 56>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+
+				timer@16 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <16>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm5: filter@5 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <5>;
-				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 92 0x400 0x01>;
-				dma-names = "rx";
+			spi5: spi@44009000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44009000 0x400>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI5_K>;
+				resets = <&rcc SPI5_R>;
+				dmas = <&dmamux1 85 0x400 0x05>,
+				<&dmamux1 86 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 57>;
 				status = "disabled";
 			};
-		};
 
-		dma1: dma-controller@48000000 {
-			compatible = "st,stm32-dma";
-			reg = <0x48000000 0x400>;
-			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc DMA1>;
-			resets = <&rcc DMA1_R>;
-			#dma-cells = <4>;
-			st,mem2mem;
-			dma-requests = <8>;
-		};
+			sai1: sai@4400a000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400a000 0x400>;
+				reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI1_R>;
+				feature-domains = <&etzpc 58>;
+				status = "disabled";
+
+				sai1a: audio-controller@4400a004 {
+					#sound-dai-cells = <0>;
+
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					clocks = <&rcc SAI1_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 87 0x400 0x01>;
+					status = "disabled";
+				};
 
-		dma2: dma-controller@48001000 {
-			compatible = "st,stm32-dma";
-			reg = <0x48001000 0x400>;
-			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc DMA2>;
-			resets = <&rcc DMA2_R>;
-			#dma-cells = <4>;
-			st,mem2mem;
-			dma-requests = <8>;
-		};
+				sai1b: audio-controller@4400a024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI1_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 88 0x400 0x01>;
+					status = "disabled";
+				};
+			};
 
-		dmamux1: dma-router@48002000 {
-			compatible = "st,stm32h7-dmamux";
-			reg = <0x48002000 0x40>;
-			#dma-cells = <3>;
-			dma-requests = <128>;
-			dma-masters = <&dma1 &dma2>;
-			dma-channels = <16>;
-			clocks = <&rcc DMAMUX>;
-			resets = <&rcc DMAMUX_R>;
-		};
+			sai2: sai@4400b000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400b000 0x400>;
+				reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI2_R>;
+				feature-domains = <&etzpc 59>;
+				status = "disabled";
+
+				sai2a: audio-controller@4400b004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					clocks = <&rcc SAI2_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 89 0x400 0x01>;
+					status = "disabled";
+				};
 
-		adc: adc@48003000 {
-			compatible = "st,stm32mp1-adc-core";
-			reg = <0x48003000 0x400>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			st,syscfg = <&syscfg>;
-			#interrupt-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
+				sai2b: audio-controller@4400b024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI2_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 90 0x400 0x01>;
+					status = "disabled";
+				};
+			};
 
-			adc1: adc@0 {
-				compatible = "st,stm32mp1-adc";
-				#io-channel-cells = <1>;
-				reg = <0x0>;
-				interrupt-parent = <&adc>;
-				interrupts = <0>;
-				dmas = <&dmamux1 9 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			sai3: sai@4400c000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400c000 0x400>;
+				reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI3_R>;
+				feature-domains = <&etzpc 60>;
+				status = "disabled";
+
+				sai3a: audio-controller@4400c004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x04 0x20>;
+					clocks = <&rcc SAI3_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 113 0x400 0x01>;
+					status = "disabled";
+				};
+
+				sai3b: audio-controller@4400c024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI3_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 114 0x400 0x01>;
+					status = "disabled";
+				};
 			};
 
-			adc2: adc@100 {
-				compatible = "st,stm32mp1-adc";
-				#io-channel-cells = <1>;
-				reg = <0x100>;
-				interrupt-parent = <&adc>;
-				interrupts = <1>;
-				dmas = <&dmamux1 10 0x400 0x01>;
-				dma-names = "rx";
+			dfsdm: dfsdm@4400d000 {
+				compatible = "st,stm32mp1-dfsdm";
+				reg = <0x4400d000 0x800>;
+				clocks = <&rcc DFSDM_K>;
+				clock-names = "dfsdm";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 61>;
 				status = "disabled";
-			};
-		};
 
-		sdmmc3: mmc@48004000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x48004000 0x400>;
-			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC3_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC3_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
+				dfsdm0: filter@0 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <0>;
+					interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 101 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		usbotg_hs: usb-otg@49000000 {
-			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-			reg = <0x49000000 0x10000>;
-			clocks = <&rcc USBO_K>;
-			clock-names = "otg";
-			resets = <&rcc USBO_R>;
-			reset-names = "dwc2";
-			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-			g-rx-fifo-size = <512>;
-			g-np-tx-fifo-size = <32>;
-			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-			dr_mode = "otg";
-			otg-rev = <0x200>;
-			usb33d-supply = <&usb33>;
-			status = "disabled";
-		};
+				dfsdm1: filter@1 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <1>;
+					interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 102 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		ipcc: mailbox@4c001000 {
-			compatible = "st,stm32mp1-ipcc";
-			#mbox-cells = <1>;
-			reg = <0x4c001000 0x400>;
-			st,proc-id = <0>;
-			interrupts-extended =
-				<&exti 61 1>,
-				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "rx", "tx";
-			clocks = <&rcc IPCC>;
-			wakeup-source;
-			status = "disabled";
-		};
-
-		dcmi: dcmi@4c006000 {
-			compatible = "st,stm32-dcmi";
-			reg = <0x4c006000 0x400>;
-			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc CAMITF_R>;
-			clocks = <&rcc DCMI>;
-			clock-names = "mclk";
-			dmas = <&dmamux1 75 0x400 0x01>;
-			dma-names = "tx";
-			status = "disabled";
-		};
+				dfsdm2: filter@2 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <2>;
+					interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 103 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		rcc: rcc@50000000 {
-			compatible = "st,stm32mp1-rcc", "syscon";
-			reg = <0x50000000 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
+				dfsdm3: filter@3 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <3>;
+					interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 104 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		pwr_regulators: pwr@50001000 {
-			compatible = "st,stm32mp1,pwr-reg";
-			reg = <0x50001000 0x10>;
+				dfsdm4: filter@4 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <4>;
+					interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 91 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-			reg11: reg11 {
-				regulator-name = "reg11";
-				regulator-min-microvolt = <1100000>;
-				regulator-max-microvolt = <1100000>;
+				dfsdm5: filter@5 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <5>;
+					interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 92 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 			};
 
-			reg18: reg18 {
-				regulator-name = "reg18";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-			};
+			dma1: dma-controller@48000000 {
+				compatible = "st,stm32-dma";
+				reg = <0x48000000 0x400>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc DMA1>;
+				resets = <&rcc DMA1_R>;
+				#dma-cells = <4>;
+				st,mem2mem;
+				dma-requests = <8>;
+				feature-domains = <&etzpc 88>;
+			};
+
+			dma2: dma-controller@48001000 {
+				compatible = "st,stm32-dma";
+				reg = <0x48001000 0x400>;
+				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc DMA2>;
+				resets = <&rcc DMA2_R>;
+				#dma-cells = <4>;
+				st,mem2mem;
+				dma-requests = <8>;
+				feature-domains = <&etzpc 89>;
+			};
+
+			dmamux1: dma-router@48002000 {
+				compatible = "st,stm32h7-dmamux";
+				reg = <0x48002000 0x40>;
+				#dma-cells = <3>;
+				dma-requests = <128>;
+				dma-masters = <&dma1 &dma2>;
+				dma-channels = <16>;
+				clocks = <&rcc DMAMUX>;
+				resets = <&rcc DMAMUX_R>;
+				feature-domains = <&etzpc 90>;
+			};
+
+			adc: adc@48003000 {
+				compatible = "st,stm32mp1-adc-core";
+				reg = <0x48003000 0x400>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+				clock-names = "bus", "adc";
+				interrupt-controller;
+				st,syscfg = <&syscfg>;
+				#interrupt-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 72>;
+				status = "disabled";
+
+				adc1: adc@0 {
+					compatible = "st,stm32mp1-adc";
+					#io-channel-cells = <1>;
+					reg = <0x0>;
+					interrupt-parent = <&adc>;
+					interrupts = <0>;
+					dmas = <&dmamux1 9 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-			usb33: usb33 {
-				regulator-name = "usb33";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
+				adc2: adc@100 {
+					compatible = "st,stm32mp1-adc";
+					#io-channel-cells = <1>;
+					reg = <0x100>;
+					interrupt-parent = <&adc>;
+					interrupts = <1>;
+					dmas = <&dmamux1 10 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 			};
-		};
 
-		pwr_mcu: pwr_mcu@50001014 {
-			compatible = "st,stm32mp151-pwr-mcu", "syscon";
-			reg = <0x50001014 0x4>;
-		};
+			sdmmc3: mmc@48004000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x00253180>;
+				reg = <0x48004000 0x400>;
+				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC3_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC3_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <120000000>;
+				feature-domains = <&etzpc 86>;
+				status = "disabled";
+			};
+
+			usbotg_hs: usb-otg@49000000 {
+				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+				reg = <0x49000000 0x10000>;
+				clocks = <&rcc USBO_K>;
+				clock-names = "otg";
+				resets = <&rcc USBO_R>;
+				reset-names = "dwc2";
+				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+				g-rx-fifo-size = <512>;
+				g-np-tx-fifo-size = <32>;
+				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+				dr_mode = "otg";
+				otg-rev = <0x200>;
+				usb33d-supply = <&usb33>;
+				feature-domains = <&etzpc 85>;
+				status = "disabled";
+			};
+
+			dcmi: dcmi@4c006000 {
+				compatible = "st,stm32-dcmi";
+				reg = <0x4c006000 0x400>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc CAMITF_R>;
+				clocks = <&rcc DCMI>;
+				clock-names = "mclk";
+				dmas = <&dmamux1 75 0x400 0x01>;
+				dma-names = "tx";
+				feature-domains = <&etzpc 70>;
+				status = "disabled";
+			};
+
+			lptimer2: timer@50021000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x50021000 0x400>;
+				interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM2_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 64>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		exti: interrupt-controller@5000d000 {
-			compatible = "st,stm32mp1-exti", "syscon";
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			reg = <0x5000d000 0x400>;
-		};
+				trigger@1 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <1>;
+					status = "disabled";
+				};
 
-		syscfg: syscon@50020000 {
-			compatible = "st,stm32mp157-syscfg", "syscon";
-			reg = <0x50020000 0x400>;
-			clocks = <&rcc SYSCFG>;
-		};
+				counter {
+					compatible = "st,stm32-lptimer-counter";
+					status = "disabled";
+				};
+			};
 
-		lptimer2: timer@50021000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x50021000 0x400>;
-			interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM2_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
+			lptimer3: timer@50022000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x50022000 0x400>;
+				interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM3_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 65>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
+				trigger@2 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <2>;
+					status = "disabled";
+				};
 			};
 
-			trigger@1 {
-				compatible = "st,stm32-lptimer-trigger";
-				reg = <1>;
+			lptimer4: timer@50023000 {
+				compatible = "st,stm32-lptimer";
+				reg = <0x50023000 0x400>;
+				interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM4_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 66>;
 				status = "disabled";
-			};
 
-			counter {
-				compatible = "st,stm32-lptimer-counter";
-				status = "disabled";
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 			};
-		};
-
-		lptimer3: timer@50022000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x50022000 0x400>;
-			interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM3_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
+			lptimer5: timer@50024000 {
+				compatible = "st,stm32-lptimer";
+				reg = <0x50024000 0x400>;
+				interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM5_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 67>;
 				status = "disabled";
-			};
 
-			trigger@2 {
-				compatible = "st,stm32-lptimer-trigger";
-				reg = <2>;
-				status = "disabled";
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 			};
-		};
 
-		lptimer4: timer@50023000 {
-			compatible = "st,stm32-lptimer";
-			reg = <0x50023000 0x400>;
-			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM4_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
+			vrefbuf: vrefbuf@50025000 {
+				compatible = "st,stm32-vrefbuf";
+				reg = <0x50025000 0x8>;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <2500000>;
+				clocks = <&rcc VREF>;
+				feature-domains = <&etzpc 69>;
 				status = "disabled";
 			};
-		};
 
-		lptimer5: timer@50024000 {
-			compatible = "st,stm32-lptimer";
-			reg = <0x50024000 0x400>;
-			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM5_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
+			sai4: sai@50027000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x50027000 0x400>;
+				reg = <0x50027000 0x4>, <0x500273f0 0x10>;
+				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI4_R>;
+				feature-domains = <&etzpc 68>;
+				status = "disabled";
+
+				sai4a: audio-controller@50027004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x04 0x20>;
+					clocks = <&rcc SAI4_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 99 0x400 0x01>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
+				sai4b: audio-controller@50027024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI4_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 100 0x400 0x01>;
+					status = "disabled";
+				};
 			};
-		};
 
-		vrefbuf: vrefbuf@50025000 {
-			compatible = "st,stm32-vrefbuf";
-			reg = <0x50025000 0x8>;
-			regulator-min-microvolt = <1500000>;
-			regulator-max-microvolt = <2500000>;
-			clocks = <&rcc VREF>;
-			status = "disabled";
-		};
-
-		sai4: sai@50027000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x50027000 0x400>;
-			reg = <0x50027000 0x4>, <0x500273f0 0x10>;
-			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI4_R>;
-			status = "disabled";
+			hash1: hash@54002000 {
+				compatible = "st,stm32f756-hash";
+				reg = <0x54002000 0x400>;
+				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc HASH1>;
+				resets = <&rcc HASH1_R>;
+				dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
+				dma-names = "in";
+				dma-maxburst = <2>;
+				feature-domains = <&etzpc 8>;
+				status = "disabled";
+			};
+
+			rng1: rng@54003000 {
+				compatible = "st,stm32-rng";
+				reg = <0x54003000 0x400>;
+				clocks = <&rcc RNG1_K>;
+				resets = <&rcc RNG1_R>;
+				feature-domains = <&etzpc 7>;
+				status = "disabled";
+			};
+
+			fmc: memory-controller@58002000 {
+				#address-cells = <2>;
+				#size-cells = <1>;
+				compatible = "st,stm32mp1-fmc2-ebi";
+				reg = <0x58002000 0x1000>;
+				clocks = <&rcc FMC_K>;
+				resets = <&rcc FMC_R>;
+				feature-domains = <&etzpc 91>;
+				status = "disabled";
+
+				ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+					 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+					 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+					 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+					 <4 0 0x80000000 0x10000000>; /* NAND */
+
+				nand-controller@4,0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "st,stm32mp1-fmc2-nfc";
+					reg = <4 0x00000000 0x1000>,
+					      <4 0x08010000 0x1000>,
+					      <4 0x08020000 0x1000>,
+					      <4 0x01000000 0x1000>,
+					      <4 0x09010000 0x1000>,
+					      <4 0x09020000 0x1000>;
+					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+					       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+					       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+					dma-names = "tx", "rx", "ecc";
+					status = "disabled";
+				};
+			};
 
-			sai4a: audio-controller@50027004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x04 0x20>;
-				clocks = <&rcc SAI4_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 99 0x400 0x01>;
-				status = "disabled";
+			qspi: spi@58003000 {
+				compatible = "st,stm32f469-qspi";
+				reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+				reg-names = "qspi", "qspi_mm";
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
+				       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
+				dma-names = "tx", "rx";
+				clocks = <&rcc QSPI_K>;
+				resets = <&rcc QSPI_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 92>;
+				status = "disabled";
+			};
+
+			ethernet0: ethernet@5800a000 {
+				compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+				reg = <0x5800a000 0x2000>;
+				reg-names = "stmmaceth";
+				interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "macirq";
+				clock-names = "stmmaceth",
+					      "mac-clk-tx",
+					      "mac-clk-rx",
+					      "eth-ck",
+					      "ptp_ref",
+					      "ethstp";
+				clocks = <&rcc ETHMAC>,
+					 <&rcc ETHTX>,
+					 <&rcc ETHRX>,
+					 <&rcc ETHCK_K>,
+					 <&rcc ETHPTP_K>,
+					 <&rcc ETHSTP>;
+				st,syscon = <&syscfg 0x4>;
+				snps,mixed-burst;
+				snps,pbl = <2>;
+				snps,en-tx-lpi-clockgating;
+				snps,axi-config = <&stmmac_axi_config_0>;
+				snps,tso;
+				feature-domains = <&etzpc 94>;
+				status = "disabled";
+
+				stmmac_axi_config_0: stmmac-axi-config {
+					snps,wr_osr_lmt = <0x7>;
+					snps,rd_osr_lmt = <0x7>;
+					snps,blen = <0 0 0 0 16 8 4>;
+				};
 			};
 
-			sai4b: audio-controller@50027024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI4_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 100 0x400 0x01>;
+			usart1: serial@5c000000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x5c000000 0x400>;
+				interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART1_K>;
+				wakeup-source;
+				feature-domains = <&etzpc 3>;
 				status = "disabled";
 			};
-		};
 
-		dts: thermal@50028000 {
-			compatible = "st,stm32-thermal";
-			reg = <0x50028000 0x100>;
-			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc TMPSENS>;
-			clock-names = "pclk";
-			#thermal-sensor-cells = <0>;
-			status = "disabled";
-		};
-
-		hash1: hash@54002000 {
-			compatible = "st,stm32f756-hash";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc HASH1>;
-			resets = <&rcc HASH1_R>;
-			dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
-			dma-names = "in";
-			dma-maxburst = <2>;
-			status = "disabled";
-		};
-
-		rng1: rng@54003000 {
-			compatible = "st,stm32-rng";
-			reg = <0x54003000 0x400>;
-			clocks = <&rcc RNG1_K>;
-			resets = <&rcc RNG1_R>;
-			status = "disabled";
-		};
-
-		mdma1: dma-controller@58000000 {
-			compatible = "st,stm32h7-mdma";
-			reg = <0x58000000 0x1000>;
-			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc MDMA>;
-			resets = <&rcc MDMA_R>;
-			#dma-cells = <5>;
-			dma-channels = <32>;
-			dma-requests = <48>;
-		};
-
-		fmc: memory-controller@58002000 {
-			#address-cells = <2>;
-			#size-cells = <1>;
-			compatible = "st,stm32mp1-fmc2-ebi";
-			reg = <0x58002000 0x1000>;
-			clocks = <&rcc FMC_K>;
-			resets = <&rcc FMC_R>;
-			status = "disabled";
-
-			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
-				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
-				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
-				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
-				 <4 0 0x80000000 0x10000000>; /* NAND */
-
-			nand-controller@4,0 {
+			spi6: spi@5c001000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "st,stm32mp1-fmc2-nfc";
-				reg = <4 0x00000000 0x1000>,
-				      <4 0x08010000 0x1000>,
-				      <4 0x08020000 0x1000>,
-				      <4 0x01000000 0x1000>,
-				      <4 0x09010000 0x1000>,
-				      <4 0x09020000 0x1000>;
-				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
-				       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
-				       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
-				dma-names = "tx", "rx", "ecc";
+				compatible = "st,stm32h7-spi";
+				reg = <0x5c001000 0x400>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI6_K>;
+				resets = <&rcc SPI6_R>;
+				dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
+				       <&mdma1 35 0x0 0x40002 0x0 0x0>;
+				feature-domains = <&etzpc 4>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			i2c4: i2c@5c002000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x5c002000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C4_K>;
+				resets = <&rcc I2C4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x8>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 5>;
 				status = "disabled";
 			};
-		};
-
-		qspi: spi@58003000 {
-			compatible = "st,stm32f469-qspi";
-			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
-			reg-names = "qspi", "qspi_mm";
-			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
-			       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
-			dma-names = "tx", "rx";
-			clocks = <&rcc QSPI_K>;
-			resets = <&rcc QSPI_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		sdmmc1: mmc@58005000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x58005000 0x1000>;
-			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC1_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC1_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
-
-		sdmmc2: mmc@58007000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x58007000 0x1000>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC2_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC2_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
-
-		crc1: crc@58009000 {
-			compatible = "st,stm32f7-crc";
-			reg = <0x58009000 0x400>;
-			clocks = <&rcc CRC1>;
-			status = "disabled";
-		};
-
-		ethernet0: ethernet@5800a000 {
-			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
-			reg = <0x5800a000 0x2000>;
-			reg-names = "stmmaceth";
-			interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
-			clock-names = "stmmaceth",
-				      "mac-clk-tx",
-				      "mac-clk-rx",
-				      "eth-ck",
-				      "ptp_ref",
-				      "ethstp";
-			clocks = <&rcc ETHMAC>,
-				 <&rcc ETHTX>,
-				 <&rcc ETHRX>,
-				 <&rcc ETHCK_K>,
-				 <&rcc ETHPTP_K>,
-				 <&rcc ETHSTP>;
-			st,syscon = <&syscfg 0x4>;
-			snps,mixed-burst;
-			snps,pbl = <2>;
-			snps,en-tx-lpi-clockgating;
-			snps,axi-config = <&stmmac_axi_config_0>;
-			snps,tso;
-			status = "disabled";
-
-			stmmac_axi_config_0: stmmac-axi-config {
-				snps,wr_osr_lmt = <0x7>;
-				snps,rd_osr_lmt = <0x7>;
-				snps,blen = <0 0 0 0 16 8 4>;
-			};
-		};
 
-		usbh_ohci: usb@5800c000 {
-			compatible = "generic-ohci";
-			reg = <0x5800c000 0x1000>;
-			clocks = <&usbphyc>, <&rcc USBH>;
-			resets = <&rcc USBH_R>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		usbh_ehci: usb@5800d000 {
-			compatible = "generic-ehci";
-			reg = <0x5800d000 0x1000>;
-			clocks = <&usbphyc>, <&rcc USBH>;
-			resets = <&rcc USBH_R>;
-			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			companion = <&usbh_ohci>;
-			status = "disabled";
-		};
-
-		ltdc: display-controller@5a001000 {
-			compatible = "st,stm32-ltdc";
-			reg = <0x5a001000 0x400>;
-			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LTDC_PX>;
-			clock-names = "lcd";
-			resets = <&rcc LTDC_R>;
-			status = "disabled";
-
-			port {
+			i2c6: i2c@5c009000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x5c009000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C6_K>;
+				resets = <&rcc I2C6_R>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x20>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 12>;
+				status = "disabled";
 			};
-		};
-
-		iwdg2: watchdog@5a002000 {
-			compatible = "st,stm32mp1-iwdg";
-			reg = <0x5a002000 0x400>;
-			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
-			clock-names = "pclk", "lsi";
-			status = "disabled";
-		};
-
-		usbphyc: usbphyc@5a006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#clock-cells = <0>;
-			compatible = "st,stm32mp1-usbphyc";
-			reg = <0x5a006000 0x1000>;
-			clocks = <&rcc USBPHY_K>;
-			resets = <&rcc USBPHY_R>;
-			vdda1v1-supply = <&reg11>;
-			vdda1v8-supply = <&reg18>;
-			status = "disabled";
-
-			usbphyc_port0: usb-phy@0 {
-				#phy-cells = <0>;
-				reg = <0>;
-			};
-
-			usbphyc_port1: usb-phy@1 {
-				#phy-cells = <1>;
-				reg = <1>;
-			};
-		};
-
-		usart1: serial@5c000000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x5c000000 0x400>;
-			interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART1_K>;
-			wakeup-source;
-			status = "disabled";
-		};
-
-		spi6: spi@5c001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x5c001000 0x400>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI6_K>;
-			resets = <&rcc SPI6_R>;
-			dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
-			       <&mdma1 35 0x0 0x40002 0x0 0x0>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2c4: i2c@5c002000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x5c002000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C4_K>;
-			resets = <&rcc I2C4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x8>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		rtc: rtc@5c004000 {
-			compatible = "st,stm32mp1-rtc";
-			reg = <0x5c004000 0x400>;
-			clocks = <&rcc RTCAPB>, <&rcc RTC>;
-			clock-names = "pclk", "rtc_ck";
-			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		bsec: efuse@5c005000 {
-			compatible = "st,stm32mp15-bsec";
-			reg = <0x5c005000 0x400>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ts_cal1: calib@5c {
-				reg = <0x5c 0x2>;
-			};
-			ts_cal2: calib@5e {
-				reg = <0x5e 0x2>;
-			};
-		};
 
-		i2c6: i2c@5c009000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x5c009000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C6_K>;
-			resets = <&rcc I2C6_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x20>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
 		};
 
 		tamp: tamp@5c00a000 {
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi
index 486084e0b80b..82073dd85f18 100644
--- a/arch/arm/boot/dts/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/stm32mp153.dtsi
@@ -28,32 +28,34 @@ timer {
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+};
 
-	soc {
-		m_can1: can@4400e000 {
-			compatible = "bosch,m_can";
-			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
-			reg-names = "m_can", "message_ram";
-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "int0", "int1";
-			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-			clock-names = "hclk", "cclk";
-			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
-			status = "disabled";
-		};
+&etzpc {
+	m_can1: can@4400e000 {
+		compatible = "bosch,m_can";
+		reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+		reg-names = "m_can", "message_ram";
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "int0", "int1";
+		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+		clock-names = "hclk", "cclk";
+		bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+		feature-domains = <&etzpc 62>;
+		status = "disabled";
+	};
 
-		m_can2: can@4400f000 {
-			compatible = "bosch,m_can";
-			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
-			reg-names = "m_can", "message_ram";
-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "int0", "int1";
-			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-			clock-names = "hclk", "cclk";
-			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
-			status = "disabled";
-		};
+	m_can2: can@4400f000 {
+		compatible = "bosch,m_can";
+		reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+		reg-names = "m_can", "message_ram";
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "int0", "int1";
+		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+		clock-names = "hclk", "cclk";
+		bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+		feature-domains = <&etzpc 62>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi
index b06a55a2fa18..55524a8d3093 100644
--- a/arch/arm/boot/dts/stm32mp15xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xc.dtsi
@@ -4,15 +4,14 @@
  * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp1: cryp@54001000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54001000 0x400>;
-			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp1: cryp@54001000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54001000 0x400>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		feature-domains = <&etzpc 9>;
+		status = "disabled";
 	};
 };
-- 
2.35.3


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^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 5/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, Gatien Chevallier, linux-iio, netdev,
	linux-usb, linux-mmc, linux-kernel, linux-spi, linux-phy,
	linux-crypto, linux-serial, dmaengine, linux-media, linux-stm32,
	linux-arm-kernel, linux-i2c

The STM32 System Bus is an internal bus on which devices are connected.
ETZPC is a peripheral overseeing the firewall bus that configures
and control access to the peripherals connected on it.

For more information on which peripheral is securable, please read
the STM32MP15 reference manual.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

No changes in V2.

Changes in V3:
	-Use appriopriate node name: bus

 arch/arm/boot/dts/stm32mp151.dtsi  | 2722 ++++++++++++++--------------
 arch/arm/boot/dts/stm32mp153.dtsi  |   52 +-
 arch/arm/boot/dts/stm32mp15xc.dtsi |   19 +-
 3 files changed, 1434 insertions(+), 1359 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
index 5491b6c4dec2..5dab96e7c2ba 100644
--- a/arch/arm/boot/dts/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/stm32mp151.dtsi
@@ -122,1526 +122,1600 @@ soc {
 		interrupt-parent = <&intc>;
 		ranges;
 
-		timers2: timer@40000000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40000000 0x400>;
-			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM2_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 18 0x400 0x1>,
-			       <&dmamux1 19 0x400 0x1>,
-			       <&dmamux1 20 0x400 0x1>,
-			       <&dmamux1 21 0x400 0x1>,
-			       <&dmamux1 22 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+		ipcc: mailbox@4c001000 {
+			compatible = "st,stm32mp1-ipcc";
+			#mbox-cells = <1>;
+			reg = <0x4c001000 0x400>;
+			st,proc-id = <0>;
+			interrupts-extended =
+				<&exti 61 1>,
+				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "rx", "tx";
+			clocks = <&rcc IPCC>;
+			wakeup-source;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@1 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <1>;
-				status = "disabled";
-			};
-
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		rcc: rcc@50000000 {
+			compatible = "st,stm32mp1-rcc", "syscon";
+			reg = <0x50000000 0x1000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
 		};
 
-		timers3: timer@40001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40001000 0x400>;
-			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM3_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 23 0x400 0x1>,
-			       <&dmamux1 24 0x400 0x1>,
-			       <&dmamux1 25 0x400 0x1>,
-			       <&dmamux1 26 0x400 0x1>,
-			       <&dmamux1 27 0x400 0x1>,
-			       <&dmamux1 28 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
-			status = "disabled";
+		pwr_regulators: pwr@50001000 {
+			compatible = "st,stm32mp1,pwr-reg";
+			reg = <0x50001000 0x10>;
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+			reg11: reg11 {
+				regulator-name = "reg11";
+				regulator-min-microvolt = <1100000>;
+				regulator-max-microvolt = <1100000>;
 			};
 
-			timer@2 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <2>;
-				status = "disabled";
+			reg18: reg18 {
+				regulator-name = "reg18";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
 			};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
+			usb33: usb33 {
+				regulator-name = "usb33";
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
 			};
 		};
 
-		timers4: timer@40002000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40002000 0x400>;
-			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM4_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 29 0x400 0x1>,
-			       <&dmamux1 30 0x400 0x1>,
-			       <&dmamux1 31 0x400 0x1>,
-			       <&dmamux1 32 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4";
-			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
+		pwr_mcu: pwr_mcu@50001014 {
+			compatible = "st,stm32mp151-pwr-mcu", "syscon";
+			reg = <0x50001014 0x4>;
+		};
 
-			timer@3 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <3>;
-				status = "disabled";
-			};
+		exti: interrupt-controller@5000d000 {
+			compatible = "st,stm32mp1-exti", "syscon";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x5000d000 0x400>;
+		};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		syscfg: syscon@50020000 {
+			compatible = "st,stm32mp157-syscfg", "syscon";
+			reg = <0x50020000 0x400>;
+			clocks = <&rcc SYSCFG>;
 		};
 
-		timers5: timer@40003000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40003000 0x400>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM5_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 55 0x400 0x1>,
-			       <&dmamux1 56 0x400 0x1>,
-			       <&dmamux1 57 0x400 0x1>,
-			       <&dmamux1 58 0x400 0x1>,
-			       <&dmamux1 59 0x400 0x1>,
-			       <&dmamux1 60 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+		dts: thermal@50028000 {
+			compatible = "st,stm32-thermal";
+			reg = <0x50028000 0x100>;
+			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc TMPSENS>;
+			clock-names = "pclk";
+			#thermal-sensor-cells = <0>;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@4 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <4>;
-				status = "disabled";
-			};
-
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
-			};
+		mdma1: dma-controller@58000000 {
+			compatible = "st,stm32h7-mdma";
+			reg = <0x58000000 0x1000>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc MDMA>;
+			resets = <&rcc MDMA_R>;
+			#dma-cells = <5>;
+			dma-channels = <32>;
+			dma-requests = <48>;
 		};
 
-		timers6: timer@40004000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40004000 0x400>;
-			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM6_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 69 0x400 0x1>;
-			dma-names = "up";
+		sdmmc1: mmc@58005000 {
+			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+			arm,primecell-periphid = <0x00253180>;
+			reg = <0x58005000 0x1000>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SDMMC1_K>;
+			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC1_R>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
 			status = "disabled";
-
-			timer@5 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <5>;
-				status = "disabled";
-			};
 		};
 
-		timers7: timer@40005000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40005000 0x400>;
-			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM7_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 70 0x400 0x1>;
-			dma-names = "up";
+		sdmmc2: mmc@58007000 {
+			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+			arm,primecell-periphid = <0x00253180>;
+			reg = <0x58007000 0x1000>;
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc SDMMC2_K>;
+			clock-names = "apb_pclk";
+			resets = <&rcc SDMMC2_R>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			max-frequency = <120000000>;
 			status = "disabled";
-
-			timer@6 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <6>;
-				status = "disabled";
-			};
 		};
 
-		timers12: timer@40006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40006000 0x400>;
-			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM12_K>;
-			clock-names = "int";
+		crc1: crc@58009000 {
+			compatible = "st,stm32f7-crc";
+			reg = <0x58009000 0x400>;
+			clocks = <&rcc CRC1>;
 			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@11 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <11>;
-				status = "disabled";
-			};
 		};
 
-		timers13: timer@40007000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40007000 0x400>;
-			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM13_K>;
-			clock-names = "int";
+		usbh_ohci: usb@5800c000 {
+			compatible = "generic-ohci";
+			reg = <0x5800c000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
+		};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			timer@12 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <12>;
-				status = "disabled";
-			};
+		usbh_ehci: usb@5800d000 {
+			compatible = "generic-ehci";
+			reg = <0x5800d000 0x1000>;
+			clocks = <&usbphyc>, <&rcc USBH>;
+			resets = <&rcc USBH_R>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			companion = <&usbh_ohci>;
+			status = "disabled";
 		};
 
-		timers14: timer@40008000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x40008000 0x400>;
-			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM14_K>;
-			clock-names = "int";
+		ltdc: display-controller@5a001000 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x5a001000 0x400>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LTDC_PX>;
+			clock-names = "lcd";
+			resets = <&rcc LTDC_R>;
 			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
 			};
+		};
 
-			timer@13 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <13>;
-				status = "disabled";
-			};
+		iwdg2: watchdog@5a002000 {
+			compatible = "st,stm32mp1-iwdg";
+			reg = <0x5a002000 0x400>;
+			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
+			clock-names = "pclk", "lsi";
+			status = "disabled";
 		};
 
-		lptimer1: timer@40009000 {
+		usbphyc: usbphyc@5a006000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x40009000 0x400>;
-			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM1_K>;
-			clock-names = "mux";
-			wakeup-source;
+			#clock-cells = <0>;
+			compatible = "st,stm32mp1-usbphyc";
+			reg = <0x5a006000 0x1000>;
+			clocks = <&rcc USBPHY_K>;
+			resets = <&rcc USBPHY_R>;
+			vdda1v1-supply = <&reg11>;
+			vdda1v8-supply = <&reg18>;
 			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
-			};
-
-			trigger@0 {
-				compatible = "st,stm32-lptimer-trigger";
+			usbphyc_port0: usb-phy@0 {
+				#phy-cells = <0>;
 				reg = <0>;
-				status = "disabled";
 			};
 
-			counter {
-				compatible = "st,stm32-lptimer-counter";
-				status = "disabled";
+			usbphyc_port1: usb-phy@1 {
+				#phy-cells = <1>;
+				reg = <1>;
 			};
 		};
 
-		spi2: spi@4000b000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x4000b000 0x400>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI2_K>;
-			resets = <&rcc SPI2_R>;
-			dmas = <&dmamux1 39 0x400 0x05>,
-			       <&dmamux1 40 0x400 0x05>;
-			dma-names = "rx", "tx";
+		rtc: rtc@5c004000 {
+			compatible = "st,stm32mp1-rtc";
+			reg = <0x5c004000 0x400>;
+			clocks = <&rcc RTCAPB>, <&rcc RTC>;
+			clock-names = "pclk", "rtc_ck";
+			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
-		i2s2: audio-controller@4000b000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x4000b000 0x400>;
-			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 39 0x400 0x01>,
-			       <&dmamux1 40 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
+		bsec: efuse@5c005000 {
+			compatible = "st,stm32mp15-bsec";
+			reg = <0x5c005000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ts_cal1: calib@5c {
+				reg = <0x5c 0x2>;
+			};
+			ts_cal2: calib@5e {
+				reg = <0x5e 0x2>;
+			};
 		};
 
-		spi3: spi@4000c000 {
+		etzpc: bus@5c007000 {
+			compatible = "st,stm32mp15-sys-bus";
+			reg = <0x5c007000 0x400>;
 			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x4000c000 0x400>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI3_K>;
-			resets = <&rcc SPI3_R>;
-			dmas = <&dmamux1 61 0x400 0x05>,
-			       <&dmamux1 62 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			#size-cells = <1>;
+			feature-domain-controller;
+			#feature-domain-cells = <1>;
+			ranges;
 
-		i2s3: audio-controller@4000c000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x4000c000 0x400>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 61 0x400 0x01>,
-			       <&dmamux1 62 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers2: timer@40000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40000000 0x400>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM2_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 18 0x400 0x1>,
+				       <&dmamux1 19 0x400 0x1>,
+				       <&dmamux1 20 0x400 0x1>,
+				       <&dmamux1 21 0x400 0x1>,
+				       <&dmamux1 22 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+				feature-domains = <&etzpc 16>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		spdifrx: audio-controller@4000d000 {
-			compatible = "st,stm32h7-spdifrx";
-			#sound-dai-cells = <0>;
-			reg = <0x4000d000 0x400>;
-			clocks = <&rcc SPDIF_K>;
-			clock-names = "kclk";
-			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 93 0x400 0x01>,
-			       <&dmamux1 94 0x400 0x01>;
-			dma-names = "rx", "rx-ctrl";
-			status = "disabled";
-		};
+				timer@1 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <1>;
+					status = "disabled";
+				};
 
-		usart2: serial@4000e000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x4000e000 0x400>;
-			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART2_K>;
-			wakeup-source;
-			dmas = <&dmamux1 43 0x400 0x15>,
-			       <&dmamux1 44 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		usart3: serial@4000f000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x4000f000 0x400>;
-			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART3_K>;
-			wakeup-source;
-			dmas = <&dmamux1 45 0x400 0x15>,
-			       <&dmamux1 46 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers3: timer@40001000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40001000 0x400>;
+				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM3_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 23 0x400 0x1>,
+				       <&dmamux1 24 0x400 0x1>,
+				       <&dmamux1 25 0x400 0x1>,
+				       <&dmamux1 26 0x400 0x1>,
+				       <&dmamux1 27 0x400 0x1>,
+				       <&dmamux1 28 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+				feature-domains = <&etzpc 17>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		uart4: serial@40010000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40010000 0x400>;
-			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART4_K>;
-			wakeup-source;
-			dmas = <&dmamux1 63 0x400 0x15>,
-			       <&dmamux1 64 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				timer@2 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <2>;
+					status = "disabled";
+				};
 
-		uart5: serial@40011000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40011000 0x400>;
-			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART5_K>;
-			wakeup-source;
-			dmas = <&dmamux1 65 0x400 0x15>,
-			       <&dmamux1 66 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		i2c1: i2c@40012000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40012000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C1_K>;
-			resets = <&rcc I2C1_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x1>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+			timers4: timer@40002000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40002000 0x400>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM4_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 29 0x400 0x1>,
+				       <&dmamux1 30 0x400 0x1>,
+				       <&dmamux1 31 0x400 0x1>,
+				       <&dmamux1 32 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4";
+				feature-domains = <&etzpc 18>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		i2c2: i2c@40013000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40013000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C2_K>;
-			resets = <&rcc I2C2_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x2>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+				timer@3 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <3>;
+					status = "disabled";
+				};
 
-		i2c3: i2c@40014000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40014000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C3_K>;
-			resets = <&rcc I2C3_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x4>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-		i2c5: i2c@40015000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x40015000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C5_K>;
-			resets = <&rcc I2C5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x10>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
+			timers5: timer@40003000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40003000 0x400>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM5_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 55 0x400 0x1>,
+				       <&dmamux1 56 0x400 0x1>,
+				       <&dmamux1 57 0x400 0x1>,
+				       <&dmamux1 58 0x400 0x1>,
+				       <&dmamux1 59 0x400 0x1>,
+				       <&dmamux1 60 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+				feature-domains = <&etzpc 19>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		cec: cec@40016000 {
-			compatible = "st,stm32-cec";
-			reg = <0x40016000 0x400>;
-			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CEC_K>, <&rcc CEC>;
-			clock-names = "cec", "hdmi-cec";
-			status = "disabled";
-		};
+				timer@4 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <4>;
+					status = "disabled";
+				};
 
-		dac: dac@40017000 {
-			compatible = "st,stm32h7-dac-core";
-			reg = <0x40017000 0x400>;
-			clocks = <&rcc DAC12>;
-			clock-names = "pclk";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
 
-			dac1: dac@1 {
-				compatible = "st,stm32-dac";
-				#io-channel-cells = <1>;
-				reg = <1>;
-				status = "disabled";
+			timers6: timer@40004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40004000 0x400>;
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM6_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 69 0x400 0x1>;
+				dma-names = "up";
+				feature-domains = <&etzpc 20>;
+				status = "disabled";
+
+				timer@5 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <5>;
+					status = "disabled";
+				};
 			};
 
-			dac2: dac@2 {
-				compatible = "st,stm32-dac";
-				#io-channel-cells = <1>;
-				reg = <2>;
-				status = "disabled";
+			timers7: timer@40005000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40005000 0x400>;
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM7_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 70 0x400 0x1>;
+				dma-names = "up";
+				feature-domains = <&etzpc 21>;
+				status = "disabled";
+
+				timer@6 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <6>;
+					status = "disabled";
+				};
 			};
-		};
 
-		uart7: serial@40018000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40018000 0x400>;
-			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART7_K>;
-			wakeup-source;
-			dmas = <&dmamux1 79 0x400 0x15>,
-			       <&dmamux1 80 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			timers12: timer@40006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40006000 0x400>;
+				interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM12_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 22>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		uart8: serial@40019000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x40019000 0x400>;
-			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc UART8_K>;
-			wakeup-source;
-			dmas = <&dmamux1 81 0x400 0x15>,
-			       <&dmamux1 82 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+				timer@11 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <11>;
+					status = "disabled";
+				};
+			};
 
-		timers1: timer@44000000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44000000 0x400>;
-			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "brk", "up", "trg-com", "cc";
-			clocks = <&rcc TIM1_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 11 0x400 0x1>,
-			       <&dmamux1 12 0x400 0x1>,
-			       <&dmamux1 13 0x400 0x1>,
-			       <&dmamux1 14 0x400 0x1>,
-			       <&dmamux1 15 0x400 0x1>,
-			       <&dmamux1 16 0x400 0x1>,
-			       <&dmamux1 17 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4",
-				    "up", "trig", "com";
-			status = "disabled";
+			timers13: timer@40007000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40007000 0x400>;
+				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM13_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 23>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+				timer@12 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <12>;
+					status = "disabled";
+				};
 			};
 
-			timer@0 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <0>;
-				status = "disabled";
-			};
+			timers14: timer@40008000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x40008000 0x400>;
+				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM14_K>;
+				clock-names = "int";
+				feature-domains = <&etzpc 24>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
-				status = "disabled";
+				timer@13 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <13>;
+					status = "disabled";
+				};
 			};
-		};
 
-		timers8: timer@44001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44001000 0x400>;
-			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "brk", "up", "trg-com", "cc";
-			clocks = <&rcc TIM8_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 47 0x400 0x1>,
-			       <&dmamux1 48 0x400 0x1>,
-			       <&dmamux1 49 0x400 0x1>,
-			       <&dmamux1 50 0x400 0x1>,
-			       <&dmamux1 51 0x400 0x1>,
-			       <&dmamux1 52 0x400 0x1>,
-			       <&dmamux1 53 0x400 0x1>;
-			dma-names = "ch1", "ch2", "ch3", "ch4",
-				    "up", "trig", "com";
-			status = "disabled";
+			lptimer1: timer@40009000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x40009000 0x400>;
+				interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM1_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 25>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
-				status = "disabled";
+				trigger@0 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <0>;
+					status = "disabled";
+				};
+
+				counter {
+					compatible = "st,stm32-lptimer-counter";
+					status = "disabled";
+				};
 			};
 
-			timer@7 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <7>;
+			i2s2: audio-controller@4000b000 {
+				compatible = "st,stm32h7-i2s";
+				#sound-dai-cells = <0>;
+				reg = <0x4000b000 0x400>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 39 0x400 0x01>,
+				       <&dmamux1 40 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 27>;
 				status = "disabled";
 			};
 
-			counter {
-				compatible = "st,stm32-timer-counter";
+			spi2: spi@4000b000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x4000b000 0x400>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI2_K>;
+				resets = <&rcc SPI2_R>;
+				dmas = <&dmamux1 39 0x400 0x05>,
+				       <&dmamux1 40 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 27>;
 				status = "disabled";
 			};
-		};
-
-		usart6: serial@44003000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x44003000 0x400>;
-			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART6_K>;
-			wakeup-source;
-			dmas = <&dmamux1 71 0x400 0x15>,
-			       <&dmamux1 72 0x400 0x11>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi1: spi@44004000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44004000 0x400>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI1_K>;
-			resets = <&rcc SPI1_R>;
-			dmas = <&dmamux1 37 0x400 0x05>,
-			       <&dmamux1 38 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2s1: audio-controller@44004000 {
-			compatible = "st,stm32h7-i2s";
-			#sound-dai-cells = <0>;
-			reg = <0x44004000 0x400>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&dmamux1 37 0x400 0x01>,
-			       <&dmamux1 38 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi4: spi@44005000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44005000 0x400>;
-			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI4_K>;
-			resets = <&rcc SPI4_R>;
-			dmas = <&dmamux1 83 0x400 0x05>,
-			       <&dmamux1 84 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		timers15: timer@44006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44006000 0x400>;
-			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM15_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 105 0x400 0x1>,
-			       <&dmamux1 106 0x400 0x1>,
-			       <&dmamux1 107 0x400 0x1>,
-			       <&dmamux1 108 0x400 0x1>;
-			dma-names = "ch1", "up", "trig", "com";
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			i2s3: audio-controller@4000c000 {
+				compatible = "st,stm32h7-i2s";
+				#sound-dai-cells = <0>;
+				reg = <0x4000c000 0x400>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 61 0x400 0x01>,
+				       <&dmamux1 62 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 28>;
 				status = "disabled";
 			};
 
-			timer@14 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <14>;
+			spi3: spi@4000c000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x4000c000 0x400>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI3_K>;
+				resets = <&rcc SPI3_R>;
+				dmas = <&dmamux1 61 0x400 0x05>,
+				       <&dmamux1 62 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 28>;
 				status = "disabled";
 			};
-		};
-
-		timers16: timer@44007000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44007000 0x400>;
-			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM16_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 109 0x400 0x1>,
-			       <&dmamux1 110 0x400 0x1>;
-			dma-names = "ch1", "up";
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			spdifrx: audio-controller@4000d000 {
+				compatible = "st,stm32h7-spdifrx";
+				#sound-dai-cells = <0>;
+				reg = <0x4000d000 0x400>;
+				clocks = <&rcc SPDIF_K>;
+				clock-names = "kclk";
+				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 93 0x400 0x01>,
+				       <&dmamux1 94 0x400 0x01>;
+				dma-names = "rx", "rx-ctrl";
+				feature-domains = <&etzpc 29>;
+				status = "disabled";
+			};
+
+			usart2: serial@4000e000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x4000e000 0x400>;
+				interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART2_K>;
+				wakeup-source;
+				dmas = <&dmamux1 43 0x400 0x15>,
+				       <&dmamux1 44 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 30>;
+				status = "disabled";
+			};
+
+			usart3: serial@4000f000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x4000f000 0x400>;
+				interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART3_K>;
+				wakeup-source;
+				dmas = <&dmamux1 45 0x400 0x15>,
+				       <&dmamux1 46 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 31>;
+				status = "disabled";
+			};
+
+			uart4: serial@40010000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40010000 0x400>;
+				interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART4_K>;
+				wakeup-source;
+				dmas = <&dmamux1 63 0x400 0x15>,
+				       <&dmamux1 64 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 32>;
+				status = "disabled";
+			};
+
+			uart5: serial@40011000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40011000 0x400>;
+				interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART5_K>;
+				wakeup-source;
+				dmas = <&dmamux1 65 0x400 0x15>,
+				       <&dmamux1 66 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 33>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@40012000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40012000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C1_K>;
+				resets = <&rcc I2C1_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x1>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 34>;
 				status = "disabled";
 			};
-			timer@15 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <15>;
+
+			i2c2: i2c@40013000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40013000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C2_K>;
+				resets = <&rcc I2C2_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x2>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 35>;
 				status = "disabled";
 			};
-		};
 
-		timers17: timer@44008000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-timers";
-			reg = <0x44008000 0x400>;
-			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "global";
-			clocks = <&rcc TIM17_K>;
-			clock-names = "int";
-			dmas = <&dmamux1 111 0x400 0x1>,
-			       <&dmamux1 112 0x400 0x1>;
-			dma-names = "ch1", "up";
-			status = "disabled";
+			i2c3: i2c@40014000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40014000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C3_K>;
+				resets = <&rcc I2C3_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x4>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 36>;
+				status = "disabled";
+			};
 
-			pwm {
-				compatible = "st,stm32-pwm";
-				#pwm-cells = <3>;
+			i2c5: i2c@40015000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x40015000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C5_K>;
+				resets = <&rcc I2C5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x10>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 37>;
 				status = "disabled";
 			};
 
-			timer@16 {
-				compatible = "st,stm32h7-timer-trigger";
-				reg = <16>;
+			cec: cec@40016000 {
+				compatible = "st,stm32-cec";
+				reg = <0x40016000 0x400>;
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc CEC_K>, <&rcc CEC>;
+				clock-names = "cec", "hdmi-cec";
+				feature-domains = <&etzpc 38>;
 				status = "disabled";
 			};
-		};
 
-		spi5: spi@44009000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x44009000 0x400>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI5_K>;
-			resets = <&rcc SPI5_R>;
-			dmas = <&dmamux1 85 0x400 0x05>,
-			       <&dmamux1 86 0x400 0x05>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
+			dac: dac@40017000 {
+				compatible = "st,stm32h7-dac-core";
+				reg = <0x40017000 0x400>;
+				clocks = <&rcc DAC12>;
+				clock-names = "pclk";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 39>;
+				status = "disabled";
 
-		sai1: sai@4400a000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400a000 0x400>;
-			reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
-			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI1_R>;
-			status = "disabled";
+				dac1: dac@1 {
+					compatible = "st,stm32-dac";
+					#io-channel-cells = <1>;
+					reg = <1>;
+					status = "disabled";
+				};
 
-			sai1a: audio-controller@4400a004 {
-				#sound-dai-cells = <0>;
+				dac2: dac@2 {
+					compatible = "st,stm32-dac";
+					#io-channel-cells = <1>;
+					reg = <2>;
+					status = "disabled";
+				};
+			};
 
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x4 0x20>;
-				clocks = <&rcc SAI1_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 87 0x400 0x01>;
+			uart7: serial@40018000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40018000 0x400>;
+				interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART7_K>;
+				wakeup-source;
+				dmas = <&dmamux1 79 0x400 0x15>,
+				       <&dmamux1 80 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 40>;
 				status = "disabled";
 			};
 
-			sai1b: audio-controller@4400a024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI1_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 88 0x400 0x01>;
+			uart8: serial@40019000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x40019000 0x400>;
+				interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc UART8_K>;
+				wakeup-source;
+				dmas = <&dmamux1 81 0x400 0x15>,
+				       <&dmamux1 82 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 41>;
 				status = "disabled";
 			};
-		};
 
-		sai2: sai@4400b000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400b000 0x400>;
-			reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
-			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI2_R>;
-			status = "disabled";
+			timers1: timer@44000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44000000 0x400>;
+				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "brk", "up", "trg-com", "cc";
+				clocks = <&rcc TIM1_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 11 0x400 0x1>,
+				       <&dmamux1 12 0x400 0x1>,
+				       <&dmamux1 13 0x400 0x1>,
+				       <&dmamux1 14 0x400 0x1>,
+				       <&dmamux1 15 0x400 0x1>,
+				       <&dmamux1 16 0x400 0x1>,
+				       <&dmamux1 17 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4",
+					    "up", "trig", "com";
+				feature-domains = <&etzpc 48>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			sai2a: audio-controller@4400b004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x4 0x20>;
-				clocks = <&rcc SAI2_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 89 0x400 0x01>;
-				status = "disabled";
-			};
+				timer@0 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <0>;
+					status = "disabled";
+				};
 
-			sai2b: audio-controller@4400b024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI2_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 90 0x400 0x01>;
-				status = "disabled";
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
 			};
-		};
 
-		sai3: sai@4400c000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x4400c000 0x400>;
-			reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
-			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI3_R>;
-			status = "disabled";
+			timers8: timer@44001000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44001000 0x400>;
+				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "brk", "up", "trg-com", "cc";
+				clocks = <&rcc TIM8_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 47 0x400 0x1>,
+				       <&dmamux1 48 0x400 0x1>,
+				       <&dmamux1 49 0x400 0x1>,
+				       <&dmamux1 50 0x400 0x1>,
+				       <&dmamux1 51 0x400 0x1>,
+				       <&dmamux1 52 0x400 0x1>,
+				       <&dmamux1 53 0x400 0x1>;
+				dma-names = "ch1", "ch2", "ch3", "ch4",
+					    "up", "trig", "com";
+				feature-domains = <&etzpc 49>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			sai3a: audio-controller@4400c004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x04 0x20>;
-				clocks = <&rcc SAI3_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 113 0x400 0x01>;
+				timer@7 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <7>;
+					status = "disabled";
+				};
+
+				counter {
+					compatible = "st,stm32-timer-counter";
+					status = "disabled";
+				};
+			};
+
+			usart6: serial@44003000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x44003000 0x400>;
+				interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART6_K>;
+				wakeup-source;
+				dmas = <&dmamux1 71 0x400 0x15>,
+				<&dmamux1 72 0x400 0x11>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 51>;
 				status = "disabled";
 			};
 
-			sai3b: audio-controller@4400c024 {
+			i2s1: audio-controller@44004000 {
+				compatible = "st,stm32h7-i2s";
 				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI3_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 114 0x400 0x01>;
+				reg = <0x44004000 0x400>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&dmamux1 37 0x400 0x01>,
+				<&dmamux1 38 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 52>;
 				status = "disabled";
 			};
-		};
-
-		dfsdm: dfsdm@4400d000 {
-			compatible = "st,stm32mp1-dfsdm";
-			reg = <0x4400d000 0x800>;
-			clocks = <&rcc DFSDM_K>;
-			clock-names = "dfsdm";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
 
-			dfsdm0: filter@0 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <0>;
-				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 101 0x400 0x01>;
-				dma-names = "rx";
+			spi1: spi@44004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44004000 0x400>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI1_K>;
+				resets = <&rcc SPI1_R>;
+				dmas = <&dmamux1 37 0x400 0x05>,
+				<&dmamux1 38 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 52>;
 				status = "disabled";
 			};
 
-			dfsdm1: filter@1 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <1>;
-				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 102 0x400 0x01>;
-				dma-names = "rx";
+			spi4: spi@44005000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44005000 0x400>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI4_K>;
+				resets = <&rcc SPI4_R>;
+				dmas = <&dmamux1 83 0x400 0x05>,
+				<&dmamux1 84 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 53>;
 				status = "disabled";
 			};
 
-			dfsdm2: filter@2 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <2>;
-				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 103 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers15: timer@44006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44006000 0x400>;
+				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM15_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 105 0x400 0x1>,
+				       <&dmamux1 106 0x400 0x1>,
+				       <&dmamux1 107 0x400 0x1>,
+				       <&dmamux1 108 0x400 0x1>;
+				dma-names = "ch1", "up", "trig", "com";
+				feature-domains = <&etzpc 54>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+
+				timer@14 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <14>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm3: filter@3 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <3>;
-				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 104 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers16: timer@44007000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44007000 0x400>;
+				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM16_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 109 0x400 0x1>,
+				<&dmamux1 110 0x400 0x1>;
+				dma-names = "ch1", "up";
+				feature-domains = <&etzpc 55>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+				timer@15 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <15>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm4: filter@4 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <4>;
-				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 91 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			timers17: timer@44008000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-timers";
+				reg = <0x44008000 0x400>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "global";
+				clocks = <&rcc TIM17_K>;
+				clock-names = "int";
+				dmas = <&dmamux1 111 0x400 0x1>,
+				<&dmamux1 112 0x400 0x1>;
+				dma-names = "ch1", "up";
+				feature-domains = <&etzpc 56>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
+
+				timer@16 {
+					compatible = "st,stm32h7-timer-trigger";
+					reg = <16>;
+					status = "disabled";
+				};
 			};
 
-			dfsdm5: filter@5 {
-				compatible = "st,stm32-dfsdm-adc";
-				#io-channel-cells = <1>;
-				reg = <5>;
-				interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&dmamux1 92 0x400 0x01>;
-				dma-names = "rx";
+			spi5: spi@44009000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32h7-spi";
+				reg = <0x44009000 0x400>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI5_K>;
+				resets = <&rcc SPI5_R>;
+				dmas = <&dmamux1 85 0x400 0x05>,
+				<&dmamux1 86 0x400 0x05>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 57>;
 				status = "disabled";
 			};
-		};
 
-		dma1: dma-controller@48000000 {
-			compatible = "st,stm32-dma";
-			reg = <0x48000000 0x400>;
-			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc DMA1>;
-			resets = <&rcc DMA1_R>;
-			#dma-cells = <4>;
-			st,mem2mem;
-			dma-requests = <8>;
-		};
+			sai1: sai@4400a000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400a000 0x400>;
+				reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI1_R>;
+				feature-domains = <&etzpc 58>;
+				status = "disabled";
+
+				sai1a: audio-controller@4400a004 {
+					#sound-dai-cells = <0>;
+
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					clocks = <&rcc SAI1_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 87 0x400 0x01>;
+					status = "disabled";
+				};
 
-		dma2: dma-controller@48001000 {
-			compatible = "st,stm32-dma";
-			reg = <0x48001000 0x400>;
-			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc DMA2>;
-			resets = <&rcc DMA2_R>;
-			#dma-cells = <4>;
-			st,mem2mem;
-			dma-requests = <8>;
-		};
+				sai1b: audio-controller@4400a024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI1_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 88 0x400 0x01>;
+					status = "disabled";
+				};
+			};
 
-		dmamux1: dma-router@48002000 {
-			compatible = "st,stm32h7-dmamux";
-			reg = <0x48002000 0x40>;
-			#dma-cells = <3>;
-			dma-requests = <128>;
-			dma-masters = <&dma1 &dma2>;
-			dma-channels = <16>;
-			clocks = <&rcc DMAMUX>;
-			resets = <&rcc DMAMUX_R>;
-		};
+			sai2: sai@4400b000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400b000 0x400>;
+				reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
+				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI2_R>;
+				feature-domains = <&etzpc 59>;
+				status = "disabled";
+
+				sai2a: audio-controller@4400b004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x4 0x20>;
+					clocks = <&rcc SAI2_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 89 0x400 0x01>;
+					status = "disabled";
+				};
 
-		adc: adc@48003000 {
-			compatible = "st,stm32mp1-adc-core";
-			reg = <0x48003000 0x400>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC12>, <&rcc ADC12_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			st,syscfg = <&syscfg>;
-			#interrupt-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
+				sai2b: audio-controller@4400b024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI2_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 90 0x400 0x01>;
+					status = "disabled";
+				};
+			};
 
-			adc1: adc@0 {
-				compatible = "st,stm32mp1-adc";
-				#io-channel-cells = <1>;
-				reg = <0x0>;
-				interrupt-parent = <&adc>;
-				interrupts = <0>;
-				dmas = <&dmamux1 9 0x400 0x01>;
-				dma-names = "rx";
-				status = "disabled";
+			sai3: sai@4400c000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x4400c000 0x400>;
+				reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI3_R>;
+				feature-domains = <&etzpc 60>;
+				status = "disabled";
+
+				sai3a: audio-controller@4400c004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x04 0x20>;
+					clocks = <&rcc SAI3_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 113 0x400 0x01>;
+					status = "disabled";
+				};
+
+				sai3b: audio-controller@4400c024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI3_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 114 0x400 0x01>;
+					status = "disabled";
+				};
 			};
 
-			adc2: adc@100 {
-				compatible = "st,stm32mp1-adc";
-				#io-channel-cells = <1>;
-				reg = <0x100>;
-				interrupt-parent = <&adc>;
-				interrupts = <1>;
-				dmas = <&dmamux1 10 0x400 0x01>;
-				dma-names = "rx";
+			dfsdm: dfsdm@4400d000 {
+				compatible = "st,stm32mp1-dfsdm";
+				reg = <0x4400d000 0x800>;
+				clocks = <&rcc DFSDM_K>;
+				clock-names = "dfsdm";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 61>;
 				status = "disabled";
-			};
-		};
 
-		sdmmc3: mmc@48004000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x48004000 0x400>;
-			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC3_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC3_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
+				dfsdm0: filter@0 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <0>;
+					interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 101 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		usbotg_hs: usb-otg@49000000 {
-			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-			reg = <0x49000000 0x10000>;
-			clocks = <&rcc USBO_K>;
-			clock-names = "otg";
-			resets = <&rcc USBO_R>;
-			reset-names = "dwc2";
-			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-			g-rx-fifo-size = <512>;
-			g-np-tx-fifo-size = <32>;
-			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-			dr_mode = "otg";
-			otg-rev = <0x200>;
-			usb33d-supply = <&usb33>;
-			status = "disabled";
-		};
+				dfsdm1: filter@1 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <1>;
+					interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 102 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		ipcc: mailbox@4c001000 {
-			compatible = "st,stm32mp1-ipcc";
-			#mbox-cells = <1>;
-			reg = <0x4c001000 0x400>;
-			st,proc-id = <0>;
-			interrupts-extended =
-				<&exti 61 1>,
-				<&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "rx", "tx";
-			clocks = <&rcc IPCC>;
-			wakeup-source;
-			status = "disabled";
-		};
-
-		dcmi: dcmi@4c006000 {
-			compatible = "st,stm32-dcmi";
-			reg = <0x4c006000 0x400>;
-			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc CAMITF_R>;
-			clocks = <&rcc DCMI>;
-			clock-names = "mclk";
-			dmas = <&dmamux1 75 0x400 0x01>;
-			dma-names = "tx";
-			status = "disabled";
-		};
+				dfsdm2: filter@2 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <2>;
+					interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 103 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		rcc: rcc@50000000 {
-			compatible = "st,stm32mp1-rcc", "syscon";
-			reg = <0x50000000 0x1000>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
+				dfsdm3: filter@3 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <3>;
+					interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 104 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-		pwr_regulators: pwr@50001000 {
-			compatible = "st,stm32mp1,pwr-reg";
-			reg = <0x50001000 0x10>;
+				dfsdm4: filter@4 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <4>;
+					interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 91 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-			reg11: reg11 {
-				regulator-name = "reg11";
-				regulator-min-microvolt = <1100000>;
-				regulator-max-microvolt = <1100000>;
+				dfsdm5: filter@5 {
+					compatible = "st,stm32-dfsdm-adc";
+					#io-channel-cells = <1>;
+					reg = <5>;
+					interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&dmamux1 92 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 			};
 
-			reg18: reg18 {
-				regulator-name = "reg18";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-			};
+			dma1: dma-controller@48000000 {
+				compatible = "st,stm32-dma";
+				reg = <0x48000000 0x400>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc DMA1>;
+				resets = <&rcc DMA1_R>;
+				#dma-cells = <4>;
+				st,mem2mem;
+				dma-requests = <8>;
+				feature-domains = <&etzpc 88>;
+			};
+
+			dma2: dma-controller@48001000 {
+				compatible = "st,stm32-dma";
+				reg = <0x48001000 0x400>;
+				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc DMA2>;
+				resets = <&rcc DMA2_R>;
+				#dma-cells = <4>;
+				st,mem2mem;
+				dma-requests = <8>;
+				feature-domains = <&etzpc 89>;
+			};
+
+			dmamux1: dma-router@48002000 {
+				compatible = "st,stm32h7-dmamux";
+				reg = <0x48002000 0x40>;
+				#dma-cells = <3>;
+				dma-requests = <128>;
+				dma-masters = <&dma1 &dma2>;
+				dma-channels = <16>;
+				clocks = <&rcc DMAMUX>;
+				resets = <&rcc DMAMUX_R>;
+				feature-domains = <&etzpc 90>;
+			};
+
+			adc: adc@48003000 {
+				compatible = "st,stm32mp1-adc-core";
+				reg = <0x48003000 0x400>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+				clock-names = "bus", "adc";
+				interrupt-controller;
+				st,syscfg = <&syscfg>;
+				#interrupt-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 72>;
+				status = "disabled";
+
+				adc1: adc@0 {
+					compatible = "st,stm32mp1-adc";
+					#io-channel-cells = <1>;
+					reg = <0x0>;
+					interrupt-parent = <&adc>;
+					interrupts = <0>;
+					dmas = <&dmamux1 9 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 
-			usb33: usb33 {
-				regulator-name = "usb33";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
+				adc2: adc@100 {
+					compatible = "st,stm32mp1-adc";
+					#io-channel-cells = <1>;
+					reg = <0x100>;
+					interrupt-parent = <&adc>;
+					interrupts = <1>;
+					dmas = <&dmamux1 10 0x400 0x01>;
+					dma-names = "rx";
+					status = "disabled";
+				};
 			};
-		};
 
-		pwr_mcu: pwr_mcu@50001014 {
-			compatible = "st,stm32mp151-pwr-mcu", "syscon";
-			reg = <0x50001014 0x4>;
-		};
+			sdmmc3: mmc@48004000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x00253180>;
+				reg = <0x48004000 0x400>;
+				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC3_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC3_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <120000000>;
+				feature-domains = <&etzpc 86>;
+				status = "disabled";
+			};
+
+			usbotg_hs: usb-otg@49000000 {
+				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+				reg = <0x49000000 0x10000>;
+				clocks = <&rcc USBO_K>;
+				clock-names = "otg";
+				resets = <&rcc USBO_R>;
+				reset-names = "dwc2";
+				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+				g-rx-fifo-size = <512>;
+				g-np-tx-fifo-size = <32>;
+				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+				dr_mode = "otg";
+				otg-rev = <0x200>;
+				usb33d-supply = <&usb33>;
+				feature-domains = <&etzpc 85>;
+				status = "disabled";
+			};
+
+			dcmi: dcmi@4c006000 {
+				compatible = "st,stm32-dcmi";
+				reg = <0x4c006000 0x400>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc CAMITF_R>;
+				clocks = <&rcc DCMI>;
+				clock-names = "mclk";
+				dmas = <&dmamux1 75 0x400 0x01>;
+				dma-names = "tx";
+				feature-domains = <&etzpc 70>;
+				status = "disabled";
+			};
+
+			lptimer2: timer@50021000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x50021000 0x400>;
+				interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM2_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 64>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-		exti: interrupt-controller@5000d000 {
-			compatible = "st,stm32mp1-exti", "syscon";
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			reg = <0x5000d000 0x400>;
-		};
+				trigger@1 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <1>;
+					status = "disabled";
+				};
 
-		syscfg: syscon@50020000 {
-			compatible = "st,stm32mp157-syscfg", "syscon";
-			reg = <0x50020000 0x400>;
-			clocks = <&rcc SYSCFG>;
-		};
+				counter {
+					compatible = "st,stm32-lptimer-counter";
+					status = "disabled";
+				};
+			};
 
-		lptimer2: timer@50021000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x50021000 0x400>;
-			interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM2_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
+			lptimer3: timer@50022000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "st,stm32-lptimer";
+				reg = <0x50022000 0x400>;
+				interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM3_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 65>;
+				status = "disabled";
+
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
+				trigger@2 {
+					compatible = "st,stm32-lptimer-trigger";
+					reg = <2>;
+					status = "disabled";
+				};
 			};
 
-			trigger@1 {
-				compatible = "st,stm32-lptimer-trigger";
-				reg = <1>;
+			lptimer4: timer@50023000 {
+				compatible = "st,stm32-lptimer";
+				reg = <0x50023000 0x400>;
+				interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM4_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 66>;
 				status = "disabled";
-			};
 
-			counter {
-				compatible = "st,stm32-lptimer-counter";
-				status = "disabled";
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 			};
-		};
-
-		lptimer3: timer@50022000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32-lptimer";
-			reg = <0x50022000 0x400>;
-			interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM3_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
+			lptimer5: timer@50024000 {
+				compatible = "st,stm32-lptimer";
+				reg = <0x50024000 0x400>;
+				interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc LPTIM5_K>;
+				clock-names = "mux";
+				wakeup-source;
+				feature-domains = <&etzpc 67>;
 				status = "disabled";
-			};
 
-			trigger@2 {
-				compatible = "st,stm32-lptimer-trigger";
-				reg = <2>;
-				status = "disabled";
+				pwm {
+					compatible = "st,stm32-pwm-lp";
+					#pwm-cells = <3>;
+					status = "disabled";
+				};
 			};
-		};
 
-		lptimer4: timer@50023000 {
-			compatible = "st,stm32-lptimer";
-			reg = <0x50023000 0x400>;
-			interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM4_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
-
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
+			vrefbuf: vrefbuf@50025000 {
+				compatible = "st,stm32-vrefbuf";
+				reg = <0x50025000 0x8>;
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <2500000>;
+				clocks = <&rcc VREF>;
+				feature-domains = <&etzpc 69>;
 				status = "disabled";
 			};
-		};
 
-		lptimer5: timer@50024000 {
-			compatible = "st,stm32-lptimer";
-			reg = <0x50024000 0x400>;
-			interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LPTIM5_K>;
-			clock-names = "mux";
-			wakeup-source;
-			status = "disabled";
+			sai4: sai@50027000 {
+				compatible = "st,stm32h7-sai";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x50027000 0x400>;
+				reg = <0x50027000 0x4>, <0x500273f0 0x10>;
+				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&rcc SAI4_R>;
+				feature-domains = <&etzpc 68>;
+				status = "disabled";
+
+				sai4a: audio-controller@50027004 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-a";
+					reg = <0x04 0x20>;
+					clocks = <&rcc SAI4_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 99 0x400 0x01>;
+					status = "disabled";
+				};
 
-			pwm {
-				compatible = "st,stm32-pwm-lp";
-				#pwm-cells = <3>;
-				status = "disabled";
+				sai4b: audio-controller@50027024 {
+					#sound-dai-cells = <0>;
+					compatible = "st,stm32-sai-sub-b";
+					reg = <0x24 0x20>;
+					clocks = <&rcc SAI4_K>;
+					clock-names = "sai_ck";
+					dmas = <&dmamux1 100 0x400 0x01>;
+					status = "disabled";
+				};
 			};
-		};
 
-		vrefbuf: vrefbuf@50025000 {
-			compatible = "st,stm32-vrefbuf";
-			reg = <0x50025000 0x8>;
-			regulator-min-microvolt = <1500000>;
-			regulator-max-microvolt = <2500000>;
-			clocks = <&rcc VREF>;
-			status = "disabled";
-		};
-
-		sai4: sai@50027000 {
-			compatible = "st,stm32h7-sai";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 0x50027000 0x400>;
-			reg = <0x50027000 0x4>, <0x500273f0 0x10>;
-			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rcc SAI4_R>;
-			status = "disabled";
+			hash1: hash@54002000 {
+				compatible = "st,stm32f756-hash";
+				reg = <0x54002000 0x400>;
+				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc HASH1>;
+				resets = <&rcc HASH1_R>;
+				dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
+				dma-names = "in";
+				dma-maxburst = <2>;
+				feature-domains = <&etzpc 8>;
+				status = "disabled";
+			};
+
+			rng1: rng@54003000 {
+				compatible = "st,stm32-rng";
+				reg = <0x54003000 0x400>;
+				clocks = <&rcc RNG1_K>;
+				resets = <&rcc RNG1_R>;
+				feature-domains = <&etzpc 7>;
+				status = "disabled";
+			};
+
+			fmc: memory-controller@58002000 {
+				#address-cells = <2>;
+				#size-cells = <1>;
+				compatible = "st,stm32mp1-fmc2-ebi";
+				reg = <0x58002000 0x1000>;
+				clocks = <&rcc FMC_K>;
+				resets = <&rcc FMC_R>;
+				feature-domains = <&etzpc 91>;
+				status = "disabled";
+
+				ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
+					 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
+					 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
+					 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
+					 <4 0 0x80000000 0x10000000>; /* NAND */
+
+				nand-controller@4,0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "st,stm32mp1-fmc2-nfc";
+					reg = <4 0x00000000 0x1000>,
+					      <4 0x08010000 0x1000>,
+					      <4 0x08020000 0x1000>,
+					      <4 0x01000000 0x1000>,
+					      <4 0x09010000 0x1000>,
+					      <4 0x09020000 0x1000>;
+					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+					dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
+					       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
+					       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
+					dma-names = "tx", "rx", "ecc";
+					status = "disabled";
+				};
+			};
 
-			sai4a: audio-controller@50027004 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-a";
-				reg = <0x04 0x20>;
-				clocks = <&rcc SAI4_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 99 0x400 0x01>;
-				status = "disabled";
+			qspi: spi@58003000 {
+				compatible = "st,stm32f469-qspi";
+				reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
+				reg-names = "qspi", "qspi_mm";
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+				dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
+				       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
+				dma-names = "tx", "rx";
+				clocks = <&rcc QSPI_K>;
+				resets = <&rcc QSPI_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 92>;
+				status = "disabled";
+			};
+
+			ethernet0: ethernet@5800a000 {
+				compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
+				reg = <0x5800a000 0x2000>;
+				reg-names = "stmmaceth";
+				interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "macirq";
+				clock-names = "stmmaceth",
+					      "mac-clk-tx",
+					      "mac-clk-rx",
+					      "eth-ck",
+					      "ptp_ref",
+					      "ethstp";
+				clocks = <&rcc ETHMAC>,
+					 <&rcc ETHTX>,
+					 <&rcc ETHRX>,
+					 <&rcc ETHCK_K>,
+					 <&rcc ETHPTP_K>,
+					 <&rcc ETHSTP>;
+				st,syscon = <&syscfg 0x4>;
+				snps,mixed-burst;
+				snps,pbl = <2>;
+				snps,en-tx-lpi-clockgating;
+				snps,axi-config = <&stmmac_axi_config_0>;
+				snps,tso;
+				feature-domains = <&etzpc 94>;
+				status = "disabled";
+
+				stmmac_axi_config_0: stmmac-axi-config {
+					snps,wr_osr_lmt = <0x7>;
+					snps,rd_osr_lmt = <0x7>;
+					snps,blen = <0 0 0 0 16 8 4>;
+				};
 			};
 
-			sai4b: audio-controller@50027024 {
-				#sound-dai-cells = <0>;
-				compatible = "st,stm32-sai-sub-b";
-				reg = <0x24 0x20>;
-				clocks = <&rcc SAI4_K>;
-				clock-names = "sai_ck";
-				dmas = <&dmamux1 100 0x400 0x01>;
+			usart1: serial@5c000000 {
+				compatible = "st,stm32h7-uart";
+				reg = <0x5c000000 0x400>;
+				interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc USART1_K>;
+				wakeup-source;
+				feature-domains = <&etzpc 3>;
 				status = "disabled";
 			};
-		};
 
-		dts: thermal@50028000 {
-			compatible = "st,stm32-thermal";
-			reg = <0x50028000 0x100>;
-			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc TMPSENS>;
-			clock-names = "pclk";
-			#thermal-sensor-cells = <0>;
-			status = "disabled";
-		};
-
-		hash1: hash@54002000 {
-			compatible = "st,stm32f756-hash";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc HASH1>;
-			resets = <&rcc HASH1_R>;
-			dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
-			dma-names = "in";
-			dma-maxburst = <2>;
-			status = "disabled";
-		};
-
-		rng1: rng@54003000 {
-			compatible = "st,stm32-rng";
-			reg = <0x54003000 0x400>;
-			clocks = <&rcc RNG1_K>;
-			resets = <&rcc RNG1_R>;
-			status = "disabled";
-		};
-
-		mdma1: dma-controller@58000000 {
-			compatible = "st,stm32h7-mdma";
-			reg = <0x58000000 0x1000>;
-			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc MDMA>;
-			resets = <&rcc MDMA_R>;
-			#dma-cells = <5>;
-			dma-channels = <32>;
-			dma-requests = <48>;
-		};
-
-		fmc: memory-controller@58002000 {
-			#address-cells = <2>;
-			#size-cells = <1>;
-			compatible = "st,stm32mp1-fmc2-ebi";
-			reg = <0x58002000 0x1000>;
-			clocks = <&rcc FMC_K>;
-			resets = <&rcc FMC_R>;
-			status = "disabled";
-
-			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
-				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
-				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
-				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
-				 <4 0 0x80000000 0x10000000>; /* NAND */
-
-			nand-controller@4,0 {
+			spi6: spi@5c001000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
-				compatible = "st,stm32mp1-fmc2-nfc";
-				reg = <4 0x00000000 0x1000>,
-				      <4 0x08010000 0x1000>,
-				      <4 0x08020000 0x1000>,
-				      <4 0x01000000 0x1000>,
-				      <4 0x09010000 0x1000>,
-				      <4 0x09020000 0x1000>;
-				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-				dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
-				       <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
-				       <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
-				dma-names = "tx", "rx", "ecc";
+				compatible = "st,stm32h7-spi";
+				reg = <0x5c001000 0x400>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI6_K>;
+				resets = <&rcc SPI6_R>;
+				dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
+				       <&mdma1 35 0x0 0x40002 0x0 0x0>;
+				feature-domains = <&etzpc 4>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			i2c4: i2c@5c002000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x5c002000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C4_K>;
+				resets = <&rcc I2C4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x8>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 5>;
 				status = "disabled";
 			};
-		};
-
-		qspi: spi@58003000 {
-			compatible = "st,stm32f469-qspi";
-			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
-			reg-names = "qspi", "qspi_mm";
-			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
-			dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
-			       <&mdma1 22 0x2 0x10100008 0x0 0x0>;
-			dma-names = "tx", "rx";
-			clocks = <&rcc QSPI_K>;
-			resets = <&rcc QSPI_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-		};
-
-		sdmmc1: mmc@58005000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x58005000 0x1000>;
-			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC1_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC1_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
-
-		sdmmc2: mmc@58007000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x00253180>;
-			reg = <0x58007000 0x1000>;
-			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC2_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC2_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <120000000>;
-			status = "disabled";
-		};
-
-		crc1: crc@58009000 {
-			compatible = "st,stm32f7-crc";
-			reg = <0x58009000 0x400>;
-			clocks = <&rcc CRC1>;
-			status = "disabled";
-		};
-
-		ethernet0: ethernet@5800a000 {
-			compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
-			reg = <0x5800a000 0x2000>;
-			reg-names = "stmmaceth";
-			interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "macirq";
-			clock-names = "stmmaceth",
-				      "mac-clk-tx",
-				      "mac-clk-rx",
-				      "eth-ck",
-				      "ptp_ref",
-				      "ethstp";
-			clocks = <&rcc ETHMAC>,
-				 <&rcc ETHTX>,
-				 <&rcc ETHRX>,
-				 <&rcc ETHCK_K>,
-				 <&rcc ETHPTP_K>,
-				 <&rcc ETHSTP>;
-			st,syscon = <&syscfg 0x4>;
-			snps,mixed-burst;
-			snps,pbl = <2>;
-			snps,en-tx-lpi-clockgating;
-			snps,axi-config = <&stmmac_axi_config_0>;
-			snps,tso;
-			status = "disabled";
-
-			stmmac_axi_config_0: stmmac-axi-config {
-				snps,wr_osr_lmt = <0x7>;
-				snps,rd_osr_lmt = <0x7>;
-				snps,blen = <0 0 0 0 16 8 4>;
-			};
-		};
 
-		usbh_ohci: usb@5800c000 {
-			compatible = "generic-ohci";
-			reg = <0x5800c000 0x1000>;
-			clocks = <&usbphyc>, <&rcc USBH>;
-			resets = <&rcc USBH_R>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		usbh_ehci: usb@5800d000 {
-			compatible = "generic-ehci";
-			reg = <0x5800d000 0x1000>;
-			clocks = <&usbphyc>, <&rcc USBH>;
-			resets = <&rcc USBH_R>;
-			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-			companion = <&usbh_ohci>;
-			status = "disabled";
-		};
-
-		ltdc: display-controller@5a001000 {
-			compatible = "st,stm32-ltdc";
-			reg = <0x5a001000 0x400>;
-			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc LTDC_PX>;
-			clock-names = "lcd";
-			resets = <&rcc LTDC_R>;
-			status = "disabled";
-
-			port {
+			i2c6: i2c@5c009000 {
+				compatible = "st,stm32mp15-i2c";
+				reg = <0x5c009000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C6_K>;
+				resets = <&rcc I2C6_R>;
 				#address-cells = <1>;
 				#size-cells = <0>;
+				st,syscfg-fmp = <&syscfg 0x4 0x20>;
+				wakeup-source;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 12>;
+				status = "disabled";
 			};
-		};
-
-		iwdg2: watchdog@5a002000 {
-			compatible = "st,stm32mp1-iwdg";
-			reg = <0x5a002000 0x400>;
-			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
-			clock-names = "pclk", "lsi";
-			status = "disabled";
-		};
-
-		usbphyc: usbphyc@5a006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#clock-cells = <0>;
-			compatible = "st,stm32mp1-usbphyc";
-			reg = <0x5a006000 0x1000>;
-			clocks = <&rcc USBPHY_K>;
-			resets = <&rcc USBPHY_R>;
-			vdda1v1-supply = <&reg11>;
-			vdda1v8-supply = <&reg18>;
-			status = "disabled";
-
-			usbphyc_port0: usb-phy@0 {
-				#phy-cells = <0>;
-				reg = <0>;
-			};
-
-			usbphyc_port1: usb-phy@1 {
-				#phy-cells = <1>;
-				reg = <1>;
-			};
-		};
-
-		usart1: serial@5c000000 {
-			compatible = "st,stm32h7-uart";
-			reg = <0x5c000000 0x400>;
-			interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc USART1_K>;
-			wakeup-source;
-			status = "disabled";
-		};
-
-		spi6: spi@5c001000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "st,stm32h7-spi";
-			reg = <0x5c001000 0x400>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI6_K>;
-			resets = <&rcc SPI6_R>;
-			dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
-			       <&mdma1 35 0x0 0x40002 0x0 0x0>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2c4: i2c@5c002000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x5c002000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C4_K>;
-			resets = <&rcc I2C4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x8>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		rtc: rtc@5c004000 {
-			compatible = "st,stm32mp1-rtc";
-			reg = <0x5c004000 0x400>;
-			clocks = <&rcc RTCAPB>, <&rcc RTC>;
-			clock-names = "pclk", "rtc_ck";
-			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
-			status = "disabled";
-		};
-
-		bsec: efuse@5c005000 {
-			compatible = "st,stm32mp15-bsec";
-			reg = <0x5c005000 0x400>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ts_cal1: calib@5c {
-				reg = <0x5c 0x2>;
-			};
-			ts_cal2: calib@5e {
-				reg = <0x5e 0x2>;
-			};
-		};
 
-		i2c6: i2c@5c009000 {
-			compatible = "st,stm32mp15-i2c";
-			reg = <0x5c009000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C6_K>;
-			resets = <&rcc I2C6_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			st,syscfg-fmp = <&syscfg 0x4 0x20>;
-			wakeup-source;
-			i2c-analog-filter;
-			status = "disabled";
 		};
 
 		tamp: tamp@5c00a000 {
diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi
index 486084e0b80b..82073dd85f18 100644
--- a/arch/arm/boot/dts/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/stm32mp153.dtsi
@@ -28,32 +28,34 @@ timer {
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+};
 
-	soc {
-		m_can1: can@4400e000 {
-			compatible = "bosch,m_can";
-			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
-			reg-names = "m_can", "message_ram";
-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "int0", "int1";
-			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-			clock-names = "hclk", "cclk";
-			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
-			status = "disabled";
-		};
+&etzpc {
+	m_can1: can@4400e000 {
+		compatible = "bosch,m_can";
+		reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
+		reg-names = "m_can", "message_ram";
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "int0", "int1";
+		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+		clock-names = "hclk", "cclk";
+		bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+		feature-domains = <&etzpc 62>;
+		status = "disabled";
+	};
 
-		m_can2: can@4400f000 {
-			compatible = "bosch,m_can";
-			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
-			reg-names = "m_can", "message_ram";
-			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "int0", "int1";
-			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
-			clock-names = "hclk", "cclk";
-			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
-			status = "disabled";
-		};
+	m_can2: can@4400f000 {
+		compatible = "bosch,m_can";
+		reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
+		reg-names = "m_can", "message_ram";
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "int0", "int1";
+		clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
+		clock-names = "hclk", "cclk";
+		bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+		feature-domains = <&etzpc 62>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/boot/dts/stm32mp15xc.dtsi b/arch/arm/boot/dts/stm32mp15xc.dtsi
index b06a55a2fa18..55524a8d3093 100644
--- a/arch/arm/boot/dts/stm32mp15xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp15xc.dtsi
@@ -4,15 +4,14 @@
  * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp1: cryp@54001000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54001000 0x400>;
-			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp1: cryp@54001000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54001000 0x400>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		feature-domains = <&etzpc 9>;
+		status = "disabled";
 	};
 };
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  2023-01-27 16:40 ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-27 16:40   ` Gatien Chevallier
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

The STM32 System Bus is an internal bus on which devices are connected.
ETZPC is a peripheral overseeing the firewall bus that configures
and control access to the peripherals connected on it.

For more information on which peripheral is securable, please read
the STM32MP13 reference manual.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

No changes in V2.

Changes in V3:
	-Use appriopriate node name: bus

 arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
 arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
 arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
 arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
 4 files changed, 258 insertions(+), 237 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
index accc3824f7e9..24462a647101 100644
--- a/arch/arm/boot/dts/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
 			dma-channels = <16>;
 		};
 
-		adc_2: adc@48004000 {
-			compatible = "st,stm32mp13-adc-core";
-			reg = <0x48004000 0x400>;
-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-
-			adc2: adc@0 {
-				compatible = "st,stm32mp13-adc";
-				#io-channel-cells = <1>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x0>;
-				interrupt-parent = <&adc_2>;
-				interrupts = <0>;
-				dmas = <&dmamux1 10 0x400 0x80000001>;
-				dma-names = "rx";
-				status = "disabled";
-
-				channel@13 {
-					reg = <13>;
-					label = "vrefint";
-				};
-				channel@14 {
-					reg = <14>;
-					label = "vddcore";
-				};
-				channel@16 {
-					reg = <16>;
-					label = "vddcpu";
-				};
-				channel@17 {
-					reg = <17>;
-					label = "vddq_ddr";
-				};
-			};
-		};
-
-		usbotg_hs: usb@49000000 {
-			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-			reg = <0x49000000 0x40000>;
-			clocks = <&rcc USBO_K>;
-			clock-names = "otg";
-			resets = <&rcc USBO_R>;
-			reset-names = "dwc2";
-			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-			g-rx-fifo-size = <512>;
-			g-np-tx-fifo-size = <32>;
-			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-			dr_mode = "otg";
-			otg-rev = <0x200>;
-			usb33d-supply = <&usb33>;
-			status = "disabled";
-		};
-
-		spi4: spi@4c002000 {
-			compatible = "st,stm32h7-spi";
-			reg = <0x4c002000 0x400>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI4_K>;
-			resets = <&rcc SPI4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 83 0x400 0x01>,
-			       <&dmamux1 84 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi5: spi@4c003000 {
-			compatible = "st,stm32h7-spi";
-			reg = <0x4c003000 0x400>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI5_K>;
-			resets = <&rcc SPI5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 85 0x400 0x01>,
-			       <&dmamux1 86 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2c3: i2c@4c004000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c004000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C3_K>;
-			resets = <&rcc I2C3_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 73 0x400 0x1>,
-			       <&dmamux1 74 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x4>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		i2c4: i2c@4c005000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c005000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C4_K>;
-			resets = <&rcc I2C4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 75 0x400 0x1>,
-			       <&dmamux1 76 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x8>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		i2c5: i2c@4c006000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c006000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C5_K>;
-			resets = <&rcc I2C5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 115 0x400 0x1>,
-			       <&dmamux1 116 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x10>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
 		rcc: rcc@50000000 {
 			compatible = "st,stm32mp13-rcc", "syscon";
 			reg = <0x50000000 0x1000>;
@@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
 			dma-requests = <48>;
 		};
 
-		sdmmc1: mmc@58005000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x20253180>;
-			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC1_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC1_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <130000000>;
-			status = "disabled";
-		};
-
-		sdmmc2: mmc@58007000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x20253180>;
-			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC2_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC2_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <130000000>;
-			status = "disabled";
-		};
-
 		usbh_ohci: usb@5800c000 {
 			compatible = "generic-ohci";
 			reg = <0x5800c000 0x1000>;
@@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
 			status = "disabled";
 		};
 
-		usbphyc: usbphyc@5a006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#clock-cells = <0>;
-			compatible = "st,stm32mp1-usbphyc";
-			reg = <0x5a006000 0x1000>;
-			clocks = <&rcc USBPHY_K>;
-			resets = <&rcc USBPHY_R>;
-			vdda1v1-supply = <&reg11>;
-			vdda1v8-supply = <&reg18>;
-			status = "disabled";
-
-			usbphyc_port0: usb-phy@0 {
-				#phy-cells = <0>;
-				reg = <0>;
-			};
-
-			usbphyc_port1: usb-phy@1 {
-				#phy-cells = <1>;
-				reg = <1>;
-			};
-		};
-
 		rtc: rtc@5c004000 {
 			compatible = "st,stm32mp1-rtc";
 			reg = <0x5c004000 0x400>;
@@ -536,6 +343,220 @@ ts_cal2: calib@5e {
 			};
 		};
 
+		etzpc: bus@5c007000 {
+			compatible = "st,stm32mp13-sys-bus";
+			reg = <0x5c007000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			feature-domain-controller;
+			#feature-domain-cells = <1>;
+			ranges;
+
+			adc_2: adc@48004000 {
+				compatible = "st,stm32mp13-adc-core";
+				reg = <0x48004000 0x400>;
+				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
+				clock-names = "bus", "adc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 33>;
+				status = "disabled";
+
+				adc2: adc@0 {
+					compatible = "st,stm32mp13-adc";
+					#io-channel-cells = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x0>;
+					interrupt-parent = <&adc_2>;
+					interrupts = <0>;
+					dmas = <&dmamux1 10 0x400 0x80000001>;
+					dma-names = "rx";
+					status = "disabled";
+
+					channel@13 {
+						reg = <13>;
+						label = "vrefint";
+					};
+					channel@14 {
+						reg = <14>;
+						label = "vddcore";
+					};
+					channel@16 {
+						reg = <16>;
+						label = "vddcpu";
+					};
+					channel@17 {
+						reg = <17>;
+						label = "vddq_ddr";
+					};
+				};
+			};
+
+			usbotg_hs: usb@49000000 {
+				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+				reg = <0x49000000 0x40000>;
+				clocks = <&rcc USBO_K>;
+				clock-names = "otg";
+				resets = <&rcc USBO_R>;
+				reset-names = "dwc2";
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				g-rx-fifo-size = <512>;
+				g-np-tx-fifo-size = <32>;
+				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+				dr_mode = "otg";
+				otg-rev = <0x200>;
+				usb33d-supply = <&usb33>;
+				feature-domains = <&etzpc 34>;
+				status = "disabled";
+			};
+
+			spi4: spi@4c002000 {
+				compatible = "st,stm32h7-spi";
+				reg = <0x4c002000 0x400>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI4_K>;
+				resets = <&rcc SPI4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 83 0x400 0x01>,
+				       <&dmamux1 84 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 18>;
+				status = "disabled";
+			};
+
+			spi5: spi@4c003000 {
+				compatible = "st,stm32h7-spi";
+				reg = <0x4c003000 0x400>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI5_K>;
+				resets = <&rcc SPI5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 85 0x400 0x01>,
+				       <&dmamux1 86 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 19>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@4c004000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c004000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C3_K>;
+				resets = <&rcc I2C3_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 73 0x400 0x1>,
+				       <&dmamux1 74 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x4>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 20>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@4c005000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c005000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C4_K>;
+				resets = <&rcc I2C4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 75 0x400 0x1>,
+				       <&dmamux1 76 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x8>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 21>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@4c006000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c006000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C5_K>;
+				resets = <&rcc I2C5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 115 0x400 0x1>,
+				       <&dmamux1 116 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x10>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 22>;
+				status = "disabled";
+			};
+
+			sdmmc1: mmc@58005000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x20253180>;
+				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC1_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC1_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <130000000>;
+				feature-domains = <&etzpc 50>;
+				status = "disabled";
+			};
+
+			sdmmc2: mmc@58007000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x20253180>;
+				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC2_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC2_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <130000000>;
+				feature-domains = <&etzpc 51>;
+				status = "disabled";
+			};
+
+			usbphyc: usbphyc@5a006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#clock-cells = <0>;
+				compatible = "st,stm32mp1-usbphyc";
+				reg = <0x5a006000 0x1000>;
+				clocks = <&rcc USBPHY_K>;
+				resets = <&rcc USBPHY_R>;
+				vdda1v1-supply = <&reg11>;
+				vdda1v8-supply = <&reg18>;
+				feature-domains = <&etzpc 5>;
+				status = "disabled";
+
+				usbphyc_port0: usb-phy@0 {
+					#phy-cells = <0>;
+					reg = <0>;
+				};
+
+				usbphyc_port1: usb-phy@1 {
+					#phy-cells = <1>;
+					reg = <1>;
+				};
+			};
+
+		};
+
 		/*
 		 * Break node order to solve dependency probe issue between
 		 * pinctrl and exti.
diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
index df451c3c2a26..be6061552683 100644
--- a/arch/arm/boot/dts/stm32mp133.dtsi
+++ b/arch/arm/boot/dts/stm32mp133.dtsi
@@ -33,35 +33,38 @@ m_can2: can@4400f000 {
 			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
 			status = "disabled";
 		};
+	};
+};
 
-		adc_1: adc@48003000 {
-			compatible = "st,stm32mp13-adc-core";
-			reg = <0x48003000 0x400>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
+&etzpc {
+	adc_1: adc@48003000 {
+		compatible = "st,stm32mp13-adc-core";
+		reg = <0x48003000 0x400>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
+		clock-names = "bus", "adc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		feature-domains = <&etzpc 32>;
+		status = "disabled";
+
+		adc1: adc@0 {
+			compatible = "st,stm32mp13-adc";
+			#io-channel-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			reg = <0x0>;
+			interrupt-parent = <&adc_1>;
+			interrupts = <0>;
+			dmas = <&dmamux1 9 0x400 0x80000001>;
+			dma-names = "rx";
 			status = "disabled";
 
-			adc1: adc@0 {
-				compatible = "st,stm32mp13-adc";
-				#io-channel-cells = <1>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x0>;
-				interrupt-parent = <&adc_1>;
-				interrupts = <0>;
-				dmas = <&dmamux1 9 0x400 0x80000001>;
-				dma-names = "rx";
-				status = "disabled";
-
-				channel@18 {
-					reg = <18>;
-					label = "vrefint";
-				};
+			channel@18 {
+				reg = <18>;
+				label = "vrefint";
 			};
 		};
 	};
diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
index 4d00e7592882..a1a7a40c2a3e 100644
--- a/arch/arm/boot/dts/stm32mp13xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
@@ -4,15 +4,14 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp: crypto@54002000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp: crypto@54002000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54002000 0x400>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		feature-domains = <&etzpc 42>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
index 4d00e7592882..b9fb071a1471 100644
--- a/arch/arm/boot/dts/stm32mp13xf.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
@@ -4,15 +4,13 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp: crypto@54002000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp: crypto@54002000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54002000 0x400>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		status = "disabled";
 	};
 };
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

The STM32 System Bus is an internal bus on which devices are connected.
ETZPC is a peripheral overseeing the firewall bus that configures
and control access to the peripherals connected on it.

For more information on which peripheral is securable, please read
the STM32MP13 reference manual.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

No changes in V2.

Changes in V3:
	-Use appriopriate node name: bus

 arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
 arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
 arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
 arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
 4 files changed, 258 insertions(+), 237 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
index accc3824f7e9..24462a647101 100644
--- a/arch/arm/boot/dts/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
 			dma-channels = <16>;
 		};
 
-		adc_2: adc@48004000 {
-			compatible = "st,stm32mp13-adc-core";
-			reg = <0x48004000 0x400>;
-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-
-			adc2: adc@0 {
-				compatible = "st,stm32mp13-adc";
-				#io-channel-cells = <1>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x0>;
-				interrupt-parent = <&adc_2>;
-				interrupts = <0>;
-				dmas = <&dmamux1 10 0x400 0x80000001>;
-				dma-names = "rx";
-				status = "disabled";
-
-				channel@13 {
-					reg = <13>;
-					label = "vrefint";
-				};
-				channel@14 {
-					reg = <14>;
-					label = "vddcore";
-				};
-				channel@16 {
-					reg = <16>;
-					label = "vddcpu";
-				};
-				channel@17 {
-					reg = <17>;
-					label = "vddq_ddr";
-				};
-			};
-		};
-
-		usbotg_hs: usb@49000000 {
-			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-			reg = <0x49000000 0x40000>;
-			clocks = <&rcc USBO_K>;
-			clock-names = "otg";
-			resets = <&rcc USBO_R>;
-			reset-names = "dwc2";
-			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-			g-rx-fifo-size = <512>;
-			g-np-tx-fifo-size = <32>;
-			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-			dr_mode = "otg";
-			otg-rev = <0x200>;
-			usb33d-supply = <&usb33>;
-			status = "disabled";
-		};
-
-		spi4: spi@4c002000 {
-			compatible = "st,stm32h7-spi";
-			reg = <0x4c002000 0x400>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI4_K>;
-			resets = <&rcc SPI4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 83 0x400 0x01>,
-			       <&dmamux1 84 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi5: spi@4c003000 {
-			compatible = "st,stm32h7-spi";
-			reg = <0x4c003000 0x400>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI5_K>;
-			resets = <&rcc SPI5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 85 0x400 0x01>,
-			       <&dmamux1 86 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2c3: i2c@4c004000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c004000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C3_K>;
-			resets = <&rcc I2C3_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 73 0x400 0x1>,
-			       <&dmamux1 74 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x4>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		i2c4: i2c@4c005000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c005000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C4_K>;
-			resets = <&rcc I2C4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 75 0x400 0x1>,
-			       <&dmamux1 76 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x8>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		i2c5: i2c@4c006000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c006000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C5_K>;
-			resets = <&rcc I2C5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 115 0x400 0x1>,
-			       <&dmamux1 116 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x10>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
 		rcc: rcc@50000000 {
 			compatible = "st,stm32mp13-rcc", "syscon";
 			reg = <0x50000000 0x1000>;
@@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
 			dma-requests = <48>;
 		};
 
-		sdmmc1: mmc@58005000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x20253180>;
-			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC1_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC1_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <130000000>;
-			status = "disabled";
-		};
-
-		sdmmc2: mmc@58007000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x20253180>;
-			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC2_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC2_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <130000000>;
-			status = "disabled";
-		};
-
 		usbh_ohci: usb@5800c000 {
 			compatible = "generic-ohci";
 			reg = <0x5800c000 0x1000>;
@@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
 			status = "disabled";
 		};
 
-		usbphyc: usbphyc@5a006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#clock-cells = <0>;
-			compatible = "st,stm32mp1-usbphyc";
-			reg = <0x5a006000 0x1000>;
-			clocks = <&rcc USBPHY_K>;
-			resets = <&rcc USBPHY_R>;
-			vdda1v1-supply = <&reg11>;
-			vdda1v8-supply = <&reg18>;
-			status = "disabled";
-
-			usbphyc_port0: usb-phy@0 {
-				#phy-cells = <0>;
-				reg = <0>;
-			};
-
-			usbphyc_port1: usb-phy@1 {
-				#phy-cells = <1>;
-				reg = <1>;
-			};
-		};
-
 		rtc: rtc@5c004000 {
 			compatible = "st,stm32mp1-rtc";
 			reg = <0x5c004000 0x400>;
@@ -536,6 +343,220 @@ ts_cal2: calib@5e {
 			};
 		};
 
+		etzpc: bus@5c007000 {
+			compatible = "st,stm32mp13-sys-bus";
+			reg = <0x5c007000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			feature-domain-controller;
+			#feature-domain-cells = <1>;
+			ranges;
+
+			adc_2: adc@48004000 {
+				compatible = "st,stm32mp13-adc-core";
+				reg = <0x48004000 0x400>;
+				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
+				clock-names = "bus", "adc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 33>;
+				status = "disabled";
+
+				adc2: adc@0 {
+					compatible = "st,stm32mp13-adc";
+					#io-channel-cells = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x0>;
+					interrupt-parent = <&adc_2>;
+					interrupts = <0>;
+					dmas = <&dmamux1 10 0x400 0x80000001>;
+					dma-names = "rx";
+					status = "disabled";
+
+					channel@13 {
+						reg = <13>;
+						label = "vrefint";
+					};
+					channel@14 {
+						reg = <14>;
+						label = "vddcore";
+					};
+					channel@16 {
+						reg = <16>;
+						label = "vddcpu";
+					};
+					channel@17 {
+						reg = <17>;
+						label = "vddq_ddr";
+					};
+				};
+			};
+
+			usbotg_hs: usb@49000000 {
+				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+				reg = <0x49000000 0x40000>;
+				clocks = <&rcc USBO_K>;
+				clock-names = "otg";
+				resets = <&rcc USBO_R>;
+				reset-names = "dwc2";
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				g-rx-fifo-size = <512>;
+				g-np-tx-fifo-size = <32>;
+				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+				dr_mode = "otg";
+				otg-rev = <0x200>;
+				usb33d-supply = <&usb33>;
+				feature-domains = <&etzpc 34>;
+				status = "disabled";
+			};
+
+			spi4: spi@4c002000 {
+				compatible = "st,stm32h7-spi";
+				reg = <0x4c002000 0x400>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI4_K>;
+				resets = <&rcc SPI4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 83 0x400 0x01>,
+				       <&dmamux1 84 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 18>;
+				status = "disabled";
+			};
+
+			spi5: spi@4c003000 {
+				compatible = "st,stm32h7-spi";
+				reg = <0x4c003000 0x400>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI5_K>;
+				resets = <&rcc SPI5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 85 0x400 0x01>,
+				       <&dmamux1 86 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 19>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@4c004000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c004000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C3_K>;
+				resets = <&rcc I2C3_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 73 0x400 0x1>,
+				       <&dmamux1 74 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x4>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 20>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@4c005000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c005000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C4_K>;
+				resets = <&rcc I2C4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 75 0x400 0x1>,
+				       <&dmamux1 76 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x8>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 21>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@4c006000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c006000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C5_K>;
+				resets = <&rcc I2C5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 115 0x400 0x1>,
+				       <&dmamux1 116 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x10>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 22>;
+				status = "disabled";
+			};
+
+			sdmmc1: mmc@58005000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x20253180>;
+				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC1_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC1_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <130000000>;
+				feature-domains = <&etzpc 50>;
+				status = "disabled";
+			};
+
+			sdmmc2: mmc@58007000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x20253180>;
+				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC2_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC2_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <130000000>;
+				feature-domains = <&etzpc 51>;
+				status = "disabled";
+			};
+
+			usbphyc: usbphyc@5a006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#clock-cells = <0>;
+				compatible = "st,stm32mp1-usbphyc";
+				reg = <0x5a006000 0x1000>;
+				clocks = <&rcc USBPHY_K>;
+				resets = <&rcc USBPHY_R>;
+				vdda1v1-supply = <&reg11>;
+				vdda1v8-supply = <&reg18>;
+				feature-domains = <&etzpc 5>;
+				status = "disabled";
+
+				usbphyc_port0: usb-phy@0 {
+					#phy-cells = <0>;
+					reg = <0>;
+				};
+
+				usbphyc_port1: usb-phy@1 {
+					#phy-cells = <1>;
+					reg = <1>;
+				};
+			};
+
+		};
+
 		/*
 		 * Break node order to solve dependency probe issue between
 		 * pinctrl and exti.
diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
index df451c3c2a26..be6061552683 100644
--- a/arch/arm/boot/dts/stm32mp133.dtsi
+++ b/arch/arm/boot/dts/stm32mp133.dtsi
@@ -33,35 +33,38 @@ m_can2: can@4400f000 {
 			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
 			status = "disabled";
 		};
+	};
+};
 
-		adc_1: adc@48003000 {
-			compatible = "st,stm32mp13-adc-core";
-			reg = <0x48003000 0x400>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
+&etzpc {
+	adc_1: adc@48003000 {
+		compatible = "st,stm32mp13-adc-core";
+		reg = <0x48003000 0x400>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
+		clock-names = "bus", "adc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		feature-domains = <&etzpc 32>;
+		status = "disabled";
+
+		adc1: adc@0 {
+			compatible = "st,stm32mp13-adc";
+			#io-channel-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			reg = <0x0>;
+			interrupt-parent = <&adc_1>;
+			interrupts = <0>;
+			dmas = <&dmamux1 9 0x400 0x80000001>;
+			dma-names = "rx";
 			status = "disabled";
 
-			adc1: adc@0 {
-				compatible = "st,stm32mp13-adc";
-				#io-channel-cells = <1>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x0>;
-				interrupt-parent = <&adc_1>;
-				interrupts = <0>;
-				dmas = <&dmamux1 9 0x400 0x80000001>;
-				dma-names = "rx";
-				status = "disabled";
-
-				channel@18 {
-					reg = <18>;
-					label = "vrefint";
-				};
+			channel@18 {
+				reg = <18>;
+				label = "vrefint";
 			};
 		};
 	};
diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
index 4d00e7592882..a1a7a40c2a3e 100644
--- a/arch/arm/boot/dts/stm32mp13xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
@@ -4,15 +4,14 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp: crypto@54002000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp: crypto@54002000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54002000 0x400>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		feature-domains = <&etzpc 42>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
index 4d00e7592882..b9fb071a1471 100644
--- a/arch/arm/boot/dts/stm32mp13xf.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
@@ -4,15 +4,13 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp: crypto@54002000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp: crypto@54002000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54002000 0x400>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		status = "disabled";
 	};
 };
-- 
2.35.3


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb, Gatien Chevallier

The STM32 System Bus is an internal bus on which devices are connected.
ETZPC is a peripheral overseeing the firewall bus that configures
and control access to the peripherals connected on it.

For more information on which peripheral is securable, please read
the STM32MP13 reference manual.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

No changes in V2.

Changes in V3:
	-Use appriopriate node name: bus

 arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
 arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
 arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
 arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
 4 files changed, 258 insertions(+), 237 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
index accc3824f7e9..24462a647101 100644
--- a/arch/arm/boot/dts/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
 			dma-channels = <16>;
 		};
 
-		adc_2: adc@48004000 {
-			compatible = "st,stm32mp13-adc-core";
-			reg = <0x48004000 0x400>;
-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-
-			adc2: adc@0 {
-				compatible = "st,stm32mp13-adc";
-				#io-channel-cells = <1>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x0>;
-				interrupt-parent = <&adc_2>;
-				interrupts = <0>;
-				dmas = <&dmamux1 10 0x400 0x80000001>;
-				dma-names = "rx";
-				status = "disabled";
-
-				channel@13 {
-					reg = <13>;
-					label = "vrefint";
-				};
-				channel@14 {
-					reg = <14>;
-					label = "vddcore";
-				};
-				channel@16 {
-					reg = <16>;
-					label = "vddcpu";
-				};
-				channel@17 {
-					reg = <17>;
-					label = "vddq_ddr";
-				};
-			};
-		};
-
-		usbotg_hs: usb@49000000 {
-			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-			reg = <0x49000000 0x40000>;
-			clocks = <&rcc USBO_K>;
-			clock-names = "otg";
-			resets = <&rcc USBO_R>;
-			reset-names = "dwc2";
-			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-			g-rx-fifo-size = <512>;
-			g-np-tx-fifo-size = <32>;
-			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-			dr_mode = "otg";
-			otg-rev = <0x200>;
-			usb33d-supply = <&usb33>;
-			status = "disabled";
-		};
-
-		spi4: spi@4c002000 {
-			compatible = "st,stm32h7-spi";
-			reg = <0x4c002000 0x400>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI4_K>;
-			resets = <&rcc SPI4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 83 0x400 0x01>,
-			       <&dmamux1 84 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi5: spi@4c003000 {
-			compatible = "st,stm32h7-spi";
-			reg = <0x4c003000 0x400>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI5_K>;
-			resets = <&rcc SPI5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 85 0x400 0x01>,
-			       <&dmamux1 86 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2c3: i2c@4c004000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c004000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C3_K>;
-			resets = <&rcc I2C3_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 73 0x400 0x1>,
-			       <&dmamux1 74 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x4>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		i2c4: i2c@4c005000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c005000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C4_K>;
-			resets = <&rcc I2C4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 75 0x400 0x1>,
-			       <&dmamux1 76 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x8>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		i2c5: i2c@4c006000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c006000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C5_K>;
-			resets = <&rcc I2C5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 115 0x400 0x1>,
-			       <&dmamux1 116 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x10>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
 		rcc: rcc@50000000 {
 			compatible = "st,stm32mp13-rcc", "syscon";
 			reg = <0x50000000 0x1000>;
@@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
 			dma-requests = <48>;
 		};
 
-		sdmmc1: mmc@58005000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x20253180>;
-			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC1_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC1_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <130000000>;
-			status = "disabled";
-		};
-
-		sdmmc2: mmc@58007000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x20253180>;
-			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC2_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC2_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <130000000>;
-			status = "disabled";
-		};
-
 		usbh_ohci: usb@5800c000 {
 			compatible = "generic-ohci";
 			reg = <0x5800c000 0x1000>;
@@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
 			status = "disabled";
 		};
 
-		usbphyc: usbphyc@5a006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#clock-cells = <0>;
-			compatible = "st,stm32mp1-usbphyc";
-			reg = <0x5a006000 0x1000>;
-			clocks = <&rcc USBPHY_K>;
-			resets = <&rcc USBPHY_R>;
-			vdda1v1-supply = <&reg11>;
-			vdda1v8-supply = <&reg18>;
-			status = "disabled";
-
-			usbphyc_port0: usb-phy@0 {
-				#phy-cells = <0>;
-				reg = <0>;
-			};
-
-			usbphyc_port1: usb-phy@1 {
-				#phy-cells = <1>;
-				reg = <1>;
-			};
-		};
-
 		rtc: rtc@5c004000 {
 			compatible = "st,stm32mp1-rtc";
 			reg = <0x5c004000 0x400>;
@@ -536,6 +343,220 @@ ts_cal2: calib@5e {
 			};
 		};
 
+		etzpc: bus@5c007000 {
+			compatible = "st,stm32mp13-sys-bus";
+			reg = <0x5c007000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			feature-domain-controller;
+			#feature-domain-cells = <1>;
+			ranges;
+
+			adc_2: adc@48004000 {
+				compatible = "st,stm32mp13-adc-core";
+				reg = <0x48004000 0x400>;
+				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
+				clock-names = "bus", "adc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 33>;
+				status = "disabled";
+
+				adc2: adc@0 {
+					compatible = "st,stm32mp13-adc";
+					#io-channel-cells = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x0>;
+					interrupt-parent = <&adc_2>;
+					interrupts = <0>;
+					dmas = <&dmamux1 10 0x400 0x80000001>;
+					dma-names = "rx";
+					status = "disabled";
+
+					channel@13 {
+						reg = <13>;
+						label = "vrefint";
+					};
+					channel@14 {
+						reg = <14>;
+						label = "vddcore";
+					};
+					channel@16 {
+						reg = <16>;
+						label = "vddcpu";
+					};
+					channel@17 {
+						reg = <17>;
+						label = "vddq_ddr";
+					};
+				};
+			};
+
+			usbotg_hs: usb@49000000 {
+				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+				reg = <0x49000000 0x40000>;
+				clocks = <&rcc USBO_K>;
+				clock-names = "otg";
+				resets = <&rcc USBO_R>;
+				reset-names = "dwc2";
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				g-rx-fifo-size = <512>;
+				g-np-tx-fifo-size = <32>;
+				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+				dr_mode = "otg";
+				otg-rev = <0x200>;
+				usb33d-supply = <&usb33>;
+				feature-domains = <&etzpc 34>;
+				status = "disabled";
+			};
+
+			spi4: spi@4c002000 {
+				compatible = "st,stm32h7-spi";
+				reg = <0x4c002000 0x400>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI4_K>;
+				resets = <&rcc SPI4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 83 0x400 0x01>,
+				       <&dmamux1 84 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 18>;
+				status = "disabled";
+			};
+
+			spi5: spi@4c003000 {
+				compatible = "st,stm32h7-spi";
+				reg = <0x4c003000 0x400>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI5_K>;
+				resets = <&rcc SPI5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 85 0x400 0x01>,
+				       <&dmamux1 86 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 19>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@4c004000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c004000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C3_K>;
+				resets = <&rcc I2C3_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 73 0x400 0x1>,
+				       <&dmamux1 74 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x4>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 20>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@4c005000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c005000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C4_K>;
+				resets = <&rcc I2C4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 75 0x400 0x1>,
+				       <&dmamux1 76 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x8>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 21>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@4c006000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c006000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C5_K>;
+				resets = <&rcc I2C5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 115 0x400 0x1>,
+				       <&dmamux1 116 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x10>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 22>;
+				status = "disabled";
+			};
+
+			sdmmc1: mmc@58005000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x20253180>;
+				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC1_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC1_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <130000000>;
+				feature-domains = <&etzpc 50>;
+				status = "disabled";
+			};
+
+			sdmmc2: mmc@58007000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x20253180>;
+				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC2_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC2_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <130000000>;
+				feature-domains = <&etzpc 51>;
+				status = "disabled";
+			};
+
+			usbphyc: usbphyc@5a006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#clock-cells = <0>;
+				compatible = "st,stm32mp1-usbphyc";
+				reg = <0x5a006000 0x1000>;
+				clocks = <&rcc USBPHY_K>;
+				resets = <&rcc USBPHY_R>;
+				vdda1v1-supply = <&reg11>;
+				vdda1v8-supply = <&reg18>;
+				feature-domains = <&etzpc 5>;
+				status = "disabled";
+
+				usbphyc_port0: usb-phy@0 {
+					#phy-cells = <0>;
+					reg = <0>;
+				};
+
+				usbphyc_port1: usb-phy@1 {
+					#phy-cells = <1>;
+					reg = <1>;
+				};
+			};
+
+		};
+
 		/*
 		 * Break node order to solve dependency probe issue between
 		 * pinctrl and exti.
diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
index df451c3c2a26..be6061552683 100644
--- a/arch/arm/boot/dts/stm32mp133.dtsi
+++ b/arch/arm/boot/dts/stm32mp133.dtsi
@@ -33,35 +33,38 @@ m_can2: can@4400f000 {
 			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
 			status = "disabled";
 		};
+	};
+};
 
-		adc_1: adc@48003000 {
-			compatible = "st,stm32mp13-adc-core";
-			reg = <0x48003000 0x400>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
+&etzpc {
+	adc_1: adc@48003000 {
+		compatible = "st,stm32mp13-adc-core";
+		reg = <0x48003000 0x400>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
+		clock-names = "bus", "adc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		feature-domains = <&etzpc 32>;
+		status = "disabled";
+
+		adc1: adc@0 {
+			compatible = "st,stm32mp13-adc";
+			#io-channel-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			reg = <0x0>;
+			interrupt-parent = <&adc_1>;
+			interrupts = <0>;
+			dmas = <&dmamux1 9 0x400 0x80000001>;
+			dma-names = "rx";
 			status = "disabled";
 
-			adc1: adc@0 {
-				compatible = "st,stm32mp13-adc";
-				#io-channel-cells = <1>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x0>;
-				interrupt-parent = <&adc_1>;
-				interrupts = <0>;
-				dmas = <&dmamux1 9 0x400 0x80000001>;
-				dma-names = "rx";
-				status = "disabled";
-
-				channel@18 {
-					reg = <18>;
-					label = "vrefint";
-				};
+			channel@18 {
+				reg = <18>;
+				label = "vrefint";
 			};
 		};
 	};
diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
index 4d00e7592882..a1a7a40c2a3e 100644
--- a/arch/arm/boot/dts/stm32mp13xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
@@ -4,15 +4,14 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp: crypto@54002000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp: crypto@54002000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54002000 0x400>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		feature-domains = <&etzpc 42>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
index 4d00e7592882..b9fb071a1471 100644
--- a/arch/arm/boot/dts/stm32mp13xf.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
@@ -4,15 +4,13 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp: crypto@54002000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp: crypto@54002000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54002000 0x400>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		status = "disabled";
 	};
 };
-- 
2.35.3


_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related	[flat|nested] 93+ messages in thread

* [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-01-27 16:40   ` Gatien Chevallier
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien Chevallier @ 2023-01-27 16:40 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, Gatien Chevallier, linux-iio, netdev,
	linux-usb, linux-mmc, linux-kernel, linux-spi, linux-phy,
	linux-crypto, linux-serial, dmaengine, linux-media, linux-stm32,
	linux-arm-kernel, linux-i2c

The STM32 System Bus is an internal bus on which devices are connected.
ETZPC is a peripheral overseeing the firewall bus that configures
and control access to the peripherals connected on it.

For more information on which peripheral is securable, please read
the STM32MP13 reference manual.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---

No changes in V2.

Changes in V3:
	-Use appriopriate node name: bus

 arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
 arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
 arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
 arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
 4 files changed, 258 insertions(+), 237 deletions(-)

diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
index accc3824f7e9..24462a647101 100644
--- a/arch/arm/boot/dts/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/stm32mp131.dtsi
@@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
 			dma-channels = <16>;
 		};
 
-		adc_2: adc@48004000 {
-			compatible = "st,stm32mp13-adc-core";
-			reg = <0x48004000 0x400>;
-			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			status = "disabled";
-
-			adc2: adc@0 {
-				compatible = "st,stm32mp13-adc";
-				#io-channel-cells = <1>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x0>;
-				interrupt-parent = <&adc_2>;
-				interrupts = <0>;
-				dmas = <&dmamux1 10 0x400 0x80000001>;
-				dma-names = "rx";
-				status = "disabled";
-
-				channel@13 {
-					reg = <13>;
-					label = "vrefint";
-				};
-				channel@14 {
-					reg = <14>;
-					label = "vddcore";
-				};
-				channel@16 {
-					reg = <16>;
-					label = "vddcpu";
-				};
-				channel@17 {
-					reg = <17>;
-					label = "vddq_ddr";
-				};
-			};
-		};
-
-		usbotg_hs: usb@49000000 {
-			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
-			reg = <0x49000000 0x40000>;
-			clocks = <&rcc USBO_K>;
-			clock-names = "otg";
-			resets = <&rcc USBO_R>;
-			reset-names = "dwc2";
-			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-			g-rx-fifo-size = <512>;
-			g-np-tx-fifo-size = <32>;
-			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
-			dr_mode = "otg";
-			otg-rev = <0x200>;
-			usb33d-supply = <&usb33>;
-			status = "disabled";
-		};
-
-		spi4: spi@4c002000 {
-			compatible = "st,stm32h7-spi";
-			reg = <0x4c002000 0x400>;
-			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI4_K>;
-			resets = <&rcc SPI4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 83 0x400 0x01>,
-			       <&dmamux1 84 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		spi5: spi@4c003000 {
-			compatible = "st,stm32h7-spi";
-			reg = <0x4c003000 0x400>;
-			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SPI5_K>;
-			resets = <&rcc SPI5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 85 0x400 0x01>,
-			       <&dmamux1 86 0x400 0x01>;
-			dma-names = "rx", "tx";
-			status = "disabled";
-		};
-
-		i2c3: i2c@4c004000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c004000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C3_K>;
-			resets = <&rcc I2C3_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 73 0x400 0x1>,
-			       <&dmamux1 74 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x4>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		i2c4: i2c@4c005000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c005000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C4_K>;
-			resets = <&rcc I2C4_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 75 0x400 0x1>,
-			       <&dmamux1 76 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x8>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
-		i2c5: i2c@4c006000 {
-			compatible = "st,stm32mp13-i2c";
-			reg = <0x4c006000 0x400>;
-			interrupt-names = "event", "error";
-			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc I2C5_K>;
-			resets = <&rcc I2C5_R>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			dmas = <&dmamux1 115 0x400 0x1>,
-			       <&dmamux1 116 0x400 0x1>;
-			dma-names = "rx", "tx";
-			st,syscfg-fmp = <&syscfg 0x4 0x10>;
-			i2c-analog-filter;
-			status = "disabled";
-		};
-
 		rcc: rcc@50000000 {
 			compatible = "st,stm32mp13-rcc", "syscon";
 			reg = <0x50000000 0x1000>;
@@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
 			dma-requests = <48>;
 		};
 
-		sdmmc1: mmc@58005000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x20253180>;
-			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC1_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC1_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <130000000>;
-			status = "disabled";
-		};
-
-		sdmmc2: mmc@58007000 {
-			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
-			arm,primecell-periphid = <0x20253180>;
-			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
-			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc SDMMC2_K>;
-			clock-names = "apb_pclk";
-			resets = <&rcc SDMMC2_R>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			max-frequency = <130000000>;
-			status = "disabled";
-		};
-
 		usbh_ohci: usb@5800c000 {
 			compatible = "generic-ohci";
 			reg = <0x5800c000 0x1000>;
@@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
 			status = "disabled";
 		};
 
-		usbphyc: usbphyc@5a006000 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			#clock-cells = <0>;
-			compatible = "st,stm32mp1-usbphyc";
-			reg = <0x5a006000 0x1000>;
-			clocks = <&rcc USBPHY_K>;
-			resets = <&rcc USBPHY_R>;
-			vdda1v1-supply = <&reg11>;
-			vdda1v8-supply = <&reg18>;
-			status = "disabled";
-
-			usbphyc_port0: usb-phy@0 {
-				#phy-cells = <0>;
-				reg = <0>;
-			};
-
-			usbphyc_port1: usb-phy@1 {
-				#phy-cells = <1>;
-				reg = <1>;
-			};
-		};
-
 		rtc: rtc@5c004000 {
 			compatible = "st,stm32mp1-rtc";
 			reg = <0x5c004000 0x400>;
@@ -536,6 +343,220 @@ ts_cal2: calib@5e {
 			};
 		};
 
+		etzpc: bus@5c007000 {
+			compatible = "st,stm32mp13-sys-bus";
+			reg = <0x5c007000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			feature-domain-controller;
+			#feature-domain-cells = <1>;
+			ranges;
+
+			adc_2: adc@48004000 {
+				compatible = "st,stm32mp13-adc-core";
+				reg = <0x48004000 0x400>;
+				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
+				clock-names = "bus", "adc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				feature-domains = <&etzpc 33>;
+				status = "disabled";
+
+				adc2: adc@0 {
+					compatible = "st,stm32mp13-adc";
+					#io-channel-cells = <1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x0>;
+					interrupt-parent = <&adc_2>;
+					interrupts = <0>;
+					dmas = <&dmamux1 10 0x400 0x80000001>;
+					dma-names = "rx";
+					status = "disabled";
+
+					channel@13 {
+						reg = <13>;
+						label = "vrefint";
+					};
+					channel@14 {
+						reg = <14>;
+						label = "vddcore";
+					};
+					channel@16 {
+						reg = <16>;
+						label = "vddcpu";
+					};
+					channel@17 {
+						reg = <17>;
+						label = "vddq_ddr";
+					};
+				};
+			};
+
+			usbotg_hs: usb@49000000 {
+				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
+				reg = <0x49000000 0x40000>;
+				clocks = <&rcc USBO_K>;
+				clock-names = "otg";
+				resets = <&rcc USBO_R>;
+				reset-names = "dwc2";
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				g-rx-fifo-size = <512>;
+				g-np-tx-fifo-size = <32>;
+				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
+				dr_mode = "otg";
+				otg-rev = <0x200>;
+				usb33d-supply = <&usb33>;
+				feature-domains = <&etzpc 34>;
+				status = "disabled";
+			};
+
+			spi4: spi@4c002000 {
+				compatible = "st,stm32h7-spi";
+				reg = <0x4c002000 0x400>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI4_K>;
+				resets = <&rcc SPI4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 83 0x400 0x01>,
+				       <&dmamux1 84 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 18>;
+				status = "disabled";
+			};
+
+			spi5: spi@4c003000 {
+				compatible = "st,stm32h7-spi";
+				reg = <0x4c003000 0x400>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SPI5_K>;
+				resets = <&rcc SPI5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 85 0x400 0x01>,
+				       <&dmamux1 86 0x400 0x01>;
+				dma-names = "rx", "tx";
+				feature-domains = <&etzpc 19>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@4c004000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c004000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C3_K>;
+				resets = <&rcc I2C3_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 73 0x400 0x1>,
+				       <&dmamux1 74 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x4>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 20>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@4c005000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c005000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C4_K>;
+				resets = <&rcc I2C4_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 75 0x400 0x1>,
+				       <&dmamux1 76 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x8>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 21>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@4c006000 {
+				compatible = "st,stm32mp13-i2c";
+				reg = <0x4c006000 0x400>;
+				interrupt-names = "event", "error";
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc I2C5_K>;
+				resets = <&rcc I2C5_R>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dmas = <&dmamux1 115 0x400 0x1>,
+				       <&dmamux1 116 0x400 0x1>;
+				dma-names = "rx", "tx";
+				st,syscfg-fmp = <&syscfg 0x4 0x10>;
+				i2c-analog-filter;
+				feature-domains = <&etzpc 22>;
+				status = "disabled";
+			};
+
+			sdmmc1: mmc@58005000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x20253180>;
+				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC1_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC1_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <130000000>;
+				feature-domains = <&etzpc 50>;
+				status = "disabled";
+			};
+
+			sdmmc2: mmc@58007000 {
+				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
+				arm,primecell-periphid = <0x20253180>;
+				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&rcc SDMMC2_K>;
+				clock-names = "apb_pclk";
+				resets = <&rcc SDMMC2_R>;
+				cap-sd-highspeed;
+				cap-mmc-highspeed;
+				max-frequency = <130000000>;
+				feature-domains = <&etzpc 51>;
+				status = "disabled";
+			};
+
+			usbphyc: usbphyc@5a006000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#clock-cells = <0>;
+				compatible = "st,stm32mp1-usbphyc";
+				reg = <0x5a006000 0x1000>;
+				clocks = <&rcc USBPHY_K>;
+				resets = <&rcc USBPHY_R>;
+				vdda1v1-supply = <&reg11>;
+				vdda1v8-supply = <&reg18>;
+				feature-domains = <&etzpc 5>;
+				status = "disabled";
+
+				usbphyc_port0: usb-phy@0 {
+					#phy-cells = <0>;
+					reg = <0>;
+				};
+
+				usbphyc_port1: usb-phy@1 {
+					#phy-cells = <1>;
+					reg = <1>;
+				};
+			};
+
+		};
+
 		/*
 		 * Break node order to solve dependency probe issue between
 		 * pinctrl and exti.
diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
index df451c3c2a26..be6061552683 100644
--- a/arch/arm/boot/dts/stm32mp133.dtsi
+++ b/arch/arm/boot/dts/stm32mp133.dtsi
@@ -33,35 +33,38 @@ m_can2: can@4400f000 {
 			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
 			status = "disabled";
 		};
+	};
+};
 
-		adc_1: adc@48003000 {
-			compatible = "st,stm32mp13-adc-core";
-			reg = <0x48003000 0x400>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
-			clock-names = "bus", "adc";
-			interrupt-controller;
-			#interrupt-cells = <1>;
+&etzpc {
+	adc_1: adc@48003000 {
+		compatible = "st,stm32mp13-adc-core";
+		reg = <0x48003000 0x400>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
+		clock-names = "bus", "adc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		feature-domains = <&etzpc 32>;
+		status = "disabled";
+
+		adc1: adc@0 {
+			compatible = "st,stm32mp13-adc";
+			#io-channel-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			reg = <0x0>;
+			interrupt-parent = <&adc_1>;
+			interrupts = <0>;
+			dmas = <&dmamux1 9 0x400 0x80000001>;
+			dma-names = "rx";
 			status = "disabled";
 
-			adc1: adc@0 {
-				compatible = "st,stm32mp13-adc";
-				#io-channel-cells = <1>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x0>;
-				interrupt-parent = <&adc_1>;
-				interrupts = <0>;
-				dmas = <&dmamux1 9 0x400 0x80000001>;
-				dma-names = "rx";
-				status = "disabled";
-
-				channel@18 {
-					reg = <18>;
-					label = "vrefint";
-				};
+			channel@18 {
+				reg = <18>;
+				label = "vrefint";
 			};
 		};
 	};
diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
index 4d00e7592882..a1a7a40c2a3e 100644
--- a/arch/arm/boot/dts/stm32mp13xc.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
@@ -4,15 +4,14 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp: crypto@54002000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp: crypto@54002000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54002000 0x400>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		feature-domains = <&etzpc 42>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
index 4d00e7592882..b9fb071a1471 100644
--- a/arch/arm/boot/dts/stm32mp13xf.dtsi
+++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
@@ -4,15 +4,13 @@
  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
  */
 
-/ {
-	soc {
-		cryp: crypto@54002000 {
-			compatible = "st,stm32mp1-cryp";
-			reg = <0x54002000 0x400>;
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&rcc CRYP1>;
-			resets = <&rcc CRYP1_R>;
-			status = "disabled";
-		};
+&etzpc {
+	cryp: crypto@54002000 {
+		compatible = "st,stm32mp1-cryp";
+		reg = <0x54002000 0x400>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&rcc CRYP1>;
+		resets = <&rcc CRYP1_R>;
+		status = "disabled";
 	};
 };
-- 
2.35.3


^ permalink raw reply related	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 1/6] dt-bindings: Document common device controller bindings
  2023-01-27 16:40   ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-27 16:49     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 93+ messages in thread
From: Krzysztof Kozlowski @ 2023-01-27 16:49 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb

On 27/01/2023 17:40, Gatien Chevallier wrote:
> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
> 
> Introducing of the common device controller bindings for the controller
> provider and consumer devices. Those bindings are intended to allow
> divided system on chip into muliple domains, that can be used to
> configure hardware permissions.
> 
> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
> ---
> 
> No change since V1. I'm letting this patch for dependency with bindings to
> avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
> appropriate thread.

There was a v6 already, this is v3 and I don't understand this comment.
What do you let? Whom? If it is not for review and not for merging,
please annotate it in the title ([IGNORE PATCH] or something).

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 1/6] dt-bindings: Document common device controller bindings
@ 2023-01-27 16:49     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 93+ messages in thread
From: Krzysztof Kozlowski @ 2023-01-27 16:49 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb

On 27/01/2023 17:40, Gatien Chevallier wrote:
> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
> 
> Introducing of the common device controller bindings for the controller
> provider and consumer devices. Those bindings are intended to allow
> divided system on chip into muliple domains, that can be used to
> configure hardware permissions.
> 
> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
> ---
> 
> No change since V1. I'm letting this patch for dependency with bindings to
> avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
> appropriate thread.

There was a v6 already, this is v3 and I don't understand this comment.
What do you let? Whom? If it is not for review and not for merging,
please annotate it in the title ([IGNORE PATCH] or something).

Best regards,
Krzysztof


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 1/6] dt-bindings: Document common device controller bindings
@ 2023-01-27 16:49     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 93+ messages in thread
From: Krzysztof Kozlowski @ 2023-01-27 16:49 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb

On 27/01/2023 17:40, Gatien Chevallier wrote:
> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
> 
> Introducing of the common device controller bindings for the controller
> provider and consumer devices. Those bindings are intended to allow
> divided system on chip into muliple domains, that can be used to
> configure hardware permissions.
> 
> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
> ---
> 
> No change since V1. I'm letting this patch for dependency with bindings to
> avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
> appropriate thread.

There was a v6 already, this is v3 and I don't understand this comment.
What do you let? Whom? If it is not for review and not for merging,
please annotate it in the title ([IGNORE PATCH] or something).

Best regards,
Krzysztof


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 1/6] dt-bindings: Document common device controller bindings
@ 2023-01-27 16:49     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 93+ messages in thread
From: Krzysztof Kozlowski @ 2023-01-27 16:49 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-phy, linux-crypto, linux-serial,
	dmaengine, linux-media, linux-stm32, linux-arm-kernel, linux-i2c

On 27/01/2023 17:40, Gatien Chevallier wrote:
> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
> 
> Introducing of the common device controller bindings for the controller
> provider and consumer devices. Those bindings are intended to allow
> divided system on chip into muliple domains, that can be used to
> configure hardware permissions.
> 
> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
> ---
> 
> No change since V1. I'm letting this patch for dependency with bindings to
> avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
> appropriate thread.

There was a v6 already, this is v3 and I don't understand this comment.
What do you let? Whom? If it is not for review and not for merging,
please annotate it in the title ([IGNORE PATCH] or something).

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 1/6] dt-bindings: Document common device controller bindings
  2023-01-27 16:49     ` Krzysztof Kozlowski
  (?)
  (?)
@ 2023-01-27 17:00       ` Gatien CHEVALLIER
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-01-27 17:00 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb

Hello Krzysztof,

On 1/27/23 17:49, Krzysztof Kozlowski wrote:
> On 27/01/2023 17:40, Gatien Chevallier wrote:
>> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
>>
>> Introducing of the common device controller bindings for the controller
>> provider and consumer devices. Those bindings are intended to allow
>> divided system on chip into muliple domains, that can be used to
>> configure hardware permissions.
>>
>> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
>> ---
>>
>> No change since V1. I'm letting this patch for dependency with bindings to
>> avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
>> appropriate thread.
> 
> There was a v6 already, this is v3 and I don't understand this comment.
> What do you let? Whom? If it is not for review and not for merging,
> please annotate it in the title ([IGNORE PATCH] or something).
> 

Sorry for not being clear in the previous comment.

I meant I'm letting this patch in this patch set so the dependencies on 
the feature-domain-controller.yaml file are satisfied.

I will annotate it with [IGNORE PATCH], as you suggest.

> Best regards,
> Krzysztof
> 

Best regards,
Gatien

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 1/6] dt-bindings: Document common device controller bindings
@ 2023-01-27 17:00       ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-01-27 17:00 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb

Hello Krzysztof,

On 1/27/23 17:49, Krzysztof Kozlowski wrote:
> On 27/01/2023 17:40, Gatien Chevallier wrote:
>> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
>>
>> Introducing of the common device controller bindings for the controller
>> provider and consumer devices. Those bindings are intended to allow
>> divided system on chip into muliple domains, that can be used to
>> configure hardware permissions.
>>
>> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
>> ---
>>
>> No change since V1. I'm letting this patch for dependency with bindings to
>> avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
>> appropriate thread.
> 
> There was a v6 already, this is v3 and I don't understand this comment.
> What do you let? Whom? If it is not for review and not for merging,
> please annotate it in the title ([IGNORE PATCH] or something).
> 

Sorry for not being clear in the previous comment.

I meant I'm letting this patch in this patch set so the dependencies on 
the feature-domain-controller.yaml file are satisfied.

I will annotate it with [IGNORE PATCH], as you suggest.

> Best regards,
> Krzysztof
> 

Best regards,
Gatien

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 1/6] dt-bindings: Document common device controller bindings
@ 2023-01-27 17:00       ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-01-27 17:00 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb

Hello Krzysztof,

On 1/27/23 17:49, Krzysztof Kozlowski wrote:
> On 27/01/2023 17:40, Gatien Chevallier wrote:
>> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
>>
>> Introducing of the common device controller bindings for the controller
>> provider and consumer devices. Those bindings are intended to allow
>> divided system on chip into muliple domains, that can be used to
>> configure hardware permissions.
>>
>> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
>> ---
>>
>> No change since V1. I'm letting this patch for dependency with bindings to
>> avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
>> appropriate thread.
> 
> There was a v6 already, this is v3 and I don't understand this comment.
> What do you let? Whom? If it is not for review and not for merging,
> please annotate it in the title ([IGNORE PATCH] or something).
> 

Sorry for not being clear in the previous comment.

I meant I'm letting this patch in this patch set so the dependencies on 
the feature-domain-controller.yaml file are satisfied.

I will annotate it with [IGNORE PATCH], as you suggest.

> Best regards,
> Krzysztof
> 

Best regards,
Gatien

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 1/6] dt-bindings: Document common device controller bindings
@ 2023-01-27 17:00       ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-01-27 17:00 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-phy, linux-crypto, linux-serial,
	dmaengine, linux-media, linux-stm32, linux-arm-kernel, linux-i2c

Hello Krzysztof,

On 1/27/23 17:49, Krzysztof Kozlowski wrote:
> On 27/01/2023 17:40, Gatien Chevallier wrote:
>> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
>>
>> Introducing of the common device controller bindings for the controller
>> provider and consumer devices. Those bindings are intended to allow
>> divided system on chip into muliple domains, that can be used to
>> configure hardware permissions.
>>
>> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
>> ---
>>
>> No change since V1. I'm letting this patch for dependency with bindings to
>> avoid noise with dt/bindings checks. Therefore, it should be reviewed on the
>> appropriate thread.
> 
> There was a v6 already, this is v3 and I don't understand this comment.
> What do you let? Whom? If it is not for review and not for merging,
> please annotate it in the title ([IGNORE PATCH] or something).
> 

Sorry for not being clear in the previous comment.

I meant I'm letting this patch in this patch set so the dependencies on 
the feature-domain-controller.yaml file are satisfied.

I will annotate it with [IGNORE PATCH], as you suggest.

> Best regards,
> Krzysztof
> 

Best regards,
Gatien

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
  2023-01-27 16:40   ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-28 15:46     ` Jonathan Cameron
  -1 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 15:46 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb

On Fri, 27 Jan 2023 17:40:36 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> feature-domains is an optional property that allows a peripheral to
> refer to one or more feature domain controller(s).
> 
> Description of this property is added to all peripheral binding files of
> the peripheral under the STM32 System Bus. It allows an accurate
> representation of the hardware, where various peripherals are connected
> to this firewall bus. The firewall can then check the peripheral accesses
> before allowing it to probe.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

There was probably a cleaner way to ensure that this could go via the various
subsystem trees, but hopefully there won't be any clashes with other work going in
and if there is, the resolution should be simple. Hence I'm fine with
this going via the dt tree.

So for the IIO ones below,

Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> index 1c340c95df16..c68b7b0e1903 100644
> --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> @@ -93,6 +93,11 @@ properties:
>    '#size-cells':
>      const: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  allOf:
>    - if:
>        properties:
> diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> index 1970503389aa..d01f60765e48 100644
> --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> @@ -59,6 +59,11 @@ properties:
>        If not, SPI CLKOUT frequency will not be accurate.
>      maximum: 20000000
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  required:
>    - compatible
>    - reg
> diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> index 0f1bf1110122..f6fe58d2f9b8 100644
> --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> @@ -45,6 +45,11 @@ properties:
>    '#size-cells':
>      const: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  additionalProperties: false

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
@ 2023-01-28 15:46     ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 15:46 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb

On Fri, 27 Jan 2023 17:40:36 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> feature-domains is an optional property that allows a peripheral to
> refer to one or more feature domain controller(s).
> 
> Description of this property is added to all peripheral binding files of
> the peripheral under the STM32 System Bus. It allows an accurate
> representation of the hardware, where various peripherals are connected
> to this firewall bus. The firewall can then check the peripheral accesses
> before allowing it to probe.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

There was probably a cleaner way to ensure that this could go via the various
subsystem trees, but hopefully there won't be any clashes with other work going in
and if there is, the resolution should be simple. Hence I'm fine with
this going via the dt tree.

So for the IIO ones below,

Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> index 1c340c95df16..c68b7b0e1903 100644
> --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> @@ -93,6 +93,11 @@ properties:
>    '#size-cells':
>      const: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  allOf:
>    - if:
>        properties:
> diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> index 1970503389aa..d01f60765e48 100644
> --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> @@ -59,6 +59,11 @@ properties:
>        If not, SPI CLKOUT frequency will not be accurate.
>      maximum: 20000000
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  required:
>    - compatible
>    - reg
> diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> index 0f1bf1110122..f6fe58d2f9b8 100644
> --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> @@ -45,6 +45,11 @@ properties:
>    '#size-cells':
>      const: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  additionalProperties: false

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
@ 2023-01-28 15:46     ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 15:46 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb

On Fri, 27 Jan 2023 17:40:36 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> feature-domains is an optional property that allows a peripheral to
> refer to one or more feature domain controller(s).
> 
> Description of this property is added to all peripheral binding files of
> the peripheral under the STM32 System Bus. It allows an accurate
> representation of the hardware, where various peripherals are connected
> to this firewall bus. The firewall can then check the peripheral accesses
> before allowing it to probe.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

There was probably a cleaner way to ensure that this could go via the various
subsystem trees, but hopefully there won't be any clashes with other work going in
and if there is, the resolution should be simple. Hence I'm fine with
this going via the dt tree.

So for the IIO ones below,

Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> index 1c340c95df16..c68b7b0e1903 100644
> --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> @@ -93,6 +93,11 @@ properties:
>    '#size-cells':
>      const: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  allOf:
>    - if:
>        properties:
> diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> index 1970503389aa..d01f60765e48 100644
> --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> @@ -59,6 +59,11 @@ properties:
>        If not, SPI CLKOUT frequency will not be accurate.
>      maximum: 20000000
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  required:
>    - compatible
>    - reg
> diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> index 0f1bf1110122..f6fe58d2f9b8 100644
> --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> @@ -45,6 +45,11 @@ properties:
>    '#size-cells':
>      const: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  additionalProperties: false

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
@ 2023-01-28 15:46     ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 15:46 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: ulf.hansson, linux-iio, alexandre.torgue, edumazet,
	Oleksii_Moisieiev, krzysztof.kozlowski+dt, linux-phy,
	linux-stm32, herbert, olivier.moysan, kuba, arnaud.pouliquen,
	pabeni, linux-media, devicetree, linux-serial, alsa-devel,
	robh+dt, mchehab, linux-arm-kernel, gregkh, linux-usb, linux-mmc,
	linux-kernel, linux-spi, vkoul, fabrice.gasnier, linux-crypto,
	netdev, dmaengine, davem, linux-i2c

On Fri, 27 Jan 2023 17:40:36 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> feature-domains is an optional property that allows a peripheral to
> refer to one or more feature domain controller(s).
> 
> Description of this property is added to all peripheral binding files of
> the peripheral under the STM32 System Bus. It allows an accurate
> representation of the hardware, where various peripherals are connected
> to this firewall bus. The firewall can then check the peripheral accesses
> before allowing it to probe.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

There was probably a cleaner way to ensure that this could go via the various
subsystem trees, but hopefully there won't be any clashes with other work going in
and if there is, the resolution should be simple. Hence I'm fine with
this going via the dt tree.

So for the IIO ones below,

Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> index 1c340c95df16..c68b7b0e1903 100644
> --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
> @@ -93,6 +93,11 @@ properties:
>    '#size-cells':
>      const: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  allOf:
>    - if:
>        properties:
> diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> index 1970503389aa..d01f60765e48 100644
> --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
> @@ -59,6 +59,11 @@ properties:
>        If not, SPI CLKOUT frequency will not be accurate.
>      maximum: 20000000
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  required:
>    - compatible
>    - reg
> diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> index 0f1bf1110122..f6fe58d2f9b8 100644
> --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
> @@ -45,6 +45,11 @@ properties:
>    '#size-cells':
>      const: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
> +    minItems: 1
> +    maxItems: 3
> +
>  additionalProperties: false

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
  2023-01-27 16:40   ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-28 15:48     ` Jonathan Cameron
  -1 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 15:48 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Fri, 27 Jan 2023 17:40:37 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> Document STM32 System Bus. This bus is intended to control firewall
> access for the peripherals connected to it.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
Trivial comment on formatting.

> +
> +examples:
> +  - |
> +    // In this example, the rng1 device refers to etzpc as its domain controller.
> +    // Same goes for fmc.
> +    // Access rights are verified before creating devices.
> +
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/stm32mp1-clks.h>
> +    #include <dt-bindings/reset/stm32mp1-resets.h>
> +
> +    etzpc: bus@5c007000 {
> +        compatible = "st,stm32mp15-sys-bus";
> +        reg = <0x5c007000 0x400>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges;
> +        feature-domain-controller;
> +        #feature-domain-cells = <1>;
> +
> +        rng1: rng@54003000 {

Odd mixture of 4 spacing and 2 spacing in this example.
I'd suggest one or the other (slight preference for 4 space indents).


> +          compatible = "st,stm32-rng";
> +          reg = <0x54003000 0x400>;
> +          clocks = <&rcc RNG1_K>;
> +          resets = <&rcc RNG1_R>;
> +          feature-domains = <&etzpc 7>;
> +          status = "disabled";
> +        };

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
@ 2023-01-28 15:48     ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 15:48 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Fri, 27 Jan 2023 17:40:37 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> Document STM32 System Bus. This bus is intended to control firewall
> access for the peripherals connected to it.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
Trivial comment on formatting.

> +
> +examples:
> +  - |
> +    // In this example, the rng1 device refers to etzpc as its domain controller.
> +    // Same goes for fmc.
> +    // Access rights are verified before creating devices.
> +
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/stm32mp1-clks.h>
> +    #include <dt-bindings/reset/stm32mp1-resets.h>
> +
> +    etzpc: bus@5c007000 {
> +        compatible = "st,stm32mp15-sys-bus";
> +        reg = <0x5c007000 0x400>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges;
> +        feature-domain-controller;
> +        #feature-domain-cells = <1>;
> +
> +        rng1: rng@54003000 {

Odd mixture of 4 spacing and 2 spacing in this example.
I'd suggest one or the other (slight preference for 4 space indents).


> +          compatible = "st,stm32-rng";
> +          reg = <0x54003000 0x400>;
> +          clocks = <&rcc RNG1_K>;
> +          resets = <&rcc RNG1_R>;
> +          feature-domains = <&etzpc 7>;
> +          status = "disabled";
> +        };

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
@ 2023-01-28 15:48     ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 15:48 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Fri, 27 Jan 2023 17:40:37 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> Document STM32 System Bus. This bus is intended to control firewall
> access for the peripherals connected to it.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
Trivial comment on formatting.

> +
> +examples:
> +  - |
> +    // In this example, the rng1 device refers to etzpc as its domain controller.
> +    // Same goes for fmc.
> +    // Access rights are verified before creating devices.
> +
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/stm32mp1-clks.h>
> +    #include <dt-bindings/reset/stm32mp1-resets.h>
> +
> +    etzpc: bus@5c007000 {
> +        compatible = "st,stm32mp15-sys-bus";
> +        reg = <0x5c007000 0x400>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges;
> +        feature-domain-controller;
> +        #feature-domain-cells = <1>;
> +
> +        rng1: rng@54003000 {

Odd mixture of 4 spacing and 2 spacing in this example.
I'd suggest one or the other (slight preference for 4 space indents).


> +          compatible = "st,stm32-rng";
> +          reg = <0x54003000 0x400>;
> +          clocks = <&rcc RNG1_K>;
> +          resets = <&rcc RNG1_R>;
> +          feature-domains = <&etzpc 7>;
> +          status = "disabled";
> +        };

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
@ 2023-01-28 15:48     ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 15:48 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: ulf.hansson, linux-iio, alexandre.torgue, edumazet,
	Oleksii_Moisieiev, krzysztof.kozlowski+dt, linux-phy,
	linux-stm32, herbert, Loic PALLARDY, olivier.moysan, kuba,
	arnaud.pouliquen, pabeni, linux-media, devicetree, linux-serial,
	alsa-devel, robh+dt, mchehab, linux-arm-kernel, gregkh,
	linux-usb, linux-mmc, linux-kernel, linux-spi, vkoul,
	fabrice.gasnier, linux-crypto, netdev, dmaengine, davem,
	linux-i2c

On Fri, 27 Jan 2023 17:40:37 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> Document STM32 System Bus. This bus is intended to control firewall
> access for the peripherals connected to it.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
Trivial comment on formatting.

> +
> +examples:
> +  - |
> +    // In this example, the rng1 device refers to etzpc as its domain controller.
> +    // Same goes for fmc.
> +    // Access rights are verified before creating devices.
> +
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/stm32mp1-clks.h>
> +    #include <dt-bindings/reset/stm32mp1-resets.h>
> +
> +    etzpc: bus@5c007000 {
> +        compatible = "st,stm32mp15-sys-bus";
> +        reg = <0x5c007000 0x400>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges;
> +        feature-domain-controller;
> +        #feature-domain-cells = <1>;
> +
> +        rng1: rng@54003000 {

Odd mixture of 4 spacing and 2 spacing in this example.
I'd suggest one or the other (slight preference for 4 space indents).


> +          compatible = "st,stm32-rng";
> +          reg = <0x54003000 0x400>;
> +          clocks = <&rcc RNG1_K>;
> +          resets = <&rcc RNG1_R>;
> +          feature-domains = <&etzpc 7>;
> +          status = "disabled";
> +        };

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
  2023-01-27 16:40   ` Gatien Chevallier
  (?)
  (?)
@ 2023-01-28 16:12     ` Jonathan Cameron
  -1 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 16:12 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Fri, 27 Jan 2023 17:40:38 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> This driver is checking the access rights of the different
> peripherals connected to the system bus. If access is denied,
> the associated device tree node is skipped so the platform bus
> does not probe it.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>

Hi Gatien,

A few comments inline,

Thanks,

Jonathan

> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
> new file mode 100644
> index 000000000000..c12926466bae
> --- /dev/null
> +++ b/drivers/bus/stm32_sys_bus.c
> @@ -0,0 +1,168 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +
> +/* ETZPC peripheral as firewall bus */
> +/* ETZPC registers */
> +#define ETZPC_DECPROT			0x10
> +
> +/* ETZPC miscellaneous */
> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
> +#define ETZPC_PROT_A7NS			0x3
> +#define ETZPC_DECPROT_SHIFT		1

This define makes the code harder to read.  What we care about is
the number of bits in the register divided by number of entries.
(which is 2) hence the shift by 1. See below for more on this.


> +
> +#define IDS_PER_DECPROT_REGS		16

> +#define STM32MP15_ETZPC_ENTRIES		96
> +#define STM32MP13_ETZPC_ENTRIES		64

These defines just make the code harder to check.
They aren't magic numbers, but rather just telling us how many
entries there are, so I would just put them in the structures directly.
Their use make it clear what they are without needing to give them a name.


> +struct stm32_sys_bus_match_data {

Comment on naming of this below.

> +	unsigned int max_entries;
> +};
> +

+static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
+{
+	int err;
+	u32 offset, reg_offset, sec_val, id;
+
+	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
+	if (err)
+		return err;
+
+	/* Check access configuration, 16 peripherals per register */
+	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;

Use of defines in here is actively unhelpful when it comes to review. I would suggest letting
the maths be self explanatory (even if it's more code).

	offset = (id % IDS_PER_DECPROT_REGS) * (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS);

Or if you prefer have a define of

#define DECPROT_BITS_PER_ID (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS)

and
	offset = (id % IDS_PER_DECPROT_REGS) * DECPROT_BITS_PER_ID;

+
+	/* Verify peripheral is non-secure and attributed to cortex A7 */
+	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+	if (sec_val != ETZPC_PROT_A7NS) {
+		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
+			reg_offset, sec_val);
+		return -EACCES;
+	}
+
+	return 0;
+}
+
...

> +static int stm32_sys_bus_probe(struct platform_device *pdev)
> +{
> +	struct sys_bus_data *pdata;
> +	void __iomem *mmio;
> +	struct device_node *np = pdev->dev.of_node;

I'd be consistent. You use dev_of_node() accessor elsewhere, so should
use it here as well.

> +
> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return -ENOMEM;
> +
> +	mmio = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(mmio))
> +		return PTR_ERR(mmio);
> +
> +	pdata->sys_bus_base = mmio;
> +	pdata->pconf = of_device_get_match_data(&pdev->dev);
> +	pdata->dev = &pdev->dev;
> +
> +	platform_set_drvdata(pdev, pdata);

Does this get used? I can't immediately spot where but maybe I just
missed it.

> +
> +	stm32_sys_bus_populate(pdata);
> +
> +	/* Populate all available nodes */
> +	return of_platform_populate(np, NULL, NULL, &pdev->dev);

As np only used here, I'd not bother with the local variable in this function.

> +}
> +
> +static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {

Naming a structure after where it comes from is a little unusual and
confusion when a given call gets it from somewhere else.

I'd expect it to be named after what sort of thing it contains.
stm32_sys_bus_info or something like that.

> +	.max_entries = STM32MP15_ETZPC_ENTRIES,
> +};
> +
> +static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
> +	.max_entries = STM32MP13_ETZPC_ENTRIES,
> +};
> +
> +static const struct of_device_id stm32_sys_bus_of_match[] = {
> +	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
> +	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },

Alphabetical order usually preferred when there isn't a strong reason for
another choice.

> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
> +
> +static struct platform_driver stm32_sys_bus_driver = {
> +	.probe  = stm32_sys_bus_probe,
> +	.driver = {
> +		.name = "stm32-sys-bus",
> +		.of_match_table = stm32_sys_bus_of_match,
> +	},
> +};
> +
> +static int __init stm32_sys_bus_init(void)
> +{
> +	return platform_driver_register(&stm32_sys_bus_driver);
> +}
> +arch_initcall(stm32_sys_bus_init);
> +

Unwanted trailing blank line.



^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-01-28 16:12     ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 16:12 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Fri, 27 Jan 2023 17:40:38 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> This driver is checking the access rights of the different
> peripherals connected to the system bus. If access is denied,
> the associated device tree node is skipped so the platform bus
> does not probe it.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>

Hi Gatien,

A few comments inline,

Thanks,

Jonathan

> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
> new file mode 100644
> index 000000000000..c12926466bae
> --- /dev/null
> +++ b/drivers/bus/stm32_sys_bus.c
> @@ -0,0 +1,168 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +
> +/* ETZPC peripheral as firewall bus */
> +/* ETZPC registers */
> +#define ETZPC_DECPROT			0x10
> +
> +/* ETZPC miscellaneous */
> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
> +#define ETZPC_PROT_A7NS			0x3
> +#define ETZPC_DECPROT_SHIFT		1

This define makes the code harder to read.  What we care about is
the number of bits in the register divided by number of entries.
(which is 2) hence the shift by 1. See below for more on this.


> +
> +#define IDS_PER_DECPROT_REGS		16

> +#define STM32MP15_ETZPC_ENTRIES		96
> +#define STM32MP13_ETZPC_ENTRIES		64

These defines just make the code harder to check.
They aren't magic numbers, but rather just telling us how many
entries there are, so I would just put them in the structures directly.
Their use make it clear what they are without needing to give them a name.


> +struct stm32_sys_bus_match_data {

Comment on naming of this below.

> +	unsigned int max_entries;
> +};
> +

+static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
+{
+	int err;
+	u32 offset, reg_offset, sec_val, id;
+
+	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
+	if (err)
+		return err;
+
+	/* Check access configuration, 16 peripherals per register */
+	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;

Use of defines in here is actively unhelpful when it comes to review. I would suggest letting
the maths be self explanatory (even if it's more code).

	offset = (id % IDS_PER_DECPROT_REGS) * (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS);

Or if you prefer have a define of

#define DECPROT_BITS_PER_ID (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS)

and
	offset = (id % IDS_PER_DECPROT_REGS) * DECPROT_BITS_PER_ID;

+
+	/* Verify peripheral is non-secure and attributed to cortex A7 */
+	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+	if (sec_val != ETZPC_PROT_A7NS) {
+		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
+			reg_offset, sec_val);
+		return -EACCES;
+	}
+
+	return 0;
+}
+
...

> +static int stm32_sys_bus_probe(struct platform_device *pdev)
> +{
> +	struct sys_bus_data *pdata;
> +	void __iomem *mmio;
> +	struct device_node *np = pdev->dev.of_node;

I'd be consistent. You use dev_of_node() accessor elsewhere, so should
use it here as well.

> +
> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return -ENOMEM;
> +
> +	mmio = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(mmio))
> +		return PTR_ERR(mmio);
> +
> +	pdata->sys_bus_base = mmio;
> +	pdata->pconf = of_device_get_match_data(&pdev->dev);
> +	pdata->dev = &pdev->dev;
> +
> +	platform_set_drvdata(pdev, pdata);

Does this get used? I can't immediately spot where but maybe I just
missed it.

> +
> +	stm32_sys_bus_populate(pdata);
> +
> +	/* Populate all available nodes */
> +	return of_platform_populate(np, NULL, NULL, &pdev->dev);

As np only used here, I'd not bother with the local variable in this function.

> +}
> +
> +static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {

Naming a structure after where it comes from is a little unusual and
confusion when a given call gets it from somewhere else.

I'd expect it to be named after what sort of thing it contains.
stm32_sys_bus_info or something like that.

> +	.max_entries = STM32MP15_ETZPC_ENTRIES,
> +};
> +
> +static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
> +	.max_entries = STM32MP13_ETZPC_ENTRIES,
> +};
> +
> +static const struct of_device_id stm32_sys_bus_of_match[] = {
> +	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
> +	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },

Alphabetical order usually preferred when there isn't a strong reason for
another choice.

> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
> +
> +static struct platform_driver stm32_sys_bus_driver = {
> +	.probe  = stm32_sys_bus_probe,
> +	.driver = {
> +		.name = "stm32-sys-bus",
> +		.of_match_table = stm32_sys_bus_of_match,
> +	},
> +};
> +
> +static int __init stm32_sys_bus_init(void)
> +{
> +	return platform_driver_register(&stm32_sys_bus_driver);
> +}
> +arch_initcall(stm32_sys_bus_init);
> +

Unwanted trailing blank line.



-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-01-28 16:12     ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 16:12 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Fri, 27 Jan 2023 17:40:38 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> This driver is checking the access rights of the different
> peripherals connected to the system bus. If access is denied,
> the associated device tree node is skipped so the platform bus
> does not probe it.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>

Hi Gatien,

A few comments inline,

Thanks,

Jonathan

> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
> new file mode 100644
> index 000000000000..c12926466bae
> --- /dev/null
> +++ b/drivers/bus/stm32_sys_bus.c
> @@ -0,0 +1,168 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +
> +/* ETZPC peripheral as firewall bus */
> +/* ETZPC registers */
> +#define ETZPC_DECPROT			0x10
> +
> +/* ETZPC miscellaneous */
> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
> +#define ETZPC_PROT_A7NS			0x3
> +#define ETZPC_DECPROT_SHIFT		1

This define makes the code harder to read.  What we care about is
the number of bits in the register divided by number of entries.
(which is 2) hence the shift by 1. See below for more on this.


> +
> +#define IDS_PER_DECPROT_REGS		16

> +#define STM32MP15_ETZPC_ENTRIES		96
> +#define STM32MP13_ETZPC_ENTRIES		64

These defines just make the code harder to check.
They aren't magic numbers, but rather just telling us how many
entries there are, so I would just put them in the structures directly.
Their use make it clear what they are without needing to give them a name.


> +struct stm32_sys_bus_match_data {

Comment on naming of this below.

> +	unsigned int max_entries;
> +};
> +

+static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
+{
+	int err;
+	u32 offset, reg_offset, sec_val, id;
+
+	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
+	if (err)
+		return err;
+
+	/* Check access configuration, 16 peripherals per register */
+	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;

Use of defines in here is actively unhelpful when it comes to review. I would suggest letting
the maths be self explanatory (even if it's more code).

	offset = (id % IDS_PER_DECPROT_REGS) * (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS);

Or if you prefer have a define of

#define DECPROT_BITS_PER_ID (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS)

and
	offset = (id % IDS_PER_DECPROT_REGS) * DECPROT_BITS_PER_ID;

+
+	/* Verify peripheral is non-secure and attributed to cortex A7 */
+	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+	if (sec_val != ETZPC_PROT_A7NS) {
+		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
+			reg_offset, sec_val);
+		return -EACCES;
+	}
+
+	return 0;
+}
+
...

> +static int stm32_sys_bus_probe(struct platform_device *pdev)
> +{
> +	struct sys_bus_data *pdata;
> +	void __iomem *mmio;
> +	struct device_node *np = pdev->dev.of_node;

I'd be consistent. You use dev_of_node() accessor elsewhere, so should
use it here as well.

> +
> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return -ENOMEM;
> +
> +	mmio = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(mmio))
> +		return PTR_ERR(mmio);
> +
> +	pdata->sys_bus_base = mmio;
> +	pdata->pconf = of_device_get_match_data(&pdev->dev);
> +	pdata->dev = &pdev->dev;
> +
> +	platform_set_drvdata(pdev, pdata);

Does this get used? I can't immediately spot where but maybe I just
missed it.

> +
> +	stm32_sys_bus_populate(pdata);
> +
> +	/* Populate all available nodes */
> +	return of_platform_populate(np, NULL, NULL, &pdev->dev);

As np only used here, I'd not bother with the local variable in this function.

> +}
> +
> +static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {

Naming a structure after where it comes from is a little unusual and
confusion when a given call gets it from somewhere else.

I'd expect it to be named after what sort of thing it contains.
stm32_sys_bus_info or something like that.

> +	.max_entries = STM32MP15_ETZPC_ENTRIES,
> +};
> +
> +static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
> +	.max_entries = STM32MP13_ETZPC_ENTRIES,
> +};
> +
> +static const struct of_device_id stm32_sys_bus_of_match[] = {
> +	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
> +	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },

Alphabetical order usually preferred when there isn't a strong reason for
another choice.

> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
> +
> +static struct platform_driver stm32_sys_bus_driver = {
> +	.probe  = stm32_sys_bus_probe,
> +	.driver = {
> +		.name = "stm32-sys-bus",
> +		.of_match_table = stm32_sys_bus_of_match,
> +	},
> +};
> +
> +static int __init stm32_sys_bus_init(void)
> +{
> +	return platform_driver_register(&stm32_sys_bus_driver);
> +}
> +arch_initcall(stm32_sys_bus_init);
> +

Unwanted trailing blank line.



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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-01-28 16:12     ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-01-28 16:12 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: ulf.hansson, linux-iio, alexandre.torgue, edumazet,
	Oleksii_Moisieiev, krzysztof.kozlowski+dt, linux-phy,
	linux-stm32, herbert, Loic PALLARDY, olivier.moysan, kuba,
	arnaud.pouliquen, pabeni, linux-media, devicetree, linux-serial,
	alsa-devel, robh+dt, mchehab, linux-arm-kernel, gregkh,
	linux-usb, linux-mmc, linux-kernel, linux-spi, vkoul,
	fabrice.gasnier, linux-crypto, netdev, dmaengine, davem,
	linux-i2c

On Fri, 27 Jan 2023 17:40:38 +0100
Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:

> This driver is checking the access rights of the different
> peripherals connected to the system bus. If access is denied,
> the associated device tree node is skipped so the platform bus
> does not probe it.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>

Hi Gatien,

A few comments inline,

Thanks,

Jonathan

> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
> new file mode 100644
> index 000000000000..c12926466bae
> --- /dev/null
> +++ b/drivers/bus/stm32_sys_bus.c
> @@ -0,0 +1,168 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +
> +/* ETZPC peripheral as firewall bus */
> +/* ETZPC registers */
> +#define ETZPC_DECPROT			0x10
> +
> +/* ETZPC miscellaneous */
> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
> +#define ETZPC_PROT_A7NS			0x3
> +#define ETZPC_DECPROT_SHIFT		1

This define makes the code harder to read.  What we care about is
the number of bits in the register divided by number of entries.
(which is 2) hence the shift by 1. See below for more on this.


> +
> +#define IDS_PER_DECPROT_REGS		16

> +#define STM32MP15_ETZPC_ENTRIES		96
> +#define STM32MP13_ETZPC_ENTRIES		64

These defines just make the code harder to check.
They aren't magic numbers, but rather just telling us how many
entries there are, so I would just put them in the structures directly.
Their use make it clear what they are without needing to give them a name.


> +struct stm32_sys_bus_match_data {

Comment on naming of this below.

> +	unsigned int max_entries;
> +};
> +

+static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
+{
+	int err;
+	u32 offset, reg_offset, sec_val, id;
+
+	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
+	if (err)
+		return err;
+
+	/* Check access configuration, 16 peripherals per register */
+	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
+	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;

Use of defines in here is actively unhelpful when it comes to review. I would suggest letting
the maths be self explanatory (even if it's more code).

	offset = (id % IDS_PER_DECPROT_REGS) * (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS);

Or if you prefer have a define of

#define DECPROT_BITS_PER_ID (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS)

and
	offset = (id % IDS_PER_DECPROT_REGS) * DECPROT_BITS_PER_ID;

+
+	/* Verify peripheral is non-secure and attributed to cortex A7 */
+	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
+	if (sec_val != ETZPC_PROT_A7NS) {
+		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
+			reg_offset, sec_val);
+		return -EACCES;
+	}
+
+	return 0;
+}
+
...

> +static int stm32_sys_bus_probe(struct platform_device *pdev)
> +{
> +	struct sys_bus_data *pdata;
> +	void __iomem *mmio;
> +	struct device_node *np = pdev->dev.of_node;

I'd be consistent. You use dev_of_node() accessor elsewhere, so should
use it here as well.

> +
> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> +	if (!pdata)
> +		return -ENOMEM;
> +
> +	mmio = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(mmio))
> +		return PTR_ERR(mmio);
> +
> +	pdata->sys_bus_base = mmio;
> +	pdata->pconf = of_device_get_match_data(&pdev->dev);
> +	pdata->dev = &pdev->dev;
> +
> +	platform_set_drvdata(pdev, pdata);

Does this get used? I can't immediately spot where but maybe I just
missed it.

> +
> +	stm32_sys_bus_populate(pdata);
> +
> +	/* Populate all available nodes */
> +	return of_platform_populate(np, NULL, NULL, &pdev->dev);

As np only used here, I'd not bother with the local variable in this function.

> +}
> +
> +static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {

Naming a structure after where it comes from is a little unusual and
confusion when a given call gets it from somewhere else.

I'd expect it to be named after what sort of thing it contains.
stm32_sys_bus_info or something like that.

> +	.max_entries = STM32MP15_ETZPC_ENTRIES,
> +};
> +
> +static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
> +	.max_entries = STM32MP13_ETZPC_ENTRIES,
> +};
> +
> +static const struct of_device_id stm32_sys_bus_of_match[] = {
> +	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
> +	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },

Alphabetical order usually preferred when there isn't a strong reason for
another choice.

> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
> +
> +static struct platform_driver stm32_sys_bus_driver = {
> +	.probe  = stm32_sys_bus_probe,
> +	.driver = {
> +		.name = "stm32-sys-bus",
> +		.of_match_table = stm32_sys_bus_of_match,
> +	},
> +};
> +
> +static int __init stm32_sys_bus_init(void)
> +{
> +	return platform_driver_register(&stm32_sys_bus_driver);
> +}
> +arch_initcall(stm32_sys_bus_init);
> +

Unwanted trailing blank line.



^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
  2023-01-27 16:40   ` Gatien Chevallier
  (?)
  (?)
@ 2023-02-03 20:57     ` Rob Herring
  -1 siblings, 0 replies; 93+ messages in thread
From: Rob Herring @ 2023-02-03 20:57 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni, linux-crypto, devicetree,
	linux-stm32, linux-arm-kernel, linux-kernel, dmaengine,
	linux-i2c, linux-iio, alsa-devel, linux-media, linux-mmc, netdev,
	linux-phy, linux-serial, linux-spi, linux-usb

On Fri, Jan 27, 2023 at 05:40:36PM +0100, Gatien Chevallier wrote:
> feature-domains is an optional property that allows a peripheral to
> refer to one or more feature domain controller(s).
> 
> Description of this property is added to all peripheral binding files of
> the peripheral under the STM32 System Bus. It allows an accurate
> representation of the hardware, where various peripherals are connected
> to this firewall bus. The firewall can then check the peripheral accesses
> before allowing it to probe.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
> 
> Patch not present in V1 and V2.
> 
>  Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 5 +++++
>  Documentation/devicetree/bindings/dma/st,stm32-dma.yaml     | 5 +++++
>  Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml  | 5 +++++
>  Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml     | 5 +++++
>  Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 5 +++++
>  .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml     | 5 +++++
>  Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 5 +++++
>  Documentation/devicetree/bindings/media/st,stm32-cec.yaml   | 5 +++++
>  Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml  | 5 +++++
>  .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml      | 5 +++++
>  Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 5 +++++
>  Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml  | 6 ++++++
>  Documentation/devicetree/bindings/mmc/arm,pl18x.yaml        | 5 +++++
>  Documentation/devicetree/bindings/net/stm32-dwmac.yaml      | 5 +++++
>  .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml          | 5 +++++
>  .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml     | 5 +++++
>  Documentation/devicetree/bindings/rng/st,stm32-rng.yaml     | 5 +++++
>  Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 5 +++++
>  Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml   | 5 +++++
>  Documentation/devicetree/bindings/sound/st,stm32-sai.yaml   | 5 +++++
>  .../devicetree/bindings/sound/st,stm32-spdifrx.yaml         | 5 +++++
>  Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml    | 5 +++++
>  Documentation/devicetree/bindings/spi/st,stm32-spi.yaml     | 5 +++++
>  Documentation/devicetree/bindings/usb/dwc2.yaml             | 5 +++++
>  24 files changed, 121 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> index 4ccb335e8063..cb2ad7d5fdb5 100644
> --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> @@ -41,6 +41,11 @@ properties:
>      maximum: 2
>      default: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains

Not how common properties work. Consumer properties should be in a 
schema with 'select: true' (the one you are referencing) and here you 
just need to define the entries. Like clocks, power-domains, etc.

> +    minItems: 1
> +    maxItems: 3

Why is this variable and what is each entry?

I still don't like the naming. Everything is a feature and a domain... 

It might be a bit easier to come up with a name with multiple users of 
this binding presented. I'm hesistant to define any new common binding 
with only 1 user as I've said multiple times on this binding.

Rob

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
@ 2023-02-03 20:57     ` Rob Herring
  0 siblings, 0 replies; 93+ messages in thread
From: Rob Herring @ 2023-02-03 20:57 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni, linux-crypto, devicetree,
	linux-stm32, linux-arm-kernel, linux-kernel, dmaengine,
	linux-i2c, linux-iio, alsa-devel, linux-media, linux-mmc, netdev,
	linux-phy, linux-serial, linux-spi, linux-usb

On Fri, Jan 27, 2023 at 05:40:36PM +0100, Gatien Chevallier wrote:
> feature-domains is an optional property that allows a peripheral to
> refer to one or more feature domain controller(s).
> 
> Description of this property is added to all peripheral binding files of
> the peripheral under the STM32 System Bus. It allows an accurate
> representation of the hardware, where various peripherals are connected
> to this firewall bus. The firewall can then check the peripheral accesses
> before allowing it to probe.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
> 
> Patch not present in V1 and V2.
> 
>  Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 5 +++++
>  Documentation/devicetree/bindings/dma/st,stm32-dma.yaml     | 5 +++++
>  Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml  | 5 +++++
>  Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml     | 5 +++++
>  Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 5 +++++
>  .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml     | 5 +++++
>  Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 5 +++++
>  Documentation/devicetree/bindings/media/st,stm32-cec.yaml   | 5 +++++
>  Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml  | 5 +++++
>  .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml      | 5 +++++
>  Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 5 +++++
>  Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml  | 6 ++++++
>  Documentation/devicetree/bindings/mmc/arm,pl18x.yaml        | 5 +++++
>  Documentation/devicetree/bindings/net/stm32-dwmac.yaml      | 5 +++++
>  .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml          | 5 +++++
>  .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml     | 5 +++++
>  Documentation/devicetree/bindings/rng/st,stm32-rng.yaml     | 5 +++++
>  Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 5 +++++
>  Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml   | 5 +++++
>  Documentation/devicetree/bindings/sound/st,stm32-sai.yaml   | 5 +++++
>  .../devicetree/bindings/sound/st,stm32-spdifrx.yaml         | 5 +++++
>  Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml    | 5 +++++
>  Documentation/devicetree/bindings/spi/st,stm32-spi.yaml     | 5 +++++
>  Documentation/devicetree/bindings/usb/dwc2.yaml             | 5 +++++
>  24 files changed, 121 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> index 4ccb335e8063..cb2ad7d5fdb5 100644
> --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> @@ -41,6 +41,11 @@ properties:
>      maximum: 2
>      default: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains

Not how common properties work. Consumer properties should be in a 
schema with 'select: true' (the one you are referencing) and here you 
just need to define the entries. Like clocks, power-domains, etc.

> +    minItems: 1
> +    maxItems: 3

Why is this variable and what is each entry?

I still don't like the naming. Everything is a feature and a domain... 

It might be a bit easier to come up with a name with multiple users of 
this binding presented. I'm hesistant to define any new common binding 
with only 1 user as I've said multiple times on this binding.

Rob

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
@ 2023-02-03 20:57     ` Rob Herring
  0 siblings, 0 replies; 93+ messages in thread
From: Rob Herring @ 2023-02-03 20:57 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni, linux-crypto, devicetree,
	linux-stm32, linux-arm-kernel, linux-kernel, dmaengine,
	linux-i2c, linux-iio, alsa-devel, linux-media, linux-mmc, netdev,
	linux-phy, linux-serial, linux-spi, linux-usb

On Fri, Jan 27, 2023 at 05:40:36PM +0100, Gatien Chevallier wrote:
> feature-domains is an optional property that allows a peripheral to
> refer to one or more feature domain controller(s).
> 
> Description of this property is added to all peripheral binding files of
> the peripheral under the STM32 System Bus. It allows an accurate
> representation of the hardware, where various peripherals are connected
> to this firewall bus. The firewall can then check the peripheral accesses
> before allowing it to probe.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
> 
> Patch not present in V1 and V2.
> 
>  Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 5 +++++
>  Documentation/devicetree/bindings/dma/st,stm32-dma.yaml     | 5 +++++
>  Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml  | 5 +++++
>  Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml     | 5 +++++
>  Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 5 +++++
>  .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml     | 5 +++++
>  Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 5 +++++
>  Documentation/devicetree/bindings/media/st,stm32-cec.yaml   | 5 +++++
>  Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml  | 5 +++++
>  .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml      | 5 +++++
>  Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 5 +++++
>  Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml  | 6 ++++++
>  Documentation/devicetree/bindings/mmc/arm,pl18x.yaml        | 5 +++++
>  Documentation/devicetree/bindings/net/stm32-dwmac.yaml      | 5 +++++
>  .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml          | 5 +++++
>  .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml     | 5 +++++
>  Documentation/devicetree/bindings/rng/st,stm32-rng.yaml     | 5 +++++
>  Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 5 +++++
>  Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml   | 5 +++++
>  Documentation/devicetree/bindings/sound/st,stm32-sai.yaml   | 5 +++++
>  .../devicetree/bindings/sound/st,stm32-spdifrx.yaml         | 5 +++++
>  Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml    | 5 +++++
>  Documentation/devicetree/bindings/spi/st,stm32-spi.yaml     | 5 +++++
>  Documentation/devicetree/bindings/usb/dwc2.yaml             | 5 +++++
>  24 files changed, 121 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> index 4ccb335e8063..cb2ad7d5fdb5 100644
> --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> @@ -41,6 +41,11 @@ properties:
>      maximum: 2
>      default: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains

Not how common properties work. Consumer properties should be in a 
schema with 'select: true' (the one you are referencing) and here you 
just need to define the entries. Like clocks, power-domains, etc.

> +    minItems: 1
> +    maxItems: 3

Why is this variable and what is each entry?

I still don't like the naming. Everything is a feature and a domain... 

It might be a bit easier to come up with a name with multiple users of 
this binding presented. I'm hesistant to define any new common binding 
with only 1 user as I've said multiple times on this binding.

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files
@ 2023-02-03 20:57     ` Rob Herring
  0 siblings, 0 replies; 93+ messages in thread
From: Rob Herring @ 2023-02-03 20:57 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: ulf.hansson, linux-iio, alexandre.torgue, edumazet,
	Oleksii_Moisieiev, krzysztof.kozlowski+dt, linux-phy,
	linux-stm32, herbert, olivier.moysan, kuba, arnaud.pouliquen,
	pabeni, linux-media, devicetree, linux-serial, alsa-devel,
	fabrice.gasnier, mchehab, linux-arm-kernel, gregkh, linux-usb,
	linux-mmc, linux-kernel, linux-spi, vkoul, linux-crypto, netdev,
	dmaengine, davem, jic23, linux-i2c

On Fri, Jan 27, 2023 at 05:40:36PM +0100, Gatien Chevallier wrote:
> feature-domains is an optional property that allows a peripheral to
> refer to one or more feature domain controller(s).
> 
> Description of this property is added to all peripheral binding files of
> the peripheral under the STM32 System Bus. It allows an accurate
> representation of the hardware, where various peripherals are connected
> to this firewall bus. The firewall can then check the peripheral accesses
> before allowing it to probe.
> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
> 
> Patch not present in V1 and V2.
> 
>  Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 5 +++++
>  Documentation/devicetree/bindings/dma/st,stm32-dma.yaml     | 5 +++++
>  Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml  | 5 +++++
>  Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml     | 5 +++++
>  Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 5 +++++
>  .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml     | 5 +++++
>  Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 5 +++++
>  Documentation/devicetree/bindings/media/st,stm32-cec.yaml   | 5 +++++
>  Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml  | 5 +++++
>  .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml      | 5 +++++
>  Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 5 +++++
>  Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml  | 6 ++++++
>  Documentation/devicetree/bindings/mmc/arm,pl18x.yaml        | 5 +++++
>  Documentation/devicetree/bindings/net/stm32-dwmac.yaml      | 5 +++++
>  .../devicetree/bindings/phy/phy-stm32-usbphyc.yaml          | 5 +++++
>  .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml     | 5 +++++
>  Documentation/devicetree/bindings/rng/st,stm32-rng.yaml     | 5 +++++
>  Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 5 +++++
>  Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml   | 5 +++++
>  Documentation/devicetree/bindings/sound/st,stm32-sai.yaml   | 5 +++++
>  .../devicetree/bindings/sound/st,stm32-spdifrx.yaml         | 5 +++++
>  Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml    | 5 +++++
>  Documentation/devicetree/bindings/spi/st,stm32-spi.yaml     | 5 +++++
>  Documentation/devicetree/bindings/usb/dwc2.yaml             | 5 +++++
>  24 files changed, 121 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> index 4ccb335e8063..cb2ad7d5fdb5 100644
> --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
> @@ -41,6 +41,11 @@ properties:
>      maximum: 2
>      default: 0
>  
> +  feature-domains:
> +    $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains

Not how common properties work. Consumer properties should be in a 
schema with 'select: true' (the one you are referencing) and here you 
just need to define the entries. Like clocks, power-domains, etc.

> +    minItems: 1
> +    maxItems: 3

Why is this variable and what is each entry?

I still don't like the naming. Everything is a feature and a domain... 

It might be a bit easier to come up with a name with multiple users of 
this binding presented. I'm hesistant to define any new common binding 
with only 1 user as I've said multiple times on this binding.

Rob

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
  2023-01-28 15:48     ` Jonathan Cameron
  (?)
@ 2023-02-07 13:31       ` Gatien CHEVALLIER
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-07 13:31 UTC (permalink / raw)
  To: Jonathan Cameron
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

Hello Jonathan,

On 1/28/23 16:48, Jonathan Cameron wrote:
> On Fri, 27 Jan 2023 17:40:37 +0100
> Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> 
>> Document STM32 System Bus. This bus is intended to control firewall
>> access for the peripherals connected to it.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
> Trivial comment on formatting.
> 
>> +
>> +examples:
>> +  - |
>> +    // In this example, the rng1 device refers to etzpc as its domain controller.
>> +    // Same goes for fmc.
>> +    // Access rights are verified before creating devices.
>> +
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/clock/stm32mp1-clks.h>
>> +    #include <dt-bindings/reset/stm32mp1-resets.h>
>> +
>> +    etzpc: bus@5c007000 {
>> +        compatible = "st,stm32mp15-sys-bus";
>> +        reg = <0x5c007000 0x400>;
>> +        #address-cells = <1>;
>> +        #size-cells = <1>;
>> +        ranges;
>> +        feature-domain-controller;
>> +        #feature-domain-cells = <1>;
>> +
>> +        rng1: rng@54003000 {
> 
> Odd mixture of 4 spacing and 2 spacing in this example.
> I'd suggest one or the other (slight preference for 4 space indents).
> 

Thank you for spotting this, I'll change to 4 space indents

> 
>> +          compatible = "st,stm32-rng";
>> +          reg = <0x54003000 0x400>;
>> +          clocks = <&rcc RNG1_K>;
>> +          resets = <&rcc RNG1_R>;
>> +          feature-domains = <&etzpc 7>;
>> +          status = "disabled";
>> +        };

Best regards,
Gatien

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
@ 2023-02-07 13:31       ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-07 13:31 UTC (permalink / raw)
  To: Jonathan Cameron
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

Hello Jonathan,

On 1/28/23 16:48, Jonathan Cameron wrote:
> On Fri, 27 Jan 2023 17:40:37 +0100
> Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> 
>> Document STM32 System Bus. This bus is intended to control firewall
>> access for the peripherals connected to it.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
> Trivial comment on formatting.
> 
>> +
>> +examples:
>> +  - |
>> +    // In this example, the rng1 device refers to etzpc as its domain controller.
>> +    // Same goes for fmc.
>> +    // Access rights are verified before creating devices.
>> +
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/clock/stm32mp1-clks.h>
>> +    #include <dt-bindings/reset/stm32mp1-resets.h>
>> +
>> +    etzpc: bus@5c007000 {
>> +        compatible = "st,stm32mp15-sys-bus";
>> +        reg = <0x5c007000 0x400>;
>> +        #address-cells = <1>;
>> +        #size-cells = <1>;
>> +        ranges;
>> +        feature-domain-controller;
>> +        #feature-domain-cells = <1>;
>> +
>> +        rng1: rng@54003000 {
> 
> Odd mixture of 4 spacing and 2 spacing in this example.
> I'd suggest one or the other (slight preference for 4 space indents).
> 

Thank you for spotting this, I'll change to 4 space indents

> 
>> +          compatible = "st,stm32-rng";
>> +          reg = <0x54003000 0x400>;
>> +          clocks = <&rcc RNG1_K>;
>> +          resets = <&rcc RNG1_R>;
>> +          feature-domains = <&etzpc 7>;
>> +          status = "disabled";
>> +        };

Best regards,
Gatien

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus
@ 2023-02-07 13:31       ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-07 13:31 UTC (permalink / raw)
  To: Jonathan Cameron
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

Hello Jonathan,

On 1/28/23 16:48, Jonathan Cameron wrote:
> On Fri, 27 Jan 2023 17:40:37 +0100
> Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> 
>> Document STM32 System Bus. This bus is intended to control firewall
>> access for the peripherals connected to it.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
> Trivial comment on formatting.
> 
>> +
>> +examples:
>> +  - |
>> +    // In this example, the rng1 device refers to etzpc as its domain controller.
>> +    // Same goes for fmc.
>> +    // Access rights are verified before creating devices.
>> +
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/clock/stm32mp1-clks.h>
>> +    #include <dt-bindings/reset/stm32mp1-resets.h>
>> +
>> +    etzpc: bus@5c007000 {
>> +        compatible = "st,stm32mp15-sys-bus";
>> +        reg = <0x5c007000 0x400>;
>> +        #address-cells = <1>;
>> +        #size-cells = <1>;
>> +        ranges;
>> +        feature-domain-controller;
>> +        #feature-domain-cells = <1>;
>> +
>> +        rng1: rng@54003000 {
> 
> Odd mixture of 4 spacing and 2 spacing in this example.
> I'd suggest one or the other (slight preference for 4 space indents).
> 

Thank you for spotting this, I'll change to 4 space indents

> 
>> +          compatible = "st,stm32-rng";
>> +          reg = <0x54003000 0x400>;
>> +          clocks = <&rcc RNG1_K>;
>> +          resets = <&rcc RNG1_R>;
>> +          feature-domains = <&etzpc 7>;
>> +          status = "disabled";
>> +        };

Best regards,
Gatien

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
  2023-01-28 16:12     ` Jonathan Cameron
  (?)
  (?)
@ 2023-02-07 14:12       ` Gatien CHEVALLIER
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-07 14:12 UTC (permalink / raw)
  To: Jonathan Cameron
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

Hi Jonathan,

On 1/28/23 17:12, Jonathan Cameron wrote:
> On Fri, 27 Jan 2023 17:40:38 +0100
> Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> 
>> This driver is checking the access rights of the different
>> peripherals connected to the system bus. If access is denied,
>> the associated device tree node is skipped so the platform bus
>> does not probe it.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
> 
> Hi Gatien,
> 
> A few comments inline,
> 
> Thanks,
> 
> Jonathan
> 
>> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
>> new file mode 100644
>> index 000000000000..c12926466bae
>> --- /dev/null
>> +++ b/drivers/bus/stm32_sys_bus.c
>> @@ -0,0 +1,168 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/bits.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/init.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +
>> +/* ETZPC peripheral as firewall bus */
>> +/* ETZPC registers */
>> +#define ETZPC_DECPROT			0x10
>> +
>> +/* ETZPC miscellaneous */
>> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
>> +#define ETZPC_PROT_A7NS			0x3
>> +#define ETZPC_DECPROT_SHIFT		1
> 
> This define makes the code harder to read.  What we care about is
> the number of bits in the register divided by number of entries.
> (which is 2) hence the shift by 1. See below for more on this.
> 
> 
>> +
>> +#define IDS_PER_DECPROT_REGS		16
> 
>> +#define STM32MP15_ETZPC_ENTRIES		96
>> +#define STM32MP13_ETZPC_ENTRIES		64
> 
> These defines just make the code harder to check.
> They aren't magic numbers, but rather just telling us how many
> entries there are, so I would just put them in the structures directly.
> Their use make it clear what they are without needing to give them a name.
> 

Honestly, I'd rather read the hardware configuration registers to get 
this information instead of differentiating MP13/15. Would you agree on 
that?

> 
>> +struct stm32_sys_bus_match_data {
> 
> Comment on naming of this below.
> 
>> +	unsigned int max_entries;
>> +};
>> +
> 
> +static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
> +{
> +	int err;
> +	u32 offset, reg_offset, sec_val, id;
> +
> +	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
> +	if (err)
> +		return err;
> +
> +	/* Check access configuration, 16 peripherals per register */
> +	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
> +	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
> 
> Use of defines in here is actively unhelpful when it comes to review. I would suggest letting
> the maths be self explanatory (even if it's more code).
> 
> 	offset = (id % IDS_PER_DECPROT_REGS) * (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS);
> 
> Or if you prefer have a define of
> 
> #define DECPROT_BITS_PER_ID (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS)
> 
> and
> 	offset = (id % IDS_PER_DECPROT_REGS) * DECPROT_BITS_PER_ID;
> 

Ok I'll rework this for better understanding. Your suggestion seems fine

> +
> +	/* Verify peripheral is non-secure and attributed to cortex A7 */
> +	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
> +	if (sec_val != ETZPC_PROT_A7NS) {
> +		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
> +			reg_offset, sec_val);
> +		return -EACCES;
> +	}
> +
> +	return 0;
> +}
> +
> ...
> 
>> +static int stm32_sys_bus_probe(struct platform_device *pdev)
>> +{
>> +	struct sys_bus_data *pdata;
>> +	void __iomem *mmio;
>> +	struct device_node *np = pdev->dev.of_node;
> 
> I'd be consistent. You use dev_of_node() accessor elsewhere, so should
> use it here as well >> +
>> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
>> +	if (!pdata)
>> +		return -ENOMEM;
>> +
>> +	mmio = devm_platform_ioremap_resource(pdev, 0);
>> +	if (IS_ERR(mmio))
>> +		return PTR_ERR(mmio);
>> +
>> +	pdata->sys_bus_base = mmio;
>> +	pdata->pconf = of_device_get_match_data(&pdev->dev);
>> +	pdata->dev = &pdev->dev;
>> +
>> +	platform_set_drvdata(pdev, pdata);
> 
> Does this get used? I can't immediately spot where but maybe I just
> missed it.
> 

Not for now :)

>> +
>> +	stm32_sys_bus_populate(pdata);
>> +
>> +	/* Populate all available nodes */
>> +	return of_platform_populate(np, NULL, NULL, &pdev->dev);
> 
> As np only used here, I'd not bother with the local variable in this function.
> 

Agreed

>> +}
>> +
>> +static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {
> 
> Naming a structure after where it comes from is a little unusual and
> confusion when a given call gets it from somewhere else.
> 
> I'd expect it to be named after what sort of thing it contains.
> stm32_sys_bus_info or something like that.
> 

Then, this shall be removed thanks to the read to hardware registers.

>> +	.max_entries = STM32MP15_ETZPC_ENTRIES,
>> +};
>> +
>> +static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
>> +	.max_entries = STM32MP13_ETZPC_ENTRIES,
>> +};
>> +
>> +static const struct of_device_id stm32_sys_bus_of_match[] = {
>> +	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
>> +	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },
> 
> Alphabetical order usually preferred when there isn't a strong reason for
> another choice.
> 

I second that

>> +	{}
>> +};
>> +MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
>> +
>> +static struct platform_driver stm32_sys_bus_driver = {
>> +	.probe  = stm32_sys_bus_probe,
>> +	.driver = {
>> +		.name = "stm32-sys-bus",
>> +		.of_match_table = stm32_sys_bus_of_match,
>> +	},
>> +};
>> +
>> +static int __init stm32_sys_bus_init(void)
>> +{
>> +	return platform_driver_register(&stm32_sys_bus_driver);
>> +}
>> +arch_initcall(stm32_sys_bus_init);
>> +
> 
> Unwanted trailing blank line.
> 

Good spot, thanks

> 

Best regards,
Gatien

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-02-07 14:12       ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-07 14:12 UTC (permalink / raw)
  To: Jonathan Cameron
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

Hi Jonathan,

On 1/28/23 17:12, Jonathan Cameron wrote:
> On Fri, 27 Jan 2023 17:40:38 +0100
> Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> 
>> This driver is checking the access rights of the different
>> peripherals connected to the system bus. If access is denied,
>> the associated device tree node is skipped so the platform bus
>> does not probe it.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
> 
> Hi Gatien,
> 
> A few comments inline,
> 
> Thanks,
> 
> Jonathan
> 
>> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
>> new file mode 100644
>> index 000000000000..c12926466bae
>> --- /dev/null
>> +++ b/drivers/bus/stm32_sys_bus.c
>> @@ -0,0 +1,168 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/bits.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/init.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +
>> +/* ETZPC peripheral as firewall bus */
>> +/* ETZPC registers */
>> +#define ETZPC_DECPROT			0x10
>> +
>> +/* ETZPC miscellaneous */
>> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
>> +#define ETZPC_PROT_A7NS			0x3
>> +#define ETZPC_DECPROT_SHIFT		1
> 
> This define makes the code harder to read.  What we care about is
> the number of bits in the register divided by number of entries.
> (which is 2) hence the shift by 1. See below for more on this.
> 
> 
>> +
>> +#define IDS_PER_DECPROT_REGS		16
> 
>> +#define STM32MP15_ETZPC_ENTRIES		96
>> +#define STM32MP13_ETZPC_ENTRIES		64
> 
> These defines just make the code harder to check.
> They aren't magic numbers, but rather just telling us how many
> entries there are, so I would just put them in the structures directly.
> Their use make it clear what they are without needing to give them a name.
> 

Honestly, I'd rather read the hardware configuration registers to get 
this information instead of differentiating MP13/15. Would you agree on 
that?

> 
>> +struct stm32_sys_bus_match_data {
> 
> Comment on naming of this below.
> 
>> +	unsigned int max_entries;
>> +};
>> +
> 
> +static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
> +{
> +	int err;
> +	u32 offset, reg_offset, sec_val, id;
> +
> +	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
> +	if (err)
> +		return err;
> +
> +	/* Check access configuration, 16 peripherals per register */
> +	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
> +	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
> 
> Use of defines in here is actively unhelpful when it comes to review. I would suggest letting
> the maths be self explanatory (even if it's more code).
> 
> 	offset = (id % IDS_PER_DECPROT_REGS) * (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS);
> 
> Or if you prefer have a define of
> 
> #define DECPROT_BITS_PER_ID (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS)
> 
> and
> 	offset = (id % IDS_PER_DECPROT_REGS) * DECPROT_BITS_PER_ID;
> 

Ok I'll rework this for better understanding. Your suggestion seems fine

> +
> +	/* Verify peripheral is non-secure and attributed to cortex A7 */
> +	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
> +	if (sec_val != ETZPC_PROT_A7NS) {
> +		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
> +			reg_offset, sec_val);
> +		return -EACCES;
> +	}
> +
> +	return 0;
> +}
> +
> ...
> 
>> +static int stm32_sys_bus_probe(struct platform_device *pdev)
>> +{
>> +	struct sys_bus_data *pdata;
>> +	void __iomem *mmio;
>> +	struct device_node *np = pdev->dev.of_node;
> 
> I'd be consistent. You use dev_of_node() accessor elsewhere, so should
> use it here as well >> +
>> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
>> +	if (!pdata)
>> +		return -ENOMEM;
>> +
>> +	mmio = devm_platform_ioremap_resource(pdev, 0);
>> +	if (IS_ERR(mmio))
>> +		return PTR_ERR(mmio);
>> +
>> +	pdata->sys_bus_base = mmio;
>> +	pdata->pconf = of_device_get_match_data(&pdev->dev);
>> +	pdata->dev = &pdev->dev;
>> +
>> +	platform_set_drvdata(pdev, pdata);
> 
> Does this get used? I can't immediately spot where but maybe I just
> missed it.
> 

Not for now :)

>> +
>> +	stm32_sys_bus_populate(pdata);
>> +
>> +	/* Populate all available nodes */
>> +	return of_platform_populate(np, NULL, NULL, &pdev->dev);
> 
> As np only used here, I'd not bother with the local variable in this function.
> 

Agreed

>> +}
>> +
>> +static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {
> 
> Naming a structure after where it comes from is a little unusual and
> confusion when a given call gets it from somewhere else.
> 
> I'd expect it to be named after what sort of thing it contains.
> stm32_sys_bus_info or something like that.
> 

Then, this shall be removed thanks to the read to hardware registers.

>> +	.max_entries = STM32MP15_ETZPC_ENTRIES,
>> +};
>> +
>> +static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
>> +	.max_entries = STM32MP13_ETZPC_ENTRIES,
>> +};
>> +
>> +static const struct of_device_id stm32_sys_bus_of_match[] = {
>> +	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
>> +	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },
> 
> Alphabetical order usually preferred when there isn't a strong reason for
> another choice.
> 

I second that

>> +	{}
>> +};
>> +MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
>> +
>> +static struct platform_driver stm32_sys_bus_driver = {
>> +	.probe  = stm32_sys_bus_probe,
>> +	.driver = {
>> +		.name = "stm32-sys-bus",
>> +		.of_match_table = stm32_sys_bus_of_match,
>> +	},
>> +};
>> +
>> +static int __init stm32_sys_bus_init(void)
>> +{
>> +	return platform_driver_register(&stm32_sys_bus_driver);
>> +}
>> +arch_initcall(stm32_sys_bus_init);
>> +
> 
> Unwanted trailing blank line.
> 

Good spot, thanks

> 

Best regards,
Gatien

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-02-07 14:12       ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-07 14:12 UTC (permalink / raw)
  To: Jonathan Cameron
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

Hi Jonathan,

On 1/28/23 17:12, Jonathan Cameron wrote:
> On Fri, 27 Jan 2023 17:40:38 +0100
> Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> 
>> This driver is checking the access rights of the different
>> peripherals connected to the system bus. If access is denied,
>> the associated device tree node is skipped so the platform bus
>> does not probe it.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
> 
> Hi Gatien,
> 
> A few comments inline,
> 
> Thanks,
> 
> Jonathan
> 
>> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
>> new file mode 100644
>> index 000000000000..c12926466bae
>> --- /dev/null
>> +++ b/drivers/bus/stm32_sys_bus.c
>> @@ -0,0 +1,168 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/bits.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/init.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +
>> +/* ETZPC peripheral as firewall bus */
>> +/* ETZPC registers */
>> +#define ETZPC_DECPROT			0x10
>> +
>> +/* ETZPC miscellaneous */
>> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
>> +#define ETZPC_PROT_A7NS			0x3
>> +#define ETZPC_DECPROT_SHIFT		1
> 
> This define makes the code harder to read.  What we care about is
> the number of bits in the register divided by number of entries.
> (which is 2) hence the shift by 1. See below for more on this.
> 
> 
>> +
>> +#define IDS_PER_DECPROT_REGS		16
> 
>> +#define STM32MP15_ETZPC_ENTRIES		96
>> +#define STM32MP13_ETZPC_ENTRIES		64
> 
> These defines just make the code harder to check.
> They aren't magic numbers, but rather just telling us how many
> entries there are, so I would just put them in the structures directly.
> Their use make it clear what they are without needing to give them a name.
> 

Honestly, I'd rather read the hardware configuration registers to get 
this information instead of differentiating MP13/15. Would you agree on 
that?

> 
>> +struct stm32_sys_bus_match_data {
> 
> Comment on naming of this below.
> 
>> +	unsigned int max_entries;
>> +};
>> +
> 
> +static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
> +{
> +	int err;
> +	u32 offset, reg_offset, sec_val, id;
> +
> +	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
> +	if (err)
> +		return err;
> +
> +	/* Check access configuration, 16 peripherals per register */
> +	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
> +	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
> 
> Use of defines in here is actively unhelpful when it comes to review. I would suggest letting
> the maths be self explanatory (even if it's more code).
> 
> 	offset = (id % IDS_PER_DECPROT_REGS) * (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS);
> 
> Or if you prefer have a define of
> 
> #define DECPROT_BITS_PER_ID (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS)
> 
> and
> 	offset = (id % IDS_PER_DECPROT_REGS) * DECPROT_BITS_PER_ID;
> 

Ok I'll rework this for better understanding. Your suggestion seems fine

> +
> +	/* Verify peripheral is non-secure and attributed to cortex A7 */
> +	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
> +	if (sec_val != ETZPC_PROT_A7NS) {
> +		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
> +			reg_offset, sec_val);
> +		return -EACCES;
> +	}
> +
> +	return 0;
> +}
> +
> ...
> 
>> +static int stm32_sys_bus_probe(struct platform_device *pdev)
>> +{
>> +	struct sys_bus_data *pdata;
>> +	void __iomem *mmio;
>> +	struct device_node *np = pdev->dev.of_node;
> 
> I'd be consistent. You use dev_of_node() accessor elsewhere, so should
> use it here as well >> +
>> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
>> +	if (!pdata)
>> +		return -ENOMEM;
>> +
>> +	mmio = devm_platform_ioremap_resource(pdev, 0);
>> +	if (IS_ERR(mmio))
>> +		return PTR_ERR(mmio);
>> +
>> +	pdata->sys_bus_base = mmio;
>> +	pdata->pconf = of_device_get_match_data(&pdev->dev);
>> +	pdata->dev = &pdev->dev;
>> +
>> +	platform_set_drvdata(pdev, pdata);
> 
> Does this get used? I can't immediately spot where but maybe I just
> missed it.
> 

Not for now :)

>> +
>> +	stm32_sys_bus_populate(pdata);
>> +
>> +	/* Populate all available nodes */
>> +	return of_platform_populate(np, NULL, NULL, &pdev->dev);
> 
> As np only used here, I'd not bother with the local variable in this function.
> 

Agreed

>> +}
>> +
>> +static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {
> 
> Naming a structure after where it comes from is a little unusual and
> confusion when a given call gets it from somewhere else.
> 
> I'd expect it to be named after what sort of thing it contains.
> stm32_sys_bus_info or something like that.
> 

Then, this shall be removed thanks to the read to hardware registers.

>> +	.max_entries = STM32MP15_ETZPC_ENTRIES,
>> +};
>> +
>> +static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
>> +	.max_entries = STM32MP13_ETZPC_ENTRIES,
>> +};
>> +
>> +static const struct of_device_id stm32_sys_bus_of_match[] = {
>> +	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
>> +	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },
> 
> Alphabetical order usually preferred when there isn't a strong reason for
> another choice.
> 

I second that

>> +	{}
>> +};
>> +MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
>> +
>> +static struct platform_driver stm32_sys_bus_driver = {
>> +	.probe  = stm32_sys_bus_probe,
>> +	.driver = {
>> +		.name = "stm32-sys-bus",
>> +		.of_match_table = stm32_sys_bus_of_match,
>> +	},
>> +};
>> +
>> +static int __init stm32_sys_bus_init(void)
>> +{
>> +	return platform_driver_register(&stm32_sys_bus_driver);
>> +}
>> +arch_initcall(stm32_sys_bus_init);
>> +
> 
> Unwanted trailing blank line.
> 

Good spot, thanks

> 

Best regards,
Gatien

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-02-07 14:12       ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-07 14:12 UTC (permalink / raw)
  To: Jonathan Cameron
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

Hi Jonathan,

On 1/28/23 17:12, Jonathan Cameron wrote:
> On Fri, 27 Jan 2023 17:40:38 +0100
> Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> 
>> This driver is checking the access rights of the different
>> peripherals connected to the system bus. If access is denied,
>> the associated device tree node is skipped so the platform bus
>> does not probe it.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
> 
> Hi Gatien,
> 
> A few comments inline,
> 
> Thanks,
> 
> Jonathan
> 
>> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
>> new file mode 100644
>> index 000000000000..c12926466bae
>> --- /dev/null
>> +++ b/drivers/bus/stm32_sys_bus.c
>> @@ -0,0 +1,168 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
>> + */
>> +
>> +#include <linux/bitfield.h>
>> +#include <linux/bits.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/init.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +
>> +/* ETZPC peripheral as firewall bus */
>> +/* ETZPC registers */
>> +#define ETZPC_DECPROT			0x10
>> +
>> +/* ETZPC miscellaneous */
>> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
>> +#define ETZPC_PROT_A7NS			0x3
>> +#define ETZPC_DECPROT_SHIFT		1
> 
> This define makes the code harder to read.  What we care about is
> the number of bits in the register divided by number of entries.
> (which is 2) hence the shift by 1. See below for more on this.
> 
> 
>> +
>> +#define IDS_PER_DECPROT_REGS		16
> 
>> +#define STM32MP15_ETZPC_ENTRIES		96
>> +#define STM32MP13_ETZPC_ENTRIES		64
> 
> These defines just make the code harder to check.
> They aren't magic numbers, but rather just telling us how many
> entries there are, so I would just put them in the structures directly.
> Their use make it clear what they are without needing to give them a name.
> 

Honestly, I'd rather read the hardware configuration registers to get 
this information instead of differentiating MP13/15. Would you agree on 
that?

> 
>> +struct stm32_sys_bus_match_data {
> 
> Comment on naming of this below.
> 
>> +	unsigned int max_entries;
>> +};
>> +
> 
> +static int stm32_etzpc_get_access(struct sys_bus_data *pdata, struct device_node *np)
> +{
> +	int err;
> +	u32 offset, reg_offset, sec_val, id;
> +
> +	err = stm32_sys_bus_get_periph_id(pdata, np, &id);
> +	if (err)
> +		return err;
> +
> +	/* Check access configuration, 16 peripherals per register */
> +	reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
> +	offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
> 
> Use of defines in here is actively unhelpful when it comes to review. I would suggest letting
> the maths be self explanatory (even if it's more code).
> 
> 	offset = (id % IDS_PER_DECPROT_REGS) * (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS);
> 
> Or if you prefer have a define of
> 
> #define DECPROT_BITS_PER_ID (sizeof(u32) * BITS_PER_BYTE / IDS_PER_DECPROT_REGS)
> 
> and
> 	offset = (id % IDS_PER_DECPROT_REGS) * DECPROT_BITS_PER_ID;
> 

Ok I'll rework this for better understanding. Your suggestion seems fine

> +
> +	/* Verify peripheral is non-secure and attributed to cortex A7 */
> +	sec_val = (readl(pdata->sys_bus_base + reg_offset) >> offset) & ETZPC_PROT_MASK;
> +	if (sec_val != ETZPC_PROT_A7NS) {
> +		dev_dbg(pdata->dev, "Invalid bus configuration: reg_offset %#x, value %d\n",
> +			reg_offset, sec_val);
> +		return -EACCES;
> +	}
> +
> +	return 0;
> +}
> +
> ...
> 
>> +static int stm32_sys_bus_probe(struct platform_device *pdev)
>> +{
>> +	struct sys_bus_data *pdata;
>> +	void __iomem *mmio;
>> +	struct device_node *np = pdev->dev.of_node;
> 
> I'd be consistent. You use dev_of_node() accessor elsewhere, so should
> use it here as well >> +
>> +	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
>> +	if (!pdata)
>> +		return -ENOMEM;
>> +
>> +	mmio = devm_platform_ioremap_resource(pdev, 0);
>> +	if (IS_ERR(mmio))
>> +		return PTR_ERR(mmio);
>> +
>> +	pdata->sys_bus_base = mmio;
>> +	pdata->pconf = of_device_get_match_data(&pdev->dev);
>> +	pdata->dev = &pdev->dev;
>> +
>> +	platform_set_drvdata(pdev, pdata);
> 
> Does this get used? I can't immediately spot where but maybe I just
> missed it.
> 

Not for now :)

>> +
>> +	stm32_sys_bus_populate(pdata);
>> +
>> +	/* Populate all available nodes */
>> +	return of_platform_populate(np, NULL, NULL, &pdev->dev);
> 
> As np only used here, I'd not bother with the local variable in this function.
> 

Agreed

>> +}
>> +
>> +static const struct stm32_sys_bus_match_data stm32mp15_sys_bus_data = {
> 
> Naming a structure after where it comes from is a little unusual and
> confusion when a given call gets it from somewhere else.
> 
> I'd expect it to be named after what sort of thing it contains.
> stm32_sys_bus_info or something like that.
> 

Then, this shall be removed thanks to the read to hardware registers.

>> +	.max_entries = STM32MP15_ETZPC_ENTRIES,
>> +};
>> +
>> +static const struct stm32_sys_bus_match_data stm32mp13_sys_bus_data = {
>> +	.max_entries = STM32MP13_ETZPC_ENTRIES,
>> +};
>> +
>> +static const struct of_device_id stm32_sys_bus_of_match[] = {
>> +	{ .compatible = "st,stm32mp15-sys-bus", .data = &stm32mp15_sys_bus_data },
>> +	{ .compatible = "st,stm32mp13-sys-bus", .data = &stm32mp13_sys_bus_data },
> 
> Alphabetical order usually preferred when there isn't a strong reason for
> another choice.
> 

I second that

>> +	{}
>> +};
>> +MODULE_DEVICE_TABLE(of, stm32_sys_bus_of_match);
>> +
>> +static struct platform_driver stm32_sys_bus_driver = {
>> +	.probe  = stm32_sys_bus_probe,
>> +	.driver = {
>> +		.name = "stm32-sys-bus",
>> +		.of_match_table = stm32_sys_bus_of_match,
>> +	},
>> +};
>> +
>> +static int __init stm32_sys_bus_init(void)
>> +{
>> +	return platform_driver_register(&stm32_sys_bus_driver);
>> +}
>> +arch_initcall(stm32_sys_bus_init);
>> +
> 
> Unwanted trailing blank line.
> 

Good spot, thanks

> 

Best regards,
Gatien

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
  2023-02-07 14:12       ` Gatien CHEVALLIER
  (?)
  (?)
@ 2023-02-08 19:08         ` Jonathan Cameron
  -1 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-02-08 19:08 UTC (permalink / raw)
  To: Gatien CHEVALLIER
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Tue, 7 Feb 2023 15:12:23 +0100
Gatien CHEVALLIER <gatien.chevallier@foss.st.com> wrote:

> Hi Jonathan,
> 
> On 1/28/23 17:12, Jonathan Cameron wrote:
> > On Fri, 27 Jan 2023 17:40:38 +0100
> > Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> >   
> >> This driver is checking the access rights of the different
> >> peripherals connected to the system bus. If access is denied,
> >> the associated device tree node is skipped so the platform bus
> >> does not probe it.
> >>
> >> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> >> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>  
> > 
> > Hi Gatien,
> > 
> > A few comments inline,
> > 
> > Thanks,
> > 
> > Jonathan
> >   
> >> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
> >> new file mode 100644
> >> index 000000000000..c12926466bae
> >> --- /dev/null
> >> +++ b/drivers/bus/stm32_sys_bus.c
> >> @@ -0,0 +1,168 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
> >> + */
> >> +
> >> +#include <linux/bitfield.h>
> >> +#include <linux/bits.h>
> >> +#include <linux/device.h>
> >> +#include <linux/err.h>
> >> +#include <linux/io.h>
> >> +#include <linux/init.h>
> >> +#include <linux/kernel.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of.h>
> >> +#include <linux/of_platform.h>
> >> +#include <linux/platform_device.h>
> >> +
> >> +/* ETZPC peripheral as firewall bus */
> >> +/* ETZPC registers */
> >> +#define ETZPC_DECPROT			0x10
> >> +
> >> +/* ETZPC miscellaneous */
> >> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
> >> +#define ETZPC_PROT_A7NS			0x3
> >> +#define ETZPC_DECPROT_SHIFT		1  
> > 
> > This define makes the code harder to read.  What we care about is
> > the number of bits in the register divided by number of entries.
> > (which is 2) hence the shift by 1. See below for more on this.
> > 
> >   
> >> +
> >> +#define IDS_PER_DECPROT_REGS		16  
> >   
> >> +#define STM32MP15_ETZPC_ENTRIES		96
> >> +#define STM32MP13_ETZPC_ENTRIES		64  
> > 
> > These defines just make the code harder to check.
> > They aren't magic numbers, but rather just telling us how many
> > entries there are, so I would just put them in the structures directly.
> > Their use make it clear what they are without needing to give them a name.
> >   
> 
> Honestly, I'd rather read the hardware configuration registers to get 
> this information instead of differentiating MP13/15. Would you agree on 
> that?

Sure, if they are discoverable even better.



^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-02-08 19:08         ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-02-08 19:08 UTC (permalink / raw)
  To: Gatien CHEVALLIER
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Tue, 7 Feb 2023 15:12:23 +0100
Gatien CHEVALLIER <gatien.chevallier@foss.st.com> wrote:

> Hi Jonathan,
> 
> On 1/28/23 17:12, Jonathan Cameron wrote:
> > On Fri, 27 Jan 2023 17:40:38 +0100
> > Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> >   
> >> This driver is checking the access rights of the different
> >> peripherals connected to the system bus. If access is denied,
> >> the associated device tree node is skipped so the platform bus
> >> does not probe it.
> >>
> >> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> >> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>  
> > 
> > Hi Gatien,
> > 
> > A few comments inline,
> > 
> > Thanks,
> > 
> > Jonathan
> >   
> >> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
> >> new file mode 100644
> >> index 000000000000..c12926466bae
> >> --- /dev/null
> >> +++ b/drivers/bus/stm32_sys_bus.c
> >> @@ -0,0 +1,168 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
> >> + */
> >> +
> >> +#include <linux/bitfield.h>
> >> +#include <linux/bits.h>
> >> +#include <linux/device.h>
> >> +#include <linux/err.h>
> >> +#include <linux/io.h>
> >> +#include <linux/init.h>
> >> +#include <linux/kernel.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of.h>
> >> +#include <linux/of_platform.h>
> >> +#include <linux/platform_device.h>
> >> +
> >> +/* ETZPC peripheral as firewall bus */
> >> +/* ETZPC registers */
> >> +#define ETZPC_DECPROT			0x10
> >> +
> >> +/* ETZPC miscellaneous */
> >> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
> >> +#define ETZPC_PROT_A7NS			0x3
> >> +#define ETZPC_DECPROT_SHIFT		1  
> > 
> > This define makes the code harder to read.  What we care about is
> > the number of bits in the register divided by number of entries.
> > (which is 2) hence the shift by 1. See below for more on this.
> > 
> >   
> >> +
> >> +#define IDS_PER_DECPROT_REGS		16  
> >   
> >> +#define STM32MP15_ETZPC_ENTRIES		96
> >> +#define STM32MP13_ETZPC_ENTRIES		64  
> > 
> > These defines just make the code harder to check.
> > They aren't magic numbers, but rather just telling us how many
> > entries there are, so I would just put them in the structures directly.
> > Their use make it clear what they are without needing to give them a name.
> >   
> 
> Honestly, I'd rather read the hardware configuration registers to get 
> this information instead of differentiating MP13/15. Would you agree on 
> that?

Sure, if they are discoverable even better.



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-02-08 19:08         ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-02-08 19:08 UTC (permalink / raw)
  To: Gatien CHEVALLIER
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Tue, 7 Feb 2023 15:12:23 +0100
Gatien CHEVALLIER <gatien.chevallier@foss.st.com> wrote:

> Hi Jonathan,
> 
> On 1/28/23 17:12, Jonathan Cameron wrote:
> > On Fri, 27 Jan 2023 17:40:38 +0100
> > Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> >   
> >> This driver is checking the access rights of the different
> >> peripherals connected to the system bus. If access is denied,
> >> the associated device tree node is skipped so the platform bus
> >> does not probe it.
> >>
> >> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> >> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>  
> > 
> > Hi Gatien,
> > 
> > A few comments inline,
> > 
> > Thanks,
> > 
> > Jonathan
> >   
> >> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
> >> new file mode 100644
> >> index 000000000000..c12926466bae
> >> --- /dev/null
> >> +++ b/drivers/bus/stm32_sys_bus.c
> >> @@ -0,0 +1,168 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
> >> + */
> >> +
> >> +#include <linux/bitfield.h>
> >> +#include <linux/bits.h>
> >> +#include <linux/device.h>
> >> +#include <linux/err.h>
> >> +#include <linux/io.h>
> >> +#include <linux/init.h>
> >> +#include <linux/kernel.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of.h>
> >> +#include <linux/of_platform.h>
> >> +#include <linux/platform_device.h>
> >> +
> >> +/* ETZPC peripheral as firewall bus */
> >> +/* ETZPC registers */
> >> +#define ETZPC_DECPROT			0x10
> >> +
> >> +/* ETZPC miscellaneous */
> >> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
> >> +#define ETZPC_PROT_A7NS			0x3
> >> +#define ETZPC_DECPROT_SHIFT		1  
> > 
> > This define makes the code harder to read.  What we care about is
> > the number of bits in the register divided by number of entries.
> > (which is 2) hence the shift by 1. See below for more on this.
> > 
> >   
> >> +
> >> +#define IDS_PER_DECPROT_REGS		16  
> >   
> >> +#define STM32MP15_ETZPC_ENTRIES		96
> >> +#define STM32MP13_ETZPC_ENTRIES		64  
> > 
> > These defines just make the code harder to check.
> > They aren't magic numbers, but rather just telling us how many
> > entries there are, so I would just put them in the structures directly.
> > Their use make it clear what they are without needing to give them a name.
> >   
> 
> Honestly, I'd rather read the hardware configuration registers to get 
> this information instead of differentiating MP13/15. Would you agree on 
> that?

Sure, if they are discoverable even better.



-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
@ 2023-02-08 19:08         ` Jonathan Cameron
  0 siblings, 0 replies; 93+ messages in thread
From: Jonathan Cameron @ 2023-02-08 19:08 UTC (permalink / raw)
  To: Gatien CHEVALLIER
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, olivier.moysan,
	arnaud.pouliquen, mchehab, fabrice.gasnier, ulf.hansson,
	edumazet, kuba, pabeni, linux-crypto, devicetree, linux-stm32,
	linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
	alsa-devel, linux-media, linux-mmc, netdev, linux-phy,
	linux-serial, linux-spi, linux-usb, Loic PALLARDY

On Tue, 7 Feb 2023 15:12:23 +0100
Gatien CHEVALLIER <gatien.chevallier@foss.st.com> wrote:

> Hi Jonathan,
> 
> On 1/28/23 17:12, Jonathan Cameron wrote:
> > On Fri, 27 Jan 2023 17:40:38 +0100
> > Gatien Chevallier <gatien.chevallier@foss.st.com> wrote:
> >   
> >> This driver is checking the access rights of the different
> >> peripherals connected to the system bus. If access is denied,
> >> the associated device tree node is skipped so the platform bus
> >> does not probe it.
> >>
> >> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> >> Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>  
> > 
> > Hi Gatien,
> > 
> > A few comments inline,
> > 
> > Thanks,
> > 
> > Jonathan
> >   
> >> diff --git a/drivers/bus/stm32_sys_bus.c b/drivers/bus/stm32_sys_bus.c
> >> new file mode 100644
> >> index 000000000000..c12926466bae
> >> --- /dev/null
> >> +++ b/drivers/bus/stm32_sys_bus.c
> >> @@ -0,0 +1,168 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
> >> + */
> >> +
> >> +#include <linux/bitfield.h>
> >> +#include <linux/bits.h>
> >> +#include <linux/device.h>
> >> +#include <linux/err.h>
> >> +#include <linux/io.h>
> >> +#include <linux/init.h>
> >> +#include <linux/kernel.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of.h>
> >> +#include <linux/of_platform.h>
> >> +#include <linux/platform_device.h>
> >> +
> >> +/* ETZPC peripheral as firewall bus */
> >> +/* ETZPC registers */
> >> +#define ETZPC_DECPROT			0x10
> >> +
> >> +/* ETZPC miscellaneous */
> >> +#define ETZPC_PROT_MASK			GENMASK(1, 0)
> >> +#define ETZPC_PROT_A7NS			0x3
> >> +#define ETZPC_DECPROT_SHIFT		1  
> > 
> > This define makes the code harder to read.  What we care about is
> > the number of bits in the register divided by number of entries.
> > (which is 2) hence the shift by 1. See below for more on this.
> > 
> >   
> >> +
> >> +#define IDS_PER_DECPROT_REGS		16  
> >   
> >> +#define STM32MP15_ETZPC_ENTRIES		96
> >> +#define STM32MP13_ETZPC_ENTRIES		64  
> > 
> > These defines just make the code harder to check.
> > They aren't magic numbers, but rather just telling us how many
> > entries there are, so I would just put them in the structures directly.
> > Their use make it clear what they are without needing to give them a name.
> >   
> 
> Honestly, I'd rather read the hardware configuration registers to get 
> this information instead of differentiating MP13/15. Would you agree on 
> that?

Sure, if they are discoverable even better.



^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  2023-01-27 16:40   ` Gatien Chevallier
  (?)
@ 2023-02-09  7:46     ` Ahmad Fatoum
  -1 siblings, 0 replies; 93+ messages in thread
From: Ahmad Fatoum @ 2023-02-09  7:46 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-phy, linux-crypto, linux-serial,
	dmaengine, linux-media, linux-stm32, linux-arm-kernel, linux-i2c

Hello Gatien,

On 27.01.23 17:40, Gatien Chevallier wrote:
> The STM32 System Bus is an internal bus on which devices are connected.
> ETZPC is a peripheral overseeing the firewall bus that configures
> and control access to the peripherals connected on it.
> 
> For more information on which peripheral is securable, please read
> the STM32MP13 reference manual.

Diff is way too big. Please split up the alphabetic reordering into its
own commit, so actual functional changes are apparent.

Thanks,
Ahmad

> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
> 
> No changes in V2.
> 
> Changes in V3:
> 	-Use appriopriate node name: bus
> 
>  arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>  arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>  arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>  arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>  4 files changed, 258 insertions(+), 237 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
> index accc3824f7e9..24462a647101 100644
> --- a/arch/arm/boot/dts/stm32mp131.dtsi
> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>  			dma-channels = <16>;
>  		};
>  
> -		adc_2: adc@48004000 {
> -			compatible = "st,stm32mp13-adc-core";
> -			reg = <0x48004000 0x400>;
> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
> -			clock-names = "bus", "adc";
> -			interrupt-controller;
> -			#interrupt-cells = <1>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			status = "disabled";
> -
> -			adc2: adc@0 {
> -				compatible = "st,stm32mp13-adc";
> -				#io-channel-cells = <1>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				reg = <0x0>;
> -				interrupt-parent = <&adc_2>;
> -				interrupts = <0>;
> -				dmas = <&dmamux1 10 0x400 0x80000001>;
> -				dma-names = "rx";
> -				status = "disabled";
> -
> -				channel@13 {
> -					reg = <13>;
> -					label = "vrefint";
> -				};
> -				channel@14 {
> -					reg = <14>;
> -					label = "vddcore";
> -				};
> -				channel@16 {
> -					reg = <16>;
> -					label = "vddcpu";
> -				};
> -				channel@17 {
> -					reg = <17>;
> -					label = "vddq_ddr";
> -				};
> -			};
> -		};
> -
> -		usbotg_hs: usb@49000000 {
> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
> -			reg = <0x49000000 0x40000>;
> -			clocks = <&rcc USBO_K>;
> -			clock-names = "otg";
> -			resets = <&rcc USBO_R>;
> -			reset-names = "dwc2";
> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> -			g-rx-fifo-size = <512>;
> -			g-np-tx-fifo-size = <32>;
> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
> -			dr_mode = "otg";
> -			otg-rev = <0x200>;
> -			usb33d-supply = <&usb33>;
> -			status = "disabled";
> -		};
> -
> -		spi4: spi@4c002000 {
> -			compatible = "st,stm32h7-spi";
> -			reg = <0x4c002000 0x400>;
> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SPI4_K>;
> -			resets = <&rcc SPI4_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 83 0x400 0x01>,
> -			       <&dmamux1 84 0x400 0x01>;
> -			dma-names = "rx", "tx";
> -			status = "disabled";
> -		};
> -
> -		spi5: spi@4c003000 {
> -			compatible = "st,stm32h7-spi";
> -			reg = <0x4c003000 0x400>;
> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SPI5_K>;
> -			resets = <&rcc SPI5_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 85 0x400 0x01>,
> -			       <&dmamux1 86 0x400 0x01>;
> -			dma-names = "rx", "tx";
> -			status = "disabled";
> -		};
> -
> -		i2c3: i2c@4c004000 {
> -			compatible = "st,stm32mp13-i2c";
> -			reg = <0x4c004000 0x400>;
> -			interrupt-names = "event", "error";
> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc I2C3_K>;
> -			resets = <&rcc I2C3_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 73 0x400 0x1>,
> -			       <&dmamux1 74 0x400 0x1>;
> -			dma-names = "rx", "tx";
> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
> -			i2c-analog-filter;
> -			status = "disabled";
> -		};
> -
> -		i2c4: i2c@4c005000 {
> -			compatible = "st,stm32mp13-i2c";
> -			reg = <0x4c005000 0x400>;
> -			interrupt-names = "event", "error";
> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc I2C4_K>;
> -			resets = <&rcc I2C4_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 75 0x400 0x1>,
> -			       <&dmamux1 76 0x400 0x1>;
> -			dma-names = "rx", "tx";
> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
> -			i2c-analog-filter;
> -			status = "disabled";
> -		};
> -
> -		i2c5: i2c@4c006000 {
> -			compatible = "st,stm32mp13-i2c";
> -			reg = <0x4c006000 0x400>;
> -			interrupt-names = "event", "error";
> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc I2C5_K>;
> -			resets = <&rcc I2C5_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 115 0x400 0x1>,
> -			       <&dmamux1 116 0x400 0x1>;
> -			dma-names = "rx", "tx";
> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
> -			i2c-analog-filter;
> -			status = "disabled";
> -		};
> -
>  		rcc: rcc@50000000 {
>  			compatible = "st,stm32mp13-rcc", "syscon";
>  			reg = <0x50000000 0x1000>;
> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>  			dma-requests = <48>;
>  		};
>  
> -		sdmmc1: mmc@58005000 {
> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> -			arm,primecell-periphid = <0x20253180>;
> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SDMMC1_K>;
> -			clock-names = "apb_pclk";
> -			resets = <&rcc SDMMC1_R>;
> -			cap-sd-highspeed;
> -			cap-mmc-highspeed;
> -			max-frequency = <130000000>;
> -			status = "disabled";
> -		};
> -
> -		sdmmc2: mmc@58007000 {
> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> -			arm,primecell-periphid = <0x20253180>;
> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SDMMC2_K>;
> -			clock-names = "apb_pclk";
> -			resets = <&rcc SDMMC2_R>;
> -			cap-sd-highspeed;
> -			cap-mmc-highspeed;
> -			max-frequency = <130000000>;
> -			status = "disabled";
> -		};
> -
>  		usbh_ohci: usb@5800c000 {
>  			compatible = "generic-ohci";
>  			reg = <0x5800c000 0x1000>;
> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>  			status = "disabled";
>  		};
>  
> -		usbphyc: usbphyc@5a006000 {
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			#clock-cells = <0>;
> -			compatible = "st,stm32mp1-usbphyc";
> -			reg = <0x5a006000 0x1000>;
> -			clocks = <&rcc USBPHY_K>;
> -			resets = <&rcc USBPHY_R>;
> -			vdda1v1-supply = <&reg11>;
> -			vdda1v8-supply = <&reg18>;
> -			status = "disabled";
> -
> -			usbphyc_port0: usb-phy@0 {
> -				#phy-cells = <0>;
> -				reg = <0>;
> -			};
> -
> -			usbphyc_port1: usb-phy@1 {
> -				#phy-cells = <1>;
> -				reg = <1>;
> -			};
> -		};
> -
>  		rtc: rtc@5c004000 {
>  			compatible = "st,stm32mp1-rtc";
>  			reg = <0x5c004000 0x400>;
> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>  			};
>  		};
>  
> +		etzpc: bus@5c007000 {
> +			compatible = "st,stm32mp13-sys-bus";
> +			reg = <0x5c007000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			feature-domain-controller;
> +			#feature-domain-cells = <1>;
> +			ranges;
> +
> +			adc_2: adc@48004000 {
> +				compatible = "st,stm32mp13-adc-core";
> +				reg = <0x48004000 0x400>;
> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
> +				clock-names = "bus", "adc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				feature-domains = <&etzpc 33>;
> +				status = "disabled";
> +
> +				adc2: adc@0 {
> +					compatible = "st,stm32mp13-adc";
> +					#io-channel-cells = <1>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x0>;
> +					interrupt-parent = <&adc_2>;
> +					interrupts = <0>;
> +					dmas = <&dmamux1 10 0x400 0x80000001>;
> +					dma-names = "rx";
> +					status = "disabled";
> +
> +					channel@13 {
> +						reg = <13>;
> +						label = "vrefint";
> +					};
> +					channel@14 {
> +						reg = <14>;
> +						label = "vddcore";
> +					};
> +					channel@16 {
> +						reg = <16>;
> +						label = "vddcpu";
> +					};
> +					channel@17 {
> +						reg = <17>;
> +						label = "vddq_ddr";
> +					};
> +				};
> +			};
> +
> +			usbotg_hs: usb@49000000 {
> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
> +				reg = <0x49000000 0x40000>;
> +				clocks = <&rcc USBO_K>;
> +				clock-names = "otg";
> +				resets = <&rcc USBO_R>;
> +				reset-names = "dwc2";
> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +				g-rx-fifo-size = <512>;
> +				g-np-tx-fifo-size = <32>;
> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
> +				dr_mode = "otg";
> +				otg-rev = <0x200>;
> +				usb33d-supply = <&usb33>;
> +				feature-domains = <&etzpc 34>;
> +				status = "disabled";
> +			};
> +
> +			spi4: spi@4c002000 {
> +				compatible = "st,stm32h7-spi";
> +				reg = <0x4c002000 0x400>;
> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SPI4_K>;
> +				resets = <&rcc SPI4_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 83 0x400 0x01>,
> +				       <&dmamux1 84 0x400 0x01>;
> +				dma-names = "rx", "tx";
> +				feature-domains = <&etzpc 18>;
> +				status = "disabled";
> +			};
> +
> +			spi5: spi@4c003000 {
> +				compatible = "st,stm32h7-spi";
> +				reg = <0x4c003000 0x400>;
> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SPI5_K>;
> +				resets = <&rcc SPI5_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 85 0x400 0x01>,
> +				       <&dmamux1 86 0x400 0x01>;
> +				dma-names = "rx", "tx";
> +				feature-domains = <&etzpc 19>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c@4c004000 {
> +				compatible = "st,stm32mp13-i2c";
> +				reg = <0x4c004000 0x400>;
> +				interrupt-names = "event", "error";
> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc I2C3_K>;
> +				resets = <&rcc I2C3_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 73 0x400 0x1>,
> +				       <&dmamux1 74 0x400 0x1>;
> +				dma-names = "rx", "tx";
> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
> +				i2c-analog-filter;
> +				feature-domains = <&etzpc 20>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c@4c005000 {
> +				compatible = "st,stm32mp13-i2c";
> +				reg = <0x4c005000 0x400>;
> +				interrupt-names = "event", "error";
> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc I2C4_K>;
> +				resets = <&rcc I2C4_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 75 0x400 0x1>,
> +				       <&dmamux1 76 0x400 0x1>;
> +				dma-names = "rx", "tx";
> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
> +				i2c-analog-filter;
> +				feature-domains = <&etzpc 21>;
> +				status = "disabled";
> +			};
> +
> +			i2c5: i2c@4c006000 {
> +				compatible = "st,stm32mp13-i2c";
> +				reg = <0x4c006000 0x400>;
> +				interrupt-names = "event", "error";
> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc I2C5_K>;
> +				resets = <&rcc I2C5_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 115 0x400 0x1>,
> +				       <&dmamux1 116 0x400 0x1>;
> +				dma-names = "rx", "tx";
> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
> +				i2c-analog-filter;
> +				feature-domains = <&etzpc 22>;
> +				status = "disabled";
> +			};
> +
> +			sdmmc1: mmc@58005000 {
> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> +				arm,primecell-periphid = <0x20253180>;
> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SDMMC1_K>;
> +				clock-names = "apb_pclk";
> +				resets = <&rcc SDMMC1_R>;
> +				cap-sd-highspeed;
> +				cap-mmc-highspeed;
> +				max-frequency = <130000000>;
> +				feature-domains = <&etzpc 50>;
> +				status = "disabled";
> +			};
> +
> +			sdmmc2: mmc@58007000 {
> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> +				arm,primecell-periphid = <0x20253180>;
> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SDMMC2_K>;
> +				clock-names = "apb_pclk";
> +				resets = <&rcc SDMMC2_R>;
> +				cap-sd-highspeed;
> +				cap-mmc-highspeed;
> +				max-frequency = <130000000>;
> +				feature-domains = <&etzpc 51>;
> +				status = "disabled";
> +			};
> +
> +			usbphyc: usbphyc@5a006000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				#clock-cells = <0>;
> +				compatible = "st,stm32mp1-usbphyc";
> +				reg = <0x5a006000 0x1000>;
> +				clocks = <&rcc USBPHY_K>;
> +				resets = <&rcc USBPHY_R>;
> +				vdda1v1-supply = <&reg11>;
> +				vdda1v8-supply = <&reg18>;
> +				feature-domains = <&etzpc 5>;
> +				status = "disabled";
> +
> +				usbphyc_port0: usb-phy@0 {
> +					#phy-cells = <0>;
> +					reg = <0>;
> +				};
> +
> +				usbphyc_port1: usb-phy@1 {
> +					#phy-cells = <1>;
> +					reg = <1>;
> +				};
> +			};
> +
> +		};
> +
>  		/*
>  		 * Break node order to solve dependency probe issue between
>  		 * pinctrl and exti.
> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
> index df451c3c2a26..be6061552683 100644
> --- a/arch/arm/boot/dts/stm32mp133.dtsi
> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>  			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>  			status = "disabled";
>  		};
> +	};
> +};
>  
> -		adc_1: adc@48003000 {
> -			compatible = "st,stm32mp13-adc-core";
> -			reg = <0x48003000 0x400>;
> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
> -			clock-names = "bus", "adc";
> -			interrupt-controller;
> -			#interrupt-cells = <1>;
> +&etzpc {
> +	adc_1: adc@48003000 {
> +		compatible = "st,stm32mp13-adc-core";
> +		reg = <0x48003000 0x400>;
> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
> +		clock-names = "bus", "adc";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		feature-domains = <&etzpc 32>;
> +		status = "disabled";
> +
> +		adc1: adc@0 {
> +			compatible = "st,stm32mp13-adc";
> +			#io-channel-cells = <1>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> +			reg = <0x0>;
> +			interrupt-parent = <&adc_1>;
> +			interrupts = <0>;
> +			dmas = <&dmamux1 9 0x400 0x80000001>;
> +			dma-names = "rx";
>  			status = "disabled";
>  
> -			adc1: adc@0 {
> -				compatible = "st,stm32mp13-adc";
> -				#io-channel-cells = <1>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				reg = <0x0>;
> -				interrupt-parent = <&adc_1>;
> -				interrupts = <0>;
> -				dmas = <&dmamux1 9 0x400 0x80000001>;
> -				dma-names = "rx";
> -				status = "disabled";
> -
> -				channel@18 {
> -					reg = <18>;
> -					label = "vrefint";
> -				};
> +			channel@18 {
> +				reg = <18>;
> +				label = "vrefint";
>  			};
>  		};
>  	};
> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
> index 4d00e7592882..a1a7a40c2a3e 100644
> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
> @@ -4,15 +4,14 @@
>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>   */
>  
> -/ {
> -	soc {
> -		cryp: crypto@54002000 {
> -			compatible = "st,stm32mp1-cryp";
> -			reg = <0x54002000 0x400>;
> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc CRYP1>;
> -			resets = <&rcc CRYP1_R>;
> -			status = "disabled";
> -		};
> +&etzpc {
> +	cryp: crypto@54002000 {
> +		compatible = "st,stm32mp1-cryp";
> +		reg = <0x54002000 0x400>;
> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&rcc CRYP1>;
> +		resets = <&rcc CRYP1_R>;
> +		feature-domains = <&etzpc 42>;
> +		status = "disabled";
>  	};
>  };
> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
> index 4d00e7592882..b9fb071a1471 100644
> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
> @@ -4,15 +4,13 @@
>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>   */
>  
> -/ {
> -	soc {
> -		cryp: crypto@54002000 {
> -			compatible = "st,stm32mp1-cryp";
> -			reg = <0x54002000 0x400>;
> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc CRYP1>;
> -			resets = <&rcc CRYP1_R>;
> -			status = "disabled";
> -		};
> +&etzpc {
> +	cryp: crypto@54002000 {
> +		compatible = "st,stm32mp1-cryp";
> +		reg = <0x54002000 0x400>;
> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&rcc CRYP1>;
> +		resets = <&rcc CRYP1_R>;
> +		status = "disabled";
>  	};
>  };

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-09  7:46     ` Ahmad Fatoum
  0 siblings, 0 replies; 93+ messages in thread
From: Ahmad Fatoum @ 2023-02-09  7:46 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-phy, linux-crypto, linux-serial,
	dmaengine, linux-media, linux-stm32, linux-arm-kernel, linux-i2c

Hello Gatien,

On 27.01.23 17:40, Gatien Chevallier wrote:
> The STM32 System Bus is an internal bus on which devices are connected.
> ETZPC is a peripheral overseeing the firewall bus that configures
> and control access to the peripherals connected on it.
> 
> For more information on which peripheral is securable, please read
> the STM32MP13 reference manual.

Diff is way too big. Please split up the alphabetic reordering into its
own commit, so actual functional changes are apparent.

Thanks,
Ahmad

> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
> 
> No changes in V2.
> 
> Changes in V3:
> 	-Use appriopriate node name: bus
> 
>  arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>  arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>  arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>  arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>  4 files changed, 258 insertions(+), 237 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
> index accc3824f7e9..24462a647101 100644
> --- a/arch/arm/boot/dts/stm32mp131.dtsi
> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>  			dma-channels = <16>;
>  		};
>  
> -		adc_2: adc@48004000 {
> -			compatible = "st,stm32mp13-adc-core";
> -			reg = <0x48004000 0x400>;
> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
> -			clock-names = "bus", "adc";
> -			interrupt-controller;
> -			#interrupt-cells = <1>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			status = "disabled";
> -
> -			adc2: adc@0 {
> -				compatible = "st,stm32mp13-adc";
> -				#io-channel-cells = <1>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				reg = <0x0>;
> -				interrupt-parent = <&adc_2>;
> -				interrupts = <0>;
> -				dmas = <&dmamux1 10 0x400 0x80000001>;
> -				dma-names = "rx";
> -				status = "disabled";
> -
> -				channel@13 {
> -					reg = <13>;
> -					label = "vrefint";
> -				};
> -				channel@14 {
> -					reg = <14>;
> -					label = "vddcore";
> -				};
> -				channel@16 {
> -					reg = <16>;
> -					label = "vddcpu";
> -				};
> -				channel@17 {
> -					reg = <17>;
> -					label = "vddq_ddr";
> -				};
> -			};
> -		};
> -
> -		usbotg_hs: usb@49000000 {
> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
> -			reg = <0x49000000 0x40000>;
> -			clocks = <&rcc USBO_K>;
> -			clock-names = "otg";
> -			resets = <&rcc USBO_R>;
> -			reset-names = "dwc2";
> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> -			g-rx-fifo-size = <512>;
> -			g-np-tx-fifo-size = <32>;
> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
> -			dr_mode = "otg";
> -			otg-rev = <0x200>;
> -			usb33d-supply = <&usb33>;
> -			status = "disabled";
> -		};
> -
> -		spi4: spi@4c002000 {
> -			compatible = "st,stm32h7-spi";
> -			reg = <0x4c002000 0x400>;
> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SPI4_K>;
> -			resets = <&rcc SPI4_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 83 0x400 0x01>,
> -			       <&dmamux1 84 0x400 0x01>;
> -			dma-names = "rx", "tx";
> -			status = "disabled";
> -		};
> -
> -		spi5: spi@4c003000 {
> -			compatible = "st,stm32h7-spi";
> -			reg = <0x4c003000 0x400>;
> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SPI5_K>;
> -			resets = <&rcc SPI5_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 85 0x400 0x01>,
> -			       <&dmamux1 86 0x400 0x01>;
> -			dma-names = "rx", "tx";
> -			status = "disabled";
> -		};
> -
> -		i2c3: i2c@4c004000 {
> -			compatible = "st,stm32mp13-i2c";
> -			reg = <0x4c004000 0x400>;
> -			interrupt-names = "event", "error";
> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc I2C3_K>;
> -			resets = <&rcc I2C3_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 73 0x400 0x1>,
> -			       <&dmamux1 74 0x400 0x1>;
> -			dma-names = "rx", "tx";
> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
> -			i2c-analog-filter;
> -			status = "disabled";
> -		};
> -
> -		i2c4: i2c@4c005000 {
> -			compatible = "st,stm32mp13-i2c";
> -			reg = <0x4c005000 0x400>;
> -			interrupt-names = "event", "error";
> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc I2C4_K>;
> -			resets = <&rcc I2C4_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 75 0x400 0x1>,
> -			       <&dmamux1 76 0x400 0x1>;
> -			dma-names = "rx", "tx";
> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
> -			i2c-analog-filter;
> -			status = "disabled";
> -		};
> -
> -		i2c5: i2c@4c006000 {
> -			compatible = "st,stm32mp13-i2c";
> -			reg = <0x4c006000 0x400>;
> -			interrupt-names = "event", "error";
> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc I2C5_K>;
> -			resets = <&rcc I2C5_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 115 0x400 0x1>,
> -			       <&dmamux1 116 0x400 0x1>;
> -			dma-names = "rx", "tx";
> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
> -			i2c-analog-filter;
> -			status = "disabled";
> -		};
> -
>  		rcc: rcc@50000000 {
>  			compatible = "st,stm32mp13-rcc", "syscon";
>  			reg = <0x50000000 0x1000>;
> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>  			dma-requests = <48>;
>  		};
>  
> -		sdmmc1: mmc@58005000 {
> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> -			arm,primecell-periphid = <0x20253180>;
> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SDMMC1_K>;
> -			clock-names = "apb_pclk";
> -			resets = <&rcc SDMMC1_R>;
> -			cap-sd-highspeed;
> -			cap-mmc-highspeed;
> -			max-frequency = <130000000>;
> -			status = "disabled";
> -		};
> -
> -		sdmmc2: mmc@58007000 {
> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> -			arm,primecell-periphid = <0x20253180>;
> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SDMMC2_K>;
> -			clock-names = "apb_pclk";
> -			resets = <&rcc SDMMC2_R>;
> -			cap-sd-highspeed;
> -			cap-mmc-highspeed;
> -			max-frequency = <130000000>;
> -			status = "disabled";
> -		};
> -
>  		usbh_ohci: usb@5800c000 {
>  			compatible = "generic-ohci";
>  			reg = <0x5800c000 0x1000>;
> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>  			status = "disabled";
>  		};
>  
> -		usbphyc: usbphyc@5a006000 {
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			#clock-cells = <0>;
> -			compatible = "st,stm32mp1-usbphyc";
> -			reg = <0x5a006000 0x1000>;
> -			clocks = <&rcc USBPHY_K>;
> -			resets = <&rcc USBPHY_R>;
> -			vdda1v1-supply = <&reg11>;
> -			vdda1v8-supply = <&reg18>;
> -			status = "disabled";
> -
> -			usbphyc_port0: usb-phy@0 {
> -				#phy-cells = <0>;
> -				reg = <0>;
> -			};
> -
> -			usbphyc_port1: usb-phy@1 {
> -				#phy-cells = <1>;
> -				reg = <1>;
> -			};
> -		};
> -
>  		rtc: rtc@5c004000 {
>  			compatible = "st,stm32mp1-rtc";
>  			reg = <0x5c004000 0x400>;
> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>  			};
>  		};
>  
> +		etzpc: bus@5c007000 {
> +			compatible = "st,stm32mp13-sys-bus";
> +			reg = <0x5c007000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			feature-domain-controller;
> +			#feature-domain-cells = <1>;
> +			ranges;
> +
> +			adc_2: adc@48004000 {
> +				compatible = "st,stm32mp13-adc-core";
> +				reg = <0x48004000 0x400>;
> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
> +				clock-names = "bus", "adc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				feature-domains = <&etzpc 33>;
> +				status = "disabled";
> +
> +				adc2: adc@0 {
> +					compatible = "st,stm32mp13-adc";
> +					#io-channel-cells = <1>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x0>;
> +					interrupt-parent = <&adc_2>;
> +					interrupts = <0>;
> +					dmas = <&dmamux1 10 0x400 0x80000001>;
> +					dma-names = "rx";
> +					status = "disabled";
> +
> +					channel@13 {
> +						reg = <13>;
> +						label = "vrefint";
> +					};
> +					channel@14 {
> +						reg = <14>;
> +						label = "vddcore";
> +					};
> +					channel@16 {
> +						reg = <16>;
> +						label = "vddcpu";
> +					};
> +					channel@17 {
> +						reg = <17>;
> +						label = "vddq_ddr";
> +					};
> +				};
> +			};
> +
> +			usbotg_hs: usb@49000000 {
> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
> +				reg = <0x49000000 0x40000>;
> +				clocks = <&rcc USBO_K>;
> +				clock-names = "otg";
> +				resets = <&rcc USBO_R>;
> +				reset-names = "dwc2";
> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +				g-rx-fifo-size = <512>;
> +				g-np-tx-fifo-size = <32>;
> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
> +				dr_mode = "otg";
> +				otg-rev = <0x200>;
> +				usb33d-supply = <&usb33>;
> +				feature-domains = <&etzpc 34>;
> +				status = "disabled";
> +			};
> +
> +			spi4: spi@4c002000 {
> +				compatible = "st,stm32h7-spi";
> +				reg = <0x4c002000 0x400>;
> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SPI4_K>;
> +				resets = <&rcc SPI4_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 83 0x400 0x01>,
> +				       <&dmamux1 84 0x400 0x01>;
> +				dma-names = "rx", "tx";
> +				feature-domains = <&etzpc 18>;
> +				status = "disabled";
> +			};
> +
> +			spi5: spi@4c003000 {
> +				compatible = "st,stm32h7-spi";
> +				reg = <0x4c003000 0x400>;
> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SPI5_K>;
> +				resets = <&rcc SPI5_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 85 0x400 0x01>,
> +				       <&dmamux1 86 0x400 0x01>;
> +				dma-names = "rx", "tx";
> +				feature-domains = <&etzpc 19>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c@4c004000 {
> +				compatible = "st,stm32mp13-i2c";
> +				reg = <0x4c004000 0x400>;
> +				interrupt-names = "event", "error";
> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc I2C3_K>;
> +				resets = <&rcc I2C3_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 73 0x400 0x1>,
> +				       <&dmamux1 74 0x400 0x1>;
> +				dma-names = "rx", "tx";
> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
> +				i2c-analog-filter;
> +				feature-domains = <&etzpc 20>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c@4c005000 {
> +				compatible = "st,stm32mp13-i2c";
> +				reg = <0x4c005000 0x400>;
> +				interrupt-names = "event", "error";
> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc I2C4_K>;
> +				resets = <&rcc I2C4_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 75 0x400 0x1>,
> +				       <&dmamux1 76 0x400 0x1>;
> +				dma-names = "rx", "tx";
> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
> +				i2c-analog-filter;
> +				feature-domains = <&etzpc 21>;
> +				status = "disabled";
> +			};
> +
> +			i2c5: i2c@4c006000 {
> +				compatible = "st,stm32mp13-i2c";
> +				reg = <0x4c006000 0x400>;
> +				interrupt-names = "event", "error";
> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc I2C5_K>;
> +				resets = <&rcc I2C5_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 115 0x400 0x1>,
> +				       <&dmamux1 116 0x400 0x1>;
> +				dma-names = "rx", "tx";
> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
> +				i2c-analog-filter;
> +				feature-domains = <&etzpc 22>;
> +				status = "disabled";
> +			};
> +
> +			sdmmc1: mmc@58005000 {
> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> +				arm,primecell-periphid = <0x20253180>;
> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SDMMC1_K>;
> +				clock-names = "apb_pclk";
> +				resets = <&rcc SDMMC1_R>;
> +				cap-sd-highspeed;
> +				cap-mmc-highspeed;
> +				max-frequency = <130000000>;
> +				feature-domains = <&etzpc 50>;
> +				status = "disabled";
> +			};
> +
> +			sdmmc2: mmc@58007000 {
> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> +				arm,primecell-periphid = <0x20253180>;
> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SDMMC2_K>;
> +				clock-names = "apb_pclk";
> +				resets = <&rcc SDMMC2_R>;
> +				cap-sd-highspeed;
> +				cap-mmc-highspeed;
> +				max-frequency = <130000000>;
> +				feature-domains = <&etzpc 51>;
> +				status = "disabled";
> +			};
> +
> +			usbphyc: usbphyc@5a006000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				#clock-cells = <0>;
> +				compatible = "st,stm32mp1-usbphyc";
> +				reg = <0x5a006000 0x1000>;
> +				clocks = <&rcc USBPHY_K>;
> +				resets = <&rcc USBPHY_R>;
> +				vdda1v1-supply = <&reg11>;
> +				vdda1v8-supply = <&reg18>;
> +				feature-domains = <&etzpc 5>;
> +				status = "disabled";
> +
> +				usbphyc_port0: usb-phy@0 {
> +					#phy-cells = <0>;
> +					reg = <0>;
> +				};
> +
> +				usbphyc_port1: usb-phy@1 {
> +					#phy-cells = <1>;
> +					reg = <1>;
> +				};
> +			};
> +
> +		};
> +
>  		/*
>  		 * Break node order to solve dependency probe issue between
>  		 * pinctrl and exti.
> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
> index df451c3c2a26..be6061552683 100644
> --- a/arch/arm/boot/dts/stm32mp133.dtsi
> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>  			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>  			status = "disabled";
>  		};
> +	};
> +};
>  
> -		adc_1: adc@48003000 {
> -			compatible = "st,stm32mp13-adc-core";
> -			reg = <0x48003000 0x400>;
> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
> -			clock-names = "bus", "adc";
> -			interrupt-controller;
> -			#interrupt-cells = <1>;
> +&etzpc {
> +	adc_1: adc@48003000 {
> +		compatible = "st,stm32mp13-adc-core";
> +		reg = <0x48003000 0x400>;
> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
> +		clock-names = "bus", "adc";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		feature-domains = <&etzpc 32>;
> +		status = "disabled";
> +
> +		adc1: adc@0 {
> +			compatible = "st,stm32mp13-adc";
> +			#io-channel-cells = <1>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> +			reg = <0x0>;
> +			interrupt-parent = <&adc_1>;
> +			interrupts = <0>;
> +			dmas = <&dmamux1 9 0x400 0x80000001>;
> +			dma-names = "rx";
>  			status = "disabled";
>  
> -			adc1: adc@0 {
> -				compatible = "st,stm32mp13-adc";
> -				#io-channel-cells = <1>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				reg = <0x0>;
> -				interrupt-parent = <&adc_1>;
> -				interrupts = <0>;
> -				dmas = <&dmamux1 9 0x400 0x80000001>;
> -				dma-names = "rx";
> -				status = "disabled";
> -
> -				channel@18 {
> -					reg = <18>;
> -					label = "vrefint";
> -				};
> +			channel@18 {
> +				reg = <18>;
> +				label = "vrefint";
>  			};
>  		};
>  	};
> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
> index 4d00e7592882..a1a7a40c2a3e 100644
> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
> @@ -4,15 +4,14 @@
>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>   */
>  
> -/ {
> -	soc {
> -		cryp: crypto@54002000 {
> -			compatible = "st,stm32mp1-cryp";
> -			reg = <0x54002000 0x400>;
> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc CRYP1>;
> -			resets = <&rcc CRYP1_R>;
> -			status = "disabled";
> -		};
> +&etzpc {
> +	cryp: crypto@54002000 {
> +		compatible = "st,stm32mp1-cryp";
> +		reg = <0x54002000 0x400>;
> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&rcc CRYP1>;
> +		resets = <&rcc CRYP1_R>;
> +		feature-domains = <&etzpc 42>;
> +		status = "disabled";
>  	};
>  };
> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
> index 4d00e7592882..b9fb071a1471 100644
> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
> @@ -4,15 +4,13 @@
>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>   */
>  
> -/ {
> -	soc {
> -		cryp: crypto@54002000 {
> -			compatible = "st,stm32mp1-cryp";
> -			reg = <0x54002000 0x400>;
> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc CRYP1>;
> -			resets = <&rcc CRYP1_R>;
> -			status = "disabled";
> -		};
> +&etzpc {
> +	cryp: crypto@54002000 {
> +		compatible = "st,stm32mp1-cryp";
> +		reg = <0x54002000 0x400>;
> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&rcc CRYP1>;
> +		resets = <&rcc CRYP1_R>;
> +		status = "disabled";
>  	};
>  };

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-09  7:46     ` Ahmad Fatoum
  0 siblings, 0 replies; 93+ messages in thread
From: Ahmad Fatoum @ 2023-02-09  7:46 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-phy, linux-crypto, linux-serial,
	dmaengine, linux-media, linux-stm32, linux-arm-kernel, linux-i2c

Hello Gatien,

On 27.01.23 17:40, Gatien Chevallier wrote:
> The STM32 System Bus is an internal bus on which devices are connected.
> ETZPC is a peripheral overseeing the firewall bus that configures
> and control access to the peripherals connected on it.
> 
> For more information on which peripheral is securable, please read
> the STM32MP13 reference manual.

Diff is way too big. Please split up the alphabetic reordering into its
own commit, so actual functional changes are apparent.

Thanks,
Ahmad

> 
> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
> ---
> 
> No changes in V2.
> 
> Changes in V3:
> 	-Use appriopriate node name: bus
> 
>  arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>  arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>  arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>  arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>  4 files changed, 258 insertions(+), 237 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
> index accc3824f7e9..24462a647101 100644
> --- a/arch/arm/boot/dts/stm32mp131.dtsi
> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>  			dma-channels = <16>;
>  		};
>  
> -		adc_2: adc@48004000 {
> -			compatible = "st,stm32mp13-adc-core";
> -			reg = <0x48004000 0x400>;
> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
> -			clock-names = "bus", "adc";
> -			interrupt-controller;
> -			#interrupt-cells = <1>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			status = "disabled";
> -
> -			adc2: adc@0 {
> -				compatible = "st,stm32mp13-adc";
> -				#io-channel-cells = <1>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				reg = <0x0>;
> -				interrupt-parent = <&adc_2>;
> -				interrupts = <0>;
> -				dmas = <&dmamux1 10 0x400 0x80000001>;
> -				dma-names = "rx";
> -				status = "disabled";
> -
> -				channel@13 {
> -					reg = <13>;
> -					label = "vrefint";
> -				};
> -				channel@14 {
> -					reg = <14>;
> -					label = "vddcore";
> -				};
> -				channel@16 {
> -					reg = <16>;
> -					label = "vddcpu";
> -				};
> -				channel@17 {
> -					reg = <17>;
> -					label = "vddq_ddr";
> -				};
> -			};
> -		};
> -
> -		usbotg_hs: usb@49000000 {
> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
> -			reg = <0x49000000 0x40000>;
> -			clocks = <&rcc USBO_K>;
> -			clock-names = "otg";
> -			resets = <&rcc USBO_R>;
> -			reset-names = "dwc2";
> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> -			g-rx-fifo-size = <512>;
> -			g-np-tx-fifo-size = <32>;
> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
> -			dr_mode = "otg";
> -			otg-rev = <0x200>;
> -			usb33d-supply = <&usb33>;
> -			status = "disabled";
> -		};
> -
> -		spi4: spi@4c002000 {
> -			compatible = "st,stm32h7-spi";
> -			reg = <0x4c002000 0x400>;
> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SPI4_K>;
> -			resets = <&rcc SPI4_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 83 0x400 0x01>,
> -			       <&dmamux1 84 0x400 0x01>;
> -			dma-names = "rx", "tx";
> -			status = "disabled";
> -		};
> -
> -		spi5: spi@4c003000 {
> -			compatible = "st,stm32h7-spi";
> -			reg = <0x4c003000 0x400>;
> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SPI5_K>;
> -			resets = <&rcc SPI5_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 85 0x400 0x01>,
> -			       <&dmamux1 86 0x400 0x01>;
> -			dma-names = "rx", "tx";
> -			status = "disabled";
> -		};
> -
> -		i2c3: i2c@4c004000 {
> -			compatible = "st,stm32mp13-i2c";
> -			reg = <0x4c004000 0x400>;
> -			interrupt-names = "event", "error";
> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc I2C3_K>;
> -			resets = <&rcc I2C3_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 73 0x400 0x1>,
> -			       <&dmamux1 74 0x400 0x1>;
> -			dma-names = "rx", "tx";
> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
> -			i2c-analog-filter;
> -			status = "disabled";
> -		};
> -
> -		i2c4: i2c@4c005000 {
> -			compatible = "st,stm32mp13-i2c";
> -			reg = <0x4c005000 0x400>;
> -			interrupt-names = "event", "error";
> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc I2C4_K>;
> -			resets = <&rcc I2C4_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 75 0x400 0x1>,
> -			       <&dmamux1 76 0x400 0x1>;
> -			dma-names = "rx", "tx";
> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
> -			i2c-analog-filter;
> -			status = "disabled";
> -		};
> -
> -		i2c5: i2c@4c006000 {
> -			compatible = "st,stm32mp13-i2c";
> -			reg = <0x4c006000 0x400>;
> -			interrupt-names = "event", "error";
> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc I2C5_K>;
> -			resets = <&rcc I2C5_R>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			dmas = <&dmamux1 115 0x400 0x1>,
> -			       <&dmamux1 116 0x400 0x1>;
> -			dma-names = "rx", "tx";
> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
> -			i2c-analog-filter;
> -			status = "disabled";
> -		};
> -
>  		rcc: rcc@50000000 {
>  			compatible = "st,stm32mp13-rcc", "syscon";
>  			reg = <0x50000000 0x1000>;
> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>  			dma-requests = <48>;
>  		};
>  
> -		sdmmc1: mmc@58005000 {
> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> -			arm,primecell-periphid = <0x20253180>;
> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SDMMC1_K>;
> -			clock-names = "apb_pclk";
> -			resets = <&rcc SDMMC1_R>;
> -			cap-sd-highspeed;
> -			cap-mmc-highspeed;
> -			max-frequency = <130000000>;
> -			status = "disabled";
> -		};
> -
> -		sdmmc2: mmc@58007000 {
> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> -			arm,primecell-periphid = <0x20253180>;
> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc SDMMC2_K>;
> -			clock-names = "apb_pclk";
> -			resets = <&rcc SDMMC2_R>;
> -			cap-sd-highspeed;
> -			cap-mmc-highspeed;
> -			max-frequency = <130000000>;
> -			status = "disabled";
> -		};
> -
>  		usbh_ohci: usb@5800c000 {
>  			compatible = "generic-ohci";
>  			reg = <0x5800c000 0x1000>;
> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>  			status = "disabled";
>  		};
>  
> -		usbphyc: usbphyc@5a006000 {
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -			#clock-cells = <0>;
> -			compatible = "st,stm32mp1-usbphyc";
> -			reg = <0x5a006000 0x1000>;
> -			clocks = <&rcc USBPHY_K>;
> -			resets = <&rcc USBPHY_R>;
> -			vdda1v1-supply = <&reg11>;
> -			vdda1v8-supply = <&reg18>;
> -			status = "disabled";
> -
> -			usbphyc_port0: usb-phy@0 {
> -				#phy-cells = <0>;
> -				reg = <0>;
> -			};
> -
> -			usbphyc_port1: usb-phy@1 {
> -				#phy-cells = <1>;
> -				reg = <1>;
> -			};
> -		};
> -
>  		rtc: rtc@5c004000 {
>  			compatible = "st,stm32mp1-rtc";
>  			reg = <0x5c004000 0x400>;
> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>  			};
>  		};
>  
> +		etzpc: bus@5c007000 {
> +			compatible = "st,stm32mp13-sys-bus";
> +			reg = <0x5c007000 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			feature-domain-controller;
> +			#feature-domain-cells = <1>;
> +			ranges;
> +
> +			adc_2: adc@48004000 {
> +				compatible = "st,stm32mp13-adc-core";
> +				reg = <0x48004000 0x400>;
> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
> +				clock-names = "bus", "adc";
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				feature-domains = <&etzpc 33>;
> +				status = "disabled";
> +
> +				adc2: adc@0 {
> +					compatible = "st,stm32mp13-adc";
> +					#io-channel-cells = <1>;
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x0>;
> +					interrupt-parent = <&adc_2>;
> +					interrupts = <0>;
> +					dmas = <&dmamux1 10 0x400 0x80000001>;
> +					dma-names = "rx";
> +					status = "disabled";
> +
> +					channel@13 {
> +						reg = <13>;
> +						label = "vrefint";
> +					};
> +					channel@14 {
> +						reg = <14>;
> +						label = "vddcore";
> +					};
> +					channel@16 {
> +						reg = <16>;
> +						label = "vddcpu";
> +					};
> +					channel@17 {
> +						reg = <17>;
> +						label = "vddq_ddr";
> +					};
> +				};
> +			};
> +
> +			usbotg_hs: usb@49000000 {
> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
> +				reg = <0x49000000 0x40000>;
> +				clocks = <&rcc USBO_K>;
> +				clock-names = "otg";
> +				resets = <&rcc USBO_R>;
> +				reset-names = "dwc2";
> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +				g-rx-fifo-size = <512>;
> +				g-np-tx-fifo-size = <32>;
> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
> +				dr_mode = "otg";
> +				otg-rev = <0x200>;
> +				usb33d-supply = <&usb33>;
> +				feature-domains = <&etzpc 34>;
> +				status = "disabled";
> +			};
> +
> +			spi4: spi@4c002000 {
> +				compatible = "st,stm32h7-spi";
> +				reg = <0x4c002000 0x400>;
> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SPI4_K>;
> +				resets = <&rcc SPI4_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 83 0x400 0x01>,
> +				       <&dmamux1 84 0x400 0x01>;
> +				dma-names = "rx", "tx";
> +				feature-domains = <&etzpc 18>;
> +				status = "disabled";
> +			};
> +
> +			spi5: spi@4c003000 {
> +				compatible = "st,stm32h7-spi";
> +				reg = <0x4c003000 0x400>;
> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SPI5_K>;
> +				resets = <&rcc SPI5_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 85 0x400 0x01>,
> +				       <&dmamux1 86 0x400 0x01>;
> +				dma-names = "rx", "tx";
> +				feature-domains = <&etzpc 19>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c@4c004000 {
> +				compatible = "st,stm32mp13-i2c";
> +				reg = <0x4c004000 0x400>;
> +				interrupt-names = "event", "error";
> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc I2C3_K>;
> +				resets = <&rcc I2C3_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 73 0x400 0x1>,
> +				       <&dmamux1 74 0x400 0x1>;
> +				dma-names = "rx", "tx";
> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
> +				i2c-analog-filter;
> +				feature-domains = <&etzpc 20>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c@4c005000 {
> +				compatible = "st,stm32mp13-i2c";
> +				reg = <0x4c005000 0x400>;
> +				interrupt-names = "event", "error";
> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc I2C4_K>;
> +				resets = <&rcc I2C4_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 75 0x400 0x1>,
> +				       <&dmamux1 76 0x400 0x1>;
> +				dma-names = "rx", "tx";
> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
> +				i2c-analog-filter;
> +				feature-domains = <&etzpc 21>;
> +				status = "disabled";
> +			};
> +
> +			i2c5: i2c@4c006000 {
> +				compatible = "st,stm32mp13-i2c";
> +				reg = <0x4c006000 0x400>;
> +				interrupt-names = "event", "error";
> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc I2C5_K>;
> +				resets = <&rcc I2C5_R>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				dmas = <&dmamux1 115 0x400 0x1>,
> +				       <&dmamux1 116 0x400 0x1>;
> +				dma-names = "rx", "tx";
> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
> +				i2c-analog-filter;
> +				feature-domains = <&etzpc 22>;
> +				status = "disabled";
> +			};
> +
> +			sdmmc1: mmc@58005000 {
> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> +				arm,primecell-periphid = <0x20253180>;
> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SDMMC1_K>;
> +				clock-names = "apb_pclk";
> +				resets = <&rcc SDMMC1_R>;
> +				cap-sd-highspeed;
> +				cap-mmc-highspeed;
> +				max-frequency = <130000000>;
> +				feature-domains = <&etzpc 50>;
> +				status = "disabled";
> +			};
> +
> +			sdmmc2: mmc@58007000 {
> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
> +				arm,primecell-periphid = <0x20253180>;
> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&rcc SDMMC2_K>;
> +				clock-names = "apb_pclk";
> +				resets = <&rcc SDMMC2_R>;
> +				cap-sd-highspeed;
> +				cap-mmc-highspeed;
> +				max-frequency = <130000000>;
> +				feature-domains = <&etzpc 51>;
> +				status = "disabled";
> +			};
> +
> +			usbphyc: usbphyc@5a006000 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				#clock-cells = <0>;
> +				compatible = "st,stm32mp1-usbphyc";
> +				reg = <0x5a006000 0x1000>;
> +				clocks = <&rcc USBPHY_K>;
> +				resets = <&rcc USBPHY_R>;
> +				vdda1v1-supply = <&reg11>;
> +				vdda1v8-supply = <&reg18>;
> +				feature-domains = <&etzpc 5>;
> +				status = "disabled";
> +
> +				usbphyc_port0: usb-phy@0 {
> +					#phy-cells = <0>;
> +					reg = <0>;
> +				};
> +
> +				usbphyc_port1: usb-phy@1 {
> +					#phy-cells = <1>;
> +					reg = <1>;
> +				};
> +			};
> +
> +		};
> +
>  		/*
>  		 * Break node order to solve dependency probe issue between
>  		 * pinctrl and exti.
> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
> index df451c3c2a26..be6061552683 100644
> --- a/arch/arm/boot/dts/stm32mp133.dtsi
> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>  			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>  			status = "disabled";
>  		};
> +	};
> +};
>  
> -		adc_1: adc@48003000 {
> -			compatible = "st,stm32mp13-adc-core";
> -			reg = <0x48003000 0x400>;
> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
> -			clock-names = "bus", "adc";
> -			interrupt-controller;
> -			#interrupt-cells = <1>;
> +&etzpc {
> +	adc_1: adc@48003000 {
> +		compatible = "st,stm32mp13-adc-core";
> +		reg = <0x48003000 0x400>;
> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
> +		clock-names = "bus", "adc";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		feature-domains = <&etzpc 32>;
> +		status = "disabled";
> +
> +		adc1: adc@0 {
> +			compatible = "st,stm32mp13-adc";
> +			#io-channel-cells = <1>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> +			reg = <0x0>;
> +			interrupt-parent = <&adc_1>;
> +			interrupts = <0>;
> +			dmas = <&dmamux1 9 0x400 0x80000001>;
> +			dma-names = "rx";
>  			status = "disabled";
>  
> -			adc1: adc@0 {
> -				compatible = "st,stm32mp13-adc";
> -				#io-channel-cells = <1>;
> -				#address-cells = <1>;
> -				#size-cells = <0>;
> -				reg = <0x0>;
> -				interrupt-parent = <&adc_1>;
> -				interrupts = <0>;
> -				dmas = <&dmamux1 9 0x400 0x80000001>;
> -				dma-names = "rx";
> -				status = "disabled";
> -
> -				channel@18 {
> -					reg = <18>;
> -					label = "vrefint";
> -				};
> +			channel@18 {
> +				reg = <18>;
> +				label = "vrefint";
>  			};
>  		};
>  	};
> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
> index 4d00e7592882..a1a7a40c2a3e 100644
> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
> @@ -4,15 +4,14 @@
>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>   */
>  
> -/ {
> -	soc {
> -		cryp: crypto@54002000 {
> -			compatible = "st,stm32mp1-cryp";
> -			reg = <0x54002000 0x400>;
> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc CRYP1>;
> -			resets = <&rcc CRYP1_R>;
> -			status = "disabled";
> -		};
> +&etzpc {
> +	cryp: crypto@54002000 {
> +		compatible = "st,stm32mp1-cryp";
> +		reg = <0x54002000 0x400>;
> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&rcc CRYP1>;
> +		resets = <&rcc CRYP1_R>;
> +		feature-domains = <&etzpc 42>;
> +		status = "disabled";
>  	};
>  };
> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
> index 4d00e7592882..b9fb071a1471 100644
> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
> @@ -4,15 +4,13 @@
>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>   */
>  
> -/ {
> -	soc {
> -		cryp: crypto@54002000 {
> -			compatible = "st,stm32mp1-cryp";
> -			reg = <0x54002000 0x400>;
> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&rcc CRYP1>;
> -			resets = <&rcc CRYP1_R>;
> -			status = "disabled";
> -		};
> +&etzpc {
> +	cryp: crypto@54002000 {
> +		compatible = "st,stm32mp1-cryp";
> +		reg = <0x54002000 0x400>;
> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&rcc CRYP1>;
> +		resets = <&rcc CRYP1_R>;
> +		status = "disabled";
>  	};
>  };

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 5/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
  2023-01-27 16:40   ` Gatien Chevallier
  (?)
@ 2023-02-09  7:51     ` Uwe Kleine-König
  -1 siblings, 0 replies; 93+ messages in thread
From: Uwe Kleine-König @ 2023-02-09  7:51 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni, linux-crypto, devicetree,
	linux-stm32, linux-arm-kernel, linux-kernel, dmaengine,
	linux-i2c, linux-iio, alsa-devel, linux-media, linux-mmc, netdev,
	linux-phy, linux-serial, linux-spi, linux-usb, kernel

[-- Attachment #1: Type: text/plain, Size: 1607 bytes --]

Hello,

On Fri, Jan 27, 2023 at 05:40:39PM +0100, Gatien Chevallier wrote:
> The STM32 System Bus is an internal bus on which devices are connected.
> ETZPC is a peripheral overseeing the firewall bus that configures
> and control access to the peripherals connected on it.
> 
> For more information on which peripheral is securable, please read
> the STM32MP15 reference manual.

it might be naive, but I somehow expected that when showing at the
resulting commit with git show -b that the patch gets quite small.

Is it really intended that &etzpc (which has reg = <0x5c007000 0x400>;)
is the parent bus of the devices with feature-domains = <&etzpc XX>; even
though their addresses are out of &etzpc's range? Doesn't a bus usually
have a ranges property and a base address that matches its contained
devices?

Looking at imx6qdl.dtsi there is:

	aips1: bus@2000000 { /* AIPS1 */
		...
		reg = <0x02000000 0x100000>;
		ranges;

		spba-bus@2000000 {
			...
			reg = <0x02000000 0x40000>;
			...
		};

		...

		sdma: dma-controller@20ec000 {
			...
			reg = <0x020ec000 0x4000>;
			...
		};
	};

and the registers configuring the aips1 bus are (I think) in

                        aipstz@207c000 { /* AIPSTZ1 */
                                reg = <0x0207c000 0x4000>;
                        };

Maybe this change could be made less intrusive by using a similar setup
here?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 5/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
@ 2023-02-09  7:51     ` Uwe Kleine-König
  0 siblings, 0 replies; 93+ messages in thread
From: Uwe Kleine-König @ 2023-02-09  7:51 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni, linux-crypto, devicetree,
	linux-stm32, linux-arm-kernel, linux-kernel, dmaengine,
	linux-i2c, linux-iio, alsa-devel, linux-media, linux-mmc, netdev,
	linux-phy, linux-serial, linux-spi, linux-usb, kernel


[-- Attachment #1.1: Type: text/plain, Size: 1607 bytes --]

Hello,

On Fri, Jan 27, 2023 at 05:40:39PM +0100, Gatien Chevallier wrote:
> The STM32 System Bus is an internal bus on which devices are connected.
> ETZPC is a peripheral overseeing the firewall bus that configures
> and control access to the peripherals connected on it.
> 
> For more information on which peripheral is securable, please read
> the STM32MP15 reference manual.

it might be naive, but I somehow expected that when showing at the
resulting commit with git show -b that the patch gets quite small.

Is it really intended that &etzpc (which has reg = <0x5c007000 0x400>;)
is the parent bus of the devices with feature-domains = <&etzpc XX>; even
though their addresses are out of &etzpc's range? Doesn't a bus usually
have a ranges property and a base address that matches its contained
devices?

Looking at imx6qdl.dtsi there is:

	aips1: bus@2000000 { /* AIPS1 */
		...
		reg = <0x02000000 0x100000>;
		ranges;

		spba-bus@2000000 {
			...
			reg = <0x02000000 0x40000>;
			...
		};

		...

		sdma: dma-controller@20ec000 {
			...
			reg = <0x020ec000 0x4000>;
			...
		};
	};

and the registers configuring the aips1 bus are (I think) in

                        aipstz@207c000 { /* AIPSTZ1 */
                                reg = <0x0207c000 0x4000>;
                        };

Maybe this change could be made less intrusive by using a similar setup
here?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

[-- Attachment #1.2: signature.asc --]
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-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 5/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
@ 2023-02-09  7:51     ` Uwe Kleine-König
  0 siblings, 0 replies; 93+ messages in thread
From: Uwe Kleine-König @ 2023-02-09  7:51 UTC (permalink / raw)
  To: Gatien Chevallier
  Cc: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni, linux-crypto, devicetree,
	linux-stm32, linux-arm-kernel, linux-kernel, dmaengine,
	linux-i2c, linux-iio, alsa-devel, linux-media, linux-mmc, netdev,
	linux-phy, linux-serial, linux-spi, linux-usb, kernel


[-- Attachment #1.1: Type: text/plain, Size: 1607 bytes --]

Hello,

On Fri, Jan 27, 2023 at 05:40:39PM +0100, Gatien Chevallier wrote:
> The STM32 System Bus is an internal bus on which devices are connected.
> ETZPC is a peripheral overseeing the firewall bus that configures
> and control access to the peripherals connected on it.
> 
> For more information on which peripheral is securable, please read
> the STM32MP15 reference manual.

it might be naive, but I somehow expected that when showing at the
resulting commit with git show -b that the patch gets quite small.

Is it really intended that &etzpc (which has reg = <0x5c007000 0x400>;)
is the parent bus of the devices with feature-domains = <&etzpc XX>; even
though their addresses are out of &etzpc's range? Doesn't a bus usually
have a ranges property and a base address that matches its contained
devices?

Looking at imx6qdl.dtsi there is:

	aips1: bus@2000000 { /* AIPS1 */
		...
		reg = <0x02000000 0x100000>;
		ranges;

		spba-bus@2000000 {
			...
			reg = <0x02000000 0x40000>;
			...
		};

		...

		sdma: dma-controller@20ec000 {
			...
			reg = <0x020ec000 0x4000>;
			...
		};
	};

and the registers configuring the aips1 bus are (I think) in

                        aipstz@207c000 { /* AIPSTZ1 */
                                reg = <0x0207c000 0x4000>;
                        };

Maybe this change could be made less intrusive by using a similar setup
here?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  2023-02-09  7:46     ` Ahmad Fatoum
  (?)
@ 2023-02-09  8:10       ` Ahmad Fatoum
  -1 siblings, 0 replies; 93+ messages in thread
From: Ahmad Fatoum @ 2023-02-09  8:10 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media

On 09.02.23 08:46, Ahmad Fatoum wrote:
> Hello Gatien,
> 
> On 27.01.23 17:40, Gatien Chevallier wrote:
>> The STM32 System Bus is an internal bus on which devices are connected.
>> ETZPC is a peripheral overseeing the firewall bus that configures
>> and control access to the peripherals connected on it.
>>
>> For more information on which peripheral is securable, please read
>> the STM32MP13 reference manual.
> 
> Diff is way too big. Please split up the alphabetic reordering into its
> own commit, so actual functional changes are apparent.

Ah, I see now that you are moving securable peripherals into a new bus.
I share Uwe's confusion of considering the ETZPC as bus.

Does this configuration even change dynamically? Why can't you implement
this binding in the bootloader and have Linux only see a DT where unavailable
nodes are status = "disabled"; secure-status = "okay"?

For inspiration, see barebox' device tree fixups when devices are disabled
per fuse:

  https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122

Cheers,
Ahmad

> 
> Thanks,
> Ahmad
> 
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> ---
>>
>> No changes in V2.
>>
>> Changes in V3:
>> 	-Use appriopriate node name: bus
>>
>>  arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>  arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>  arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>  arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>  4 files changed, 258 insertions(+), 237 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>> index accc3824f7e9..24462a647101 100644
>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>  			dma-channels = <16>;
>>  		};
>>  
>> -		adc_2: adc@48004000 {
>> -			compatible = "st,stm32mp13-adc-core";
>> -			reg = <0x48004000 0x400>;
>> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>> -			clock-names = "bus", "adc";
>> -			interrupt-controller;
>> -			#interrupt-cells = <1>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			status = "disabled";
>> -
>> -			adc2: adc@0 {
>> -				compatible = "st,stm32mp13-adc";
>> -				#io-channel-cells = <1>;
>> -				#address-cells = <1>;
>> -				#size-cells = <0>;
>> -				reg = <0x0>;
>> -				interrupt-parent = <&adc_2>;
>> -				interrupts = <0>;
>> -				dmas = <&dmamux1 10 0x400 0x80000001>;
>> -				dma-names = "rx";
>> -				status = "disabled";
>> -
>> -				channel@13 {
>> -					reg = <13>;
>> -					label = "vrefint";
>> -				};
>> -				channel@14 {
>> -					reg = <14>;
>> -					label = "vddcore";
>> -				};
>> -				channel@16 {
>> -					reg = <16>;
>> -					label = "vddcpu";
>> -				};
>> -				channel@17 {
>> -					reg = <17>;
>> -					label = "vddq_ddr";
>> -				};
>> -			};
>> -		};
>> -
>> -		usbotg_hs: usb@49000000 {
>> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>> -			reg = <0x49000000 0x40000>;
>> -			clocks = <&rcc USBO_K>;
>> -			clock-names = "otg";
>> -			resets = <&rcc USBO_R>;
>> -			reset-names = "dwc2";
>> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> -			g-rx-fifo-size = <512>;
>> -			g-np-tx-fifo-size = <32>;
>> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>> -			dr_mode = "otg";
>> -			otg-rev = <0x200>;
>> -			usb33d-supply = <&usb33>;
>> -			status = "disabled";
>> -		};
>> -
>> -		spi4: spi@4c002000 {
>> -			compatible = "st,stm32h7-spi";
>> -			reg = <0x4c002000 0x400>;
>> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SPI4_K>;
>> -			resets = <&rcc SPI4_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 83 0x400 0x01>,
>> -			       <&dmamux1 84 0x400 0x01>;
>> -			dma-names = "rx", "tx";
>> -			status = "disabled";
>> -		};
>> -
>> -		spi5: spi@4c003000 {
>> -			compatible = "st,stm32h7-spi";
>> -			reg = <0x4c003000 0x400>;
>> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SPI5_K>;
>> -			resets = <&rcc SPI5_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 85 0x400 0x01>,
>> -			       <&dmamux1 86 0x400 0x01>;
>> -			dma-names = "rx", "tx";
>> -			status = "disabled";
>> -		};
>> -
>> -		i2c3: i2c@4c004000 {
>> -			compatible = "st,stm32mp13-i2c";
>> -			reg = <0x4c004000 0x400>;
>> -			interrupt-names = "event", "error";
>> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc I2C3_K>;
>> -			resets = <&rcc I2C3_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 73 0x400 0x1>,
>> -			       <&dmamux1 74 0x400 0x1>;
>> -			dma-names = "rx", "tx";
>> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
>> -			i2c-analog-filter;
>> -			status = "disabled";
>> -		};
>> -
>> -		i2c4: i2c@4c005000 {
>> -			compatible = "st,stm32mp13-i2c";
>> -			reg = <0x4c005000 0x400>;
>> -			interrupt-names = "event", "error";
>> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc I2C4_K>;
>> -			resets = <&rcc I2C4_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 75 0x400 0x1>,
>> -			       <&dmamux1 76 0x400 0x1>;
>> -			dma-names = "rx", "tx";
>> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
>> -			i2c-analog-filter;
>> -			status = "disabled";
>> -		};
>> -
>> -		i2c5: i2c@4c006000 {
>> -			compatible = "st,stm32mp13-i2c";
>> -			reg = <0x4c006000 0x400>;
>> -			interrupt-names = "event", "error";
>> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc I2C5_K>;
>> -			resets = <&rcc I2C5_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 115 0x400 0x1>,
>> -			       <&dmamux1 116 0x400 0x1>;
>> -			dma-names = "rx", "tx";
>> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
>> -			i2c-analog-filter;
>> -			status = "disabled";
>> -		};
>> -
>>  		rcc: rcc@50000000 {
>>  			compatible = "st,stm32mp13-rcc", "syscon";
>>  			reg = <0x50000000 0x1000>;
>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>  			dma-requests = <48>;
>>  		};
>>  
>> -		sdmmc1: mmc@58005000 {
>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> -			arm,primecell-periphid = <0x20253180>;
>> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SDMMC1_K>;
>> -			clock-names = "apb_pclk";
>> -			resets = <&rcc SDMMC1_R>;
>> -			cap-sd-highspeed;
>> -			cap-mmc-highspeed;
>> -			max-frequency = <130000000>;
>> -			status = "disabled";
>> -		};
>> -
>> -		sdmmc2: mmc@58007000 {
>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> -			arm,primecell-periphid = <0x20253180>;
>> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SDMMC2_K>;
>> -			clock-names = "apb_pclk";
>> -			resets = <&rcc SDMMC2_R>;
>> -			cap-sd-highspeed;
>> -			cap-mmc-highspeed;
>> -			max-frequency = <130000000>;
>> -			status = "disabled";
>> -		};
>> -
>>  		usbh_ohci: usb@5800c000 {
>>  			compatible = "generic-ohci";
>>  			reg = <0x5800c000 0x1000>;
>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>  			status = "disabled";
>>  		};
>>  
>> -		usbphyc: usbphyc@5a006000 {
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			#clock-cells = <0>;
>> -			compatible = "st,stm32mp1-usbphyc";
>> -			reg = <0x5a006000 0x1000>;
>> -			clocks = <&rcc USBPHY_K>;
>> -			resets = <&rcc USBPHY_R>;
>> -			vdda1v1-supply = <&reg11>;
>> -			vdda1v8-supply = <&reg18>;
>> -			status = "disabled";
>> -
>> -			usbphyc_port0: usb-phy@0 {
>> -				#phy-cells = <0>;
>> -				reg = <0>;
>> -			};
>> -
>> -			usbphyc_port1: usb-phy@1 {
>> -				#phy-cells = <1>;
>> -				reg = <1>;
>> -			};
>> -		};
>> -
>>  		rtc: rtc@5c004000 {
>>  			compatible = "st,stm32mp1-rtc";
>>  			reg = <0x5c004000 0x400>;
>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>  			};
>>  		};
>>  
>> +		etzpc: bus@5c007000 {
>> +			compatible = "st,stm32mp13-sys-bus";
>> +			reg = <0x5c007000 0x400>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			feature-domain-controller;
>> +			#feature-domain-cells = <1>;
>> +			ranges;
>> +
>> +			adc_2: adc@48004000 {
>> +				compatible = "st,stm32mp13-adc-core";
>> +				reg = <0x48004000 0x400>;
>> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>> +				clock-names = "bus", "adc";
>> +				interrupt-controller;
>> +				#interrupt-cells = <1>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				feature-domains = <&etzpc 33>;
>> +				status = "disabled";
>> +
>> +				adc2: adc@0 {
>> +					compatible = "st,stm32mp13-adc";
>> +					#io-channel-cells = <1>;
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +					reg = <0x0>;
>> +					interrupt-parent = <&adc_2>;
>> +					interrupts = <0>;
>> +					dmas = <&dmamux1 10 0x400 0x80000001>;
>> +					dma-names = "rx";
>> +					status = "disabled";
>> +
>> +					channel@13 {
>> +						reg = <13>;
>> +						label = "vrefint";
>> +					};
>> +					channel@14 {
>> +						reg = <14>;
>> +						label = "vddcore";
>> +					};
>> +					channel@16 {
>> +						reg = <16>;
>> +						label = "vddcpu";
>> +					};
>> +					channel@17 {
>> +						reg = <17>;
>> +						label = "vddq_ddr";
>> +					};
>> +				};
>> +			};
>> +
>> +			usbotg_hs: usb@49000000 {
>> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>> +				reg = <0x49000000 0x40000>;
>> +				clocks = <&rcc USBO_K>;
>> +				clock-names = "otg";
>> +				resets = <&rcc USBO_R>;
>> +				reset-names = "dwc2";
>> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> +				g-rx-fifo-size = <512>;
>> +				g-np-tx-fifo-size = <32>;
>> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>> +				dr_mode = "otg";
>> +				otg-rev = <0x200>;
>> +				usb33d-supply = <&usb33>;
>> +				feature-domains = <&etzpc 34>;
>> +				status = "disabled";
>> +			};
>> +
>> +			spi4: spi@4c002000 {
>> +				compatible = "st,stm32h7-spi";
>> +				reg = <0x4c002000 0x400>;
>> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SPI4_K>;
>> +				resets = <&rcc SPI4_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 83 0x400 0x01>,
>> +				       <&dmamux1 84 0x400 0x01>;
>> +				dma-names = "rx", "tx";
>> +				feature-domains = <&etzpc 18>;
>> +				status = "disabled";
>> +			};
>> +
>> +			spi5: spi@4c003000 {
>> +				compatible = "st,stm32h7-spi";
>> +				reg = <0x4c003000 0x400>;
>> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SPI5_K>;
>> +				resets = <&rcc SPI5_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 85 0x400 0x01>,
>> +				       <&dmamux1 86 0x400 0x01>;
>> +				dma-names = "rx", "tx";
>> +				feature-domains = <&etzpc 19>;
>> +				status = "disabled";
>> +			};
>> +
>> +			i2c3: i2c@4c004000 {
>> +				compatible = "st,stm32mp13-i2c";
>> +				reg = <0x4c004000 0x400>;
>> +				interrupt-names = "event", "error";
>> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc I2C3_K>;
>> +				resets = <&rcc I2C3_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 73 0x400 0x1>,
>> +				       <&dmamux1 74 0x400 0x1>;
>> +				dma-names = "rx", "tx";
>> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
>> +				i2c-analog-filter;
>> +				feature-domains = <&etzpc 20>;
>> +				status = "disabled";
>> +			};
>> +
>> +			i2c4: i2c@4c005000 {
>> +				compatible = "st,stm32mp13-i2c";
>> +				reg = <0x4c005000 0x400>;
>> +				interrupt-names = "event", "error";
>> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc I2C4_K>;
>> +				resets = <&rcc I2C4_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 75 0x400 0x1>,
>> +				       <&dmamux1 76 0x400 0x1>;
>> +				dma-names = "rx", "tx";
>> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
>> +				i2c-analog-filter;
>> +				feature-domains = <&etzpc 21>;
>> +				status = "disabled";
>> +			};
>> +
>> +			i2c5: i2c@4c006000 {
>> +				compatible = "st,stm32mp13-i2c";
>> +				reg = <0x4c006000 0x400>;
>> +				interrupt-names = "event", "error";
>> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc I2C5_K>;
>> +				resets = <&rcc I2C5_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 115 0x400 0x1>,
>> +				       <&dmamux1 116 0x400 0x1>;
>> +				dma-names = "rx", "tx";
>> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
>> +				i2c-analog-filter;
>> +				feature-domains = <&etzpc 22>;
>> +				status = "disabled";
>> +			};
>> +
>> +			sdmmc1: mmc@58005000 {
>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> +				arm,primecell-periphid = <0x20253180>;
>> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SDMMC1_K>;
>> +				clock-names = "apb_pclk";
>> +				resets = <&rcc SDMMC1_R>;
>> +				cap-sd-highspeed;
>> +				cap-mmc-highspeed;
>> +				max-frequency = <130000000>;
>> +				feature-domains = <&etzpc 50>;
>> +				status = "disabled";
>> +			};
>> +
>> +			sdmmc2: mmc@58007000 {
>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> +				arm,primecell-periphid = <0x20253180>;
>> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SDMMC2_K>;
>> +				clock-names = "apb_pclk";
>> +				resets = <&rcc SDMMC2_R>;
>> +				cap-sd-highspeed;
>> +				cap-mmc-highspeed;
>> +				max-frequency = <130000000>;
>> +				feature-domains = <&etzpc 51>;
>> +				status = "disabled";
>> +			};
>> +
>> +			usbphyc: usbphyc@5a006000 {
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				#clock-cells = <0>;
>> +				compatible = "st,stm32mp1-usbphyc";
>> +				reg = <0x5a006000 0x1000>;
>> +				clocks = <&rcc USBPHY_K>;
>> +				resets = <&rcc USBPHY_R>;
>> +				vdda1v1-supply = <&reg11>;
>> +				vdda1v8-supply = <&reg18>;
>> +				feature-domains = <&etzpc 5>;
>> +				status = "disabled";
>> +
>> +				usbphyc_port0: usb-phy@0 {
>> +					#phy-cells = <0>;
>> +					reg = <0>;
>> +				};
>> +
>> +				usbphyc_port1: usb-phy@1 {
>> +					#phy-cells = <1>;
>> +					reg = <1>;
>> +				};
>> +			};
>> +
>> +		};
>> +
>>  		/*
>>  		 * Break node order to solve dependency probe issue between
>>  		 * pinctrl and exti.
>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>> index df451c3c2a26..be6061552683 100644
>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>  			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>  			status = "disabled";
>>  		};
>> +	};
>> +};
>>  
>> -		adc_1: adc@48003000 {
>> -			compatible = "st,stm32mp13-adc-core";
>> -			reg = <0x48003000 0x400>;
>> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>> -			clock-names = "bus", "adc";
>> -			interrupt-controller;
>> -			#interrupt-cells = <1>;
>> +&etzpc {
>> +	adc_1: adc@48003000 {
>> +		compatible = "st,stm32mp13-adc-core";
>> +		reg = <0x48003000 0x400>;
>> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>> +		clock-names = "bus", "adc";
>> +		interrupt-controller;
>> +		#interrupt-cells = <1>;
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		feature-domains = <&etzpc 32>;
>> +		status = "disabled";
>> +
>> +		adc1: adc@0 {
>> +			compatible = "st,stm32mp13-adc";
>> +			#io-channel-cells = <1>;
>>  			#address-cells = <1>;
>>  			#size-cells = <0>;
>> +			reg = <0x0>;
>> +			interrupt-parent = <&adc_1>;
>> +			interrupts = <0>;
>> +			dmas = <&dmamux1 9 0x400 0x80000001>;
>> +			dma-names = "rx";
>>  			status = "disabled";
>>  
>> -			adc1: adc@0 {
>> -				compatible = "st,stm32mp13-adc";
>> -				#io-channel-cells = <1>;
>> -				#address-cells = <1>;
>> -				#size-cells = <0>;
>> -				reg = <0x0>;
>> -				interrupt-parent = <&adc_1>;
>> -				interrupts = <0>;
>> -				dmas = <&dmamux1 9 0x400 0x80000001>;
>> -				dma-names = "rx";
>> -				status = "disabled";
>> -
>> -				channel@18 {
>> -					reg = <18>;
>> -					label = "vrefint";
>> -				};
>> +			channel@18 {
>> +				reg = <18>;
>> +				label = "vrefint";
>>  			};
>>  		};
>>  	};
>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>> index 4d00e7592882..a1a7a40c2a3e 100644
>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>> @@ -4,15 +4,14 @@
>>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>   */
>>  
>> -/ {
>> -	soc {
>> -		cryp: crypto@54002000 {
>> -			compatible = "st,stm32mp1-cryp";
>> -			reg = <0x54002000 0x400>;
>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc CRYP1>;
>> -			resets = <&rcc CRYP1_R>;
>> -			status = "disabled";
>> -		};
>> +&etzpc {
>> +	cryp: crypto@54002000 {
>> +		compatible = "st,stm32mp1-cryp";
>> +		reg = <0x54002000 0x400>;
>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&rcc CRYP1>;
>> +		resets = <&rcc CRYP1_R>;
>> +		feature-domains = <&etzpc 42>;
>> +		status = "disabled";
>>  	};
>>  };
>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>> index 4d00e7592882..b9fb071a1471 100644
>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>> @@ -4,15 +4,13 @@
>>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>   */
>>  
>> -/ {
>> -	soc {
>> -		cryp: crypto@54002000 {
>> -			compatible = "st,stm32mp1-cryp";
>> -			reg = <0x54002000 0x400>;
>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc CRYP1>;
>> -			resets = <&rcc CRYP1_R>;
>> -			status = "disabled";
>> -		};
>> +&etzpc {
>> +	cryp: crypto@54002000 {
>> +		compatible = "st,stm32mp1-cryp";
>> +		reg = <0x54002000 0x400>;
>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&rcc CRYP1>;
>> +		resets = <&rcc CRYP1_R>;
>> +		status = "disabled";
>>  	};
>>  };
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-09  8:10       ` Ahmad Fatoum
  0 siblings, 0 replies; 93+ messages in thread
From: Ahmad Fatoum @ 2023-02-09  8:10 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media

On 09.02.23 08:46, Ahmad Fatoum wrote:
> Hello Gatien,
> 
> On 27.01.23 17:40, Gatien Chevallier wrote:
>> The STM32 System Bus is an internal bus on which devices are connected.
>> ETZPC is a peripheral overseeing the firewall bus that configures
>> and control access to the peripherals connected on it.
>>
>> For more information on which peripheral is securable, please read
>> the STM32MP13 reference manual.
> 
> Diff is way too big. Please split up the alphabetic reordering into its
> own commit, so actual functional changes are apparent.

Ah, I see now that you are moving securable peripherals into a new bus.
I share Uwe's confusion of considering the ETZPC as bus.

Does this configuration even change dynamically? Why can't you implement
this binding in the bootloader and have Linux only see a DT where unavailable
nodes are status = "disabled"; secure-status = "okay"?

For inspiration, see barebox' device tree fixups when devices are disabled
per fuse:

  https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122

Cheers,
Ahmad

> 
> Thanks,
> Ahmad
> 
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> ---
>>
>> No changes in V2.
>>
>> Changes in V3:
>> 	-Use appriopriate node name: bus
>>
>>  arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>  arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>  arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>  arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>  4 files changed, 258 insertions(+), 237 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>> index accc3824f7e9..24462a647101 100644
>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>  			dma-channels = <16>;
>>  		};
>>  
>> -		adc_2: adc@48004000 {
>> -			compatible = "st,stm32mp13-adc-core";
>> -			reg = <0x48004000 0x400>;
>> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>> -			clock-names = "bus", "adc";
>> -			interrupt-controller;
>> -			#interrupt-cells = <1>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			status = "disabled";
>> -
>> -			adc2: adc@0 {
>> -				compatible = "st,stm32mp13-adc";
>> -				#io-channel-cells = <1>;
>> -				#address-cells = <1>;
>> -				#size-cells = <0>;
>> -				reg = <0x0>;
>> -				interrupt-parent = <&adc_2>;
>> -				interrupts = <0>;
>> -				dmas = <&dmamux1 10 0x400 0x80000001>;
>> -				dma-names = "rx";
>> -				status = "disabled";
>> -
>> -				channel@13 {
>> -					reg = <13>;
>> -					label = "vrefint";
>> -				};
>> -				channel@14 {
>> -					reg = <14>;
>> -					label = "vddcore";
>> -				};
>> -				channel@16 {
>> -					reg = <16>;
>> -					label = "vddcpu";
>> -				};
>> -				channel@17 {
>> -					reg = <17>;
>> -					label = "vddq_ddr";
>> -				};
>> -			};
>> -		};
>> -
>> -		usbotg_hs: usb@49000000 {
>> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>> -			reg = <0x49000000 0x40000>;
>> -			clocks = <&rcc USBO_K>;
>> -			clock-names = "otg";
>> -			resets = <&rcc USBO_R>;
>> -			reset-names = "dwc2";
>> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> -			g-rx-fifo-size = <512>;
>> -			g-np-tx-fifo-size = <32>;
>> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>> -			dr_mode = "otg";
>> -			otg-rev = <0x200>;
>> -			usb33d-supply = <&usb33>;
>> -			status = "disabled";
>> -		};
>> -
>> -		spi4: spi@4c002000 {
>> -			compatible = "st,stm32h7-spi";
>> -			reg = <0x4c002000 0x400>;
>> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SPI4_K>;
>> -			resets = <&rcc SPI4_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 83 0x400 0x01>,
>> -			       <&dmamux1 84 0x400 0x01>;
>> -			dma-names = "rx", "tx";
>> -			status = "disabled";
>> -		};
>> -
>> -		spi5: spi@4c003000 {
>> -			compatible = "st,stm32h7-spi";
>> -			reg = <0x4c003000 0x400>;
>> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SPI5_K>;
>> -			resets = <&rcc SPI5_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 85 0x400 0x01>,
>> -			       <&dmamux1 86 0x400 0x01>;
>> -			dma-names = "rx", "tx";
>> -			status = "disabled";
>> -		};
>> -
>> -		i2c3: i2c@4c004000 {
>> -			compatible = "st,stm32mp13-i2c";
>> -			reg = <0x4c004000 0x400>;
>> -			interrupt-names = "event", "error";
>> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc I2C3_K>;
>> -			resets = <&rcc I2C3_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 73 0x400 0x1>,
>> -			       <&dmamux1 74 0x400 0x1>;
>> -			dma-names = "rx", "tx";
>> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
>> -			i2c-analog-filter;
>> -			status = "disabled";
>> -		};
>> -
>> -		i2c4: i2c@4c005000 {
>> -			compatible = "st,stm32mp13-i2c";
>> -			reg = <0x4c005000 0x400>;
>> -			interrupt-names = "event", "error";
>> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc I2C4_K>;
>> -			resets = <&rcc I2C4_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 75 0x400 0x1>,
>> -			       <&dmamux1 76 0x400 0x1>;
>> -			dma-names = "rx", "tx";
>> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
>> -			i2c-analog-filter;
>> -			status = "disabled";
>> -		};
>> -
>> -		i2c5: i2c@4c006000 {
>> -			compatible = "st,stm32mp13-i2c";
>> -			reg = <0x4c006000 0x400>;
>> -			interrupt-names = "event", "error";
>> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc I2C5_K>;
>> -			resets = <&rcc I2C5_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 115 0x400 0x1>,
>> -			       <&dmamux1 116 0x400 0x1>;
>> -			dma-names = "rx", "tx";
>> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
>> -			i2c-analog-filter;
>> -			status = "disabled";
>> -		};
>> -
>>  		rcc: rcc@50000000 {
>>  			compatible = "st,stm32mp13-rcc", "syscon";
>>  			reg = <0x50000000 0x1000>;
>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>  			dma-requests = <48>;
>>  		};
>>  
>> -		sdmmc1: mmc@58005000 {
>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> -			arm,primecell-periphid = <0x20253180>;
>> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SDMMC1_K>;
>> -			clock-names = "apb_pclk";
>> -			resets = <&rcc SDMMC1_R>;
>> -			cap-sd-highspeed;
>> -			cap-mmc-highspeed;
>> -			max-frequency = <130000000>;
>> -			status = "disabled";
>> -		};
>> -
>> -		sdmmc2: mmc@58007000 {
>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> -			arm,primecell-periphid = <0x20253180>;
>> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SDMMC2_K>;
>> -			clock-names = "apb_pclk";
>> -			resets = <&rcc SDMMC2_R>;
>> -			cap-sd-highspeed;
>> -			cap-mmc-highspeed;
>> -			max-frequency = <130000000>;
>> -			status = "disabled";
>> -		};
>> -
>>  		usbh_ohci: usb@5800c000 {
>>  			compatible = "generic-ohci";
>>  			reg = <0x5800c000 0x1000>;
>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>  			status = "disabled";
>>  		};
>>  
>> -		usbphyc: usbphyc@5a006000 {
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			#clock-cells = <0>;
>> -			compatible = "st,stm32mp1-usbphyc";
>> -			reg = <0x5a006000 0x1000>;
>> -			clocks = <&rcc USBPHY_K>;
>> -			resets = <&rcc USBPHY_R>;
>> -			vdda1v1-supply = <&reg11>;
>> -			vdda1v8-supply = <&reg18>;
>> -			status = "disabled";
>> -
>> -			usbphyc_port0: usb-phy@0 {
>> -				#phy-cells = <0>;
>> -				reg = <0>;
>> -			};
>> -
>> -			usbphyc_port1: usb-phy@1 {
>> -				#phy-cells = <1>;
>> -				reg = <1>;
>> -			};
>> -		};
>> -
>>  		rtc: rtc@5c004000 {
>>  			compatible = "st,stm32mp1-rtc";
>>  			reg = <0x5c004000 0x400>;
>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>  			};
>>  		};
>>  
>> +		etzpc: bus@5c007000 {
>> +			compatible = "st,stm32mp13-sys-bus";
>> +			reg = <0x5c007000 0x400>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			feature-domain-controller;
>> +			#feature-domain-cells = <1>;
>> +			ranges;
>> +
>> +			adc_2: adc@48004000 {
>> +				compatible = "st,stm32mp13-adc-core";
>> +				reg = <0x48004000 0x400>;
>> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>> +				clock-names = "bus", "adc";
>> +				interrupt-controller;
>> +				#interrupt-cells = <1>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				feature-domains = <&etzpc 33>;
>> +				status = "disabled";
>> +
>> +				adc2: adc@0 {
>> +					compatible = "st,stm32mp13-adc";
>> +					#io-channel-cells = <1>;
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +					reg = <0x0>;
>> +					interrupt-parent = <&adc_2>;
>> +					interrupts = <0>;
>> +					dmas = <&dmamux1 10 0x400 0x80000001>;
>> +					dma-names = "rx";
>> +					status = "disabled";
>> +
>> +					channel@13 {
>> +						reg = <13>;
>> +						label = "vrefint";
>> +					};
>> +					channel@14 {
>> +						reg = <14>;
>> +						label = "vddcore";
>> +					};
>> +					channel@16 {
>> +						reg = <16>;
>> +						label = "vddcpu";
>> +					};
>> +					channel@17 {
>> +						reg = <17>;
>> +						label = "vddq_ddr";
>> +					};
>> +				};
>> +			};
>> +
>> +			usbotg_hs: usb@49000000 {
>> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>> +				reg = <0x49000000 0x40000>;
>> +				clocks = <&rcc USBO_K>;
>> +				clock-names = "otg";
>> +				resets = <&rcc USBO_R>;
>> +				reset-names = "dwc2";
>> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> +				g-rx-fifo-size = <512>;
>> +				g-np-tx-fifo-size = <32>;
>> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>> +				dr_mode = "otg";
>> +				otg-rev = <0x200>;
>> +				usb33d-supply = <&usb33>;
>> +				feature-domains = <&etzpc 34>;
>> +				status = "disabled";
>> +			};
>> +
>> +			spi4: spi@4c002000 {
>> +				compatible = "st,stm32h7-spi";
>> +				reg = <0x4c002000 0x400>;
>> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SPI4_K>;
>> +				resets = <&rcc SPI4_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 83 0x400 0x01>,
>> +				       <&dmamux1 84 0x400 0x01>;
>> +				dma-names = "rx", "tx";
>> +				feature-domains = <&etzpc 18>;
>> +				status = "disabled";
>> +			};
>> +
>> +			spi5: spi@4c003000 {
>> +				compatible = "st,stm32h7-spi";
>> +				reg = <0x4c003000 0x400>;
>> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SPI5_K>;
>> +				resets = <&rcc SPI5_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 85 0x400 0x01>,
>> +				       <&dmamux1 86 0x400 0x01>;
>> +				dma-names = "rx", "tx";
>> +				feature-domains = <&etzpc 19>;
>> +				status = "disabled";
>> +			};
>> +
>> +			i2c3: i2c@4c004000 {
>> +				compatible = "st,stm32mp13-i2c";
>> +				reg = <0x4c004000 0x400>;
>> +				interrupt-names = "event", "error";
>> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc I2C3_K>;
>> +				resets = <&rcc I2C3_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 73 0x400 0x1>,
>> +				       <&dmamux1 74 0x400 0x1>;
>> +				dma-names = "rx", "tx";
>> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
>> +				i2c-analog-filter;
>> +				feature-domains = <&etzpc 20>;
>> +				status = "disabled";
>> +			};
>> +
>> +			i2c4: i2c@4c005000 {
>> +				compatible = "st,stm32mp13-i2c";
>> +				reg = <0x4c005000 0x400>;
>> +				interrupt-names = "event", "error";
>> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc I2C4_K>;
>> +				resets = <&rcc I2C4_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 75 0x400 0x1>,
>> +				       <&dmamux1 76 0x400 0x1>;
>> +				dma-names = "rx", "tx";
>> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
>> +				i2c-analog-filter;
>> +				feature-domains = <&etzpc 21>;
>> +				status = "disabled";
>> +			};
>> +
>> +			i2c5: i2c@4c006000 {
>> +				compatible = "st,stm32mp13-i2c";
>> +				reg = <0x4c006000 0x400>;
>> +				interrupt-names = "event", "error";
>> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc I2C5_K>;
>> +				resets = <&rcc I2C5_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 115 0x400 0x1>,
>> +				       <&dmamux1 116 0x400 0x1>;
>> +				dma-names = "rx", "tx";
>> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
>> +				i2c-analog-filter;
>> +				feature-domains = <&etzpc 22>;
>> +				status = "disabled";
>> +			};
>> +
>> +			sdmmc1: mmc@58005000 {
>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> +				arm,primecell-periphid = <0x20253180>;
>> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SDMMC1_K>;
>> +				clock-names = "apb_pclk";
>> +				resets = <&rcc SDMMC1_R>;
>> +				cap-sd-highspeed;
>> +				cap-mmc-highspeed;
>> +				max-frequency = <130000000>;
>> +				feature-domains = <&etzpc 50>;
>> +				status = "disabled";
>> +			};
>> +
>> +			sdmmc2: mmc@58007000 {
>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> +				arm,primecell-periphid = <0x20253180>;
>> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SDMMC2_K>;
>> +				clock-names = "apb_pclk";
>> +				resets = <&rcc SDMMC2_R>;
>> +				cap-sd-highspeed;
>> +				cap-mmc-highspeed;
>> +				max-frequency = <130000000>;
>> +				feature-domains = <&etzpc 51>;
>> +				status = "disabled";
>> +			};
>> +
>> +			usbphyc: usbphyc@5a006000 {
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				#clock-cells = <0>;
>> +				compatible = "st,stm32mp1-usbphyc";
>> +				reg = <0x5a006000 0x1000>;
>> +				clocks = <&rcc USBPHY_K>;
>> +				resets = <&rcc USBPHY_R>;
>> +				vdda1v1-supply = <&reg11>;
>> +				vdda1v8-supply = <&reg18>;
>> +				feature-domains = <&etzpc 5>;
>> +				status = "disabled";
>> +
>> +				usbphyc_port0: usb-phy@0 {
>> +					#phy-cells = <0>;
>> +					reg = <0>;
>> +				};
>> +
>> +				usbphyc_port1: usb-phy@1 {
>> +					#phy-cells = <1>;
>> +					reg = <1>;
>> +				};
>> +			};
>> +
>> +		};
>> +
>>  		/*
>>  		 * Break node order to solve dependency probe issue between
>>  		 * pinctrl and exti.
>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>> index df451c3c2a26..be6061552683 100644
>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>  			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>  			status = "disabled";
>>  		};
>> +	};
>> +};
>>  
>> -		adc_1: adc@48003000 {
>> -			compatible = "st,stm32mp13-adc-core";
>> -			reg = <0x48003000 0x400>;
>> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>> -			clock-names = "bus", "adc";
>> -			interrupt-controller;
>> -			#interrupt-cells = <1>;
>> +&etzpc {
>> +	adc_1: adc@48003000 {
>> +		compatible = "st,stm32mp13-adc-core";
>> +		reg = <0x48003000 0x400>;
>> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>> +		clock-names = "bus", "adc";
>> +		interrupt-controller;
>> +		#interrupt-cells = <1>;
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		feature-domains = <&etzpc 32>;
>> +		status = "disabled";
>> +
>> +		adc1: adc@0 {
>> +			compatible = "st,stm32mp13-adc";
>> +			#io-channel-cells = <1>;
>>  			#address-cells = <1>;
>>  			#size-cells = <0>;
>> +			reg = <0x0>;
>> +			interrupt-parent = <&adc_1>;
>> +			interrupts = <0>;
>> +			dmas = <&dmamux1 9 0x400 0x80000001>;
>> +			dma-names = "rx";
>>  			status = "disabled";
>>  
>> -			adc1: adc@0 {
>> -				compatible = "st,stm32mp13-adc";
>> -				#io-channel-cells = <1>;
>> -				#address-cells = <1>;
>> -				#size-cells = <0>;
>> -				reg = <0x0>;
>> -				interrupt-parent = <&adc_1>;
>> -				interrupts = <0>;
>> -				dmas = <&dmamux1 9 0x400 0x80000001>;
>> -				dma-names = "rx";
>> -				status = "disabled";
>> -
>> -				channel@18 {
>> -					reg = <18>;
>> -					label = "vrefint";
>> -				};
>> +			channel@18 {
>> +				reg = <18>;
>> +				label = "vrefint";
>>  			};
>>  		};
>>  	};
>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>> index 4d00e7592882..a1a7a40c2a3e 100644
>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>> @@ -4,15 +4,14 @@
>>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>   */
>>  
>> -/ {
>> -	soc {
>> -		cryp: crypto@54002000 {
>> -			compatible = "st,stm32mp1-cryp";
>> -			reg = <0x54002000 0x400>;
>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc CRYP1>;
>> -			resets = <&rcc CRYP1_R>;
>> -			status = "disabled";
>> -		};
>> +&etzpc {
>> +	cryp: crypto@54002000 {
>> +		compatible = "st,stm32mp1-cryp";
>> +		reg = <0x54002000 0x400>;
>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&rcc CRYP1>;
>> +		resets = <&rcc CRYP1_R>;
>> +		feature-domains = <&etzpc 42>;
>> +		status = "disabled";
>>  	};
>>  };
>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>> index 4d00e7592882..b9fb071a1471 100644
>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>> @@ -4,15 +4,13 @@
>>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>   */
>>  
>> -/ {
>> -	soc {
>> -		cryp: crypto@54002000 {
>> -			compatible = "st,stm32mp1-cryp";
>> -			reg = <0x54002000 0x400>;
>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc CRYP1>;
>> -			resets = <&rcc CRYP1_R>;
>> -			status = "disabled";
>> -		};
>> +&etzpc {
>> +	cryp: crypto@54002000 {
>> +		compatible = "st,stm32mp1-cryp";
>> +		reg = <0x54002000 0x400>;
>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&rcc CRYP1>;
>> +		resets = <&rcc CRYP1_R>;
>> +		status = "disabled";
>>  	};
>>  };
> 

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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-09  8:10       ` Ahmad Fatoum
  0 siblings, 0 replies; 93+ messages in thread
From: Ahmad Fatoum @ 2023-02-09  8:10 UTC (permalink / raw)
  To: Gatien Chevallier, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media

On 09.02.23 08:46, Ahmad Fatoum wrote:
> Hello Gatien,
> 
> On 27.01.23 17:40, Gatien Chevallier wrote:
>> The STM32 System Bus is an internal bus on which devices are connected.
>> ETZPC is a peripheral overseeing the firewall bus that configures
>> and control access to the peripherals connected on it.
>>
>> For more information on which peripheral is securable, please read
>> the STM32MP13 reference manual.
> 
> Diff is way too big. Please split up the alphabetic reordering into its
> own commit, so actual functional changes are apparent.

Ah, I see now that you are moving securable peripherals into a new bus.
I share Uwe's confusion of considering the ETZPC as bus.

Does this configuration even change dynamically? Why can't you implement
this binding in the bootloader and have Linux only see a DT where unavailable
nodes are status = "disabled"; secure-status = "okay"?

For inspiration, see barebox' device tree fixups when devices are disabled
per fuse:

  https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122

Cheers,
Ahmad

> 
> Thanks,
> Ahmad
> 
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> ---
>>
>> No changes in V2.
>>
>> Changes in V3:
>> 	-Use appriopriate node name: bus
>>
>>  arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>  arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>  arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>  arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>  4 files changed, 258 insertions(+), 237 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>> index accc3824f7e9..24462a647101 100644
>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>  			dma-channels = <16>;
>>  		};
>>  
>> -		adc_2: adc@48004000 {
>> -			compatible = "st,stm32mp13-adc-core";
>> -			reg = <0x48004000 0x400>;
>> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>> -			clock-names = "bus", "adc";
>> -			interrupt-controller;
>> -			#interrupt-cells = <1>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			status = "disabled";
>> -
>> -			adc2: adc@0 {
>> -				compatible = "st,stm32mp13-adc";
>> -				#io-channel-cells = <1>;
>> -				#address-cells = <1>;
>> -				#size-cells = <0>;
>> -				reg = <0x0>;
>> -				interrupt-parent = <&adc_2>;
>> -				interrupts = <0>;
>> -				dmas = <&dmamux1 10 0x400 0x80000001>;
>> -				dma-names = "rx";
>> -				status = "disabled";
>> -
>> -				channel@13 {
>> -					reg = <13>;
>> -					label = "vrefint";
>> -				};
>> -				channel@14 {
>> -					reg = <14>;
>> -					label = "vddcore";
>> -				};
>> -				channel@16 {
>> -					reg = <16>;
>> -					label = "vddcpu";
>> -				};
>> -				channel@17 {
>> -					reg = <17>;
>> -					label = "vddq_ddr";
>> -				};
>> -			};
>> -		};
>> -
>> -		usbotg_hs: usb@49000000 {
>> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>> -			reg = <0x49000000 0x40000>;
>> -			clocks = <&rcc USBO_K>;
>> -			clock-names = "otg";
>> -			resets = <&rcc USBO_R>;
>> -			reset-names = "dwc2";
>> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> -			g-rx-fifo-size = <512>;
>> -			g-np-tx-fifo-size = <32>;
>> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>> -			dr_mode = "otg";
>> -			otg-rev = <0x200>;
>> -			usb33d-supply = <&usb33>;
>> -			status = "disabled";
>> -		};
>> -
>> -		spi4: spi@4c002000 {
>> -			compatible = "st,stm32h7-spi";
>> -			reg = <0x4c002000 0x400>;
>> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SPI4_K>;
>> -			resets = <&rcc SPI4_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 83 0x400 0x01>,
>> -			       <&dmamux1 84 0x400 0x01>;
>> -			dma-names = "rx", "tx";
>> -			status = "disabled";
>> -		};
>> -
>> -		spi5: spi@4c003000 {
>> -			compatible = "st,stm32h7-spi";
>> -			reg = <0x4c003000 0x400>;
>> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SPI5_K>;
>> -			resets = <&rcc SPI5_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 85 0x400 0x01>,
>> -			       <&dmamux1 86 0x400 0x01>;
>> -			dma-names = "rx", "tx";
>> -			status = "disabled";
>> -		};
>> -
>> -		i2c3: i2c@4c004000 {
>> -			compatible = "st,stm32mp13-i2c";
>> -			reg = <0x4c004000 0x400>;
>> -			interrupt-names = "event", "error";
>> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc I2C3_K>;
>> -			resets = <&rcc I2C3_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 73 0x400 0x1>,
>> -			       <&dmamux1 74 0x400 0x1>;
>> -			dma-names = "rx", "tx";
>> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
>> -			i2c-analog-filter;
>> -			status = "disabled";
>> -		};
>> -
>> -		i2c4: i2c@4c005000 {
>> -			compatible = "st,stm32mp13-i2c";
>> -			reg = <0x4c005000 0x400>;
>> -			interrupt-names = "event", "error";
>> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc I2C4_K>;
>> -			resets = <&rcc I2C4_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 75 0x400 0x1>,
>> -			       <&dmamux1 76 0x400 0x1>;
>> -			dma-names = "rx", "tx";
>> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
>> -			i2c-analog-filter;
>> -			status = "disabled";
>> -		};
>> -
>> -		i2c5: i2c@4c006000 {
>> -			compatible = "st,stm32mp13-i2c";
>> -			reg = <0x4c006000 0x400>;
>> -			interrupt-names = "event", "error";
>> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc I2C5_K>;
>> -			resets = <&rcc I2C5_R>;
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			dmas = <&dmamux1 115 0x400 0x1>,
>> -			       <&dmamux1 116 0x400 0x1>;
>> -			dma-names = "rx", "tx";
>> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
>> -			i2c-analog-filter;
>> -			status = "disabled";
>> -		};
>> -
>>  		rcc: rcc@50000000 {
>>  			compatible = "st,stm32mp13-rcc", "syscon";
>>  			reg = <0x50000000 0x1000>;
>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>  			dma-requests = <48>;
>>  		};
>>  
>> -		sdmmc1: mmc@58005000 {
>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> -			arm,primecell-periphid = <0x20253180>;
>> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SDMMC1_K>;
>> -			clock-names = "apb_pclk";
>> -			resets = <&rcc SDMMC1_R>;
>> -			cap-sd-highspeed;
>> -			cap-mmc-highspeed;
>> -			max-frequency = <130000000>;
>> -			status = "disabled";
>> -		};
>> -
>> -		sdmmc2: mmc@58007000 {
>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> -			arm,primecell-periphid = <0x20253180>;
>> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc SDMMC2_K>;
>> -			clock-names = "apb_pclk";
>> -			resets = <&rcc SDMMC2_R>;
>> -			cap-sd-highspeed;
>> -			cap-mmc-highspeed;
>> -			max-frequency = <130000000>;
>> -			status = "disabled";
>> -		};
>> -
>>  		usbh_ohci: usb@5800c000 {
>>  			compatible = "generic-ohci";
>>  			reg = <0x5800c000 0x1000>;
>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>  			status = "disabled";
>>  		};
>>  
>> -		usbphyc: usbphyc@5a006000 {
>> -			#address-cells = <1>;
>> -			#size-cells = <0>;
>> -			#clock-cells = <0>;
>> -			compatible = "st,stm32mp1-usbphyc";
>> -			reg = <0x5a006000 0x1000>;
>> -			clocks = <&rcc USBPHY_K>;
>> -			resets = <&rcc USBPHY_R>;
>> -			vdda1v1-supply = <&reg11>;
>> -			vdda1v8-supply = <&reg18>;
>> -			status = "disabled";
>> -
>> -			usbphyc_port0: usb-phy@0 {
>> -				#phy-cells = <0>;
>> -				reg = <0>;
>> -			};
>> -
>> -			usbphyc_port1: usb-phy@1 {
>> -				#phy-cells = <1>;
>> -				reg = <1>;
>> -			};
>> -		};
>> -
>>  		rtc: rtc@5c004000 {
>>  			compatible = "st,stm32mp1-rtc";
>>  			reg = <0x5c004000 0x400>;
>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>  			};
>>  		};
>>  
>> +		etzpc: bus@5c007000 {
>> +			compatible = "st,stm32mp13-sys-bus";
>> +			reg = <0x5c007000 0x400>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			feature-domain-controller;
>> +			#feature-domain-cells = <1>;
>> +			ranges;
>> +
>> +			adc_2: adc@48004000 {
>> +				compatible = "st,stm32mp13-adc-core";
>> +				reg = <0x48004000 0x400>;
>> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>> +				clock-names = "bus", "adc";
>> +				interrupt-controller;
>> +				#interrupt-cells = <1>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				feature-domains = <&etzpc 33>;
>> +				status = "disabled";
>> +
>> +				adc2: adc@0 {
>> +					compatible = "st,stm32mp13-adc";
>> +					#io-channel-cells = <1>;
>> +					#address-cells = <1>;
>> +					#size-cells = <0>;
>> +					reg = <0x0>;
>> +					interrupt-parent = <&adc_2>;
>> +					interrupts = <0>;
>> +					dmas = <&dmamux1 10 0x400 0x80000001>;
>> +					dma-names = "rx";
>> +					status = "disabled";
>> +
>> +					channel@13 {
>> +						reg = <13>;
>> +						label = "vrefint";
>> +					};
>> +					channel@14 {
>> +						reg = <14>;
>> +						label = "vddcore";
>> +					};
>> +					channel@16 {
>> +						reg = <16>;
>> +						label = "vddcpu";
>> +					};
>> +					channel@17 {
>> +						reg = <17>;
>> +						label = "vddq_ddr";
>> +					};
>> +				};
>> +			};
>> +
>> +			usbotg_hs: usb@49000000 {
>> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>> +				reg = <0x49000000 0x40000>;
>> +				clocks = <&rcc USBO_K>;
>> +				clock-names = "otg";
>> +				resets = <&rcc USBO_R>;
>> +				reset-names = "dwc2";
>> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> +				g-rx-fifo-size = <512>;
>> +				g-np-tx-fifo-size = <32>;
>> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>> +				dr_mode = "otg";
>> +				otg-rev = <0x200>;
>> +				usb33d-supply = <&usb33>;
>> +				feature-domains = <&etzpc 34>;
>> +				status = "disabled";
>> +			};
>> +
>> +			spi4: spi@4c002000 {
>> +				compatible = "st,stm32h7-spi";
>> +				reg = <0x4c002000 0x400>;
>> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SPI4_K>;
>> +				resets = <&rcc SPI4_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 83 0x400 0x01>,
>> +				       <&dmamux1 84 0x400 0x01>;
>> +				dma-names = "rx", "tx";
>> +				feature-domains = <&etzpc 18>;
>> +				status = "disabled";
>> +			};
>> +
>> +			spi5: spi@4c003000 {
>> +				compatible = "st,stm32h7-spi";
>> +				reg = <0x4c003000 0x400>;
>> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SPI5_K>;
>> +				resets = <&rcc SPI5_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 85 0x400 0x01>,
>> +				       <&dmamux1 86 0x400 0x01>;
>> +				dma-names = "rx", "tx";
>> +				feature-domains = <&etzpc 19>;
>> +				status = "disabled";
>> +			};
>> +
>> +			i2c3: i2c@4c004000 {
>> +				compatible = "st,stm32mp13-i2c";
>> +				reg = <0x4c004000 0x400>;
>> +				interrupt-names = "event", "error";
>> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc I2C3_K>;
>> +				resets = <&rcc I2C3_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 73 0x400 0x1>,
>> +				       <&dmamux1 74 0x400 0x1>;
>> +				dma-names = "rx", "tx";
>> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
>> +				i2c-analog-filter;
>> +				feature-domains = <&etzpc 20>;
>> +				status = "disabled";
>> +			};
>> +
>> +			i2c4: i2c@4c005000 {
>> +				compatible = "st,stm32mp13-i2c";
>> +				reg = <0x4c005000 0x400>;
>> +				interrupt-names = "event", "error";
>> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc I2C4_K>;
>> +				resets = <&rcc I2C4_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 75 0x400 0x1>,
>> +				       <&dmamux1 76 0x400 0x1>;
>> +				dma-names = "rx", "tx";
>> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
>> +				i2c-analog-filter;
>> +				feature-domains = <&etzpc 21>;
>> +				status = "disabled";
>> +			};
>> +
>> +			i2c5: i2c@4c006000 {
>> +				compatible = "st,stm32mp13-i2c";
>> +				reg = <0x4c006000 0x400>;
>> +				interrupt-names = "event", "error";
>> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc I2C5_K>;
>> +				resets = <&rcc I2C5_R>;
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				dmas = <&dmamux1 115 0x400 0x1>,
>> +				       <&dmamux1 116 0x400 0x1>;
>> +				dma-names = "rx", "tx";
>> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
>> +				i2c-analog-filter;
>> +				feature-domains = <&etzpc 22>;
>> +				status = "disabled";
>> +			};
>> +
>> +			sdmmc1: mmc@58005000 {
>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> +				arm,primecell-periphid = <0x20253180>;
>> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SDMMC1_K>;
>> +				clock-names = "apb_pclk";
>> +				resets = <&rcc SDMMC1_R>;
>> +				cap-sd-highspeed;
>> +				cap-mmc-highspeed;
>> +				max-frequency = <130000000>;
>> +				feature-domains = <&etzpc 50>;
>> +				status = "disabled";
>> +			};
>> +
>> +			sdmmc2: mmc@58007000 {
>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>> +				arm,primecell-periphid = <0x20253180>;
>> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>> +				clocks = <&rcc SDMMC2_K>;
>> +				clock-names = "apb_pclk";
>> +				resets = <&rcc SDMMC2_R>;
>> +				cap-sd-highspeed;
>> +				cap-mmc-highspeed;
>> +				max-frequency = <130000000>;
>> +				feature-domains = <&etzpc 51>;
>> +				status = "disabled";
>> +			};
>> +
>> +			usbphyc: usbphyc@5a006000 {
>> +				#address-cells = <1>;
>> +				#size-cells = <0>;
>> +				#clock-cells = <0>;
>> +				compatible = "st,stm32mp1-usbphyc";
>> +				reg = <0x5a006000 0x1000>;
>> +				clocks = <&rcc USBPHY_K>;
>> +				resets = <&rcc USBPHY_R>;
>> +				vdda1v1-supply = <&reg11>;
>> +				vdda1v8-supply = <&reg18>;
>> +				feature-domains = <&etzpc 5>;
>> +				status = "disabled";
>> +
>> +				usbphyc_port0: usb-phy@0 {
>> +					#phy-cells = <0>;
>> +					reg = <0>;
>> +				};
>> +
>> +				usbphyc_port1: usb-phy@1 {
>> +					#phy-cells = <1>;
>> +					reg = <1>;
>> +				};
>> +			};
>> +
>> +		};
>> +
>>  		/*
>>  		 * Break node order to solve dependency probe issue between
>>  		 * pinctrl and exti.
>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>> index df451c3c2a26..be6061552683 100644
>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>  			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>  			status = "disabled";
>>  		};
>> +	};
>> +};
>>  
>> -		adc_1: adc@48003000 {
>> -			compatible = "st,stm32mp13-adc-core";
>> -			reg = <0x48003000 0x400>;
>> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>> -			clock-names = "bus", "adc";
>> -			interrupt-controller;
>> -			#interrupt-cells = <1>;
>> +&etzpc {
>> +	adc_1: adc@48003000 {
>> +		compatible = "st,stm32mp13-adc-core";
>> +		reg = <0x48003000 0x400>;
>> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>> +		clock-names = "bus", "adc";
>> +		interrupt-controller;
>> +		#interrupt-cells = <1>;
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		feature-domains = <&etzpc 32>;
>> +		status = "disabled";
>> +
>> +		adc1: adc@0 {
>> +			compatible = "st,stm32mp13-adc";
>> +			#io-channel-cells = <1>;
>>  			#address-cells = <1>;
>>  			#size-cells = <0>;
>> +			reg = <0x0>;
>> +			interrupt-parent = <&adc_1>;
>> +			interrupts = <0>;
>> +			dmas = <&dmamux1 9 0x400 0x80000001>;
>> +			dma-names = "rx";
>>  			status = "disabled";
>>  
>> -			adc1: adc@0 {
>> -				compatible = "st,stm32mp13-adc";
>> -				#io-channel-cells = <1>;
>> -				#address-cells = <1>;
>> -				#size-cells = <0>;
>> -				reg = <0x0>;
>> -				interrupt-parent = <&adc_1>;
>> -				interrupts = <0>;
>> -				dmas = <&dmamux1 9 0x400 0x80000001>;
>> -				dma-names = "rx";
>> -				status = "disabled";
>> -
>> -				channel@18 {
>> -					reg = <18>;
>> -					label = "vrefint";
>> -				};
>> +			channel@18 {
>> +				reg = <18>;
>> +				label = "vrefint";
>>  			};
>>  		};
>>  	};
>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>> index 4d00e7592882..a1a7a40c2a3e 100644
>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>> @@ -4,15 +4,14 @@
>>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>   */
>>  
>> -/ {
>> -	soc {
>> -		cryp: crypto@54002000 {
>> -			compatible = "st,stm32mp1-cryp";
>> -			reg = <0x54002000 0x400>;
>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc CRYP1>;
>> -			resets = <&rcc CRYP1_R>;
>> -			status = "disabled";
>> -		};
>> +&etzpc {
>> +	cryp: crypto@54002000 {
>> +		compatible = "st,stm32mp1-cryp";
>> +		reg = <0x54002000 0x400>;
>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&rcc CRYP1>;
>> +		resets = <&rcc CRYP1_R>;
>> +		feature-domains = <&etzpc 42>;
>> +		status = "disabled";
>>  	};
>>  };
>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>> index 4d00e7592882..b9fb071a1471 100644
>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>> @@ -4,15 +4,13 @@
>>   * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>   */
>>  
>> -/ {
>> -	soc {
>> -		cryp: crypto@54002000 {
>> -			compatible = "st,stm32mp1-cryp";
>> -			reg = <0x54002000 0x400>;
>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&rcc CRYP1>;
>> -			resets = <&rcc CRYP1_R>;
>> -			status = "disabled";
>> -		};
>> +&etzpc {
>> +	cryp: crypto@54002000 {
>> +		compatible = "st,stm32mp1-cryp";
>> +		reg = <0x54002000 0x400>;
>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>> +		clocks = <&rcc CRYP1>;
>> +		resets = <&rcc CRYP1_R>;
>> +		status = "disabled";
>>  	};
>>  };
> 

-- 
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31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  2023-02-09  8:10       ` Ahmad Fatoum
  (?)
  (?)
@ 2023-02-13 10:54         ` Gatien CHEVALLIER
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-13 10:54 UTC (permalink / raw)
  To: Ahmad Fatoum, Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media

Hi Ahmad, Uwe,

On 2/9/23 09:10, Ahmad Fatoum wrote:
> On 09.02.23 08:46, Ahmad Fatoum wrote:
>> Hello Gatien,
>>
>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>> The STM32 System Bus is an internal bus on which devices are connected.
>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>> and control access to the peripherals connected on it.
>>>
>>> For more information on which peripheral is securable, please read
>>> the STM32MP13 reference manual.
>>
>> Diff is way too big. Please split up the alphabetic reordering into its
>> own commit, so actual functional changes are apparent.
> 
> Ah, I see now that you are moving securable peripherals into a new bus.
> I share Uwe's confusion of considering the ETZPC as bus.
> 
> Does this configuration even change dynamically? Why can't you implement
> this binding in the bootloader and have Linux only see a DT where unavailable
> nodes are status = "disabled"; secure-status = "okay"?
> 
> For inspiration, see barebox' device tree fixups when devices are disabled
> per fuse:
> 
>    https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
> 
> Cheers,
> Ahmad

This configuration can change dynamically. The binding will be 
implemented in the bootloader, where the ETZPC is already implemented as 
a bus in our downstream.

I find the mentionned example valid.

Now, why is it a bus? :D

It is the result of the discussion on the previous submission by 
Benjamin (Sorry for the lack of link but I saw that you participated on 
these threads)+ we need the bus mechanism to control whether a subnode 
should be probed or not. You can see it as a firewall bus.

The ETZPC relies on the ARM TrustZone extension to the AHB bus and 
propagation through bridges to the APB bus. Therefore, I find it 
relevant to consider it as a bus, what is your opinion?

This patchset is a first step to the implementation of an API to control 
accesses dynamically.

> 
>>
>> Thanks,
>> Ahmad
>>
>>>
>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>> ---
>>>
>>> No changes in V2.
>>>
>>> Changes in V3:
>>> 	-Use appriopriate node name: bus
>>>
>>>   arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>   arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>   arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>   arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>   4 files changed, 258 insertions(+), 237 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>> index accc3824f7e9..24462a647101 100644
>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>   			dma-channels = <16>;
>>>   		};
>>>   
>>> -		adc_2: adc@48004000 {
>>> -			compatible = "st,stm32mp13-adc-core";
>>> -			reg = <0x48004000 0x400>;
>>> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>> -			clock-names = "bus", "adc";
>>> -			interrupt-controller;
>>> -			#interrupt-cells = <1>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			status = "disabled";
>>> -
>>> -			adc2: adc@0 {
>>> -				compatible = "st,stm32mp13-adc";
>>> -				#io-channel-cells = <1>;
>>> -				#address-cells = <1>;
>>> -				#size-cells = <0>;
>>> -				reg = <0x0>;
>>> -				interrupt-parent = <&adc_2>;
>>> -				interrupts = <0>;
>>> -				dmas = <&dmamux1 10 0x400 0x80000001>;
>>> -				dma-names = "rx";
>>> -				status = "disabled";
>>> -
>>> -				channel@13 {
>>> -					reg = <13>;
>>> -					label = "vrefint";
>>> -				};
>>> -				channel@14 {
>>> -					reg = <14>;
>>> -					label = "vddcore";
>>> -				};
>>> -				channel@16 {
>>> -					reg = <16>;
>>> -					label = "vddcpu";
>>> -				};
>>> -				channel@17 {
>>> -					reg = <17>;
>>> -					label = "vddq_ddr";
>>> -				};
>>> -			};
>>> -		};
>>> -
>>> -		usbotg_hs: usb@49000000 {
>>> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>> -			reg = <0x49000000 0x40000>;
>>> -			clocks = <&rcc USBO_K>;
>>> -			clock-names = "otg";
>>> -			resets = <&rcc USBO_R>;
>>> -			reset-names = "dwc2";
>>> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> -			g-rx-fifo-size = <512>;
>>> -			g-np-tx-fifo-size = <32>;
>>> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>> -			dr_mode = "otg";
>>> -			otg-rev = <0x200>;
>>> -			usb33d-supply = <&usb33>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		spi4: spi@4c002000 {
>>> -			compatible = "st,stm32h7-spi";
>>> -			reg = <0x4c002000 0x400>;
>>> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SPI4_K>;
>>> -			resets = <&rcc SPI4_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 83 0x400 0x01>,
>>> -			       <&dmamux1 84 0x400 0x01>;
>>> -			dma-names = "rx", "tx";
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		spi5: spi@4c003000 {
>>> -			compatible = "st,stm32h7-spi";
>>> -			reg = <0x4c003000 0x400>;
>>> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SPI5_K>;
>>> -			resets = <&rcc SPI5_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 85 0x400 0x01>,
>>> -			       <&dmamux1 86 0x400 0x01>;
>>> -			dma-names = "rx", "tx";
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c3: i2c@4c004000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c004000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C3_K>;
>>> -			resets = <&rcc I2C3_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 73 0x400 0x1>,
>>> -			       <&dmamux1 74 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c4: i2c@4c005000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c005000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C4_K>;
>>> -			resets = <&rcc I2C4_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 75 0x400 0x1>,
>>> -			       <&dmamux1 76 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c5: i2c@4c006000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c006000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C5_K>;
>>> -			resets = <&rcc I2C5_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 115 0x400 0x1>,
>>> -			       <&dmamux1 116 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>>   		rcc: rcc@50000000 {
>>>   			compatible = "st,stm32mp13-rcc", "syscon";
>>>   			reg = <0x50000000 0x1000>;
>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>   			dma-requests = <48>;
>>>   		};
>>>   
>>> -		sdmmc1: mmc@58005000 {
>>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> -			arm,primecell-periphid = <0x20253180>;
>>> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SDMMC1_K>;
>>> -			clock-names = "apb_pclk";
>>> -			resets = <&rcc SDMMC1_R>;
>>> -			cap-sd-highspeed;
>>> -			cap-mmc-highspeed;
>>> -			max-frequency = <130000000>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		sdmmc2: mmc@58007000 {
>>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> -			arm,primecell-periphid = <0x20253180>;
>>> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SDMMC2_K>;
>>> -			clock-names = "apb_pclk";
>>> -			resets = <&rcc SDMMC2_R>;
>>> -			cap-sd-highspeed;
>>> -			cap-mmc-highspeed;
>>> -			max-frequency = <130000000>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>>   		usbh_ohci: usb@5800c000 {
>>>   			compatible = "generic-ohci";
>>>   			reg = <0x5800c000 0x1000>;
>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>   			status = "disabled";
>>>   		};
>>>   
>>> -		usbphyc: usbphyc@5a006000 {
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			#clock-cells = <0>;
>>> -			compatible = "st,stm32mp1-usbphyc";
>>> -			reg = <0x5a006000 0x1000>;
>>> -			clocks = <&rcc USBPHY_K>;
>>> -			resets = <&rcc USBPHY_R>;
>>> -			vdda1v1-supply = <&reg11>;
>>> -			vdda1v8-supply = <&reg18>;
>>> -			status = "disabled";
>>> -
>>> -			usbphyc_port0: usb-phy@0 {
>>> -				#phy-cells = <0>;
>>> -				reg = <0>;
>>> -			};
>>> -
>>> -			usbphyc_port1: usb-phy@1 {
>>> -				#phy-cells = <1>;
>>> -				reg = <1>;
>>> -			};
>>> -		};
>>> -
>>>   		rtc: rtc@5c004000 {
>>>   			compatible = "st,stm32mp1-rtc";
>>>   			reg = <0x5c004000 0x400>;
>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>   			};
>>>   		};
>>>   
>>> +		etzpc: bus@5c007000 {
>>> +			compatible = "st,stm32mp13-sys-bus";
>>> +			reg = <0x5c007000 0x400>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <1>;
>>> +			feature-domain-controller;
>>> +			#feature-domain-cells = <1>;
>>> +			ranges;
>>> +
>>> +			adc_2: adc@48004000 {
>>> +				compatible = "st,stm32mp13-adc-core";
>>> +				reg = <0x48004000 0x400>;
>>> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>> +				clock-names = "bus", "adc";
>>> +				interrupt-controller;
>>> +				#interrupt-cells = <1>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				feature-domains = <&etzpc 33>;
>>> +				status = "disabled";
>>> +
>>> +				adc2: adc@0 {
>>> +					compatible = "st,stm32mp13-adc";
>>> +					#io-channel-cells = <1>;
>>> +					#address-cells = <1>;
>>> +					#size-cells = <0>;
>>> +					reg = <0x0>;
>>> +					interrupt-parent = <&adc_2>;
>>> +					interrupts = <0>;
>>> +					dmas = <&dmamux1 10 0x400 0x80000001>;
>>> +					dma-names = "rx";
>>> +					status = "disabled";
>>> +
>>> +					channel@13 {
>>> +						reg = <13>;
>>> +						label = "vrefint";
>>> +					};
>>> +					channel@14 {
>>> +						reg = <14>;
>>> +						label = "vddcore";
>>> +					};
>>> +					channel@16 {
>>> +						reg = <16>;
>>> +						label = "vddcpu";
>>> +					};
>>> +					channel@17 {
>>> +						reg = <17>;
>>> +						label = "vddq_ddr";
>>> +					};
>>> +				};
>>> +			};
>>> +
>>> +			usbotg_hs: usb@49000000 {
>>> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>> +				reg = <0x49000000 0x40000>;
>>> +				clocks = <&rcc USBO_K>;
>>> +				clock-names = "otg";
>>> +				resets = <&rcc USBO_R>;
>>> +				reset-names = "dwc2";
>>> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> +				g-rx-fifo-size = <512>;
>>> +				g-np-tx-fifo-size = <32>;
>>> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>> +				dr_mode = "otg";
>>> +				otg-rev = <0x200>;
>>> +				usb33d-supply = <&usb33>;
>>> +				feature-domains = <&etzpc 34>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			spi4: spi@4c002000 {
>>> +				compatible = "st,stm32h7-spi";
>>> +				reg = <0x4c002000 0x400>;
>>> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SPI4_K>;
>>> +				resets = <&rcc SPI4_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 83 0x400 0x01>,
>>> +				       <&dmamux1 84 0x400 0x01>;
>>> +				dma-names = "rx", "tx";
>>> +				feature-domains = <&etzpc 18>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			spi5: spi@4c003000 {
>>> +				compatible = "st,stm32h7-spi";
>>> +				reg = <0x4c003000 0x400>;
>>> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SPI5_K>;
>>> +				resets = <&rcc SPI5_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 85 0x400 0x01>,
>>> +				       <&dmamux1 86 0x400 0x01>;
>>> +				dma-names = "rx", "tx";
>>> +				feature-domains = <&etzpc 19>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c3: i2c@4c004000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c004000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C3_K>;
>>> +				resets = <&rcc I2C3_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 73 0x400 0x1>,
>>> +				       <&dmamux1 74 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 20>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c4: i2c@4c005000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c005000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C4_K>;
>>> +				resets = <&rcc I2C4_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 75 0x400 0x1>,
>>> +				       <&dmamux1 76 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 21>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c5: i2c@4c006000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c006000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C5_K>;
>>> +				resets = <&rcc I2C5_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 115 0x400 0x1>,
>>> +				       <&dmamux1 116 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 22>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			sdmmc1: mmc@58005000 {
>>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> +				arm,primecell-periphid = <0x20253180>;
>>> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SDMMC1_K>;
>>> +				clock-names = "apb_pclk";
>>> +				resets = <&rcc SDMMC1_R>;
>>> +				cap-sd-highspeed;
>>> +				cap-mmc-highspeed;
>>> +				max-frequency = <130000000>;
>>> +				feature-domains = <&etzpc 50>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			sdmmc2: mmc@58007000 {
>>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> +				arm,primecell-periphid = <0x20253180>;
>>> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SDMMC2_K>;
>>> +				clock-names = "apb_pclk";
>>> +				resets = <&rcc SDMMC2_R>;
>>> +				cap-sd-highspeed;
>>> +				cap-mmc-highspeed;
>>> +				max-frequency = <130000000>;
>>> +				feature-domains = <&etzpc 51>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			usbphyc: usbphyc@5a006000 {
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				#clock-cells = <0>;
>>> +				compatible = "st,stm32mp1-usbphyc";
>>> +				reg = <0x5a006000 0x1000>;
>>> +				clocks = <&rcc USBPHY_K>;
>>> +				resets = <&rcc USBPHY_R>;
>>> +				vdda1v1-supply = <&reg11>;
>>> +				vdda1v8-supply = <&reg18>;
>>> +				feature-domains = <&etzpc 5>;
>>> +				status = "disabled";
>>> +
>>> +				usbphyc_port0: usb-phy@0 {
>>> +					#phy-cells = <0>;
>>> +					reg = <0>;
>>> +				};
>>> +
>>> +				usbphyc_port1: usb-phy@1 {
>>> +					#phy-cells = <1>;
>>> +					reg = <1>;
>>> +				};
>>> +			};
>>> +
>>> +		};
>>> +
>>>   		/*
>>>   		 * Break node order to solve dependency probe issue between
>>>   		 * pinctrl and exti.
>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>> index df451c3c2a26..be6061552683 100644
>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>   			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>   			status = "disabled";
>>>   		};
>>> +	};
>>> +};
>>>   
>>> -		adc_1: adc@48003000 {
>>> -			compatible = "st,stm32mp13-adc-core";
>>> -			reg = <0x48003000 0x400>;
>>> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>> -			clock-names = "bus", "adc";
>>> -			interrupt-controller;
>>> -			#interrupt-cells = <1>;
>>> +&etzpc {
>>> +	adc_1: adc@48003000 {
>>> +		compatible = "st,stm32mp13-adc-core";
>>> +		reg = <0x48003000 0x400>;
>>> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>> +		clock-names = "bus", "adc";
>>> +		interrupt-controller;
>>> +		#interrupt-cells = <1>;
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +		feature-domains = <&etzpc 32>;
>>> +		status = "disabled";
>>> +
>>> +		adc1: adc@0 {
>>> +			compatible = "st,stm32mp13-adc";
>>> +			#io-channel-cells = <1>;
>>>   			#address-cells = <1>;
>>>   			#size-cells = <0>;
>>> +			reg = <0x0>;
>>> +			interrupt-parent = <&adc_1>;
>>> +			interrupts = <0>;
>>> +			dmas = <&dmamux1 9 0x400 0x80000001>;
>>> +			dma-names = "rx";
>>>   			status = "disabled";
>>>   
>>> -			adc1: adc@0 {
>>> -				compatible = "st,stm32mp13-adc";
>>> -				#io-channel-cells = <1>;
>>> -				#address-cells = <1>;
>>> -				#size-cells = <0>;
>>> -				reg = <0x0>;
>>> -				interrupt-parent = <&adc_1>;
>>> -				interrupts = <0>;
>>> -				dmas = <&dmamux1 9 0x400 0x80000001>;
>>> -				dma-names = "rx";
>>> -				status = "disabled";
>>> -
>>> -				channel@18 {
>>> -					reg = <18>;
>>> -					label = "vrefint";
>>> -				};
>>> +			channel@18 {
>>> +				reg = <18>;
>>> +				label = "vrefint";
>>>   			};
>>>   		};
>>>   	};
>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> @@ -4,15 +4,14 @@
>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>    */
>>>   
>>> -/ {
>>> -	soc {
>>> -		cryp: crypto@54002000 {
>>> -			compatible = "st,stm32mp1-cryp";
>>> -			reg = <0x54002000 0x400>;
>>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc CRYP1>;
>>> -			resets = <&rcc CRYP1_R>;
>>> -			status = "disabled";
>>> -		};
>>> +&etzpc {
>>> +	cryp: crypto@54002000 {
>>> +		compatible = "st,stm32mp1-cryp";
>>> +		reg = <0x54002000 0x400>;
>>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc CRYP1>;
>>> +		resets = <&rcc CRYP1_R>;
>>> +		feature-domains = <&etzpc 42>;
>>> +		status = "disabled";
>>>   	};
>>>   };
>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> index 4d00e7592882..b9fb071a1471 100644
>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> @@ -4,15 +4,13 @@
>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>    */
>>>   
>>> -/ {
>>> -	soc {
>>> -		cryp: crypto@54002000 {
>>> -			compatible = "st,stm32mp1-cryp";
>>> -			reg = <0x54002000 0x400>;
>>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc CRYP1>;
>>> -			resets = <&rcc CRYP1_R>;
>>> -			status = "disabled";
>>> -		};
>>> +&etzpc {
>>> +	cryp: crypto@54002000 {
>>> +		compatible = "st,stm32mp1-cryp";
>>> +		reg = <0x54002000 0x400>;
>>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc CRYP1>;
>>> +		resets = <&rcc CRYP1_R>;
>>> +		status = "disabled";
>>>   	};
>>>   };
>>
> 

Regarding the patch itself, I can separate it in two patches.
1)Introduce ETZPC
2)Move peripherals under ETZPC

Best regards,
Gatien

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-13 10:54         ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-13 10:54 UTC (permalink / raw)
  To: Ahmad Fatoum, Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media

Hi Ahmad, Uwe,

On 2/9/23 09:10, Ahmad Fatoum wrote:
> On 09.02.23 08:46, Ahmad Fatoum wrote:
>> Hello Gatien,
>>
>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>> The STM32 System Bus is an internal bus on which devices are connected.
>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>> and control access to the peripherals connected on it.
>>>
>>> For more information on which peripheral is securable, please read
>>> the STM32MP13 reference manual.
>>
>> Diff is way too big. Please split up the alphabetic reordering into its
>> own commit, so actual functional changes are apparent.
> 
> Ah, I see now that you are moving securable peripherals into a new bus.
> I share Uwe's confusion of considering the ETZPC as bus.
> 
> Does this configuration even change dynamically? Why can't you implement
> this binding in the bootloader and have Linux only see a DT where unavailable
> nodes are status = "disabled"; secure-status = "okay"?
> 
> For inspiration, see barebox' device tree fixups when devices are disabled
> per fuse:
> 
>    https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
> 
> Cheers,
> Ahmad

This configuration can change dynamically. The binding will be 
implemented in the bootloader, where the ETZPC is already implemented as 
a bus in our downstream.

I find the mentionned example valid.

Now, why is it a bus? :D

It is the result of the discussion on the previous submission by 
Benjamin (Sorry for the lack of link but I saw that you participated on 
these threads)+ we need the bus mechanism to control whether a subnode 
should be probed or not. You can see it as a firewall bus.

The ETZPC relies on the ARM TrustZone extension to the AHB bus and 
propagation through bridges to the APB bus. Therefore, I find it 
relevant to consider it as a bus, what is your opinion?

This patchset is a first step to the implementation of an API to control 
accesses dynamically.

> 
>>
>> Thanks,
>> Ahmad
>>
>>>
>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>> ---
>>>
>>> No changes in V2.
>>>
>>> Changes in V3:
>>> 	-Use appriopriate node name: bus
>>>
>>>   arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>   arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>   arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>   arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>   4 files changed, 258 insertions(+), 237 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>> index accc3824f7e9..24462a647101 100644
>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>   			dma-channels = <16>;
>>>   		};
>>>   
>>> -		adc_2: adc@48004000 {
>>> -			compatible = "st,stm32mp13-adc-core";
>>> -			reg = <0x48004000 0x400>;
>>> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>> -			clock-names = "bus", "adc";
>>> -			interrupt-controller;
>>> -			#interrupt-cells = <1>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			status = "disabled";
>>> -
>>> -			adc2: adc@0 {
>>> -				compatible = "st,stm32mp13-adc";
>>> -				#io-channel-cells = <1>;
>>> -				#address-cells = <1>;
>>> -				#size-cells = <0>;
>>> -				reg = <0x0>;
>>> -				interrupt-parent = <&adc_2>;
>>> -				interrupts = <0>;
>>> -				dmas = <&dmamux1 10 0x400 0x80000001>;
>>> -				dma-names = "rx";
>>> -				status = "disabled";
>>> -
>>> -				channel@13 {
>>> -					reg = <13>;
>>> -					label = "vrefint";
>>> -				};
>>> -				channel@14 {
>>> -					reg = <14>;
>>> -					label = "vddcore";
>>> -				};
>>> -				channel@16 {
>>> -					reg = <16>;
>>> -					label = "vddcpu";
>>> -				};
>>> -				channel@17 {
>>> -					reg = <17>;
>>> -					label = "vddq_ddr";
>>> -				};
>>> -			};
>>> -		};
>>> -
>>> -		usbotg_hs: usb@49000000 {
>>> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>> -			reg = <0x49000000 0x40000>;
>>> -			clocks = <&rcc USBO_K>;
>>> -			clock-names = "otg";
>>> -			resets = <&rcc USBO_R>;
>>> -			reset-names = "dwc2";
>>> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> -			g-rx-fifo-size = <512>;
>>> -			g-np-tx-fifo-size = <32>;
>>> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>> -			dr_mode = "otg";
>>> -			otg-rev = <0x200>;
>>> -			usb33d-supply = <&usb33>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		spi4: spi@4c002000 {
>>> -			compatible = "st,stm32h7-spi";
>>> -			reg = <0x4c002000 0x400>;
>>> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SPI4_K>;
>>> -			resets = <&rcc SPI4_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 83 0x400 0x01>,
>>> -			       <&dmamux1 84 0x400 0x01>;
>>> -			dma-names = "rx", "tx";
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		spi5: spi@4c003000 {
>>> -			compatible = "st,stm32h7-spi";
>>> -			reg = <0x4c003000 0x400>;
>>> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SPI5_K>;
>>> -			resets = <&rcc SPI5_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 85 0x400 0x01>,
>>> -			       <&dmamux1 86 0x400 0x01>;
>>> -			dma-names = "rx", "tx";
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c3: i2c@4c004000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c004000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C3_K>;
>>> -			resets = <&rcc I2C3_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 73 0x400 0x1>,
>>> -			       <&dmamux1 74 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c4: i2c@4c005000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c005000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C4_K>;
>>> -			resets = <&rcc I2C4_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 75 0x400 0x1>,
>>> -			       <&dmamux1 76 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c5: i2c@4c006000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c006000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C5_K>;
>>> -			resets = <&rcc I2C5_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 115 0x400 0x1>,
>>> -			       <&dmamux1 116 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>>   		rcc: rcc@50000000 {
>>>   			compatible = "st,stm32mp13-rcc", "syscon";
>>>   			reg = <0x50000000 0x1000>;
>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>   			dma-requests = <48>;
>>>   		};
>>>   
>>> -		sdmmc1: mmc@58005000 {
>>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> -			arm,primecell-periphid = <0x20253180>;
>>> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SDMMC1_K>;
>>> -			clock-names = "apb_pclk";
>>> -			resets = <&rcc SDMMC1_R>;
>>> -			cap-sd-highspeed;
>>> -			cap-mmc-highspeed;
>>> -			max-frequency = <130000000>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		sdmmc2: mmc@58007000 {
>>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> -			arm,primecell-periphid = <0x20253180>;
>>> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SDMMC2_K>;
>>> -			clock-names = "apb_pclk";
>>> -			resets = <&rcc SDMMC2_R>;
>>> -			cap-sd-highspeed;
>>> -			cap-mmc-highspeed;
>>> -			max-frequency = <130000000>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>>   		usbh_ohci: usb@5800c000 {
>>>   			compatible = "generic-ohci";
>>>   			reg = <0x5800c000 0x1000>;
>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>   			status = "disabled";
>>>   		};
>>>   
>>> -		usbphyc: usbphyc@5a006000 {
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			#clock-cells = <0>;
>>> -			compatible = "st,stm32mp1-usbphyc";
>>> -			reg = <0x5a006000 0x1000>;
>>> -			clocks = <&rcc USBPHY_K>;
>>> -			resets = <&rcc USBPHY_R>;
>>> -			vdda1v1-supply = <&reg11>;
>>> -			vdda1v8-supply = <&reg18>;
>>> -			status = "disabled";
>>> -
>>> -			usbphyc_port0: usb-phy@0 {
>>> -				#phy-cells = <0>;
>>> -				reg = <0>;
>>> -			};
>>> -
>>> -			usbphyc_port1: usb-phy@1 {
>>> -				#phy-cells = <1>;
>>> -				reg = <1>;
>>> -			};
>>> -		};
>>> -
>>>   		rtc: rtc@5c004000 {
>>>   			compatible = "st,stm32mp1-rtc";
>>>   			reg = <0x5c004000 0x400>;
>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>   			};
>>>   		};
>>>   
>>> +		etzpc: bus@5c007000 {
>>> +			compatible = "st,stm32mp13-sys-bus";
>>> +			reg = <0x5c007000 0x400>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <1>;
>>> +			feature-domain-controller;
>>> +			#feature-domain-cells = <1>;
>>> +			ranges;
>>> +
>>> +			adc_2: adc@48004000 {
>>> +				compatible = "st,stm32mp13-adc-core";
>>> +				reg = <0x48004000 0x400>;
>>> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>> +				clock-names = "bus", "adc";
>>> +				interrupt-controller;
>>> +				#interrupt-cells = <1>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				feature-domains = <&etzpc 33>;
>>> +				status = "disabled";
>>> +
>>> +				adc2: adc@0 {
>>> +					compatible = "st,stm32mp13-adc";
>>> +					#io-channel-cells = <1>;
>>> +					#address-cells = <1>;
>>> +					#size-cells = <0>;
>>> +					reg = <0x0>;
>>> +					interrupt-parent = <&adc_2>;
>>> +					interrupts = <0>;
>>> +					dmas = <&dmamux1 10 0x400 0x80000001>;
>>> +					dma-names = "rx";
>>> +					status = "disabled";
>>> +
>>> +					channel@13 {
>>> +						reg = <13>;
>>> +						label = "vrefint";
>>> +					};
>>> +					channel@14 {
>>> +						reg = <14>;
>>> +						label = "vddcore";
>>> +					};
>>> +					channel@16 {
>>> +						reg = <16>;
>>> +						label = "vddcpu";
>>> +					};
>>> +					channel@17 {
>>> +						reg = <17>;
>>> +						label = "vddq_ddr";
>>> +					};
>>> +				};
>>> +			};
>>> +
>>> +			usbotg_hs: usb@49000000 {
>>> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>> +				reg = <0x49000000 0x40000>;
>>> +				clocks = <&rcc USBO_K>;
>>> +				clock-names = "otg";
>>> +				resets = <&rcc USBO_R>;
>>> +				reset-names = "dwc2";
>>> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> +				g-rx-fifo-size = <512>;
>>> +				g-np-tx-fifo-size = <32>;
>>> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>> +				dr_mode = "otg";
>>> +				otg-rev = <0x200>;
>>> +				usb33d-supply = <&usb33>;
>>> +				feature-domains = <&etzpc 34>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			spi4: spi@4c002000 {
>>> +				compatible = "st,stm32h7-spi";
>>> +				reg = <0x4c002000 0x400>;
>>> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SPI4_K>;
>>> +				resets = <&rcc SPI4_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 83 0x400 0x01>,
>>> +				       <&dmamux1 84 0x400 0x01>;
>>> +				dma-names = "rx", "tx";
>>> +				feature-domains = <&etzpc 18>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			spi5: spi@4c003000 {
>>> +				compatible = "st,stm32h7-spi";
>>> +				reg = <0x4c003000 0x400>;
>>> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SPI5_K>;
>>> +				resets = <&rcc SPI5_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 85 0x400 0x01>,
>>> +				       <&dmamux1 86 0x400 0x01>;
>>> +				dma-names = "rx", "tx";
>>> +				feature-domains = <&etzpc 19>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c3: i2c@4c004000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c004000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C3_K>;
>>> +				resets = <&rcc I2C3_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 73 0x400 0x1>,
>>> +				       <&dmamux1 74 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 20>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c4: i2c@4c005000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c005000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C4_K>;
>>> +				resets = <&rcc I2C4_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 75 0x400 0x1>,
>>> +				       <&dmamux1 76 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 21>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c5: i2c@4c006000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c006000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C5_K>;
>>> +				resets = <&rcc I2C5_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 115 0x400 0x1>,
>>> +				       <&dmamux1 116 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 22>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			sdmmc1: mmc@58005000 {
>>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> +				arm,primecell-periphid = <0x20253180>;
>>> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SDMMC1_K>;
>>> +				clock-names = "apb_pclk";
>>> +				resets = <&rcc SDMMC1_R>;
>>> +				cap-sd-highspeed;
>>> +				cap-mmc-highspeed;
>>> +				max-frequency = <130000000>;
>>> +				feature-domains = <&etzpc 50>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			sdmmc2: mmc@58007000 {
>>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> +				arm,primecell-periphid = <0x20253180>;
>>> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SDMMC2_K>;
>>> +				clock-names = "apb_pclk";
>>> +				resets = <&rcc SDMMC2_R>;
>>> +				cap-sd-highspeed;
>>> +				cap-mmc-highspeed;
>>> +				max-frequency = <130000000>;
>>> +				feature-domains = <&etzpc 51>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			usbphyc: usbphyc@5a006000 {
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				#clock-cells = <0>;
>>> +				compatible = "st,stm32mp1-usbphyc";
>>> +				reg = <0x5a006000 0x1000>;
>>> +				clocks = <&rcc USBPHY_K>;
>>> +				resets = <&rcc USBPHY_R>;
>>> +				vdda1v1-supply = <&reg11>;
>>> +				vdda1v8-supply = <&reg18>;
>>> +				feature-domains = <&etzpc 5>;
>>> +				status = "disabled";
>>> +
>>> +				usbphyc_port0: usb-phy@0 {
>>> +					#phy-cells = <0>;
>>> +					reg = <0>;
>>> +				};
>>> +
>>> +				usbphyc_port1: usb-phy@1 {
>>> +					#phy-cells = <1>;
>>> +					reg = <1>;
>>> +				};
>>> +			};
>>> +
>>> +		};
>>> +
>>>   		/*
>>>   		 * Break node order to solve dependency probe issue between
>>>   		 * pinctrl and exti.
>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>> index df451c3c2a26..be6061552683 100644
>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>   			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>   			status = "disabled";
>>>   		};
>>> +	};
>>> +};
>>>   
>>> -		adc_1: adc@48003000 {
>>> -			compatible = "st,stm32mp13-adc-core";
>>> -			reg = <0x48003000 0x400>;
>>> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>> -			clock-names = "bus", "adc";
>>> -			interrupt-controller;
>>> -			#interrupt-cells = <1>;
>>> +&etzpc {
>>> +	adc_1: adc@48003000 {
>>> +		compatible = "st,stm32mp13-adc-core";
>>> +		reg = <0x48003000 0x400>;
>>> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>> +		clock-names = "bus", "adc";
>>> +		interrupt-controller;
>>> +		#interrupt-cells = <1>;
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +		feature-domains = <&etzpc 32>;
>>> +		status = "disabled";
>>> +
>>> +		adc1: adc@0 {
>>> +			compatible = "st,stm32mp13-adc";
>>> +			#io-channel-cells = <1>;
>>>   			#address-cells = <1>;
>>>   			#size-cells = <0>;
>>> +			reg = <0x0>;
>>> +			interrupt-parent = <&adc_1>;
>>> +			interrupts = <0>;
>>> +			dmas = <&dmamux1 9 0x400 0x80000001>;
>>> +			dma-names = "rx";
>>>   			status = "disabled";
>>>   
>>> -			adc1: adc@0 {
>>> -				compatible = "st,stm32mp13-adc";
>>> -				#io-channel-cells = <1>;
>>> -				#address-cells = <1>;
>>> -				#size-cells = <0>;
>>> -				reg = <0x0>;
>>> -				interrupt-parent = <&adc_1>;
>>> -				interrupts = <0>;
>>> -				dmas = <&dmamux1 9 0x400 0x80000001>;
>>> -				dma-names = "rx";
>>> -				status = "disabled";
>>> -
>>> -				channel@18 {
>>> -					reg = <18>;
>>> -					label = "vrefint";
>>> -				};
>>> +			channel@18 {
>>> +				reg = <18>;
>>> +				label = "vrefint";
>>>   			};
>>>   		};
>>>   	};
>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> @@ -4,15 +4,14 @@
>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>    */
>>>   
>>> -/ {
>>> -	soc {
>>> -		cryp: crypto@54002000 {
>>> -			compatible = "st,stm32mp1-cryp";
>>> -			reg = <0x54002000 0x400>;
>>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc CRYP1>;
>>> -			resets = <&rcc CRYP1_R>;
>>> -			status = "disabled";
>>> -		};
>>> +&etzpc {
>>> +	cryp: crypto@54002000 {
>>> +		compatible = "st,stm32mp1-cryp";
>>> +		reg = <0x54002000 0x400>;
>>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc CRYP1>;
>>> +		resets = <&rcc CRYP1_R>;
>>> +		feature-domains = <&etzpc 42>;
>>> +		status = "disabled";
>>>   	};
>>>   };
>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> index 4d00e7592882..b9fb071a1471 100644
>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> @@ -4,15 +4,13 @@
>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>    */
>>>   
>>> -/ {
>>> -	soc {
>>> -		cryp: crypto@54002000 {
>>> -			compatible = "st,stm32mp1-cryp";
>>> -			reg = <0x54002000 0x400>;
>>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc CRYP1>;
>>> -			resets = <&rcc CRYP1_R>;
>>> -			status = "disabled";
>>> -		};
>>> +&etzpc {
>>> +	cryp: crypto@54002000 {
>>> +		compatible = "st,stm32mp1-cryp";
>>> +		reg = <0x54002000 0x400>;
>>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc CRYP1>;
>>> +		resets = <&rcc CRYP1_R>;
>>> +		status = "disabled";
>>>   	};
>>>   };
>>
> 

Regarding the patch itself, I can separate it in two patches.
1)Introduce ETZPC
2)Move peripherals under ETZPC

Best regards,
Gatien

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-13 10:54         ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-13 10:54 UTC (permalink / raw)
  To: Ahmad Fatoum, Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media

Hi Ahmad, Uwe,

On 2/9/23 09:10, Ahmad Fatoum wrote:
> On 09.02.23 08:46, Ahmad Fatoum wrote:
>> Hello Gatien,
>>
>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>> The STM32 System Bus is an internal bus on which devices are connected.
>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>> and control access to the peripherals connected on it.
>>>
>>> For more information on which peripheral is securable, please read
>>> the STM32MP13 reference manual.
>>
>> Diff is way too big. Please split up the alphabetic reordering into its
>> own commit, so actual functional changes are apparent.
> 
> Ah, I see now that you are moving securable peripherals into a new bus.
> I share Uwe's confusion of considering the ETZPC as bus.
> 
> Does this configuration even change dynamically? Why can't you implement
> this binding in the bootloader and have Linux only see a DT where unavailable
> nodes are status = "disabled"; secure-status = "okay"?
> 
> For inspiration, see barebox' device tree fixups when devices are disabled
> per fuse:
> 
>    https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
> 
> Cheers,
> Ahmad

This configuration can change dynamically. The binding will be 
implemented in the bootloader, where the ETZPC is already implemented as 
a bus in our downstream.

I find the mentionned example valid.

Now, why is it a bus? :D

It is the result of the discussion on the previous submission by 
Benjamin (Sorry for the lack of link but I saw that you participated on 
these threads)+ we need the bus mechanism to control whether a subnode 
should be probed or not. You can see it as a firewall bus.

The ETZPC relies on the ARM TrustZone extension to the AHB bus and 
propagation through bridges to the APB bus. Therefore, I find it 
relevant to consider it as a bus, what is your opinion?

This patchset is a first step to the implementation of an API to control 
accesses dynamically.

> 
>>
>> Thanks,
>> Ahmad
>>
>>>
>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>> ---
>>>
>>> No changes in V2.
>>>
>>> Changes in V3:
>>> 	-Use appriopriate node name: bus
>>>
>>>   arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>   arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>   arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>   arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>   4 files changed, 258 insertions(+), 237 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>> index accc3824f7e9..24462a647101 100644
>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>   			dma-channels = <16>;
>>>   		};
>>>   
>>> -		adc_2: adc@48004000 {
>>> -			compatible = "st,stm32mp13-adc-core";
>>> -			reg = <0x48004000 0x400>;
>>> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>> -			clock-names = "bus", "adc";
>>> -			interrupt-controller;
>>> -			#interrupt-cells = <1>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			status = "disabled";
>>> -
>>> -			adc2: adc@0 {
>>> -				compatible = "st,stm32mp13-adc";
>>> -				#io-channel-cells = <1>;
>>> -				#address-cells = <1>;
>>> -				#size-cells = <0>;
>>> -				reg = <0x0>;
>>> -				interrupt-parent = <&adc_2>;
>>> -				interrupts = <0>;
>>> -				dmas = <&dmamux1 10 0x400 0x80000001>;
>>> -				dma-names = "rx";
>>> -				status = "disabled";
>>> -
>>> -				channel@13 {
>>> -					reg = <13>;
>>> -					label = "vrefint";
>>> -				};
>>> -				channel@14 {
>>> -					reg = <14>;
>>> -					label = "vddcore";
>>> -				};
>>> -				channel@16 {
>>> -					reg = <16>;
>>> -					label = "vddcpu";
>>> -				};
>>> -				channel@17 {
>>> -					reg = <17>;
>>> -					label = "vddq_ddr";
>>> -				};
>>> -			};
>>> -		};
>>> -
>>> -		usbotg_hs: usb@49000000 {
>>> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>> -			reg = <0x49000000 0x40000>;
>>> -			clocks = <&rcc USBO_K>;
>>> -			clock-names = "otg";
>>> -			resets = <&rcc USBO_R>;
>>> -			reset-names = "dwc2";
>>> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> -			g-rx-fifo-size = <512>;
>>> -			g-np-tx-fifo-size = <32>;
>>> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>> -			dr_mode = "otg";
>>> -			otg-rev = <0x200>;
>>> -			usb33d-supply = <&usb33>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		spi4: spi@4c002000 {
>>> -			compatible = "st,stm32h7-spi";
>>> -			reg = <0x4c002000 0x400>;
>>> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SPI4_K>;
>>> -			resets = <&rcc SPI4_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 83 0x400 0x01>,
>>> -			       <&dmamux1 84 0x400 0x01>;
>>> -			dma-names = "rx", "tx";
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		spi5: spi@4c003000 {
>>> -			compatible = "st,stm32h7-spi";
>>> -			reg = <0x4c003000 0x400>;
>>> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SPI5_K>;
>>> -			resets = <&rcc SPI5_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 85 0x400 0x01>,
>>> -			       <&dmamux1 86 0x400 0x01>;
>>> -			dma-names = "rx", "tx";
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c3: i2c@4c004000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c004000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C3_K>;
>>> -			resets = <&rcc I2C3_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 73 0x400 0x1>,
>>> -			       <&dmamux1 74 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c4: i2c@4c005000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c005000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C4_K>;
>>> -			resets = <&rcc I2C4_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 75 0x400 0x1>,
>>> -			       <&dmamux1 76 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c5: i2c@4c006000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c006000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C5_K>;
>>> -			resets = <&rcc I2C5_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 115 0x400 0x1>,
>>> -			       <&dmamux1 116 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>>   		rcc: rcc@50000000 {
>>>   			compatible = "st,stm32mp13-rcc", "syscon";
>>>   			reg = <0x50000000 0x1000>;
>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>   			dma-requests = <48>;
>>>   		};
>>>   
>>> -		sdmmc1: mmc@58005000 {
>>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> -			arm,primecell-periphid = <0x20253180>;
>>> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SDMMC1_K>;
>>> -			clock-names = "apb_pclk";
>>> -			resets = <&rcc SDMMC1_R>;
>>> -			cap-sd-highspeed;
>>> -			cap-mmc-highspeed;
>>> -			max-frequency = <130000000>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		sdmmc2: mmc@58007000 {
>>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> -			arm,primecell-periphid = <0x20253180>;
>>> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SDMMC2_K>;
>>> -			clock-names = "apb_pclk";
>>> -			resets = <&rcc SDMMC2_R>;
>>> -			cap-sd-highspeed;
>>> -			cap-mmc-highspeed;
>>> -			max-frequency = <130000000>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>>   		usbh_ohci: usb@5800c000 {
>>>   			compatible = "generic-ohci";
>>>   			reg = <0x5800c000 0x1000>;
>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>   			status = "disabled";
>>>   		};
>>>   
>>> -		usbphyc: usbphyc@5a006000 {
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			#clock-cells = <0>;
>>> -			compatible = "st,stm32mp1-usbphyc";
>>> -			reg = <0x5a006000 0x1000>;
>>> -			clocks = <&rcc USBPHY_K>;
>>> -			resets = <&rcc USBPHY_R>;
>>> -			vdda1v1-supply = <&reg11>;
>>> -			vdda1v8-supply = <&reg18>;
>>> -			status = "disabled";
>>> -
>>> -			usbphyc_port0: usb-phy@0 {
>>> -				#phy-cells = <0>;
>>> -				reg = <0>;
>>> -			};
>>> -
>>> -			usbphyc_port1: usb-phy@1 {
>>> -				#phy-cells = <1>;
>>> -				reg = <1>;
>>> -			};
>>> -		};
>>> -
>>>   		rtc: rtc@5c004000 {
>>>   			compatible = "st,stm32mp1-rtc";
>>>   			reg = <0x5c004000 0x400>;
>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>   			};
>>>   		};
>>>   
>>> +		etzpc: bus@5c007000 {
>>> +			compatible = "st,stm32mp13-sys-bus";
>>> +			reg = <0x5c007000 0x400>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <1>;
>>> +			feature-domain-controller;
>>> +			#feature-domain-cells = <1>;
>>> +			ranges;
>>> +
>>> +			adc_2: adc@48004000 {
>>> +				compatible = "st,stm32mp13-adc-core";
>>> +				reg = <0x48004000 0x400>;
>>> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>> +				clock-names = "bus", "adc";
>>> +				interrupt-controller;
>>> +				#interrupt-cells = <1>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				feature-domains = <&etzpc 33>;
>>> +				status = "disabled";
>>> +
>>> +				adc2: adc@0 {
>>> +					compatible = "st,stm32mp13-adc";
>>> +					#io-channel-cells = <1>;
>>> +					#address-cells = <1>;
>>> +					#size-cells = <0>;
>>> +					reg = <0x0>;
>>> +					interrupt-parent = <&adc_2>;
>>> +					interrupts = <0>;
>>> +					dmas = <&dmamux1 10 0x400 0x80000001>;
>>> +					dma-names = "rx";
>>> +					status = "disabled";
>>> +
>>> +					channel@13 {
>>> +						reg = <13>;
>>> +						label = "vrefint";
>>> +					};
>>> +					channel@14 {
>>> +						reg = <14>;
>>> +						label = "vddcore";
>>> +					};
>>> +					channel@16 {
>>> +						reg = <16>;
>>> +						label = "vddcpu";
>>> +					};
>>> +					channel@17 {
>>> +						reg = <17>;
>>> +						label = "vddq_ddr";
>>> +					};
>>> +				};
>>> +			};
>>> +
>>> +			usbotg_hs: usb@49000000 {
>>> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>> +				reg = <0x49000000 0x40000>;
>>> +				clocks = <&rcc USBO_K>;
>>> +				clock-names = "otg";
>>> +				resets = <&rcc USBO_R>;
>>> +				reset-names = "dwc2";
>>> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> +				g-rx-fifo-size = <512>;
>>> +				g-np-tx-fifo-size = <32>;
>>> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>> +				dr_mode = "otg";
>>> +				otg-rev = <0x200>;
>>> +				usb33d-supply = <&usb33>;
>>> +				feature-domains = <&etzpc 34>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			spi4: spi@4c002000 {
>>> +				compatible = "st,stm32h7-spi";
>>> +				reg = <0x4c002000 0x400>;
>>> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SPI4_K>;
>>> +				resets = <&rcc SPI4_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 83 0x400 0x01>,
>>> +				       <&dmamux1 84 0x400 0x01>;
>>> +				dma-names = "rx", "tx";
>>> +				feature-domains = <&etzpc 18>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			spi5: spi@4c003000 {
>>> +				compatible = "st,stm32h7-spi";
>>> +				reg = <0x4c003000 0x400>;
>>> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SPI5_K>;
>>> +				resets = <&rcc SPI5_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 85 0x400 0x01>,
>>> +				       <&dmamux1 86 0x400 0x01>;
>>> +				dma-names = "rx", "tx";
>>> +				feature-domains = <&etzpc 19>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c3: i2c@4c004000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c004000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C3_K>;
>>> +				resets = <&rcc I2C3_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 73 0x400 0x1>,
>>> +				       <&dmamux1 74 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 20>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c4: i2c@4c005000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c005000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C4_K>;
>>> +				resets = <&rcc I2C4_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 75 0x400 0x1>,
>>> +				       <&dmamux1 76 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 21>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c5: i2c@4c006000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c006000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C5_K>;
>>> +				resets = <&rcc I2C5_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 115 0x400 0x1>,
>>> +				       <&dmamux1 116 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 22>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			sdmmc1: mmc@58005000 {
>>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> +				arm,primecell-periphid = <0x20253180>;
>>> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SDMMC1_K>;
>>> +				clock-names = "apb_pclk";
>>> +				resets = <&rcc SDMMC1_R>;
>>> +				cap-sd-highspeed;
>>> +				cap-mmc-highspeed;
>>> +				max-frequency = <130000000>;
>>> +				feature-domains = <&etzpc 50>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			sdmmc2: mmc@58007000 {
>>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> +				arm,primecell-periphid = <0x20253180>;
>>> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SDMMC2_K>;
>>> +				clock-names = "apb_pclk";
>>> +				resets = <&rcc SDMMC2_R>;
>>> +				cap-sd-highspeed;
>>> +				cap-mmc-highspeed;
>>> +				max-frequency = <130000000>;
>>> +				feature-domains = <&etzpc 51>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			usbphyc: usbphyc@5a006000 {
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				#clock-cells = <0>;
>>> +				compatible = "st,stm32mp1-usbphyc";
>>> +				reg = <0x5a006000 0x1000>;
>>> +				clocks = <&rcc USBPHY_K>;
>>> +				resets = <&rcc USBPHY_R>;
>>> +				vdda1v1-supply = <&reg11>;
>>> +				vdda1v8-supply = <&reg18>;
>>> +				feature-domains = <&etzpc 5>;
>>> +				status = "disabled";
>>> +
>>> +				usbphyc_port0: usb-phy@0 {
>>> +					#phy-cells = <0>;
>>> +					reg = <0>;
>>> +				};
>>> +
>>> +				usbphyc_port1: usb-phy@1 {
>>> +					#phy-cells = <1>;
>>> +					reg = <1>;
>>> +				};
>>> +			};
>>> +
>>> +		};
>>> +
>>>   		/*
>>>   		 * Break node order to solve dependency probe issue between
>>>   		 * pinctrl and exti.
>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>> index df451c3c2a26..be6061552683 100644
>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>   			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>   			status = "disabled";
>>>   		};
>>> +	};
>>> +};
>>>   
>>> -		adc_1: adc@48003000 {
>>> -			compatible = "st,stm32mp13-adc-core";
>>> -			reg = <0x48003000 0x400>;
>>> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>> -			clock-names = "bus", "adc";
>>> -			interrupt-controller;
>>> -			#interrupt-cells = <1>;
>>> +&etzpc {
>>> +	adc_1: adc@48003000 {
>>> +		compatible = "st,stm32mp13-adc-core";
>>> +		reg = <0x48003000 0x400>;
>>> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>> +		clock-names = "bus", "adc";
>>> +		interrupt-controller;
>>> +		#interrupt-cells = <1>;
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +		feature-domains = <&etzpc 32>;
>>> +		status = "disabled";
>>> +
>>> +		adc1: adc@0 {
>>> +			compatible = "st,stm32mp13-adc";
>>> +			#io-channel-cells = <1>;
>>>   			#address-cells = <1>;
>>>   			#size-cells = <0>;
>>> +			reg = <0x0>;
>>> +			interrupt-parent = <&adc_1>;
>>> +			interrupts = <0>;
>>> +			dmas = <&dmamux1 9 0x400 0x80000001>;
>>> +			dma-names = "rx";
>>>   			status = "disabled";
>>>   
>>> -			adc1: adc@0 {
>>> -				compatible = "st,stm32mp13-adc";
>>> -				#io-channel-cells = <1>;
>>> -				#address-cells = <1>;
>>> -				#size-cells = <0>;
>>> -				reg = <0x0>;
>>> -				interrupt-parent = <&adc_1>;
>>> -				interrupts = <0>;
>>> -				dmas = <&dmamux1 9 0x400 0x80000001>;
>>> -				dma-names = "rx";
>>> -				status = "disabled";
>>> -
>>> -				channel@18 {
>>> -					reg = <18>;
>>> -					label = "vrefint";
>>> -				};
>>> +			channel@18 {
>>> +				reg = <18>;
>>> +				label = "vrefint";
>>>   			};
>>>   		};
>>>   	};
>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> @@ -4,15 +4,14 @@
>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>    */
>>>   
>>> -/ {
>>> -	soc {
>>> -		cryp: crypto@54002000 {
>>> -			compatible = "st,stm32mp1-cryp";
>>> -			reg = <0x54002000 0x400>;
>>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc CRYP1>;
>>> -			resets = <&rcc CRYP1_R>;
>>> -			status = "disabled";
>>> -		};
>>> +&etzpc {
>>> +	cryp: crypto@54002000 {
>>> +		compatible = "st,stm32mp1-cryp";
>>> +		reg = <0x54002000 0x400>;
>>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc CRYP1>;
>>> +		resets = <&rcc CRYP1_R>;
>>> +		feature-domains = <&etzpc 42>;
>>> +		status = "disabled";
>>>   	};
>>>   };
>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> index 4d00e7592882..b9fb071a1471 100644
>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> @@ -4,15 +4,13 @@
>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>    */
>>>   
>>> -/ {
>>> -	soc {
>>> -		cryp: crypto@54002000 {
>>> -			compatible = "st,stm32mp1-cryp";
>>> -			reg = <0x54002000 0x400>;
>>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc CRYP1>;
>>> -			resets = <&rcc CRYP1_R>;
>>> -			status = "disabled";
>>> -		};
>>> +&etzpc {
>>> +	cryp: crypto@54002000 {
>>> +		compatible = "st,stm32mp1-cryp";
>>> +		reg = <0x54002000 0x400>;
>>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc CRYP1>;
>>> +		resets = <&rcc CRYP1_R>;
>>> +		status = "disabled";
>>>   	};
>>>   };
>>
> 

Regarding the patch itself, I can separate it in two patches.
1)Introduce ETZPC
2)Move peripherals under ETZPC

Best regards,
Gatien

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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-13 10:54         ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-13 10:54 UTC (permalink / raw)
  To: Ahmad Fatoum, Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media

Hi Ahmad, Uwe,

On 2/9/23 09:10, Ahmad Fatoum wrote:
> On 09.02.23 08:46, Ahmad Fatoum wrote:
>> Hello Gatien,
>>
>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>> The STM32 System Bus is an internal bus on which devices are connected.
>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>> and control access to the peripherals connected on it.
>>>
>>> For more information on which peripheral is securable, please read
>>> the STM32MP13 reference manual.
>>
>> Diff is way too big. Please split up the alphabetic reordering into its
>> own commit, so actual functional changes are apparent.
> 
> Ah, I see now that you are moving securable peripherals into a new bus.
> I share Uwe's confusion of considering the ETZPC as bus.
> 
> Does this configuration even change dynamically? Why can't you implement
> this binding in the bootloader and have Linux only see a DT where unavailable
> nodes are status = "disabled"; secure-status = "okay"?
> 
> For inspiration, see barebox' device tree fixups when devices are disabled
> per fuse:
> 
>    https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
> 
> Cheers,
> Ahmad

This configuration can change dynamically. The binding will be 
implemented in the bootloader, where the ETZPC is already implemented as 
a bus in our downstream.

I find the mentionned example valid.

Now, why is it a bus? :D

It is the result of the discussion on the previous submission by 
Benjamin (Sorry for the lack of link but I saw that you participated on 
these threads)+ we need the bus mechanism to control whether a subnode 
should be probed or not. You can see it as a firewall bus.

The ETZPC relies on the ARM TrustZone extension to the AHB bus and 
propagation through bridges to the APB bus. Therefore, I find it 
relevant to consider it as a bus, what is your opinion?

This patchset is a first step to the implementation of an API to control 
accesses dynamically.

> 
>>
>> Thanks,
>> Ahmad
>>
>>>
>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>> ---
>>>
>>> No changes in V2.
>>>
>>> Changes in V3:
>>> 	-Use appriopriate node name: bus
>>>
>>>   arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>   arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>   arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>   arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>   4 files changed, 258 insertions(+), 237 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>> index accc3824f7e9..24462a647101 100644
>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>   			dma-channels = <16>;
>>>   		};
>>>   
>>> -		adc_2: adc@48004000 {
>>> -			compatible = "st,stm32mp13-adc-core";
>>> -			reg = <0x48004000 0x400>;
>>> -			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>> -			clock-names = "bus", "adc";
>>> -			interrupt-controller;
>>> -			#interrupt-cells = <1>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			status = "disabled";
>>> -
>>> -			adc2: adc@0 {
>>> -				compatible = "st,stm32mp13-adc";
>>> -				#io-channel-cells = <1>;
>>> -				#address-cells = <1>;
>>> -				#size-cells = <0>;
>>> -				reg = <0x0>;
>>> -				interrupt-parent = <&adc_2>;
>>> -				interrupts = <0>;
>>> -				dmas = <&dmamux1 10 0x400 0x80000001>;
>>> -				dma-names = "rx";
>>> -				status = "disabled";
>>> -
>>> -				channel@13 {
>>> -					reg = <13>;
>>> -					label = "vrefint";
>>> -				};
>>> -				channel@14 {
>>> -					reg = <14>;
>>> -					label = "vddcore";
>>> -				};
>>> -				channel@16 {
>>> -					reg = <16>;
>>> -					label = "vddcpu";
>>> -				};
>>> -				channel@17 {
>>> -					reg = <17>;
>>> -					label = "vddq_ddr";
>>> -				};
>>> -			};
>>> -		};
>>> -
>>> -		usbotg_hs: usb@49000000 {
>>> -			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>> -			reg = <0x49000000 0x40000>;
>>> -			clocks = <&rcc USBO_K>;
>>> -			clock-names = "otg";
>>> -			resets = <&rcc USBO_R>;
>>> -			reset-names = "dwc2";
>>> -			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> -			g-rx-fifo-size = <512>;
>>> -			g-np-tx-fifo-size = <32>;
>>> -			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>> -			dr_mode = "otg";
>>> -			otg-rev = <0x200>;
>>> -			usb33d-supply = <&usb33>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		spi4: spi@4c002000 {
>>> -			compatible = "st,stm32h7-spi";
>>> -			reg = <0x4c002000 0x400>;
>>> -			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SPI4_K>;
>>> -			resets = <&rcc SPI4_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 83 0x400 0x01>,
>>> -			       <&dmamux1 84 0x400 0x01>;
>>> -			dma-names = "rx", "tx";
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		spi5: spi@4c003000 {
>>> -			compatible = "st,stm32h7-spi";
>>> -			reg = <0x4c003000 0x400>;
>>> -			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SPI5_K>;
>>> -			resets = <&rcc SPI5_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 85 0x400 0x01>,
>>> -			       <&dmamux1 86 0x400 0x01>;
>>> -			dma-names = "rx", "tx";
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c3: i2c@4c004000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c004000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C3_K>;
>>> -			resets = <&rcc I2C3_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 73 0x400 0x1>,
>>> -			       <&dmamux1 74 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c4: i2c@4c005000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c005000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C4_K>;
>>> -			resets = <&rcc I2C4_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 75 0x400 0x1>,
>>> -			       <&dmamux1 76 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		i2c5: i2c@4c006000 {
>>> -			compatible = "st,stm32mp13-i2c";
>>> -			reg = <0x4c006000 0x400>;
>>> -			interrupt-names = "event", "error";
>>> -			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>> -				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc I2C5_K>;
>>> -			resets = <&rcc I2C5_R>;
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			dmas = <&dmamux1 115 0x400 0x1>,
>>> -			       <&dmamux1 116 0x400 0x1>;
>>> -			dma-names = "rx", "tx";
>>> -			st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>> -			i2c-analog-filter;
>>> -			status = "disabled";
>>> -		};
>>> -
>>>   		rcc: rcc@50000000 {
>>>   			compatible = "st,stm32mp13-rcc", "syscon";
>>>   			reg = <0x50000000 0x1000>;
>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>   			dma-requests = <48>;
>>>   		};
>>>   
>>> -		sdmmc1: mmc@58005000 {
>>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> -			arm,primecell-periphid = <0x20253180>;
>>> -			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SDMMC1_K>;
>>> -			clock-names = "apb_pclk";
>>> -			resets = <&rcc SDMMC1_R>;
>>> -			cap-sd-highspeed;
>>> -			cap-mmc-highspeed;
>>> -			max-frequency = <130000000>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>> -		sdmmc2: mmc@58007000 {
>>> -			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> -			arm,primecell-periphid = <0x20253180>;
>>> -			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>> -			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc SDMMC2_K>;
>>> -			clock-names = "apb_pclk";
>>> -			resets = <&rcc SDMMC2_R>;
>>> -			cap-sd-highspeed;
>>> -			cap-mmc-highspeed;
>>> -			max-frequency = <130000000>;
>>> -			status = "disabled";
>>> -		};
>>> -
>>>   		usbh_ohci: usb@5800c000 {
>>>   			compatible = "generic-ohci";
>>>   			reg = <0x5800c000 0x1000>;
>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>   			status = "disabled";
>>>   		};
>>>   
>>> -		usbphyc: usbphyc@5a006000 {
>>> -			#address-cells = <1>;
>>> -			#size-cells = <0>;
>>> -			#clock-cells = <0>;
>>> -			compatible = "st,stm32mp1-usbphyc";
>>> -			reg = <0x5a006000 0x1000>;
>>> -			clocks = <&rcc USBPHY_K>;
>>> -			resets = <&rcc USBPHY_R>;
>>> -			vdda1v1-supply = <&reg11>;
>>> -			vdda1v8-supply = <&reg18>;
>>> -			status = "disabled";
>>> -
>>> -			usbphyc_port0: usb-phy@0 {
>>> -				#phy-cells = <0>;
>>> -				reg = <0>;
>>> -			};
>>> -
>>> -			usbphyc_port1: usb-phy@1 {
>>> -				#phy-cells = <1>;
>>> -				reg = <1>;
>>> -			};
>>> -		};
>>> -
>>>   		rtc: rtc@5c004000 {
>>>   			compatible = "st,stm32mp1-rtc";
>>>   			reg = <0x5c004000 0x400>;
>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>   			};
>>>   		};
>>>   
>>> +		etzpc: bus@5c007000 {
>>> +			compatible = "st,stm32mp13-sys-bus";
>>> +			reg = <0x5c007000 0x400>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <1>;
>>> +			feature-domain-controller;
>>> +			#feature-domain-cells = <1>;
>>> +			ranges;
>>> +
>>> +			adc_2: adc@48004000 {
>>> +				compatible = "st,stm32mp13-adc-core";
>>> +				reg = <0x48004000 0x400>;
>>> +				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>> +				clock-names = "bus", "adc";
>>> +				interrupt-controller;
>>> +				#interrupt-cells = <1>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				feature-domains = <&etzpc 33>;
>>> +				status = "disabled";
>>> +
>>> +				adc2: adc@0 {
>>> +					compatible = "st,stm32mp13-adc";
>>> +					#io-channel-cells = <1>;
>>> +					#address-cells = <1>;
>>> +					#size-cells = <0>;
>>> +					reg = <0x0>;
>>> +					interrupt-parent = <&adc_2>;
>>> +					interrupts = <0>;
>>> +					dmas = <&dmamux1 10 0x400 0x80000001>;
>>> +					dma-names = "rx";
>>> +					status = "disabled";
>>> +
>>> +					channel@13 {
>>> +						reg = <13>;
>>> +						label = "vrefint";
>>> +					};
>>> +					channel@14 {
>>> +						reg = <14>;
>>> +						label = "vddcore";
>>> +					};
>>> +					channel@16 {
>>> +						reg = <16>;
>>> +						label = "vddcpu";
>>> +					};
>>> +					channel@17 {
>>> +						reg = <17>;
>>> +						label = "vddq_ddr";
>>> +					};
>>> +				};
>>> +			};
>>> +
>>> +			usbotg_hs: usb@49000000 {
>>> +				compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>> +				reg = <0x49000000 0x40000>;
>>> +				clocks = <&rcc USBO_K>;
>>> +				clock-names = "otg";
>>> +				resets = <&rcc USBO_R>;
>>> +				reset-names = "dwc2";
>>> +				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>> +				g-rx-fifo-size = <512>;
>>> +				g-np-tx-fifo-size = <32>;
>>> +				g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>> +				dr_mode = "otg";
>>> +				otg-rev = <0x200>;
>>> +				usb33d-supply = <&usb33>;
>>> +				feature-domains = <&etzpc 34>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			spi4: spi@4c002000 {
>>> +				compatible = "st,stm32h7-spi";
>>> +				reg = <0x4c002000 0x400>;
>>> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SPI4_K>;
>>> +				resets = <&rcc SPI4_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 83 0x400 0x01>,
>>> +				       <&dmamux1 84 0x400 0x01>;
>>> +				dma-names = "rx", "tx";
>>> +				feature-domains = <&etzpc 18>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			spi5: spi@4c003000 {
>>> +				compatible = "st,stm32h7-spi";
>>> +				reg = <0x4c003000 0x400>;
>>> +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SPI5_K>;
>>> +				resets = <&rcc SPI5_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 85 0x400 0x01>,
>>> +				       <&dmamux1 86 0x400 0x01>;
>>> +				dma-names = "rx", "tx";
>>> +				feature-domains = <&etzpc 19>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c3: i2c@4c004000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c004000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C3_K>;
>>> +				resets = <&rcc I2C3_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 73 0x400 0x1>,
>>> +				       <&dmamux1 74 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 20>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c4: i2c@4c005000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c005000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C4_K>;
>>> +				resets = <&rcc I2C4_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 75 0x400 0x1>,
>>> +				       <&dmamux1 76 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 21>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			i2c5: i2c@4c006000 {
>>> +				compatible = "st,stm32mp13-i2c";
>>> +				reg = <0x4c006000 0x400>;
>>> +				interrupt-names = "event", "error";
>>> +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>> +					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc I2C5_K>;
>>> +				resets = <&rcc I2C5_R>;
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				dmas = <&dmamux1 115 0x400 0x1>,
>>> +				       <&dmamux1 116 0x400 0x1>;
>>> +				dma-names = "rx", "tx";
>>> +				st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>> +				i2c-analog-filter;
>>> +				feature-domains = <&etzpc 22>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			sdmmc1: mmc@58005000 {
>>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> +				arm,primecell-periphid = <0x20253180>;
>>> +				reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>> +				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SDMMC1_K>;
>>> +				clock-names = "apb_pclk";
>>> +				resets = <&rcc SDMMC1_R>;
>>> +				cap-sd-highspeed;
>>> +				cap-mmc-highspeed;
>>> +				max-frequency = <130000000>;
>>> +				feature-domains = <&etzpc 50>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			sdmmc2: mmc@58007000 {
>>> +				compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>> +				arm,primecell-periphid = <0x20253180>;
>>> +				reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>> +				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>> +				clocks = <&rcc SDMMC2_K>;
>>> +				clock-names = "apb_pclk";
>>> +				resets = <&rcc SDMMC2_R>;
>>> +				cap-sd-highspeed;
>>> +				cap-mmc-highspeed;
>>> +				max-frequency = <130000000>;
>>> +				feature-domains = <&etzpc 51>;
>>> +				status = "disabled";
>>> +			};
>>> +
>>> +			usbphyc: usbphyc@5a006000 {
>>> +				#address-cells = <1>;
>>> +				#size-cells = <0>;
>>> +				#clock-cells = <0>;
>>> +				compatible = "st,stm32mp1-usbphyc";
>>> +				reg = <0x5a006000 0x1000>;
>>> +				clocks = <&rcc USBPHY_K>;
>>> +				resets = <&rcc USBPHY_R>;
>>> +				vdda1v1-supply = <&reg11>;
>>> +				vdda1v8-supply = <&reg18>;
>>> +				feature-domains = <&etzpc 5>;
>>> +				status = "disabled";
>>> +
>>> +				usbphyc_port0: usb-phy@0 {
>>> +					#phy-cells = <0>;
>>> +					reg = <0>;
>>> +				};
>>> +
>>> +				usbphyc_port1: usb-phy@1 {
>>> +					#phy-cells = <1>;
>>> +					reg = <1>;
>>> +				};
>>> +			};
>>> +
>>> +		};
>>> +
>>>   		/*
>>>   		 * Break node order to solve dependency probe issue between
>>>   		 * pinctrl and exti.
>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>> index df451c3c2a26..be6061552683 100644
>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>   			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>   			status = "disabled";
>>>   		};
>>> +	};
>>> +};
>>>   
>>> -		adc_1: adc@48003000 {
>>> -			compatible = "st,stm32mp13-adc-core";
>>> -			reg = <0x48003000 0x400>;
>>> -			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>> -			clock-names = "bus", "adc";
>>> -			interrupt-controller;
>>> -			#interrupt-cells = <1>;
>>> +&etzpc {
>>> +	adc_1: adc@48003000 {
>>> +		compatible = "st,stm32mp13-adc-core";
>>> +		reg = <0x48003000 0x400>;
>>> +		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>> +		clock-names = "bus", "adc";
>>> +		interrupt-controller;
>>> +		#interrupt-cells = <1>;
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +		feature-domains = <&etzpc 32>;
>>> +		status = "disabled";
>>> +
>>> +		adc1: adc@0 {
>>> +			compatible = "st,stm32mp13-adc";
>>> +			#io-channel-cells = <1>;
>>>   			#address-cells = <1>;
>>>   			#size-cells = <0>;
>>> +			reg = <0x0>;
>>> +			interrupt-parent = <&adc_1>;
>>> +			interrupts = <0>;
>>> +			dmas = <&dmamux1 9 0x400 0x80000001>;
>>> +			dma-names = "rx";
>>>   			status = "disabled";
>>>   
>>> -			adc1: adc@0 {
>>> -				compatible = "st,stm32mp13-adc";
>>> -				#io-channel-cells = <1>;
>>> -				#address-cells = <1>;
>>> -				#size-cells = <0>;
>>> -				reg = <0x0>;
>>> -				interrupt-parent = <&adc_1>;
>>> -				interrupts = <0>;
>>> -				dmas = <&dmamux1 9 0x400 0x80000001>;
>>> -				dma-names = "rx";
>>> -				status = "disabled";
>>> -
>>> -				channel@18 {
>>> -					reg = <18>;
>>> -					label = "vrefint";
>>> -				};
>>> +			channel@18 {
>>> +				reg = <18>;
>>> +				label = "vrefint";
>>>   			};
>>>   		};
>>>   	};
>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>> @@ -4,15 +4,14 @@
>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>    */
>>>   
>>> -/ {
>>> -	soc {
>>> -		cryp: crypto@54002000 {
>>> -			compatible = "st,stm32mp1-cryp";
>>> -			reg = <0x54002000 0x400>;
>>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc CRYP1>;
>>> -			resets = <&rcc CRYP1_R>;
>>> -			status = "disabled";
>>> -		};
>>> +&etzpc {
>>> +	cryp: crypto@54002000 {
>>> +		compatible = "st,stm32mp1-cryp";
>>> +		reg = <0x54002000 0x400>;
>>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc CRYP1>;
>>> +		resets = <&rcc CRYP1_R>;
>>> +		feature-domains = <&etzpc 42>;
>>> +		status = "disabled";
>>>   	};
>>>   };
>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> index 4d00e7592882..b9fb071a1471 100644
>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>> @@ -4,15 +4,13 @@
>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>    */
>>>   
>>> -/ {
>>> -	soc {
>>> -		cryp: crypto@54002000 {
>>> -			compatible = "st,stm32mp1-cryp";
>>> -			reg = <0x54002000 0x400>;
>>> -			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> -			clocks = <&rcc CRYP1>;
>>> -			resets = <&rcc CRYP1_R>;
>>> -			status = "disabled";
>>> -		};
>>> +&etzpc {
>>> +	cryp: crypto@54002000 {
>>> +		compatible = "st,stm32mp1-cryp";
>>> +		reg = <0x54002000 0x400>;
>>> +		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>> +		clocks = <&rcc CRYP1>;
>>> +		resets = <&rcc CRYP1_R>;
>>> +		status = "disabled";
>>>   	};
>>>   };
>>
> 

Regarding the patch itself, I can separate it in two patches.
1)Introduce ETZPC
2)Move peripherals under ETZPC

Best regards,
Gatien

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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  2023-02-13 10:54         ` Gatien CHEVALLIER
  (?)
@ 2023-02-13 11:27           ` Ahmad Fatoum
  -1 siblings, 0 replies; 93+ messages in thread
From: Ahmad Fatoum @ 2023-02-13 11:27 UTC (permalink / raw)
  To: Gatien CHEVALLIER, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team

Hello Gatien,

On 13.02.23 11:54, Gatien CHEVALLIER wrote:
> On 2/9/23 09:10, Ahmad Fatoum wrote:
>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>> Hello Gatien,
>>>
>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>> The STM32 System Bus is an internal bus on which devices are connected.
>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>> and control access to the peripherals connected on it.
>>>>
>>>> For more information on which peripheral is securable, please read
>>>> the STM32MP13 reference manual.
>>>
>>> Diff is way too big. Please split up the alphabetic reordering into its
>>> own commit, so actual functional changes are apparent.
>>
>> Ah, I see now that you are moving securable peripherals into a new bus.
>> I share Uwe's confusion of considering the ETZPC as bus.
>>
>> Does this configuration even change dynamically? Why can't you implement
>> this binding in the bootloader and have Linux only see a DT where unavailable
>> nodes are status = "disabled"; secure-status = "okay"?
>>
>> For inspiration, see barebox' device tree fixups when devices are disabled
>> per fuse:
>>
>>    https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
>>
>> Cheers,
>> Ahmad
> 
> This configuration can change dynamically. The binding will be implemented in the bootloader, where the ETZPC is already implemented as a bus in our downstream.
> 
> I find the mentionned example valid.
> 
> Now, why is it a bus? :D
> 
> It is the result of the discussion on the previous submission by Benjamin (Sorry for the lack of link but I saw that you participated on these threads)+ we need the bus mechanism to control whether a subnode should be probed or not. You can see it as a firewall bus.
> 
> The ETZPC relies on the ARM TrustZone extension to the AHB bus and propagation through bridges to the APB bus. Therefore, I find it relevant to consider it as a bus, what is your opinion?
> 
> This patchset is a first step to the implementation of an API to control accesses dynamically.

I still don't get what's dynamic about this. Either:

  - Configuration _can_ change while Linux is running: You'll need to do
    way more than what your current bus provides to somwhow synchronize state
    with the secure monitor; otherwise a newly secured device will cause the driver
    to trigger data aborts that you'll have to handle and unbind the driver.
    (like if a USB drive is yanked out).

  - Configuration _can't_ change while Linux is running: You can have the bootloader
    fixup the device tree and Linux need not care at all about devices that the
    ETZPC is securing.

My understanding is that the latter is your use case, so I don't see why we
even need the normal world to be aware of the partitioning.

Cheers,
Ahmad

> 
>>
>>>
>>> Thanks,
>>> Ahmad
>>>
>>>>
>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>> ---
>>>>
>>>> No changes in V2.
>>>>
>>>> Changes in V3:
>>>>     -Use appriopriate node name: bus
>>>>
>>>>   arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>>   arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>   arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>   arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>   4 files changed, 258 insertions(+), 237 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>>> index accc3824f7e9..24462a647101 100644
>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>               dma-channels = <16>;
>>>>           };
>>>>   -        adc_2: adc@48004000 {
>>>> -            compatible = "st,stm32mp13-adc-core";
>>>> -            reg = <0x48004000 0x400>;
>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>> -            clock-names = "bus", "adc";
>>>> -            interrupt-controller;
>>>> -            #interrupt-cells = <1>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            status = "disabled";
>>>> -
>>>> -            adc2: adc@0 {
>>>> -                compatible = "st,stm32mp13-adc";
>>>> -                #io-channel-cells = <1>;
>>>> -                #address-cells = <1>;
>>>> -                #size-cells = <0>;
>>>> -                reg = <0x0>;
>>>> -                interrupt-parent = <&adc_2>;
>>>> -                interrupts = <0>;
>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>> -                dma-names = "rx";
>>>> -                status = "disabled";
>>>> -
>>>> -                channel@13 {
>>>> -                    reg = <13>;
>>>> -                    label = "vrefint";
>>>> -                };
>>>> -                channel@14 {
>>>> -                    reg = <14>;
>>>> -                    label = "vddcore";
>>>> -                };
>>>> -                channel@16 {
>>>> -                    reg = <16>;
>>>> -                    label = "vddcpu";
>>>> -                };
>>>> -                channel@17 {
>>>> -                    reg = <17>;
>>>> -                    label = "vddq_ddr";
>>>> -                };
>>>> -            };
>>>> -        };
>>>> -
>>>> -        usbotg_hs: usb@49000000 {
>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>> -            reg = <0x49000000 0x40000>;
>>>> -            clocks = <&rcc USBO_K>;
>>>> -            clock-names = "otg";
>>>> -            resets = <&rcc USBO_R>;
>>>> -            reset-names = "dwc2";
>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            g-rx-fifo-size = <512>;
>>>> -            g-np-tx-fifo-size = <32>;
>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>> -            dr_mode = "otg";
>>>> -            otg-rev = <0x200>;
>>>> -            usb33d-supply = <&usb33>;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        spi4: spi@4c002000 {
>>>> -            compatible = "st,stm32h7-spi";
>>>> -            reg = <0x4c002000 0x400>;
>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SPI4_K>;
>>>> -            resets = <&rcc SPI4_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>> -            dma-names = "rx", "tx";
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        spi5: spi@4c003000 {
>>>> -            compatible = "st,stm32h7-spi";
>>>> -            reg = <0x4c003000 0x400>;
>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SPI5_K>;
>>>> -            resets = <&rcc SPI5_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>> -            dma-names = "rx", "tx";
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        i2c3: i2c@4c004000 {
>>>> -            compatible = "st,stm32mp13-i2c";
>>>> -            reg = <0x4c004000 0x400>;
>>>> -            interrupt-names = "event", "error";
>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc I2C3_K>;
>>>> -            resets = <&rcc I2C3_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>> -            dma-names = "rx", "tx";
>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>> -            i2c-analog-filter;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        i2c4: i2c@4c005000 {
>>>> -            compatible = "st,stm32mp13-i2c";
>>>> -            reg = <0x4c005000 0x400>;
>>>> -            interrupt-names = "event", "error";
>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc I2C4_K>;
>>>> -            resets = <&rcc I2C4_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>> -            dma-names = "rx", "tx";
>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>> -            i2c-analog-filter;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        i2c5: i2c@4c006000 {
>>>> -            compatible = "st,stm32mp13-i2c";
>>>> -            reg = <0x4c006000 0x400>;
>>>> -            interrupt-names = "event", "error";
>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc I2C5_K>;
>>>> -            resets = <&rcc I2C5_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>> -            dma-names = "rx", "tx";
>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>> -            i2c-analog-filter;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>>           rcc: rcc@50000000 {
>>>>               compatible = "st,stm32mp13-rcc", "syscon";
>>>>               reg = <0x50000000 0x1000>;
>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>               dma-requests = <48>;
>>>>           };
>>>>   -        sdmmc1: mmc@58005000 {
>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> -            arm,primecell-periphid = <0x20253180>;
>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SDMMC1_K>;
>>>> -            clock-names = "apb_pclk";
>>>> -            resets = <&rcc SDMMC1_R>;
>>>> -            cap-sd-highspeed;
>>>> -            cap-mmc-highspeed;
>>>> -            max-frequency = <130000000>;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        sdmmc2: mmc@58007000 {
>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> -            arm,primecell-periphid = <0x20253180>;
>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SDMMC2_K>;
>>>> -            clock-names = "apb_pclk";
>>>> -            resets = <&rcc SDMMC2_R>;
>>>> -            cap-sd-highspeed;
>>>> -            cap-mmc-highspeed;
>>>> -            max-frequency = <130000000>;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>>           usbh_ohci: usb@5800c000 {
>>>>               compatible = "generic-ohci";
>>>>               reg = <0x5800c000 0x1000>;
>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>               status = "disabled";
>>>>           };
>>>>   -        usbphyc: usbphyc@5a006000 {
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            #clock-cells = <0>;
>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>> -            reg = <0x5a006000 0x1000>;
>>>> -            clocks = <&rcc USBPHY_K>;
>>>> -            resets = <&rcc USBPHY_R>;
>>>> -            vdda1v1-supply = <&reg11>;
>>>> -            vdda1v8-supply = <&reg18>;
>>>> -            status = "disabled";
>>>> -
>>>> -            usbphyc_port0: usb-phy@0 {
>>>> -                #phy-cells = <0>;
>>>> -                reg = <0>;
>>>> -            };
>>>> -
>>>> -            usbphyc_port1: usb-phy@1 {
>>>> -                #phy-cells = <1>;
>>>> -                reg = <1>;
>>>> -            };
>>>> -        };
>>>> -
>>>>           rtc: rtc@5c004000 {
>>>>               compatible = "st,stm32mp1-rtc";
>>>>               reg = <0x5c004000 0x400>;
>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>               };
>>>>           };
>>>>   +        etzpc: bus@5c007000 {
>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>> +            reg = <0x5c007000 0x400>;
>>>> +            #address-cells = <1>;
>>>> +            #size-cells = <1>;
>>>> +            feature-domain-controller;
>>>> +            #feature-domain-cells = <1>;
>>>> +            ranges;
>>>> +
>>>> +            adc_2: adc@48004000 {
>>>> +                compatible = "st,stm32mp13-adc-core";
>>>> +                reg = <0x48004000 0x400>;
>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>> +                clock-names = "bus", "adc";
>>>> +                interrupt-controller;
>>>> +                #interrupt-cells = <1>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                feature-domains = <&etzpc 33>;
>>>> +                status = "disabled";
>>>> +
>>>> +                adc2: adc@0 {
>>>> +                    compatible = "st,stm32mp13-adc";
>>>> +                    #io-channel-cells = <1>;
>>>> +                    #address-cells = <1>;
>>>> +                    #size-cells = <0>;
>>>> +                    reg = <0x0>;
>>>> +                    interrupt-parent = <&adc_2>;
>>>> +                    interrupts = <0>;
>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>> +                    dma-names = "rx";
>>>> +                    status = "disabled";
>>>> +
>>>> +                    channel@13 {
>>>> +                        reg = <13>;
>>>> +                        label = "vrefint";
>>>> +                    };
>>>> +                    channel@14 {
>>>> +                        reg = <14>;
>>>> +                        label = "vddcore";
>>>> +                    };
>>>> +                    channel@16 {
>>>> +                        reg = <16>;
>>>> +                        label = "vddcpu";
>>>> +                    };
>>>> +                    channel@17 {
>>>> +                        reg = <17>;
>>>> +                        label = "vddq_ddr";
>>>> +                    };
>>>> +                };
>>>> +            };
>>>> +
>>>> +            usbotg_hs: usb@49000000 {
>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>> +                reg = <0x49000000 0x40000>;
>>>> +                clocks = <&rcc USBO_K>;
>>>> +                clock-names = "otg";
>>>> +                resets = <&rcc USBO_R>;
>>>> +                reset-names = "dwc2";
>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                g-rx-fifo-size = <512>;
>>>> +                g-np-tx-fifo-size = <32>;
>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>> +                dr_mode = "otg";
>>>> +                otg-rev = <0x200>;
>>>> +                usb33d-supply = <&usb33>;
>>>> +                feature-domains = <&etzpc 34>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            spi4: spi@4c002000 {
>>>> +                compatible = "st,stm32h7-spi";
>>>> +                reg = <0x4c002000 0x400>;
>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SPI4_K>;
>>>> +                resets = <&rcc SPI4_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>> +                dma-names = "rx", "tx";
>>>> +                feature-domains = <&etzpc 18>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            spi5: spi@4c003000 {
>>>> +                compatible = "st,stm32h7-spi";
>>>> +                reg = <0x4c003000 0x400>;
>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SPI5_K>;
>>>> +                resets = <&rcc SPI5_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>> +                dma-names = "rx", "tx";
>>>> +                feature-domains = <&etzpc 19>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            i2c3: i2c@4c004000 {
>>>> +                compatible = "st,stm32mp13-i2c";
>>>> +                reg = <0x4c004000 0x400>;
>>>> +                interrupt-names = "event", "error";
>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc I2C3_K>;
>>>> +                resets = <&rcc I2C3_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>> +                dma-names = "rx", "tx";
>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>> +                i2c-analog-filter;
>>>> +                feature-domains = <&etzpc 20>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            i2c4: i2c@4c005000 {
>>>> +                compatible = "st,stm32mp13-i2c";
>>>> +                reg = <0x4c005000 0x400>;
>>>> +                interrupt-names = "event", "error";
>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc I2C4_K>;
>>>> +                resets = <&rcc I2C4_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>> +                dma-names = "rx", "tx";
>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>> +                i2c-analog-filter;
>>>> +                feature-domains = <&etzpc 21>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            i2c5: i2c@4c006000 {
>>>> +                compatible = "st,stm32mp13-i2c";
>>>> +                reg = <0x4c006000 0x400>;
>>>> +                interrupt-names = "event", "error";
>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc I2C5_K>;
>>>> +                resets = <&rcc I2C5_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>> +                dma-names = "rx", "tx";
>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>> +                i2c-analog-filter;
>>>> +                feature-domains = <&etzpc 22>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            sdmmc1: mmc@58005000 {
>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> +                arm,primecell-periphid = <0x20253180>;
>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SDMMC1_K>;
>>>> +                clock-names = "apb_pclk";
>>>> +                resets = <&rcc SDMMC1_R>;
>>>> +                cap-sd-highspeed;
>>>> +                cap-mmc-highspeed;
>>>> +                max-frequency = <130000000>;
>>>> +                feature-domains = <&etzpc 50>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            sdmmc2: mmc@58007000 {
>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> +                arm,primecell-periphid = <0x20253180>;
>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SDMMC2_K>;
>>>> +                clock-names = "apb_pclk";
>>>> +                resets = <&rcc SDMMC2_R>;
>>>> +                cap-sd-highspeed;
>>>> +                cap-mmc-highspeed;
>>>> +                max-frequency = <130000000>;
>>>> +                feature-domains = <&etzpc 51>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            usbphyc: usbphyc@5a006000 {
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                #clock-cells = <0>;
>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>> +                reg = <0x5a006000 0x1000>;
>>>> +                clocks = <&rcc USBPHY_K>;
>>>> +                resets = <&rcc USBPHY_R>;
>>>> +                vdda1v1-supply = <&reg11>;
>>>> +                vdda1v8-supply = <&reg18>;
>>>> +                feature-domains = <&etzpc 5>;
>>>> +                status = "disabled";
>>>> +
>>>> +                usbphyc_port0: usb-phy@0 {
>>>> +                    #phy-cells = <0>;
>>>> +                    reg = <0>;
>>>> +                };
>>>> +
>>>> +                usbphyc_port1: usb-phy@1 {
>>>> +                    #phy-cells = <1>;
>>>> +                    reg = <1>;
>>>> +                };
>>>> +            };
>>>> +
>>>> +        };
>>>> +
>>>>           /*
>>>>            * Break node order to solve dependency probe issue between
>>>>            * pinctrl and exti.
>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>>> index df451c3c2a26..be6061552683 100644
>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>               bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>               status = "disabled";
>>>>           };
>>>> +    };
>>>> +};
>>>>   -        adc_1: adc@48003000 {
>>>> -            compatible = "st,stm32mp13-adc-core";
>>>> -            reg = <0x48003000 0x400>;
>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>> -            clock-names = "bus", "adc";
>>>> -            interrupt-controller;
>>>> -            #interrupt-cells = <1>;
>>>> +&etzpc {
>>>> +    adc_1: adc@48003000 {
>>>> +        compatible = "st,stm32mp13-adc-core";
>>>> +        reg = <0x48003000 0x400>;
>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>> +        clock-names = "bus", "adc";
>>>> +        interrupt-controller;
>>>> +        #interrupt-cells = <1>;
>>>> +        #address-cells = <1>;
>>>> +        #size-cells = <0>;
>>>> +        feature-domains = <&etzpc 32>;
>>>> +        status = "disabled";
>>>> +
>>>> +        adc1: adc@0 {
>>>> +            compatible = "st,stm32mp13-adc";
>>>> +            #io-channel-cells = <1>;
>>>>               #address-cells = <1>;
>>>>               #size-cells = <0>;
>>>> +            reg = <0x0>;
>>>> +            interrupt-parent = <&adc_1>;
>>>> +            interrupts = <0>;
>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>> +            dma-names = "rx";
>>>>               status = "disabled";
>>>>   -            adc1: adc@0 {
>>>> -                compatible = "st,stm32mp13-adc";
>>>> -                #io-channel-cells = <1>;
>>>> -                #address-cells = <1>;
>>>> -                #size-cells = <0>;
>>>> -                reg = <0x0>;
>>>> -                interrupt-parent = <&adc_1>;
>>>> -                interrupts = <0>;
>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>> -                dma-names = "rx";
>>>> -                status = "disabled";
>>>> -
>>>> -                channel@18 {
>>>> -                    reg = <18>;
>>>> -                    label = "vrefint";
>>>> -                };
>>>> +            channel@18 {
>>>> +                reg = <18>;
>>>> +                label = "vrefint";
>>>>               };
>>>>           };
>>>>       };
>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>> @@ -4,15 +4,14 @@
>>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>    */
>>>>   -/ {
>>>> -    soc {
>>>> -        cryp: crypto@54002000 {
>>>> -            compatible = "st,stm32mp1-cryp";
>>>> -            reg = <0x54002000 0x400>;
>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc CRYP1>;
>>>> -            resets = <&rcc CRYP1_R>;
>>>> -            status = "disabled";
>>>> -        };
>>>> +&etzpc {
>>>> +    cryp: crypto@54002000 {
>>>> +        compatible = "st,stm32mp1-cryp";
>>>> +        reg = <0x54002000 0x400>;
>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> +        clocks = <&rcc CRYP1>;
>>>> +        resets = <&rcc CRYP1_R>;
>>>> +        feature-domains = <&etzpc 42>;
>>>> +        status = "disabled";
>>>>       };
>>>>   };
>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>> index 4d00e7592882..b9fb071a1471 100644
>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>> @@ -4,15 +4,13 @@
>>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>    */
>>>>   -/ {
>>>> -    soc {
>>>> -        cryp: crypto@54002000 {
>>>> -            compatible = "st,stm32mp1-cryp";
>>>> -            reg = <0x54002000 0x400>;
>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc CRYP1>;
>>>> -            resets = <&rcc CRYP1_R>;
>>>> -            status = "disabled";
>>>> -        };
>>>> +&etzpc {
>>>> +    cryp: crypto@54002000 {
>>>> +        compatible = "st,stm32mp1-cryp";
>>>> +        reg = <0x54002000 0x400>;
>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> +        clocks = <&rcc CRYP1>;
>>>> +        resets = <&rcc CRYP1_R>;
>>>> +        status = "disabled";
>>>>       };
>>>>   };
>>>
>>
> 
> Regarding the patch itself, I can separate it in two patches.
> 1)Introduce ETZPC
> 2)Move peripherals under ETZPC
> 
> Best regards,
> Gatien
> 

-- 
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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-13 11:27           ` Ahmad Fatoum
  0 siblings, 0 replies; 93+ messages in thread
From: Ahmad Fatoum @ 2023-02-13 11:27 UTC (permalink / raw)
  To: Gatien CHEVALLIER, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team

Hello Gatien,

On 13.02.23 11:54, Gatien CHEVALLIER wrote:
> On 2/9/23 09:10, Ahmad Fatoum wrote:
>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>> Hello Gatien,
>>>
>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>> The STM32 System Bus is an internal bus on which devices are connected.
>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>> and control access to the peripherals connected on it.
>>>>
>>>> For more information on which peripheral is securable, please read
>>>> the STM32MP13 reference manual.
>>>
>>> Diff is way too big. Please split up the alphabetic reordering into its
>>> own commit, so actual functional changes are apparent.
>>
>> Ah, I see now that you are moving securable peripherals into a new bus.
>> I share Uwe's confusion of considering the ETZPC as bus.
>>
>> Does this configuration even change dynamically? Why can't you implement
>> this binding in the bootloader and have Linux only see a DT where unavailable
>> nodes are status = "disabled"; secure-status = "okay"?
>>
>> For inspiration, see barebox' device tree fixups when devices are disabled
>> per fuse:
>>
>>    https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
>>
>> Cheers,
>> Ahmad
> 
> This configuration can change dynamically. The binding will be implemented in the bootloader, where the ETZPC is already implemented as a bus in our downstream.
> 
> I find the mentionned example valid.
> 
> Now, why is it a bus? :D
> 
> It is the result of the discussion on the previous submission by Benjamin (Sorry for the lack of link but I saw that you participated on these threads)+ we need the bus mechanism to control whether a subnode should be probed or not. You can see it as a firewall bus.
> 
> The ETZPC relies on the ARM TrustZone extension to the AHB bus and propagation through bridges to the APB bus. Therefore, I find it relevant to consider it as a bus, what is your opinion?
> 
> This patchset is a first step to the implementation of an API to control accesses dynamically.

I still don't get what's dynamic about this. Either:

  - Configuration _can_ change while Linux is running: You'll need to do
    way more than what your current bus provides to somwhow synchronize state
    with the secure monitor; otherwise a newly secured device will cause the driver
    to trigger data aborts that you'll have to handle and unbind the driver.
    (like if a USB drive is yanked out).

  - Configuration _can't_ change while Linux is running: You can have the bootloader
    fixup the device tree and Linux need not care at all about devices that the
    ETZPC is securing.

My understanding is that the latter is your use case, so I don't see why we
even need the normal world to be aware of the partitioning.

Cheers,
Ahmad

> 
>>
>>>
>>> Thanks,
>>> Ahmad
>>>
>>>>
>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>> ---
>>>>
>>>> No changes in V2.
>>>>
>>>> Changes in V3:
>>>>     -Use appriopriate node name: bus
>>>>
>>>>   arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>>   arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>   arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>   arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>   4 files changed, 258 insertions(+), 237 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>>> index accc3824f7e9..24462a647101 100644
>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>               dma-channels = <16>;
>>>>           };
>>>>   -        adc_2: adc@48004000 {
>>>> -            compatible = "st,stm32mp13-adc-core";
>>>> -            reg = <0x48004000 0x400>;
>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>> -            clock-names = "bus", "adc";
>>>> -            interrupt-controller;
>>>> -            #interrupt-cells = <1>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            status = "disabled";
>>>> -
>>>> -            adc2: adc@0 {
>>>> -                compatible = "st,stm32mp13-adc";
>>>> -                #io-channel-cells = <1>;
>>>> -                #address-cells = <1>;
>>>> -                #size-cells = <0>;
>>>> -                reg = <0x0>;
>>>> -                interrupt-parent = <&adc_2>;
>>>> -                interrupts = <0>;
>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>> -                dma-names = "rx";
>>>> -                status = "disabled";
>>>> -
>>>> -                channel@13 {
>>>> -                    reg = <13>;
>>>> -                    label = "vrefint";
>>>> -                };
>>>> -                channel@14 {
>>>> -                    reg = <14>;
>>>> -                    label = "vddcore";
>>>> -                };
>>>> -                channel@16 {
>>>> -                    reg = <16>;
>>>> -                    label = "vddcpu";
>>>> -                };
>>>> -                channel@17 {
>>>> -                    reg = <17>;
>>>> -                    label = "vddq_ddr";
>>>> -                };
>>>> -            };
>>>> -        };
>>>> -
>>>> -        usbotg_hs: usb@49000000 {
>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>> -            reg = <0x49000000 0x40000>;
>>>> -            clocks = <&rcc USBO_K>;
>>>> -            clock-names = "otg";
>>>> -            resets = <&rcc USBO_R>;
>>>> -            reset-names = "dwc2";
>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            g-rx-fifo-size = <512>;
>>>> -            g-np-tx-fifo-size = <32>;
>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>> -            dr_mode = "otg";
>>>> -            otg-rev = <0x200>;
>>>> -            usb33d-supply = <&usb33>;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        spi4: spi@4c002000 {
>>>> -            compatible = "st,stm32h7-spi";
>>>> -            reg = <0x4c002000 0x400>;
>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SPI4_K>;
>>>> -            resets = <&rcc SPI4_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>> -            dma-names = "rx", "tx";
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        spi5: spi@4c003000 {
>>>> -            compatible = "st,stm32h7-spi";
>>>> -            reg = <0x4c003000 0x400>;
>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SPI5_K>;
>>>> -            resets = <&rcc SPI5_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>> -            dma-names = "rx", "tx";
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        i2c3: i2c@4c004000 {
>>>> -            compatible = "st,stm32mp13-i2c";
>>>> -            reg = <0x4c004000 0x400>;
>>>> -            interrupt-names = "event", "error";
>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc I2C3_K>;
>>>> -            resets = <&rcc I2C3_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>> -            dma-names = "rx", "tx";
>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>> -            i2c-analog-filter;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        i2c4: i2c@4c005000 {
>>>> -            compatible = "st,stm32mp13-i2c";
>>>> -            reg = <0x4c005000 0x400>;
>>>> -            interrupt-names = "event", "error";
>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc I2C4_K>;
>>>> -            resets = <&rcc I2C4_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>> -            dma-names = "rx", "tx";
>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>> -            i2c-analog-filter;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        i2c5: i2c@4c006000 {
>>>> -            compatible = "st,stm32mp13-i2c";
>>>> -            reg = <0x4c006000 0x400>;
>>>> -            interrupt-names = "event", "error";
>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc I2C5_K>;
>>>> -            resets = <&rcc I2C5_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>> -            dma-names = "rx", "tx";
>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>> -            i2c-analog-filter;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>>           rcc: rcc@50000000 {
>>>>               compatible = "st,stm32mp13-rcc", "syscon";
>>>>               reg = <0x50000000 0x1000>;
>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>               dma-requests = <48>;
>>>>           };
>>>>   -        sdmmc1: mmc@58005000 {
>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> -            arm,primecell-periphid = <0x20253180>;
>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SDMMC1_K>;
>>>> -            clock-names = "apb_pclk";
>>>> -            resets = <&rcc SDMMC1_R>;
>>>> -            cap-sd-highspeed;
>>>> -            cap-mmc-highspeed;
>>>> -            max-frequency = <130000000>;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        sdmmc2: mmc@58007000 {
>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> -            arm,primecell-periphid = <0x20253180>;
>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SDMMC2_K>;
>>>> -            clock-names = "apb_pclk";
>>>> -            resets = <&rcc SDMMC2_R>;
>>>> -            cap-sd-highspeed;
>>>> -            cap-mmc-highspeed;
>>>> -            max-frequency = <130000000>;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>>           usbh_ohci: usb@5800c000 {
>>>>               compatible = "generic-ohci";
>>>>               reg = <0x5800c000 0x1000>;
>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>               status = "disabled";
>>>>           };
>>>>   -        usbphyc: usbphyc@5a006000 {
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            #clock-cells = <0>;
>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>> -            reg = <0x5a006000 0x1000>;
>>>> -            clocks = <&rcc USBPHY_K>;
>>>> -            resets = <&rcc USBPHY_R>;
>>>> -            vdda1v1-supply = <&reg11>;
>>>> -            vdda1v8-supply = <&reg18>;
>>>> -            status = "disabled";
>>>> -
>>>> -            usbphyc_port0: usb-phy@0 {
>>>> -                #phy-cells = <0>;
>>>> -                reg = <0>;
>>>> -            };
>>>> -
>>>> -            usbphyc_port1: usb-phy@1 {
>>>> -                #phy-cells = <1>;
>>>> -                reg = <1>;
>>>> -            };
>>>> -        };
>>>> -
>>>>           rtc: rtc@5c004000 {
>>>>               compatible = "st,stm32mp1-rtc";
>>>>               reg = <0x5c004000 0x400>;
>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>               };
>>>>           };
>>>>   +        etzpc: bus@5c007000 {
>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>> +            reg = <0x5c007000 0x400>;
>>>> +            #address-cells = <1>;
>>>> +            #size-cells = <1>;
>>>> +            feature-domain-controller;
>>>> +            #feature-domain-cells = <1>;
>>>> +            ranges;
>>>> +
>>>> +            adc_2: adc@48004000 {
>>>> +                compatible = "st,stm32mp13-adc-core";
>>>> +                reg = <0x48004000 0x400>;
>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>> +                clock-names = "bus", "adc";
>>>> +                interrupt-controller;
>>>> +                #interrupt-cells = <1>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                feature-domains = <&etzpc 33>;
>>>> +                status = "disabled";
>>>> +
>>>> +                adc2: adc@0 {
>>>> +                    compatible = "st,stm32mp13-adc";
>>>> +                    #io-channel-cells = <1>;
>>>> +                    #address-cells = <1>;
>>>> +                    #size-cells = <0>;
>>>> +                    reg = <0x0>;
>>>> +                    interrupt-parent = <&adc_2>;
>>>> +                    interrupts = <0>;
>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>> +                    dma-names = "rx";
>>>> +                    status = "disabled";
>>>> +
>>>> +                    channel@13 {
>>>> +                        reg = <13>;
>>>> +                        label = "vrefint";
>>>> +                    };
>>>> +                    channel@14 {
>>>> +                        reg = <14>;
>>>> +                        label = "vddcore";
>>>> +                    };
>>>> +                    channel@16 {
>>>> +                        reg = <16>;
>>>> +                        label = "vddcpu";
>>>> +                    };
>>>> +                    channel@17 {
>>>> +                        reg = <17>;
>>>> +                        label = "vddq_ddr";
>>>> +                    };
>>>> +                };
>>>> +            };
>>>> +
>>>> +            usbotg_hs: usb@49000000 {
>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>> +                reg = <0x49000000 0x40000>;
>>>> +                clocks = <&rcc USBO_K>;
>>>> +                clock-names = "otg";
>>>> +                resets = <&rcc USBO_R>;
>>>> +                reset-names = "dwc2";
>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                g-rx-fifo-size = <512>;
>>>> +                g-np-tx-fifo-size = <32>;
>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>> +                dr_mode = "otg";
>>>> +                otg-rev = <0x200>;
>>>> +                usb33d-supply = <&usb33>;
>>>> +                feature-domains = <&etzpc 34>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            spi4: spi@4c002000 {
>>>> +                compatible = "st,stm32h7-spi";
>>>> +                reg = <0x4c002000 0x400>;
>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SPI4_K>;
>>>> +                resets = <&rcc SPI4_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>> +                dma-names = "rx", "tx";
>>>> +                feature-domains = <&etzpc 18>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            spi5: spi@4c003000 {
>>>> +                compatible = "st,stm32h7-spi";
>>>> +                reg = <0x4c003000 0x400>;
>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SPI5_K>;
>>>> +                resets = <&rcc SPI5_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>> +                dma-names = "rx", "tx";
>>>> +                feature-domains = <&etzpc 19>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            i2c3: i2c@4c004000 {
>>>> +                compatible = "st,stm32mp13-i2c";
>>>> +                reg = <0x4c004000 0x400>;
>>>> +                interrupt-names = "event", "error";
>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc I2C3_K>;
>>>> +                resets = <&rcc I2C3_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>> +                dma-names = "rx", "tx";
>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>> +                i2c-analog-filter;
>>>> +                feature-domains = <&etzpc 20>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            i2c4: i2c@4c005000 {
>>>> +                compatible = "st,stm32mp13-i2c";
>>>> +                reg = <0x4c005000 0x400>;
>>>> +                interrupt-names = "event", "error";
>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc I2C4_K>;
>>>> +                resets = <&rcc I2C4_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>> +                dma-names = "rx", "tx";
>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>> +                i2c-analog-filter;
>>>> +                feature-domains = <&etzpc 21>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            i2c5: i2c@4c006000 {
>>>> +                compatible = "st,stm32mp13-i2c";
>>>> +                reg = <0x4c006000 0x400>;
>>>> +                interrupt-names = "event", "error";
>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc I2C5_K>;
>>>> +                resets = <&rcc I2C5_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>> +                dma-names = "rx", "tx";
>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>> +                i2c-analog-filter;
>>>> +                feature-domains = <&etzpc 22>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            sdmmc1: mmc@58005000 {
>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> +                arm,primecell-periphid = <0x20253180>;
>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SDMMC1_K>;
>>>> +                clock-names = "apb_pclk";
>>>> +                resets = <&rcc SDMMC1_R>;
>>>> +                cap-sd-highspeed;
>>>> +                cap-mmc-highspeed;
>>>> +                max-frequency = <130000000>;
>>>> +                feature-domains = <&etzpc 50>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            sdmmc2: mmc@58007000 {
>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> +                arm,primecell-periphid = <0x20253180>;
>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SDMMC2_K>;
>>>> +                clock-names = "apb_pclk";
>>>> +                resets = <&rcc SDMMC2_R>;
>>>> +                cap-sd-highspeed;
>>>> +                cap-mmc-highspeed;
>>>> +                max-frequency = <130000000>;
>>>> +                feature-domains = <&etzpc 51>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            usbphyc: usbphyc@5a006000 {
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                #clock-cells = <0>;
>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>> +                reg = <0x5a006000 0x1000>;
>>>> +                clocks = <&rcc USBPHY_K>;
>>>> +                resets = <&rcc USBPHY_R>;
>>>> +                vdda1v1-supply = <&reg11>;
>>>> +                vdda1v8-supply = <&reg18>;
>>>> +                feature-domains = <&etzpc 5>;
>>>> +                status = "disabled";
>>>> +
>>>> +                usbphyc_port0: usb-phy@0 {
>>>> +                    #phy-cells = <0>;
>>>> +                    reg = <0>;
>>>> +                };
>>>> +
>>>> +                usbphyc_port1: usb-phy@1 {
>>>> +                    #phy-cells = <1>;
>>>> +                    reg = <1>;
>>>> +                };
>>>> +            };
>>>> +
>>>> +        };
>>>> +
>>>>           /*
>>>>            * Break node order to solve dependency probe issue between
>>>>            * pinctrl and exti.
>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>>> index df451c3c2a26..be6061552683 100644
>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>               bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>               status = "disabled";
>>>>           };
>>>> +    };
>>>> +};
>>>>   -        adc_1: adc@48003000 {
>>>> -            compatible = "st,stm32mp13-adc-core";
>>>> -            reg = <0x48003000 0x400>;
>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>> -            clock-names = "bus", "adc";
>>>> -            interrupt-controller;
>>>> -            #interrupt-cells = <1>;
>>>> +&etzpc {
>>>> +    adc_1: adc@48003000 {
>>>> +        compatible = "st,stm32mp13-adc-core";
>>>> +        reg = <0x48003000 0x400>;
>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>> +        clock-names = "bus", "adc";
>>>> +        interrupt-controller;
>>>> +        #interrupt-cells = <1>;
>>>> +        #address-cells = <1>;
>>>> +        #size-cells = <0>;
>>>> +        feature-domains = <&etzpc 32>;
>>>> +        status = "disabled";
>>>> +
>>>> +        adc1: adc@0 {
>>>> +            compatible = "st,stm32mp13-adc";
>>>> +            #io-channel-cells = <1>;
>>>>               #address-cells = <1>;
>>>>               #size-cells = <0>;
>>>> +            reg = <0x0>;
>>>> +            interrupt-parent = <&adc_1>;
>>>> +            interrupts = <0>;
>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>> +            dma-names = "rx";
>>>>               status = "disabled";
>>>>   -            adc1: adc@0 {
>>>> -                compatible = "st,stm32mp13-adc";
>>>> -                #io-channel-cells = <1>;
>>>> -                #address-cells = <1>;
>>>> -                #size-cells = <0>;
>>>> -                reg = <0x0>;
>>>> -                interrupt-parent = <&adc_1>;
>>>> -                interrupts = <0>;
>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>> -                dma-names = "rx";
>>>> -                status = "disabled";
>>>> -
>>>> -                channel@18 {
>>>> -                    reg = <18>;
>>>> -                    label = "vrefint";
>>>> -                };
>>>> +            channel@18 {
>>>> +                reg = <18>;
>>>> +                label = "vrefint";
>>>>               };
>>>>           };
>>>>       };
>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>> @@ -4,15 +4,14 @@
>>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>    */
>>>>   -/ {
>>>> -    soc {
>>>> -        cryp: crypto@54002000 {
>>>> -            compatible = "st,stm32mp1-cryp";
>>>> -            reg = <0x54002000 0x400>;
>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc CRYP1>;
>>>> -            resets = <&rcc CRYP1_R>;
>>>> -            status = "disabled";
>>>> -        };
>>>> +&etzpc {
>>>> +    cryp: crypto@54002000 {
>>>> +        compatible = "st,stm32mp1-cryp";
>>>> +        reg = <0x54002000 0x400>;
>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> +        clocks = <&rcc CRYP1>;
>>>> +        resets = <&rcc CRYP1_R>;
>>>> +        feature-domains = <&etzpc 42>;
>>>> +        status = "disabled";
>>>>       };
>>>>   };
>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>> index 4d00e7592882..b9fb071a1471 100644
>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>> @@ -4,15 +4,13 @@
>>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>    */
>>>>   -/ {
>>>> -    soc {
>>>> -        cryp: crypto@54002000 {
>>>> -            compatible = "st,stm32mp1-cryp";
>>>> -            reg = <0x54002000 0x400>;
>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc CRYP1>;
>>>> -            resets = <&rcc CRYP1_R>;
>>>> -            status = "disabled";
>>>> -        };
>>>> +&etzpc {
>>>> +    cryp: crypto@54002000 {
>>>> +        compatible = "st,stm32mp1-cryp";
>>>> +        reg = <0x54002000 0x400>;
>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> +        clocks = <&rcc CRYP1>;
>>>> +        resets = <&rcc CRYP1_R>;
>>>> +        status = "disabled";
>>>>       };
>>>>   };
>>>
>>
> 
> Regarding the patch itself, I can separate it in two patches.
> 1)Introduce ETZPC
> 2)Move peripherals under ETZPC
> 
> Best regards,
> Gatien
> 

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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-13 11:27           ` Ahmad Fatoum
  0 siblings, 0 replies; 93+ messages in thread
From: Ahmad Fatoum @ 2023-02-13 11:27 UTC (permalink / raw)
  To: Gatien CHEVALLIER, Oleksii_Moisieiev, gregkh, herbert, davem,
	robh+dt, krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team

Hello Gatien,

On 13.02.23 11:54, Gatien CHEVALLIER wrote:
> On 2/9/23 09:10, Ahmad Fatoum wrote:
>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>> Hello Gatien,
>>>
>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>> The STM32 System Bus is an internal bus on which devices are connected.
>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>> and control access to the peripherals connected on it.
>>>>
>>>> For more information on which peripheral is securable, please read
>>>> the STM32MP13 reference manual.
>>>
>>> Diff is way too big. Please split up the alphabetic reordering into its
>>> own commit, so actual functional changes are apparent.
>>
>> Ah, I see now that you are moving securable peripherals into a new bus.
>> I share Uwe's confusion of considering the ETZPC as bus.
>>
>> Does this configuration even change dynamically? Why can't you implement
>> this binding in the bootloader and have Linux only see a DT where unavailable
>> nodes are status = "disabled"; secure-status = "okay"?
>>
>> For inspiration, see barebox' device tree fixups when devices are disabled
>> per fuse:
>>
>>    https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
>>
>> Cheers,
>> Ahmad
> 
> This configuration can change dynamically. The binding will be implemented in the bootloader, where the ETZPC is already implemented as a bus in our downstream.
> 
> I find the mentionned example valid.
> 
> Now, why is it a bus? :D
> 
> It is the result of the discussion on the previous submission by Benjamin (Sorry for the lack of link but I saw that you participated on these threads)+ we need the bus mechanism to control whether a subnode should be probed or not. You can see it as a firewall bus.
> 
> The ETZPC relies on the ARM TrustZone extension to the AHB bus and propagation through bridges to the APB bus. Therefore, I find it relevant to consider it as a bus, what is your opinion?
> 
> This patchset is a first step to the implementation of an API to control accesses dynamically.

I still don't get what's dynamic about this. Either:

  - Configuration _can_ change while Linux is running: You'll need to do
    way more than what your current bus provides to somwhow synchronize state
    with the secure monitor; otherwise a newly secured device will cause the driver
    to trigger data aborts that you'll have to handle and unbind the driver.
    (like if a USB drive is yanked out).

  - Configuration _can't_ change while Linux is running: You can have the bootloader
    fixup the device tree and Linux need not care at all about devices that the
    ETZPC is securing.

My understanding is that the latter is your use case, so I don't see why we
even need the normal world to be aware of the partitioning.

Cheers,
Ahmad

> 
>>
>>>
>>> Thanks,
>>> Ahmad
>>>
>>>>
>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>> ---
>>>>
>>>> No changes in V2.
>>>>
>>>> Changes in V3:
>>>>     -Use appriopriate node name: bus
>>>>
>>>>   arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>>   arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>   arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>   arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>   4 files changed, 258 insertions(+), 237 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>>> index accc3824f7e9..24462a647101 100644
>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>               dma-channels = <16>;
>>>>           };
>>>>   -        adc_2: adc@48004000 {
>>>> -            compatible = "st,stm32mp13-adc-core";
>>>> -            reg = <0x48004000 0x400>;
>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>> -            clock-names = "bus", "adc";
>>>> -            interrupt-controller;
>>>> -            #interrupt-cells = <1>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            status = "disabled";
>>>> -
>>>> -            adc2: adc@0 {
>>>> -                compatible = "st,stm32mp13-adc";
>>>> -                #io-channel-cells = <1>;
>>>> -                #address-cells = <1>;
>>>> -                #size-cells = <0>;
>>>> -                reg = <0x0>;
>>>> -                interrupt-parent = <&adc_2>;
>>>> -                interrupts = <0>;
>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>> -                dma-names = "rx";
>>>> -                status = "disabled";
>>>> -
>>>> -                channel@13 {
>>>> -                    reg = <13>;
>>>> -                    label = "vrefint";
>>>> -                };
>>>> -                channel@14 {
>>>> -                    reg = <14>;
>>>> -                    label = "vddcore";
>>>> -                };
>>>> -                channel@16 {
>>>> -                    reg = <16>;
>>>> -                    label = "vddcpu";
>>>> -                };
>>>> -                channel@17 {
>>>> -                    reg = <17>;
>>>> -                    label = "vddq_ddr";
>>>> -                };
>>>> -            };
>>>> -        };
>>>> -
>>>> -        usbotg_hs: usb@49000000 {
>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>> -            reg = <0x49000000 0x40000>;
>>>> -            clocks = <&rcc USBO_K>;
>>>> -            clock-names = "otg";
>>>> -            resets = <&rcc USBO_R>;
>>>> -            reset-names = "dwc2";
>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            g-rx-fifo-size = <512>;
>>>> -            g-np-tx-fifo-size = <32>;
>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>> -            dr_mode = "otg";
>>>> -            otg-rev = <0x200>;
>>>> -            usb33d-supply = <&usb33>;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        spi4: spi@4c002000 {
>>>> -            compatible = "st,stm32h7-spi";
>>>> -            reg = <0x4c002000 0x400>;
>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SPI4_K>;
>>>> -            resets = <&rcc SPI4_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>> -            dma-names = "rx", "tx";
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        spi5: spi@4c003000 {
>>>> -            compatible = "st,stm32h7-spi";
>>>> -            reg = <0x4c003000 0x400>;
>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SPI5_K>;
>>>> -            resets = <&rcc SPI5_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>> -            dma-names = "rx", "tx";
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        i2c3: i2c@4c004000 {
>>>> -            compatible = "st,stm32mp13-i2c";
>>>> -            reg = <0x4c004000 0x400>;
>>>> -            interrupt-names = "event", "error";
>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc I2C3_K>;
>>>> -            resets = <&rcc I2C3_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>> -            dma-names = "rx", "tx";
>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>> -            i2c-analog-filter;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        i2c4: i2c@4c005000 {
>>>> -            compatible = "st,stm32mp13-i2c";
>>>> -            reg = <0x4c005000 0x400>;
>>>> -            interrupt-names = "event", "error";
>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc I2C4_K>;
>>>> -            resets = <&rcc I2C4_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>> -            dma-names = "rx", "tx";
>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>> -            i2c-analog-filter;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        i2c5: i2c@4c006000 {
>>>> -            compatible = "st,stm32mp13-i2c";
>>>> -            reg = <0x4c006000 0x400>;
>>>> -            interrupt-names = "event", "error";
>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc I2C5_K>;
>>>> -            resets = <&rcc I2C5_R>;
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>> -            dma-names = "rx", "tx";
>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>> -            i2c-analog-filter;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>>           rcc: rcc@50000000 {
>>>>               compatible = "st,stm32mp13-rcc", "syscon";
>>>>               reg = <0x50000000 0x1000>;
>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>               dma-requests = <48>;
>>>>           };
>>>>   -        sdmmc1: mmc@58005000 {
>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> -            arm,primecell-periphid = <0x20253180>;
>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SDMMC1_K>;
>>>> -            clock-names = "apb_pclk";
>>>> -            resets = <&rcc SDMMC1_R>;
>>>> -            cap-sd-highspeed;
>>>> -            cap-mmc-highspeed;
>>>> -            max-frequency = <130000000>;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>> -        sdmmc2: mmc@58007000 {
>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> -            arm,primecell-periphid = <0x20253180>;
>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc SDMMC2_K>;
>>>> -            clock-names = "apb_pclk";
>>>> -            resets = <&rcc SDMMC2_R>;
>>>> -            cap-sd-highspeed;
>>>> -            cap-mmc-highspeed;
>>>> -            max-frequency = <130000000>;
>>>> -            status = "disabled";
>>>> -        };
>>>> -
>>>>           usbh_ohci: usb@5800c000 {
>>>>               compatible = "generic-ohci";
>>>>               reg = <0x5800c000 0x1000>;
>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>               status = "disabled";
>>>>           };
>>>>   -        usbphyc: usbphyc@5a006000 {
>>>> -            #address-cells = <1>;
>>>> -            #size-cells = <0>;
>>>> -            #clock-cells = <0>;
>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>> -            reg = <0x5a006000 0x1000>;
>>>> -            clocks = <&rcc USBPHY_K>;
>>>> -            resets = <&rcc USBPHY_R>;
>>>> -            vdda1v1-supply = <&reg11>;
>>>> -            vdda1v8-supply = <&reg18>;
>>>> -            status = "disabled";
>>>> -
>>>> -            usbphyc_port0: usb-phy@0 {
>>>> -                #phy-cells = <0>;
>>>> -                reg = <0>;
>>>> -            };
>>>> -
>>>> -            usbphyc_port1: usb-phy@1 {
>>>> -                #phy-cells = <1>;
>>>> -                reg = <1>;
>>>> -            };
>>>> -        };
>>>> -
>>>>           rtc: rtc@5c004000 {
>>>>               compatible = "st,stm32mp1-rtc";
>>>>               reg = <0x5c004000 0x400>;
>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>               };
>>>>           };
>>>>   +        etzpc: bus@5c007000 {
>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>> +            reg = <0x5c007000 0x400>;
>>>> +            #address-cells = <1>;
>>>> +            #size-cells = <1>;
>>>> +            feature-domain-controller;
>>>> +            #feature-domain-cells = <1>;
>>>> +            ranges;
>>>> +
>>>> +            adc_2: adc@48004000 {
>>>> +                compatible = "st,stm32mp13-adc-core";
>>>> +                reg = <0x48004000 0x400>;
>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>> +                clock-names = "bus", "adc";
>>>> +                interrupt-controller;
>>>> +                #interrupt-cells = <1>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                feature-domains = <&etzpc 33>;
>>>> +                status = "disabled";
>>>> +
>>>> +                adc2: adc@0 {
>>>> +                    compatible = "st,stm32mp13-adc";
>>>> +                    #io-channel-cells = <1>;
>>>> +                    #address-cells = <1>;
>>>> +                    #size-cells = <0>;
>>>> +                    reg = <0x0>;
>>>> +                    interrupt-parent = <&adc_2>;
>>>> +                    interrupts = <0>;
>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>> +                    dma-names = "rx";
>>>> +                    status = "disabled";
>>>> +
>>>> +                    channel@13 {
>>>> +                        reg = <13>;
>>>> +                        label = "vrefint";
>>>> +                    };
>>>> +                    channel@14 {
>>>> +                        reg = <14>;
>>>> +                        label = "vddcore";
>>>> +                    };
>>>> +                    channel@16 {
>>>> +                        reg = <16>;
>>>> +                        label = "vddcpu";
>>>> +                    };
>>>> +                    channel@17 {
>>>> +                        reg = <17>;
>>>> +                        label = "vddq_ddr";
>>>> +                    };
>>>> +                };
>>>> +            };
>>>> +
>>>> +            usbotg_hs: usb@49000000 {
>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>> +                reg = <0x49000000 0x40000>;
>>>> +                clocks = <&rcc USBO_K>;
>>>> +                clock-names = "otg";
>>>> +                resets = <&rcc USBO_R>;
>>>> +                reset-names = "dwc2";
>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                g-rx-fifo-size = <512>;
>>>> +                g-np-tx-fifo-size = <32>;
>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>> +                dr_mode = "otg";
>>>> +                otg-rev = <0x200>;
>>>> +                usb33d-supply = <&usb33>;
>>>> +                feature-domains = <&etzpc 34>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            spi4: spi@4c002000 {
>>>> +                compatible = "st,stm32h7-spi";
>>>> +                reg = <0x4c002000 0x400>;
>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SPI4_K>;
>>>> +                resets = <&rcc SPI4_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>> +                dma-names = "rx", "tx";
>>>> +                feature-domains = <&etzpc 18>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            spi5: spi@4c003000 {
>>>> +                compatible = "st,stm32h7-spi";
>>>> +                reg = <0x4c003000 0x400>;
>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SPI5_K>;
>>>> +                resets = <&rcc SPI5_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>> +                dma-names = "rx", "tx";
>>>> +                feature-domains = <&etzpc 19>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            i2c3: i2c@4c004000 {
>>>> +                compatible = "st,stm32mp13-i2c";
>>>> +                reg = <0x4c004000 0x400>;
>>>> +                interrupt-names = "event", "error";
>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc I2C3_K>;
>>>> +                resets = <&rcc I2C3_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>> +                dma-names = "rx", "tx";
>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>> +                i2c-analog-filter;
>>>> +                feature-domains = <&etzpc 20>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            i2c4: i2c@4c005000 {
>>>> +                compatible = "st,stm32mp13-i2c";
>>>> +                reg = <0x4c005000 0x400>;
>>>> +                interrupt-names = "event", "error";
>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc I2C4_K>;
>>>> +                resets = <&rcc I2C4_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>> +                dma-names = "rx", "tx";
>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>> +                i2c-analog-filter;
>>>> +                feature-domains = <&etzpc 21>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            i2c5: i2c@4c006000 {
>>>> +                compatible = "st,stm32mp13-i2c";
>>>> +                reg = <0x4c006000 0x400>;
>>>> +                interrupt-names = "event", "error";
>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc I2C5_K>;
>>>> +                resets = <&rcc I2C5_R>;
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>> +                dma-names = "rx", "tx";
>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>> +                i2c-analog-filter;
>>>> +                feature-domains = <&etzpc 22>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            sdmmc1: mmc@58005000 {
>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> +                arm,primecell-periphid = <0x20253180>;
>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SDMMC1_K>;
>>>> +                clock-names = "apb_pclk";
>>>> +                resets = <&rcc SDMMC1_R>;
>>>> +                cap-sd-highspeed;
>>>> +                cap-mmc-highspeed;
>>>> +                max-frequency = <130000000>;
>>>> +                feature-domains = <&etzpc 50>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            sdmmc2: mmc@58007000 {
>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>> +                arm,primecell-periphid = <0x20253180>;
>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>> +                clocks = <&rcc SDMMC2_K>;
>>>> +                clock-names = "apb_pclk";
>>>> +                resets = <&rcc SDMMC2_R>;
>>>> +                cap-sd-highspeed;
>>>> +                cap-mmc-highspeed;
>>>> +                max-frequency = <130000000>;
>>>> +                feature-domains = <&etzpc 51>;
>>>> +                status = "disabled";
>>>> +            };
>>>> +
>>>> +            usbphyc: usbphyc@5a006000 {
>>>> +                #address-cells = <1>;
>>>> +                #size-cells = <0>;
>>>> +                #clock-cells = <0>;
>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>> +                reg = <0x5a006000 0x1000>;
>>>> +                clocks = <&rcc USBPHY_K>;
>>>> +                resets = <&rcc USBPHY_R>;
>>>> +                vdda1v1-supply = <&reg11>;
>>>> +                vdda1v8-supply = <&reg18>;
>>>> +                feature-domains = <&etzpc 5>;
>>>> +                status = "disabled";
>>>> +
>>>> +                usbphyc_port0: usb-phy@0 {
>>>> +                    #phy-cells = <0>;
>>>> +                    reg = <0>;
>>>> +                };
>>>> +
>>>> +                usbphyc_port1: usb-phy@1 {
>>>> +                    #phy-cells = <1>;
>>>> +                    reg = <1>;
>>>> +                };
>>>> +            };
>>>> +
>>>> +        };
>>>> +
>>>>           /*
>>>>            * Break node order to solve dependency probe issue between
>>>>            * pinctrl and exti.
>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>>> index df451c3c2a26..be6061552683 100644
>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>               bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>               status = "disabled";
>>>>           };
>>>> +    };
>>>> +};
>>>>   -        adc_1: adc@48003000 {
>>>> -            compatible = "st,stm32mp13-adc-core";
>>>> -            reg = <0x48003000 0x400>;
>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>> -            clock-names = "bus", "adc";
>>>> -            interrupt-controller;
>>>> -            #interrupt-cells = <1>;
>>>> +&etzpc {
>>>> +    adc_1: adc@48003000 {
>>>> +        compatible = "st,stm32mp13-adc-core";
>>>> +        reg = <0x48003000 0x400>;
>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>> +        clock-names = "bus", "adc";
>>>> +        interrupt-controller;
>>>> +        #interrupt-cells = <1>;
>>>> +        #address-cells = <1>;
>>>> +        #size-cells = <0>;
>>>> +        feature-domains = <&etzpc 32>;
>>>> +        status = "disabled";
>>>> +
>>>> +        adc1: adc@0 {
>>>> +            compatible = "st,stm32mp13-adc";
>>>> +            #io-channel-cells = <1>;
>>>>               #address-cells = <1>;
>>>>               #size-cells = <0>;
>>>> +            reg = <0x0>;
>>>> +            interrupt-parent = <&adc_1>;
>>>> +            interrupts = <0>;
>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>> +            dma-names = "rx";
>>>>               status = "disabled";
>>>>   -            adc1: adc@0 {
>>>> -                compatible = "st,stm32mp13-adc";
>>>> -                #io-channel-cells = <1>;
>>>> -                #address-cells = <1>;
>>>> -                #size-cells = <0>;
>>>> -                reg = <0x0>;
>>>> -                interrupt-parent = <&adc_1>;
>>>> -                interrupts = <0>;
>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>> -                dma-names = "rx";
>>>> -                status = "disabled";
>>>> -
>>>> -                channel@18 {
>>>> -                    reg = <18>;
>>>> -                    label = "vrefint";
>>>> -                };
>>>> +            channel@18 {
>>>> +                reg = <18>;
>>>> +                label = "vrefint";
>>>>               };
>>>>           };
>>>>       };
>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>> @@ -4,15 +4,14 @@
>>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>    */
>>>>   -/ {
>>>> -    soc {
>>>> -        cryp: crypto@54002000 {
>>>> -            compatible = "st,stm32mp1-cryp";
>>>> -            reg = <0x54002000 0x400>;
>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc CRYP1>;
>>>> -            resets = <&rcc CRYP1_R>;
>>>> -            status = "disabled";
>>>> -        };
>>>> +&etzpc {
>>>> +    cryp: crypto@54002000 {
>>>> +        compatible = "st,stm32mp1-cryp";
>>>> +        reg = <0x54002000 0x400>;
>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> +        clocks = <&rcc CRYP1>;
>>>> +        resets = <&rcc CRYP1_R>;
>>>> +        feature-domains = <&etzpc 42>;
>>>> +        status = "disabled";
>>>>       };
>>>>   };
>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>> index 4d00e7592882..b9fb071a1471 100644
>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>> @@ -4,15 +4,13 @@
>>>>    * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>    */
>>>>   -/ {
>>>> -    soc {
>>>> -        cryp: crypto@54002000 {
>>>> -            compatible = "st,stm32mp1-cryp";
>>>> -            reg = <0x54002000 0x400>;
>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> -            clocks = <&rcc CRYP1>;
>>>> -            resets = <&rcc CRYP1_R>;
>>>> -            status = "disabled";
>>>> -        };
>>>> +&etzpc {
>>>> +    cryp: crypto@54002000 {
>>>> +        compatible = "st,stm32mp1-cryp";
>>>> +        reg = <0x54002000 0x400>;
>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>> +        clocks = <&rcc CRYP1>;
>>>> +        resets = <&rcc CRYP1_R>;
>>>> +        status = "disabled";
>>>>       };
>>>>   };
>>>
>>
> 
> Regarding the patch itself, I can separate it in two patches.
> 1)Introduce ETZPC
> 2)Move peripherals under ETZPC
> 
> Best regards,
> Gatien
> 

-- 
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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  2023-02-13 11:27           ` Ahmad Fatoum
  (?)
  (?)
@ 2023-02-27 11:26             ` Gatien CHEVALLIER
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-27 11:26 UTC (permalink / raw)
  To: Ahmad Fatoum, Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team

Hello Ahmad,

Sorry for the delay :)

On 2/13/23 12:27, Ahmad Fatoum wrote:
> Hello Gatien,
> 
> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>> Hello Gatien,
>>>>
>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>> The STM32 System Bus is an internal bus on which devices are connected.
>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>> and control access to the peripherals connected on it.
>>>>>
>>>>> For more information on which peripheral is securable, please read
>>>>> the STM32MP13 reference manual.
>>>>
>>>> Diff is way too big. Please split up the alphabetic reordering into its
>>>> own commit, so actual functional changes are apparent.
>>>
>>> Ah, I see now that you are moving securable peripherals into a new bus.
>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>
>>> Does this configuration even change dynamically? Why can't you implement
>>> this binding in the bootloader and have Linux only see a DT where unavailable
>>> nodes are status = "disabled"; secure-status = "okay"?
>>>
>>> For inspiration, see barebox' device tree fixups when devices are disabled
>>> per fuse:
>>>
>>>     https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
>>>
>>> Cheers,
>>> Ahmad
>>
>> This configuration can change dynamically. The binding will be implemented in the bootloader, where the ETZPC is already implemented as a bus in our downstream.
>>
>> I find the mentionned example valid.
>>
>> Now, why is it a bus? :D
>>
>> It is the result of the discussion on the previous submission by Benjamin (Sorry for the lack of link but I saw that you participated on these threads)+ we need the bus mechanism to control whether a subnode should be probed or not. You can see it as a firewall bus.
>>
>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and propagation through bridges to the APB bus. Therefore, I find it relevant to consider it as a bus, what is your opinion?
>>
>> This patchset is a first step to the implementation of an API to control accesses dynamically.
> 
> I still don't get what's dynamic about this. Either:
> 
>    - Configuration _can_ change while Linux is running: You'll need to do
>      way more than what your current bus provides to somwhow synchronize state
>      with the secure monitor; otherwise a newly secured device will cause the driver
>      to trigger data aborts that you'll have to handle and unbind the driver.
>      (like if a USB drive is yanked out).
> 
>    - Configuration _can't_ change while Linux is running: You can have the bootloader
>      fixup the device tree and Linux need not care at all about devices that the
>      ETZPC is securing.
> 
> My understanding is that the latter is your use case, so I don't see why we
> even need the normal world to be aware of the partitioning.
> 
> Cheers,
> Ahmad
> 
What about the case where we do not have a U-Boot/bootloader to fixup 
the device tree?

On the other hand, ETZPC is a hardware firewall and is on the bus. 
Therefore, shouldn't it be represented as a bus in the file that 
describes the hardware?

Best regards,
Gatien

>>
>>>
>>>>
>>>> Thanks,
>>>> Ahmad
>>>>
>>>>>
>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>> ---
>>>>>
>>>>> No changes in V2.
>>>>>
>>>>> Changes in V3:
>>>>>      -Use appriopriate node name: bus
>>>>>
>>>>>    arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>>>    arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>    arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>    arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>    4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> index accc3824f7e9..24462a647101 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>                dma-channels = <16>;
>>>>>            };
>>>>>    -        adc_2: adc@48004000 {
>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>> -            reg = <0x48004000 0x400>;
>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>> -            clock-names = "bus", "adc";
>>>>> -            interrupt-controller;
>>>>> -            #interrupt-cells = <1>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            status = "disabled";
>>>>> -
>>>>> -            adc2: adc@0 {
>>>>> -                compatible = "st,stm32mp13-adc";
>>>>> -                #io-channel-cells = <1>;
>>>>> -                #address-cells = <1>;
>>>>> -                #size-cells = <0>;
>>>>> -                reg = <0x0>;
>>>>> -                interrupt-parent = <&adc_2>;
>>>>> -                interrupts = <0>;
>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>> -                dma-names = "rx";
>>>>> -                status = "disabled";
>>>>> -
>>>>> -                channel@13 {
>>>>> -                    reg = <13>;
>>>>> -                    label = "vrefint";
>>>>> -                };
>>>>> -                channel@14 {
>>>>> -                    reg = <14>;
>>>>> -                    label = "vddcore";
>>>>> -                };
>>>>> -                channel@16 {
>>>>> -                    reg = <16>;
>>>>> -                    label = "vddcpu";
>>>>> -                };
>>>>> -                channel@17 {
>>>>> -                    reg = <17>;
>>>>> -                    label = "vddq_ddr";
>>>>> -                };
>>>>> -            };
>>>>> -        };
>>>>> -
>>>>> -        usbotg_hs: usb@49000000 {
>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>> -            reg = <0x49000000 0x40000>;
>>>>> -            clocks = <&rcc USBO_K>;
>>>>> -            clock-names = "otg";
>>>>> -            resets = <&rcc USBO_R>;
>>>>> -            reset-names = "dwc2";
>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            g-rx-fifo-size = <512>;
>>>>> -            g-np-tx-fifo-size = <32>;
>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>> -            dr_mode = "otg";
>>>>> -            otg-rev = <0x200>;
>>>>> -            usb33d-supply = <&usb33>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        spi4: spi@4c002000 {
>>>>> -            compatible = "st,stm32h7-spi";
>>>>> -            reg = <0x4c002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SPI4_K>;
>>>>> -            resets = <&rcc SPI4_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        spi5: spi@4c003000 {
>>>>> -            compatible = "st,stm32h7-spi";
>>>>> -            reg = <0x4c003000 0x400>;
>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SPI5_K>;
>>>>> -            resets = <&rcc SPI5_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c3: i2c@4c004000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c004000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C3_K>;
>>>>> -            resets = <&rcc I2C3_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c4: i2c@4c005000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c005000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C4_K>;
>>>>> -            resets = <&rcc I2C4_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c5: i2c@4c006000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c006000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C5_K>;
>>>>> -            resets = <&rcc I2C5_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>>            rcc: rcc@50000000 {
>>>>>                compatible = "st,stm32mp13-rcc", "syscon";
>>>>>                reg = <0x50000000 0x1000>;
>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>                dma-requests = <48>;
>>>>>            };
>>>>>    -        sdmmc1: mmc@58005000 {
>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>> -            clock-names = "apb_pclk";
>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>> -            cap-sd-highspeed;
>>>>> -            cap-mmc-highspeed;
>>>>> -            max-frequency = <130000000>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        sdmmc2: mmc@58007000 {
>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>> -            clock-names = "apb_pclk";
>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>> -            cap-sd-highspeed;
>>>>> -            cap-mmc-highspeed;
>>>>> -            max-frequency = <130000000>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>>            usbh_ohci: usb@5800c000 {
>>>>>                compatible = "generic-ohci";
>>>>>                reg = <0x5800c000 0x1000>;
>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>                status = "disabled";
>>>>>            };
>>>>>    -        usbphyc: usbphyc@5a006000 {
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            #clock-cells = <0>;
>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>> -            reg = <0x5a006000 0x1000>;
>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>> -            resets = <&rcc USBPHY_R>;
>>>>> -            vdda1v1-supply = <&reg11>;
>>>>> -            vdda1v8-supply = <&reg18>;
>>>>> -            status = "disabled";
>>>>> -
>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>> -                #phy-cells = <0>;
>>>>> -                reg = <0>;
>>>>> -            };
>>>>> -
>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>> -                #phy-cells = <1>;
>>>>> -                reg = <1>;
>>>>> -            };
>>>>> -        };
>>>>> -
>>>>>            rtc: rtc@5c004000 {
>>>>>                compatible = "st,stm32mp1-rtc";
>>>>>                reg = <0x5c004000 0x400>;
>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>                };
>>>>>            };
>>>>>    +        etzpc: bus@5c007000 {
>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>> +            reg = <0x5c007000 0x400>;
>>>>> +            #address-cells = <1>;
>>>>> +            #size-cells = <1>;
>>>>> +            feature-domain-controller;
>>>>> +            #feature-domain-cells = <1>;
>>>>> +            ranges;
>>>>> +
>>>>> +            adc_2: adc@48004000 {
>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>> +                reg = <0x48004000 0x400>;
>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>> +                clock-names = "bus", "adc";
>>>>> +                interrupt-controller;
>>>>> +                #interrupt-cells = <1>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                feature-domains = <&etzpc 33>;
>>>>> +                status = "disabled";
>>>>> +
>>>>> +                adc2: adc@0 {
>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>> +                    #io-channel-cells = <1>;
>>>>> +                    #address-cells = <1>;
>>>>> +                    #size-cells = <0>;
>>>>> +                    reg = <0x0>;
>>>>> +                    interrupt-parent = <&adc_2>;
>>>>> +                    interrupts = <0>;
>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>> +                    dma-names = "rx";
>>>>> +                    status = "disabled";
>>>>> +
>>>>> +                    channel@13 {
>>>>> +                        reg = <13>;
>>>>> +                        label = "vrefint";
>>>>> +                    };
>>>>> +                    channel@14 {
>>>>> +                        reg = <14>;
>>>>> +                        label = "vddcore";
>>>>> +                    };
>>>>> +                    channel@16 {
>>>>> +                        reg = <16>;
>>>>> +                        label = "vddcpu";
>>>>> +                    };
>>>>> +                    channel@17 {
>>>>> +                        reg = <17>;
>>>>> +                        label = "vddq_ddr";
>>>>> +                    };
>>>>> +                };
>>>>> +            };
>>>>> +
>>>>> +            usbotg_hs: usb@49000000 {
>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>> +                reg = <0x49000000 0x40000>;
>>>>> +                clocks = <&rcc USBO_K>;
>>>>> +                clock-names = "otg";
>>>>> +                resets = <&rcc USBO_R>;
>>>>> +                reset-names = "dwc2";
>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                g-rx-fifo-size = <512>;
>>>>> +                g-np-tx-fifo-size = <32>;
>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>> +                dr_mode = "otg";
>>>>> +                otg-rev = <0x200>;
>>>>> +                usb33d-supply = <&usb33>;
>>>>> +                feature-domains = <&etzpc 34>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            spi4: spi@4c002000 {
>>>>> +                compatible = "st,stm32h7-spi";
>>>>> +                reg = <0x4c002000 0x400>;
>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SPI4_K>;
>>>>> +                resets = <&rcc SPI4_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                feature-domains = <&etzpc 18>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            spi5: spi@4c003000 {
>>>>> +                compatible = "st,stm32h7-spi";
>>>>> +                reg = <0x4c003000 0x400>;
>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SPI5_K>;
>>>>> +                resets = <&rcc SPI5_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                feature-domains = <&etzpc 19>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c3: i2c@4c004000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c004000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C3_K>;
>>>>> +                resets = <&rcc I2C3_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 20>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c4: i2c@4c005000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c005000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C4_K>;
>>>>> +                resets = <&rcc I2C4_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 21>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c5: i2c@4c006000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c006000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C5_K>;
>>>>> +                resets = <&rcc I2C5_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 22>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            sdmmc1: mmc@58005000 {
>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>> +                clock-names = "apb_pclk";
>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>> +                cap-sd-highspeed;
>>>>> +                cap-mmc-highspeed;
>>>>> +                max-frequency = <130000000>;
>>>>> +                feature-domains = <&etzpc 50>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            sdmmc2: mmc@58007000 {
>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>> +                clock-names = "apb_pclk";
>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>> +                cap-sd-highspeed;
>>>>> +                cap-mmc-highspeed;
>>>>> +                max-frequency = <130000000>;
>>>>> +                feature-domains = <&etzpc 51>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                #clock-cells = <0>;
>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>> +                reg = <0x5a006000 0x1000>;
>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>> +                resets = <&rcc USBPHY_R>;
>>>>> +                vdda1v1-supply = <&reg11>;
>>>>> +                vdda1v8-supply = <&reg18>;
>>>>> +                feature-domains = <&etzpc 5>;
>>>>> +                status = "disabled";
>>>>> +
>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>> +                    #phy-cells = <0>;
>>>>> +                    reg = <0>;
>>>>> +                };
>>>>> +
>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>> +                    #phy-cells = <1>;
>>>>> +                    reg = <1>;
>>>>> +                };
>>>>> +            };
>>>>> +
>>>>> +        };
>>>>> +
>>>>>            /*
>>>>>             * Break node order to solve dependency probe issue between
>>>>>             * pinctrl and exti.
>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> index df451c3c2a26..be6061552683 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>                bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>                status = "disabled";
>>>>>            };
>>>>> +    };
>>>>> +};
>>>>>    -        adc_1: adc@48003000 {
>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>> -            reg = <0x48003000 0x400>;
>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>> -            clock-names = "bus", "adc";
>>>>> -            interrupt-controller;
>>>>> -            #interrupt-cells = <1>;
>>>>> +&etzpc {
>>>>> +    adc_1: adc@48003000 {
>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>> +        reg = <0x48003000 0x400>;
>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>> +        clock-names = "bus", "adc";
>>>>> +        interrupt-controller;
>>>>> +        #interrupt-cells = <1>;
>>>>> +        #address-cells = <1>;
>>>>> +        #size-cells = <0>;
>>>>> +        feature-domains = <&etzpc 32>;
>>>>> +        status = "disabled";
>>>>> +
>>>>> +        adc1: adc@0 {
>>>>> +            compatible = "st,stm32mp13-adc";
>>>>> +            #io-channel-cells = <1>;
>>>>>                #address-cells = <1>;
>>>>>                #size-cells = <0>;
>>>>> +            reg = <0x0>;
>>>>> +            interrupt-parent = <&adc_1>;
>>>>> +            interrupts = <0>;
>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>> +            dma-names = "rx";
>>>>>                status = "disabled";
>>>>>    -            adc1: adc@0 {
>>>>> -                compatible = "st,stm32mp13-adc";
>>>>> -                #io-channel-cells = <1>;
>>>>> -                #address-cells = <1>;
>>>>> -                #size-cells = <0>;
>>>>> -                reg = <0x0>;
>>>>> -                interrupt-parent = <&adc_1>;
>>>>> -                interrupts = <0>;
>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>> -                dma-names = "rx";
>>>>> -                status = "disabled";
>>>>> -
>>>>> -                channel@18 {
>>>>> -                    reg = <18>;
>>>>> -                    label = "vrefint";
>>>>> -                };
>>>>> +            channel@18 {
>>>>> +                reg = <18>;
>>>>> +                label = "vrefint";
>>>>>                };
>>>>>            };
>>>>>        };
>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> @@ -4,15 +4,14 @@
>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>>     */
>>>>>    -/ {
>>>>> -    soc {
>>>>> -        cryp: crypto@54002000 {
>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>> -            reg = <0x54002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc CRYP1>;
>>>>> -            resets = <&rcc CRYP1_R>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> +&etzpc {
>>>>> +    cryp: crypto@54002000 {
>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>> +        reg = <0x54002000 0x400>;
>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc CRYP1>;
>>>>> +        resets = <&rcc CRYP1_R>;
>>>>> +        feature-domains = <&etzpc 42>;
>>>>> +        status = "disabled";
>>>>>        };
>>>>>    };
>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> @@ -4,15 +4,13 @@
>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>>     */
>>>>>    -/ {
>>>>> -    soc {
>>>>> -        cryp: crypto@54002000 {
>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>> -            reg = <0x54002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc CRYP1>;
>>>>> -            resets = <&rcc CRYP1_R>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> +&etzpc {
>>>>> +    cryp: crypto@54002000 {
>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>> +        reg = <0x54002000 0x400>;
>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc CRYP1>;
>>>>> +        resets = <&rcc CRYP1_R>;
>>>>> +        status = "disabled";
>>>>>        };
>>>>>    };
>>>>
>>>
>>
>> Regarding the patch itself, I can separate it in two patches.
>> 1)Introduce ETZPC
>> 2)Move peripherals under ETZPC
>>
>> Best regards,
>> Gatien
>>
> 

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-27 11:26             ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-27 11:26 UTC (permalink / raw)
  To: Ahmad Fatoum, Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team

Hello Ahmad,

Sorry for the delay :)

On 2/13/23 12:27, Ahmad Fatoum wrote:
> Hello Gatien,
> 
> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>> Hello Gatien,
>>>>
>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>> The STM32 System Bus is an internal bus on which devices are connected.
>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>> and control access to the peripherals connected on it.
>>>>>
>>>>> For more information on which peripheral is securable, please read
>>>>> the STM32MP13 reference manual.
>>>>
>>>> Diff is way too big. Please split up the alphabetic reordering into its
>>>> own commit, so actual functional changes are apparent.
>>>
>>> Ah, I see now that you are moving securable peripherals into a new bus.
>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>
>>> Does this configuration even change dynamically? Why can't you implement
>>> this binding in the bootloader and have Linux only see a DT where unavailable
>>> nodes are status = "disabled"; secure-status = "okay"?
>>>
>>> For inspiration, see barebox' device tree fixups when devices are disabled
>>> per fuse:
>>>
>>>     https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
>>>
>>> Cheers,
>>> Ahmad
>>
>> This configuration can change dynamically. The binding will be implemented in the bootloader, where the ETZPC is already implemented as a bus in our downstream.
>>
>> I find the mentionned example valid.
>>
>> Now, why is it a bus? :D
>>
>> It is the result of the discussion on the previous submission by Benjamin (Sorry for the lack of link but I saw that you participated on these threads)+ we need the bus mechanism to control whether a subnode should be probed or not. You can see it as a firewall bus.
>>
>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and propagation through bridges to the APB bus. Therefore, I find it relevant to consider it as a bus, what is your opinion?
>>
>> This patchset is a first step to the implementation of an API to control accesses dynamically.
> 
> I still don't get what's dynamic about this. Either:
> 
>    - Configuration _can_ change while Linux is running: You'll need to do
>      way more than what your current bus provides to somwhow synchronize state
>      with the secure monitor; otherwise a newly secured device will cause the driver
>      to trigger data aborts that you'll have to handle and unbind the driver.
>      (like if a USB drive is yanked out).
> 
>    - Configuration _can't_ change while Linux is running: You can have the bootloader
>      fixup the device tree and Linux need not care at all about devices that the
>      ETZPC is securing.
> 
> My understanding is that the latter is your use case, so I don't see why we
> even need the normal world to be aware of the partitioning.
> 
> Cheers,
> Ahmad
> 
What about the case where we do not have a U-Boot/bootloader to fixup 
the device tree?

On the other hand, ETZPC is a hardware firewall and is on the bus. 
Therefore, shouldn't it be represented as a bus in the file that 
describes the hardware?

Best regards,
Gatien

>>
>>>
>>>>
>>>> Thanks,
>>>> Ahmad
>>>>
>>>>>
>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>> ---
>>>>>
>>>>> No changes in V2.
>>>>>
>>>>> Changes in V3:
>>>>>      -Use appriopriate node name: bus
>>>>>
>>>>>    arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>>>    arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>    arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>    arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>    4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> index accc3824f7e9..24462a647101 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>                dma-channels = <16>;
>>>>>            };
>>>>>    -        adc_2: adc@48004000 {
>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>> -            reg = <0x48004000 0x400>;
>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>> -            clock-names = "bus", "adc";
>>>>> -            interrupt-controller;
>>>>> -            #interrupt-cells = <1>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            status = "disabled";
>>>>> -
>>>>> -            adc2: adc@0 {
>>>>> -                compatible = "st,stm32mp13-adc";
>>>>> -                #io-channel-cells = <1>;
>>>>> -                #address-cells = <1>;
>>>>> -                #size-cells = <0>;
>>>>> -                reg = <0x0>;
>>>>> -                interrupt-parent = <&adc_2>;
>>>>> -                interrupts = <0>;
>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>> -                dma-names = "rx";
>>>>> -                status = "disabled";
>>>>> -
>>>>> -                channel@13 {
>>>>> -                    reg = <13>;
>>>>> -                    label = "vrefint";
>>>>> -                };
>>>>> -                channel@14 {
>>>>> -                    reg = <14>;
>>>>> -                    label = "vddcore";
>>>>> -                };
>>>>> -                channel@16 {
>>>>> -                    reg = <16>;
>>>>> -                    label = "vddcpu";
>>>>> -                };
>>>>> -                channel@17 {
>>>>> -                    reg = <17>;
>>>>> -                    label = "vddq_ddr";
>>>>> -                };
>>>>> -            };
>>>>> -        };
>>>>> -
>>>>> -        usbotg_hs: usb@49000000 {
>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>> -            reg = <0x49000000 0x40000>;
>>>>> -            clocks = <&rcc USBO_K>;
>>>>> -            clock-names = "otg";
>>>>> -            resets = <&rcc USBO_R>;
>>>>> -            reset-names = "dwc2";
>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            g-rx-fifo-size = <512>;
>>>>> -            g-np-tx-fifo-size = <32>;
>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>> -            dr_mode = "otg";
>>>>> -            otg-rev = <0x200>;
>>>>> -            usb33d-supply = <&usb33>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        spi4: spi@4c002000 {
>>>>> -            compatible = "st,stm32h7-spi";
>>>>> -            reg = <0x4c002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SPI4_K>;
>>>>> -            resets = <&rcc SPI4_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        spi5: spi@4c003000 {
>>>>> -            compatible = "st,stm32h7-spi";
>>>>> -            reg = <0x4c003000 0x400>;
>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SPI5_K>;
>>>>> -            resets = <&rcc SPI5_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c3: i2c@4c004000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c004000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C3_K>;
>>>>> -            resets = <&rcc I2C3_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c4: i2c@4c005000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c005000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C4_K>;
>>>>> -            resets = <&rcc I2C4_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c5: i2c@4c006000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c006000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C5_K>;
>>>>> -            resets = <&rcc I2C5_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>>            rcc: rcc@50000000 {
>>>>>                compatible = "st,stm32mp13-rcc", "syscon";
>>>>>                reg = <0x50000000 0x1000>;
>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>                dma-requests = <48>;
>>>>>            };
>>>>>    -        sdmmc1: mmc@58005000 {
>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>> -            clock-names = "apb_pclk";
>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>> -            cap-sd-highspeed;
>>>>> -            cap-mmc-highspeed;
>>>>> -            max-frequency = <130000000>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        sdmmc2: mmc@58007000 {
>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>> -            clock-names = "apb_pclk";
>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>> -            cap-sd-highspeed;
>>>>> -            cap-mmc-highspeed;
>>>>> -            max-frequency = <130000000>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>>            usbh_ohci: usb@5800c000 {
>>>>>                compatible = "generic-ohci";
>>>>>                reg = <0x5800c000 0x1000>;
>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>                status = "disabled";
>>>>>            };
>>>>>    -        usbphyc: usbphyc@5a006000 {
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            #clock-cells = <0>;
>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>> -            reg = <0x5a006000 0x1000>;
>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>> -            resets = <&rcc USBPHY_R>;
>>>>> -            vdda1v1-supply = <&reg11>;
>>>>> -            vdda1v8-supply = <&reg18>;
>>>>> -            status = "disabled";
>>>>> -
>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>> -                #phy-cells = <0>;
>>>>> -                reg = <0>;
>>>>> -            };
>>>>> -
>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>> -                #phy-cells = <1>;
>>>>> -                reg = <1>;
>>>>> -            };
>>>>> -        };
>>>>> -
>>>>>            rtc: rtc@5c004000 {
>>>>>                compatible = "st,stm32mp1-rtc";
>>>>>                reg = <0x5c004000 0x400>;
>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>                };
>>>>>            };
>>>>>    +        etzpc: bus@5c007000 {
>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>> +            reg = <0x5c007000 0x400>;
>>>>> +            #address-cells = <1>;
>>>>> +            #size-cells = <1>;
>>>>> +            feature-domain-controller;
>>>>> +            #feature-domain-cells = <1>;
>>>>> +            ranges;
>>>>> +
>>>>> +            adc_2: adc@48004000 {
>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>> +                reg = <0x48004000 0x400>;
>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>> +                clock-names = "bus", "adc";
>>>>> +                interrupt-controller;
>>>>> +                #interrupt-cells = <1>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                feature-domains = <&etzpc 33>;
>>>>> +                status = "disabled";
>>>>> +
>>>>> +                adc2: adc@0 {
>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>> +                    #io-channel-cells = <1>;
>>>>> +                    #address-cells = <1>;
>>>>> +                    #size-cells = <0>;
>>>>> +                    reg = <0x0>;
>>>>> +                    interrupt-parent = <&adc_2>;
>>>>> +                    interrupts = <0>;
>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>> +                    dma-names = "rx";
>>>>> +                    status = "disabled";
>>>>> +
>>>>> +                    channel@13 {
>>>>> +                        reg = <13>;
>>>>> +                        label = "vrefint";
>>>>> +                    };
>>>>> +                    channel@14 {
>>>>> +                        reg = <14>;
>>>>> +                        label = "vddcore";
>>>>> +                    };
>>>>> +                    channel@16 {
>>>>> +                        reg = <16>;
>>>>> +                        label = "vddcpu";
>>>>> +                    };
>>>>> +                    channel@17 {
>>>>> +                        reg = <17>;
>>>>> +                        label = "vddq_ddr";
>>>>> +                    };
>>>>> +                };
>>>>> +            };
>>>>> +
>>>>> +            usbotg_hs: usb@49000000 {
>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>> +                reg = <0x49000000 0x40000>;
>>>>> +                clocks = <&rcc USBO_K>;
>>>>> +                clock-names = "otg";
>>>>> +                resets = <&rcc USBO_R>;
>>>>> +                reset-names = "dwc2";
>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                g-rx-fifo-size = <512>;
>>>>> +                g-np-tx-fifo-size = <32>;
>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>> +                dr_mode = "otg";
>>>>> +                otg-rev = <0x200>;
>>>>> +                usb33d-supply = <&usb33>;
>>>>> +                feature-domains = <&etzpc 34>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            spi4: spi@4c002000 {
>>>>> +                compatible = "st,stm32h7-spi";
>>>>> +                reg = <0x4c002000 0x400>;
>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SPI4_K>;
>>>>> +                resets = <&rcc SPI4_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                feature-domains = <&etzpc 18>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            spi5: spi@4c003000 {
>>>>> +                compatible = "st,stm32h7-spi";
>>>>> +                reg = <0x4c003000 0x400>;
>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SPI5_K>;
>>>>> +                resets = <&rcc SPI5_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                feature-domains = <&etzpc 19>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c3: i2c@4c004000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c004000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C3_K>;
>>>>> +                resets = <&rcc I2C3_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 20>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c4: i2c@4c005000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c005000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C4_K>;
>>>>> +                resets = <&rcc I2C4_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 21>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c5: i2c@4c006000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c006000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C5_K>;
>>>>> +                resets = <&rcc I2C5_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 22>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            sdmmc1: mmc@58005000 {
>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>> +                clock-names = "apb_pclk";
>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>> +                cap-sd-highspeed;
>>>>> +                cap-mmc-highspeed;
>>>>> +                max-frequency = <130000000>;
>>>>> +                feature-domains = <&etzpc 50>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            sdmmc2: mmc@58007000 {
>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>> +                clock-names = "apb_pclk";
>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>> +                cap-sd-highspeed;
>>>>> +                cap-mmc-highspeed;
>>>>> +                max-frequency = <130000000>;
>>>>> +                feature-domains = <&etzpc 51>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                #clock-cells = <0>;
>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>> +                reg = <0x5a006000 0x1000>;
>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>> +                resets = <&rcc USBPHY_R>;
>>>>> +                vdda1v1-supply = <&reg11>;
>>>>> +                vdda1v8-supply = <&reg18>;
>>>>> +                feature-domains = <&etzpc 5>;
>>>>> +                status = "disabled";
>>>>> +
>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>> +                    #phy-cells = <0>;
>>>>> +                    reg = <0>;
>>>>> +                };
>>>>> +
>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>> +                    #phy-cells = <1>;
>>>>> +                    reg = <1>;
>>>>> +                };
>>>>> +            };
>>>>> +
>>>>> +        };
>>>>> +
>>>>>            /*
>>>>>             * Break node order to solve dependency probe issue between
>>>>>             * pinctrl and exti.
>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> index df451c3c2a26..be6061552683 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>                bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>                status = "disabled";
>>>>>            };
>>>>> +    };
>>>>> +};
>>>>>    -        adc_1: adc@48003000 {
>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>> -            reg = <0x48003000 0x400>;
>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>> -            clock-names = "bus", "adc";
>>>>> -            interrupt-controller;
>>>>> -            #interrupt-cells = <1>;
>>>>> +&etzpc {
>>>>> +    adc_1: adc@48003000 {
>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>> +        reg = <0x48003000 0x400>;
>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>> +        clock-names = "bus", "adc";
>>>>> +        interrupt-controller;
>>>>> +        #interrupt-cells = <1>;
>>>>> +        #address-cells = <1>;
>>>>> +        #size-cells = <0>;
>>>>> +        feature-domains = <&etzpc 32>;
>>>>> +        status = "disabled";
>>>>> +
>>>>> +        adc1: adc@0 {
>>>>> +            compatible = "st,stm32mp13-adc";
>>>>> +            #io-channel-cells = <1>;
>>>>>                #address-cells = <1>;
>>>>>                #size-cells = <0>;
>>>>> +            reg = <0x0>;
>>>>> +            interrupt-parent = <&adc_1>;
>>>>> +            interrupts = <0>;
>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>> +            dma-names = "rx";
>>>>>                status = "disabled";
>>>>>    -            adc1: adc@0 {
>>>>> -                compatible = "st,stm32mp13-adc";
>>>>> -                #io-channel-cells = <1>;
>>>>> -                #address-cells = <1>;
>>>>> -                #size-cells = <0>;
>>>>> -                reg = <0x0>;
>>>>> -                interrupt-parent = <&adc_1>;
>>>>> -                interrupts = <0>;
>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>> -                dma-names = "rx";
>>>>> -                status = "disabled";
>>>>> -
>>>>> -                channel@18 {
>>>>> -                    reg = <18>;
>>>>> -                    label = "vrefint";
>>>>> -                };
>>>>> +            channel@18 {
>>>>> +                reg = <18>;
>>>>> +                label = "vrefint";
>>>>>                };
>>>>>            };
>>>>>        };
>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> @@ -4,15 +4,14 @@
>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>>     */
>>>>>    -/ {
>>>>> -    soc {
>>>>> -        cryp: crypto@54002000 {
>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>> -            reg = <0x54002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc CRYP1>;
>>>>> -            resets = <&rcc CRYP1_R>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> +&etzpc {
>>>>> +    cryp: crypto@54002000 {
>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>> +        reg = <0x54002000 0x400>;
>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc CRYP1>;
>>>>> +        resets = <&rcc CRYP1_R>;
>>>>> +        feature-domains = <&etzpc 42>;
>>>>> +        status = "disabled";
>>>>>        };
>>>>>    };
>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> @@ -4,15 +4,13 @@
>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>>     */
>>>>>    -/ {
>>>>> -    soc {
>>>>> -        cryp: crypto@54002000 {
>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>> -            reg = <0x54002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc CRYP1>;
>>>>> -            resets = <&rcc CRYP1_R>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> +&etzpc {
>>>>> +    cryp: crypto@54002000 {
>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>> +        reg = <0x54002000 0x400>;
>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc CRYP1>;
>>>>> +        resets = <&rcc CRYP1_R>;
>>>>> +        status = "disabled";
>>>>>        };
>>>>>    };
>>>>
>>>
>>
>> Regarding the patch itself, I can separate it in two patches.
>> 1)Introduce ETZPC
>> 2)Move peripherals under ETZPC
>>
>> Best regards,
>> Gatien
>>
> 

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-27 11:26             ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-27 11:26 UTC (permalink / raw)
  To: Ahmad Fatoum, Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team

Hello Ahmad,

Sorry for the delay :)

On 2/13/23 12:27, Ahmad Fatoum wrote:
> Hello Gatien,
> 
> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>> Hello Gatien,
>>>>
>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>> The STM32 System Bus is an internal bus on which devices are connected.
>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>> and control access to the peripherals connected on it.
>>>>>
>>>>> For more information on which peripheral is securable, please read
>>>>> the STM32MP13 reference manual.
>>>>
>>>> Diff is way too big. Please split up the alphabetic reordering into its
>>>> own commit, so actual functional changes are apparent.
>>>
>>> Ah, I see now that you are moving securable peripherals into a new bus.
>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>
>>> Does this configuration even change dynamically? Why can't you implement
>>> this binding in the bootloader and have Linux only see a DT where unavailable
>>> nodes are status = "disabled"; secure-status = "okay"?
>>>
>>> For inspiration, see barebox' device tree fixups when devices are disabled
>>> per fuse:
>>>
>>>     https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
>>>
>>> Cheers,
>>> Ahmad
>>
>> This configuration can change dynamically. The binding will be implemented in the bootloader, where the ETZPC is already implemented as a bus in our downstream.
>>
>> I find the mentionned example valid.
>>
>> Now, why is it a bus? :D
>>
>> It is the result of the discussion on the previous submission by Benjamin (Sorry for the lack of link but I saw that you participated on these threads)+ we need the bus mechanism to control whether a subnode should be probed or not. You can see it as a firewall bus.
>>
>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and propagation through bridges to the APB bus. Therefore, I find it relevant to consider it as a bus, what is your opinion?
>>
>> This patchset is a first step to the implementation of an API to control accesses dynamically.
> 
> I still don't get what's dynamic about this. Either:
> 
>    - Configuration _can_ change while Linux is running: You'll need to do
>      way more than what your current bus provides to somwhow synchronize state
>      with the secure monitor; otherwise a newly secured device will cause the driver
>      to trigger data aborts that you'll have to handle and unbind the driver.
>      (like if a USB drive is yanked out).
> 
>    - Configuration _can't_ change while Linux is running: You can have the bootloader
>      fixup the device tree and Linux need not care at all about devices that the
>      ETZPC is securing.
> 
> My understanding is that the latter is your use case, so I don't see why we
> even need the normal world to be aware of the partitioning.
> 
> Cheers,
> Ahmad
> 
What about the case where we do not have a U-Boot/bootloader to fixup 
the device tree?

On the other hand, ETZPC is a hardware firewall and is on the bus. 
Therefore, shouldn't it be represented as a bus in the file that 
describes the hardware?

Best regards,
Gatien

>>
>>>
>>>>
>>>> Thanks,
>>>> Ahmad
>>>>
>>>>>
>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>> ---
>>>>>
>>>>> No changes in V2.
>>>>>
>>>>> Changes in V3:
>>>>>      -Use appriopriate node name: bus
>>>>>
>>>>>    arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>>>    arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>    arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>    arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>    4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> index accc3824f7e9..24462a647101 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>                dma-channels = <16>;
>>>>>            };
>>>>>    -        adc_2: adc@48004000 {
>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>> -            reg = <0x48004000 0x400>;
>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>> -            clock-names = "bus", "adc";
>>>>> -            interrupt-controller;
>>>>> -            #interrupt-cells = <1>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            status = "disabled";
>>>>> -
>>>>> -            adc2: adc@0 {
>>>>> -                compatible = "st,stm32mp13-adc";
>>>>> -                #io-channel-cells = <1>;
>>>>> -                #address-cells = <1>;
>>>>> -                #size-cells = <0>;
>>>>> -                reg = <0x0>;
>>>>> -                interrupt-parent = <&adc_2>;
>>>>> -                interrupts = <0>;
>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>> -                dma-names = "rx";
>>>>> -                status = "disabled";
>>>>> -
>>>>> -                channel@13 {
>>>>> -                    reg = <13>;
>>>>> -                    label = "vrefint";
>>>>> -                };
>>>>> -                channel@14 {
>>>>> -                    reg = <14>;
>>>>> -                    label = "vddcore";
>>>>> -                };
>>>>> -                channel@16 {
>>>>> -                    reg = <16>;
>>>>> -                    label = "vddcpu";
>>>>> -                };
>>>>> -                channel@17 {
>>>>> -                    reg = <17>;
>>>>> -                    label = "vddq_ddr";
>>>>> -                };
>>>>> -            };
>>>>> -        };
>>>>> -
>>>>> -        usbotg_hs: usb@49000000 {
>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>> -            reg = <0x49000000 0x40000>;
>>>>> -            clocks = <&rcc USBO_K>;
>>>>> -            clock-names = "otg";
>>>>> -            resets = <&rcc USBO_R>;
>>>>> -            reset-names = "dwc2";
>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            g-rx-fifo-size = <512>;
>>>>> -            g-np-tx-fifo-size = <32>;
>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>> -            dr_mode = "otg";
>>>>> -            otg-rev = <0x200>;
>>>>> -            usb33d-supply = <&usb33>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        spi4: spi@4c002000 {
>>>>> -            compatible = "st,stm32h7-spi";
>>>>> -            reg = <0x4c002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SPI4_K>;
>>>>> -            resets = <&rcc SPI4_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        spi5: spi@4c003000 {
>>>>> -            compatible = "st,stm32h7-spi";
>>>>> -            reg = <0x4c003000 0x400>;
>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SPI5_K>;
>>>>> -            resets = <&rcc SPI5_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c3: i2c@4c004000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c004000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C3_K>;
>>>>> -            resets = <&rcc I2C3_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c4: i2c@4c005000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c005000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C4_K>;
>>>>> -            resets = <&rcc I2C4_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c5: i2c@4c006000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c006000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C5_K>;
>>>>> -            resets = <&rcc I2C5_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>>            rcc: rcc@50000000 {
>>>>>                compatible = "st,stm32mp13-rcc", "syscon";
>>>>>                reg = <0x50000000 0x1000>;
>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>                dma-requests = <48>;
>>>>>            };
>>>>>    -        sdmmc1: mmc@58005000 {
>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>> -            clock-names = "apb_pclk";
>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>> -            cap-sd-highspeed;
>>>>> -            cap-mmc-highspeed;
>>>>> -            max-frequency = <130000000>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        sdmmc2: mmc@58007000 {
>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>> -            clock-names = "apb_pclk";
>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>> -            cap-sd-highspeed;
>>>>> -            cap-mmc-highspeed;
>>>>> -            max-frequency = <130000000>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>>            usbh_ohci: usb@5800c000 {
>>>>>                compatible = "generic-ohci";
>>>>>                reg = <0x5800c000 0x1000>;
>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>                status = "disabled";
>>>>>            };
>>>>>    -        usbphyc: usbphyc@5a006000 {
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            #clock-cells = <0>;
>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>> -            reg = <0x5a006000 0x1000>;
>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>> -            resets = <&rcc USBPHY_R>;
>>>>> -            vdda1v1-supply = <&reg11>;
>>>>> -            vdda1v8-supply = <&reg18>;
>>>>> -            status = "disabled";
>>>>> -
>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>> -                #phy-cells = <0>;
>>>>> -                reg = <0>;
>>>>> -            };
>>>>> -
>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>> -                #phy-cells = <1>;
>>>>> -                reg = <1>;
>>>>> -            };
>>>>> -        };
>>>>> -
>>>>>            rtc: rtc@5c004000 {
>>>>>                compatible = "st,stm32mp1-rtc";
>>>>>                reg = <0x5c004000 0x400>;
>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>                };
>>>>>            };
>>>>>    +        etzpc: bus@5c007000 {
>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>> +            reg = <0x5c007000 0x400>;
>>>>> +            #address-cells = <1>;
>>>>> +            #size-cells = <1>;
>>>>> +            feature-domain-controller;
>>>>> +            #feature-domain-cells = <1>;
>>>>> +            ranges;
>>>>> +
>>>>> +            adc_2: adc@48004000 {
>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>> +                reg = <0x48004000 0x400>;
>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>> +                clock-names = "bus", "adc";
>>>>> +                interrupt-controller;
>>>>> +                #interrupt-cells = <1>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                feature-domains = <&etzpc 33>;
>>>>> +                status = "disabled";
>>>>> +
>>>>> +                adc2: adc@0 {
>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>> +                    #io-channel-cells = <1>;
>>>>> +                    #address-cells = <1>;
>>>>> +                    #size-cells = <0>;
>>>>> +                    reg = <0x0>;
>>>>> +                    interrupt-parent = <&adc_2>;
>>>>> +                    interrupts = <0>;
>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>> +                    dma-names = "rx";
>>>>> +                    status = "disabled";
>>>>> +
>>>>> +                    channel@13 {
>>>>> +                        reg = <13>;
>>>>> +                        label = "vrefint";
>>>>> +                    };
>>>>> +                    channel@14 {
>>>>> +                        reg = <14>;
>>>>> +                        label = "vddcore";
>>>>> +                    };
>>>>> +                    channel@16 {
>>>>> +                        reg = <16>;
>>>>> +                        label = "vddcpu";
>>>>> +                    };
>>>>> +                    channel@17 {
>>>>> +                        reg = <17>;
>>>>> +                        label = "vddq_ddr";
>>>>> +                    };
>>>>> +                };
>>>>> +            };
>>>>> +
>>>>> +            usbotg_hs: usb@49000000 {
>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>> +                reg = <0x49000000 0x40000>;
>>>>> +                clocks = <&rcc USBO_K>;
>>>>> +                clock-names = "otg";
>>>>> +                resets = <&rcc USBO_R>;
>>>>> +                reset-names = "dwc2";
>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                g-rx-fifo-size = <512>;
>>>>> +                g-np-tx-fifo-size = <32>;
>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>> +                dr_mode = "otg";
>>>>> +                otg-rev = <0x200>;
>>>>> +                usb33d-supply = <&usb33>;
>>>>> +                feature-domains = <&etzpc 34>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            spi4: spi@4c002000 {
>>>>> +                compatible = "st,stm32h7-spi";
>>>>> +                reg = <0x4c002000 0x400>;
>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SPI4_K>;
>>>>> +                resets = <&rcc SPI4_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                feature-domains = <&etzpc 18>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            spi5: spi@4c003000 {
>>>>> +                compatible = "st,stm32h7-spi";
>>>>> +                reg = <0x4c003000 0x400>;
>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SPI5_K>;
>>>>> +                resets = <&rcc SPI5_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                feature-domains = <&etzpc 19>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c3: i2c@4c004000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c004000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C3_K>;
>>>>> +                resets = <&rcc I2C3_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 20>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c4: i2c@4c005000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c005000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C4_K>;
>>>>> +                resets = <&rcc I2C4_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 21>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c5: i2c@4c006000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c006000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C5_K>;
>>>>> +                resets = <&rcc I2C5_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 22>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            sdmmc1: mmc@58005000 {
>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>> +                clock-names = "apb_pclk";
>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>> +                cap-sd-highspeed;
>>>>> +                cap-mmc-highspeed;
>>>>> +                max-frequency = <130000000>;
>>>>> +                feature-domains = <&etzpc 50>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            sdmmc2: mmc@58007000 {
>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>> +                clock-names = "apb_pclk";
>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>> +                cap-sd-highspeed;
>>>>> +                cap-mmc-highspeed;
>>>>> +                max-frequency = <130000000>;
>>>>> +                feature-domains = <&etzpc 51>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                #clock-cells = <0>;
>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>> +                reg = <0x5a006000 0x1000>;
>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>> +                resets = <&rcc USBPHY_R>;
>>>>> +                vdda1v1-supply = <&reg11>;
>>>>> +                vdda1v8-supply = <&reg18>;
>>>>> +                feature-domains = <&etzpc 5>;
>>>>> +                status = "disabled";
>>>>> +
>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>> +                    #phy-cells = <0>;
>>>>> +                    reg = <0>;
>>>>> +                };
>>>>> +
>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>> +                    #phy-cells = <1>;
>>>>> +                    reg = <1>;
>>>>> +                };
>>>>> +            };
>>>>> +
>>>>> +        };
>>>>> +
>>>>>            /*
>>>>>             * Break node order to solve dependency probe issue between
>>>>>             * pinctrl and exti.
>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> index df451c3c2a26..be6061552683 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>                bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>                status = "disabled";
>>>>>            };
>>>>> +    };
>>>>> +};
>>>>>    -        adc_1: adc@48003000 {
>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>> -            reg = <0x48003000 0x400>;
>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>> -            clock-names = "bus", "adc";
>>>>> -            interrupt-controller;
>>>>> -            #interrupt-cells = <1>;
>>>>> +&etzpc {
>>>>> +    adc_1: adc@48003000 {
>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>> +        reg = <0x48003000 0x400>;
>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>> +        clock-names = "bus", "adc";
>>>>> +        interrupt-controller;
>>>>> +        #interrupt-cells = <1>;
>>>>> +        #address-cells = <1>;
>>>>> +        #size-cells = <0>;
>>>>> +        feature-domains = <&etzpc 32>;
>>>>> +        status = "disabled";
>>>>> +
>>>>> +        adc1: adc@0 {
>>>>> +            compatible = "st,stm32mp13-adc";
>>>>> +            #io-channel-cells = <1>;
>>>>>                #address-cells = <1>;
>>>>>                #size-cells = <0>;
>>>>> +            reg = <0x0>;
>>>>> +            interrupt-parent = <&adc_1>;
>>>>> +            interrupts = <0>;
>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>> +            dma-names = "rx";
>>>>>                status = "disabled";
>>>>>    -            adc1: adc@0 {
>>>>> -                compatible = "st,stm32mp13-adc";
>>>>> -                #io-channel-cells = <1>;
>>>>> -                #address-cells = <1>;
>>>>> -                #size-cells = <0>;
>>>>> -                reg = <0x0>;
>>>>> -                interrupt-parent = <&adc_1>;
>>>>> -                interrupts = <0>;
>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>> -                dma-names = "rx";
>>>>> -                status = "disabled";
>>>>> -
>>>>> -                channel@18 {
>>>>> -                    reg = <18>;
>>>>> -                    label = "vrefint";
>>>>> -                };
>>>>> +            channel@18 {
>>>>> +                reg = <18>;
>>>>> +                label = "vrefint";
>>>>>                };
>>>>>            };
>>>>>        };
>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> @@ -4,15 +4,14 @@
>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>>     */
>>>>>    -/ {
>>>>> -    soc {
>>>>> -        cryp: crypto@54002000 {
>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>> -            reg = <0x54002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc CRYP1>;
>>>>> -            resets = <&rcc CRYP1_R>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> +&etzpc {
>>>>> +    cryp: crypto@54002000 {
>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>> +        reg = <0x54002000 0x400>;
>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc CRYP1>;
>>>>> +        resets = <&rcc CRYP1_R>;
>>>>> +        feature-domains = <&etzpc 42>;
>>>>> +        status = "disabled";
>>>>>        };
>>>>>    };
>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> @@ -4,15 +4,13 @@
>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>>     */
>>>>>    -/ {
>>>>> -    soc {
>>>>> -        cryp: crypto@54002000 {
>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>> -            reg = <0x54002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc CRYP1>;
>>>>> -            resets = <&rcc CRYP1_R>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> +&etzpc {
>>>>> +    cryp: crypto@54002000 {
>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>> +        reg = <0x54002000 0x400>;
>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc CRYP1>;
>>>>> +        resets = <&rcc CRYP1_R>;
>>>>> +        status = "disabled";
>>>>>        };
>>>>>    };
>>>>
>>>
>>
>> Regarding the patch itself, I can separate it in two patches.
>> 1)Introduce ETZPC
>> 2)Move peripherals under ETZPC
>>
>> Best regards,
>> Gatien
>>
> 

-- 
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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-02-27 11:26             ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-02-27 11:26 UTC (permalink / raw)
  To: Ahmad Fatoum, Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team

Hello Ahmad,

Sorry for the delay :)

On 2/13/23 12:27, Ahmad Fatoum wrote:
> Hello Gatien,
> 
> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>> Hello Gatien,
>>>>
>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>> The STM32 System Bus is an internal bus on which devices are connected.
>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>> and control access to the peripherals connected on it.
>>>>>
>>>>> For more information on which peripheral is securable, please read
>>>>> the STM32MP13 reference manual.
>>>>
>>>> Diff is way too big. Please split up the alphabetic reordering into its
>>>> own commit, so actual functional changes are apparent.
>>>
>>> Ah, I see now that you are moving securable peripherals into a new bus.
>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>
>>> Does this configuration even change dynamically? Why can't you implement
>>> this binding in the bootloader and have Linux only see a DT where unavailable
>>> nodes are status = "disabled"; secure-status = "okay"?
>>>
>>> For inspiration, see barebox' device tree fixups when devices are disabled
>>> per fuse:
>>>
>>>     https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c#L122
>>>
>>> Cheers,
>>> Ahmad
>>
>> This configuration can change dynamically. The binding will be implemented in the bootloader, where the ETZPC is already implemented as a bus in our downstream.
>>
>> I find the mentionned example valid.
>>
>> Now, why is it a bus? :D
>>
>> It is the result of the discussion on the previous submission by Benjamin (Sorry for the lack of link but I saw that you participated on these threads)+ we need the bus mechanism to control whether a subnode should be probed or not. You can see it as a firewall bus.
>>
>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and propagation through bridges to the APB bus. Therefore, I find it relevant to consider it as a bus, what is your opinion?
>>
>> This patchset is a first step to the implementation of an API to control accesses dynamically.
> 
> I still don't get what's dynamic about this. Either:
> 
>    - Configuration _can_ change while Linux is running: You'll need to do
>      way more than what your current bus provides to somwhow synchronize state
>      with the secure monitor; otherwise a newly secured device will cause the driver
>      to trigger data aborts that you'll have to handle and unbind the driver.
>      (like if a USB drive is yanked out).
> 
>    - Configuration _can't_ change while Linux is running: You can have the bootloader
>      fixup the device tree and Linux need not care at all about devices that the
>      ETZPC is securing.
> 
> My understanding is that the latter is your use case, so I don't see why we
> even need the normal world to be aware of the partitioning.
> 
> Cheers,
> Ahmad
> 
What about the case where we do not have a U-Boot/bootloader to fixup 
the device tree?

On the other hand, ETZPC is a hardware firewall and is on the bus. 
Therefore, shouldn't it be represented as a bus in the file that 
describes the hardware?

Best regards,
Gatien

>>
>>>
>>>>
>>>> Thanks,
>>>> Ahmad
>>>>
>>>>>
>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>> ---
>>>>>
>>>>> No changes in V2.
>>>>>
>>>>> Changes in V3:
>>>>>      -Use appriopriate node name: bus
>>>>>
>>>>>    arch/arm/boot/dts/stm32mp131.dtsi  | 407 +++++++++++++++--------------
>>>>>    arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>    arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>    arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>    4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> index accc3824f7e9..24462a647101 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>                dma-channels = <16>;
>>>>>            };
>>>>>    -        adc_2: adc@48004000 {
>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>> -            reg = <0x48004000 0x400>;
>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>> -            clock-names = "bus", "adc";
>>>>> -            interrupt-controller;
>>>>> -            #interrupt-cells = <1>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            status = "disabled";
>>>>> -
>>>>> -            adc2: adc@0 {
>>>>> -                compatible = "st,stm32mp13-adc";
>>>>> -                #io-channel-cells = <1>;
>>>>> -                #address-cells = <1>;
>>>>> -                #size-cells = <0>;
>>>>> -                reg = <0x0>;
>>>>> -                interrupt-parent = <&adc_2>;
>>>>> -                interrupts = <0>;
>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>> -                dma-names = "rx";
>>>>> -                status = "disabled";
>>>>> -
>>>>> -                channel@13 {
>>>>> -                    reg = <13>;
>>>>> -                    label = "vrefint";
>>>>> -                };
>>>>> -                channel@14 {
>>>>> -                    reg = <14>;
>>>>> -                    label = "vddcore";
>>>>> -                };
>>>>> -                channel@16 {
>>>>> -                    reg = <16>;
>>>>> -                    label = "vddcpu";
>>>>> -                };
>>>>> -                channel@17 {
>>>>> -                    reg = <17>;
>>>>> -                    label = "vddq_ddr";
>>>>> -                };
>>>>> -            };
>>>>> -        };
>>>>> -
>>>>> -        usbotg_hs: usb@49000000 {
>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>> -            reg = <0x49000000 0x40000>;
>>>>> -            clocks = <&rcc USBO_K>;
>>>>> -            clock-names = "otg";
>>>>> -            resets = <&rcc USBO_R>;
>>>>> -            reset-names = "dwc2";
>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            g-rx-fifo-size = <512>;
>>>>> -            g-np-tx-fifo-size = <32>;
>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>> -            dr_mode = "otg";
>>>>> -            otg-rev = <0x200>;
>>>>> -            usb33d-supply = <&usb33>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        spi4: spi@4c002000 {
>>>>> -            compatible = "st,stm32h7-spi";
>>>>> -            reg = <0x4c002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SPI4_K>;
>>>>> -            resets = <&rcc SPI4_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        spi5: spi@4c003000 {
>>>>> -            compatible = "st,stm32h7-spi";
>>>>> -            reg = <0x4c003000 0x400>;
>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SPI5_K>;
>>>>> -            resets = <&rcc SPI5_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c3: i2c@4c004000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c004000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C3_K>;
>>>>> -            resets = <&rcc I2C3_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c4: i2c@4c005000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c005000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C4_K>;
>>>>> -            resets = <&rcc I2C4_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        i2c5: i2c@4c006000 {
>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>> -            reg = <0x4c006000 0x400>;
>>>>> -            interrupt-names = "event", "error";
>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc I2C5_K>;
>>>>> -            resets = <&rcc I2C5_R>;
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>> -            dma-names = "rx", "tx";
>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>> -            i2c-analog-filter;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>>            rcc: rcc@50000000 {
>>>>>                compatible = "st,stm32mp13-rcc", "syscon";
>>>>>                reg = <0x50000000 0x1000>;
>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>                dma-requests = <48>;
>>>>>            };
>>>>>    -        sdmmc1: mmc@58005000 {
>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>> -            clock-names = "apb_pclk";
>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>> -            cap-sd-highspeed;
>>>>> -            cap-mmc-highspeed;
>>>>> -            max-frequency = <130000000>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>> -        sdmmc2: mmc@58007000 {
>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>> -            clock-names = "apb_pclk";
>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>> -            cap-sd-highspeed;
>>>>> -            cap-mmc-highspeed;
>>>>> -            max-frequency = <130000000>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> -
>>>>>            usbh_ohci: usb@5800c000 {
>>>>>                compatible = "generic-ohci";
>>>>>                reg = <0x5800c000 0x1000>;
>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>                status = "disabled";
>>>>>            };
>>>>>    -        usbphyc: usbphyc@5a006000 {
>>>>> -            #address-cells = <1>;
>>>>> -            #size-cells = <0>;
>>>>> -            #clock-cells = <0>;
>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>> -            reg = <0x5a006000 0x1000>;
>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>> -            resets = <&rcc USBPHY_R>;
>>>>> -            vdda1v1-supply = <&reg11>;
>>>>> -            vdda1v8-supply = <&reg18>;
>>>>> -            status = "disabled";
>>>>> -
>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>> -                #phy-cells = <0>;
>>>>> -                reg = <0>;
>>>>> -            };
>>>>> -
>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>> -                #phy-cells = <1>;
>>>>> -                reg = <1>;
>>>>> -            };
>>>>> -        };
>>>>> -
>>>>>            rtc: rtc@5c004000 {
>>>>>                compatible = "st,stm32mp1-rtc";
>>>>>                reg = <0x5c004000 0x400>;
>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>                };
>>>>>            };
>>>>>    +        etzpc: bus@5c007000 {
>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>> +            reg = <0x5c007000 0x400>;
>>>>> +            #address-cells = <1>;
>>>>> +            #size-cells = <1>;
>>>>> +            feature-domain-controller;
>>>>> +            #feature-domain-cells = <1>;
>>>>> +            ranges;
>>>>> +
>>>>> +            adc_2: adc@48004000 {
>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>> +                reg = <0x48004000 0x400>;
>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>> +                clock-names = "bus", "adc";
>>>>> +                interrupt-controller;
>>>>> +                #interrupt-cells = <1>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                feature-domains = <&etzpc 33>;
>>>>> +                status = "disabled";
>>>>> +
>>>>> +                adc2: adc@0 {
>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>> +                    #io-channel-cells = <1>;
>>>>> +                    #address-cells = <1>;
>>>>> +                    #size-cells = <0>;
>>>>> +                    reg = <0x0>;
>>>>> +                    interrupt-parent = <&adc_2>;
>>>>> +                    interrupts = <0>;
>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>> +                    dma-names = "rx";
>>>>> +                    status = "disabled";
>>>>> +
>>>>> +                    channel@13 {
>>>>> +                        reg = <13>;
>>>>> +                        label = "vrefint";
>>>>> +                    };
>>>>> +                    channel@14 {
>>>>> +                        reg = <14>;
>>>>> +                        label = "vddcore";
>>>>> +                    };
>>>>> +                    channel@16 {
>>>>> +                        reg = <16>;
>>>>> +                        label = "vddcpu";
>>>>> +                    };
>>>>> +                    channel@17 {
>>>>> +                        reg = <17>;
>>>>> +                        label = "vddq_ddr";
>>>>> +                    };
>>>>> +                };
>>>>> +            };
>>>>> +
>>>>> +            usbotg_hs: usb@49000000 {
>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>> +                reg = <0x49000000 0x40000>;
>>>>> +                clocks = <&rcc USBO_K>;
>>>>> +                clock-names = "otg";
>>>>> +                resets = <&rcc USBO_R>;
>>>>> +                reset-names = "dwc2";
>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                g-rx-fifo-size = <512>;
>>>>> +                g-np-tx-fifo-size = <32>;
>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>> +                dr_mode = "otg";
>>>>> +                otg-rev = <0x200>;
>>>>> +                usb33d-supply = <&usb33>;
>>>>> +                feature-domains = <&etzpc 34>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            spi4: spi@4c002000 {
>>>>> +                compatible = "st,stm32h7-spi";
>>>>> +                reg = <0x4c002000 0x400>;
>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SPI4_K>;
>>>>> +                resets = <&rcc SPI4_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                feature-domains = <&etzpc 18>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            spi5: spi@4c003000 {
>>>>> +                compatible = "st,stm32h7-spi";
>>>>> +                reg = <0x4c003000 0x400>;
>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SPI5_K>;
>>>>> +                resets = <&rcc SPI5_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                feature-domains = <&etzpc 19>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c3: i2c@4c004000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c004000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C3_K>;
>>>>> +                resets = <&rcc I2C3_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 20>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c4: i2c@4c005000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c005000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C4_K>;
>>>>> +                resets = <&rcc I2C4_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 21>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            i2c5: i2c@4c006000 {
>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>> +                reg = <0x4c006000 0x400>;
>>>>> +                interrupt-names = "event", "error";
>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc I2C5_K>;
>>>>> +                resets = <&rcc I2C5_R>;
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>> +                dma-names = "rx", "tx";
>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>> +                i2c-analog-filter;
>>>>> +                feature-domains = <&etzpc 22>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            sdmmc1: mmc@58005000 {
>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>> +                clock-names = "apb_pclk";
>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>> +                cap-sd-highspeed;
>>>>> +                cap-mmc-highspeed;
>>>>> +                max-frequency = <130000000>;
>>>>> +                feature-domains = <&etzpc 50>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            sdmmc2: mmc@58007000 {
>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>> +                clock-names = "apb_pclk";
>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>> +                cap-sd-highspeed;
>>>>> +                cap-mmc-highspeed;
>>>>> +                max-frequency = <130000000>;
>>>>> +                feature-domains = <&etzpc 51>;
>>>>> +                status = "disabled";
>>>>> +            };
>>>>> +
>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>> +                #address-cells = <1>;
>>>>> +                #size-cells = <0>;
>>>>> +                #clock-cells = <0>;
>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>> +                reg = <0x5a006000 0x1000>;
>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>> +                resets = <&rcc USBPHY_R>;
>>>>> +                vdda1v1-supply = <&reg11>;
>>>>> +                vdda1v8-supply = <&reg18>;
>>>>> +                feature-domains = <&etzpc 5>;
>>>>> +                status = "disabled";
>>>>> +
>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>> +                    #phy-cells = <0>;
>>>>> +                    reg = <0>;
>>>>> +                };
>>>>> +
>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>> +                    #phy-cells = <1>;
>>>>> +                    reg = <1>;
>>>>> +                };
>>>>> +            };
>>>>> +
>>>>> +        };
>>>>> +
>>>>>            /*
>>>>>             * Break node order to solve dependency probe issue between
>>>>>             * pinctrl and exti.
>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> index df451c3c2a26..be6061552683 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>                bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>                status = "disabled";
>>>>>            };
>>>>> +    };
>>>>> +};
>>>>>    -        adc_1: adc@48003000 {
>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>> -            reg = <0x48003000 0x400>;
>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>> -            clock-names = "bus", "adc";
>>>>> -            interrupt-controller;
>>>>> -            #interrupt-cells = <1>;
>>>>> +&etzpc {
>>>>> +    adc_1: adc@48003000 {
>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>> +        reg = <0x48003000 0x400>;
>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>> +        clock-names = "bus", "adc";
>>>>> +        interrupt-controller;
>>>>> +        #interrupt-cells = <1>;
>>>>> +        #address-cells = <1>;
>>>>> +        #size-cells = <0>;
>>>>> +        feature-domains = <&etzpc 32>;
>>>>> +        status = "disabled";
>>>>> +
>>>>> +        adc1: adc@0 {
>>>>> +            compatible = "st,stm32mp13-adc";
>>>>> +            #io-channel-cells = <1>;
>>>>>                #address-cells = <1>;
>>>>>                #size-cells = <0>;
>>>>> +            reg = <0x0>;
>>>>> +            interrupt-parent = <&adc_1>;
>>>>> +            interrupts = <0>;
>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>> +            dma-names = "rx";
>>>>>                status = "disabled";
>>>>>    -            adc1: adc@0 {
>>>>> -                compatible = "st,stm32mp13-adc";
>>>>> -                #io-channel-cells = <1>;
>>>>> -                #address-cells = <1>;
>>>>> -                #size-cells = <0>;
>>>>> -                reg = <0x0>;
>>>>> -                interrupt-parent = <&adc_1>;
>>>>> -                interrupts = <0>;
>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>> -                dma-names = "rx";
>>>>> -                status = "disabled";
>>>>> -
>>>>> -                channel@18 {
>>>>> -                    reg = <18>;
>>>>> -                    label = "vrefint";
>>>>> -                };
>>>>> +            channel@18 {
>>>>> +                reg = <18>;
>>>>> +                label = "vrefint";
>>>>>                };
>>>>>            };
>>>>>        };
>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>> @@ -4,15 +4,14 @@
>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>>     */
>>>>>    -/ {
>>>>> -    soc {
>>>>> -        cryp: crypto@54002000 {
>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>> -            reg = <0x54002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc CRYP1>;
>>>>> -            resets = <&rcc CRYP1_R>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> +&etzpc {
>>>>> +    cryp: crypto@54002000 {
>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>> +        reg = <0x54002000 0x400>;
>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc CRYP1>;
>>>>> +        resets = <&rcc CRYP1_R>;
>>>>> +        feature-domains = <&etzpc 42>;
>>>>> +        status = "disabled";
>>>>>        };
>>>>>    };
>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>> @@ -4,15 +4,13 @@
>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
>>>>>     */
>>>>>    -/ {
>>>>> -    soc {
>>>>> -        cryp: crypto@54002000 {
>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>> -            reg = <0x54002000 0x400>;
>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> -            clocks = <&rcc CRYP1>;
>>>>> -            resets = <&rcc CRYP1_R>;
>>>>> -            status = "disabled";
>>>>> -        };
>>>>> +&etzpc {
>>>>> +    cryp: crypto@54002000 {
>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>> +        reg = <0x54002000 0x400>;
>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +        clocks = <&rcc CRYP1>;
>>>>> +        resets = <&rcc CRYP1_R>;
>>>>> +        status = "disabled";
>>>>>        };
>>>>>    };
>>>>
>>>
>>
>> Regarding the patch itself, I can separate it in two patches.
>> 1)Introduce ETZPC
>> 2)Move peripherals under ETZPC
>>
>> Best regards,
>> Gatien
>>
> 

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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  2023-02-27 11:26             ` Gatien CHEVALLIER
  (?)
@ 2023-04-21 10:19               ` Oleksii Moisieiev
  -1 siblings, 0 replies; 93+ messages in thread
From: Oleksii Moisieiev @ 2023-04-21 10:19 UTC (permalink / raw)
  To: Gatien CHEVALLIER, Ahmad Fatoum, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team, Peng Fan

Hello,

I'm just wandering what is the status of the Patch Series?

Cc'ed Peng Fang as he also has an interest in the domain-controller 
bindings.

Oleksii.

On 27.02.23 13:26, Gatien CHEVALLIER wrote:
> Hello Ahmad,
>
> Sorry for the delay :)
>
> On 2/13/23 12:27, Ahmad Fatoum wrote:
>> Hello Gatien,
>>
>> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>>> Hello Gatien,
>>>>>
>>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>>> The STM32 System Bus is an internal bus on which devices are 
>>>>>> connected.
>>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>>> and control access to the peripherals connected on it.
>>>>>>
>>>>>> For more information on which peripheral is securable, please read
>>>>>> the STM32MP13 reference manual.
>>>>>
>>>>> Diff is way too big. Please split up the alphabetic reordering 
>>>>> into its
>>>>> own commit, so actual functional changes are apparent.
>>>>
>>>> Ah, I see now that you are moving securable peripherals into a new 
>>>> bus.
>>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>>
>>>> Does this configuration even change dynamically? Why can't you 
>>>> implement
>>>> this binding in the bootloader and have Linux only see a DT where 
>>>> unavailable
>>>> nodes are status = "disabled"; secure-status = "okay"?
>>>>
>>>> For inspiration, see barebox' device tree fixups when devices are 
>>>> disabled
>>>> per fuse:
>>>>
>>>> https://urldefense.com/v3/__https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c*L122__;Iw!!GF_29dbcQIUBPA!2CT6VXNxfrLUg3mPkiAykgwwu8y8TVPaVa5FupuehHDyeuPvx4a2aNuMs-ayUCqP8q364P8u0GxYprlqwrvgvnXndYBmii57$ 
>>>> [elixir[.]bootlin[.]com]
>>>>
>>>> Cheers,
>>>> Ahmad
>>>
>>> This configuration can change dynamically. The binding will be 
>>> implemented in the bootloader, where the ETZPC is already 
>>> implemented as a bus in our downstream.
>>>
>>> I find the mentionned example valid.
>>>
>>> Now, why is it a bus? :D
>>>
>>> It is the result of the discussion on the previous submission by 
>>> Benjamin (Sorry for the lack of link but I saw that you participated 
>>> on these threads)+ we need the bus mechanism to control whether a 
>>> subnode should be probed or not. You can see it as a firewall bus.
>>>
>>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and 
>>> propagation through bridges to the APB bus. Therefore, I find it 
>>> relevant to consider it as a bus, what is your opinion?
>>>
>>> This patchset is a first step to the implementation of an API to 
>>> control accesses dynamically.
>>
>> I still don't get what's dynamic about this. Either:
>>
>>    - Configuration _can_ change while Linux is running: You'll need 
>> to do
>>      way more than what your current bus provides to somwhow 
>> synchronize state
>>      with the secure monitor; otherwise a newly secured device will 
>> cause the driver
>>      to trigger data aborts that you'll have to handle and unbind the 
>> driver.
>>      (like if a USB drive is yanked out).
>>
>>    - Configuration _can't_ change while Linux is running: You can 
>> have the bootloader
>>      fixup the device tree and Linux need not care at all about 
>> devices that the
>>      ETZPC is securing.
>>
>> My understanding is that the latter is your use case, so I don't see 
>> why we
>> even need the normal world to be aware of the partitioning.
>>
>> Cheers,
>> Ahmad
>>
> What about the case where we do not have a U-Boot/bootloader to fixup 
> the device tree?
>
> On the other hand, ETZPC is a hardware firewall and is on the bus. 
> Therefore, shouldn't it be represented as a bus in the file that 
> describes the hardware?
>
> Best regards,
> Gatien
>
>>>
>>>>
>>>>>
>>>>> Thanks,
>>>>> Ahmad
>>>>>
>>>>>>
>>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>>> ---
>>>>>>
>>>>>> No changes in V2.
>>>>>>
>>>>>> Changes in V3:
>>>>>>      -Use appriopriate node name: bus
>>>>>>
>>>>>>    arch/arm/boot/dts/stm32mp131.dtsi  | 407 
>>>>>> +++++++++++++++--------------
>>>>>>    arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>>    arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>>    arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>>    4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> index accc3824f7e9..24462a647101 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>>                dma-channels = <16>;
>>>>>>            };
>>>>>>    -        adc_2: adc@48004000 {
>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>> -            reg = <0x48004000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>> -            clock-names = "bus", "adc";
>>>>>> -            interrupt-controller;
>>>>>> -            #interrupt-cells = <1>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            status = "disabled";
>>>>>> -
>>>>>> -            adc2: adc@0 {
>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>> -                #io-channel-cells = <1>;
>>>>>> -                #address-cells = <1>;
>>>>>> -                #size-cells = <0>;
>>>>>> -                reg = <0x0>;
>>>>>> -                interrupt-parent = <&adc_2>;
>>>>>> -                interrupts = <0>;
>>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>> -                dma-names = "rx";
>>>>>> -                status = "disabled";
>>>>>> -
>>>>>> -                channel@13 {
>>>>>> -                    reg = <13>;
>>>>>> -                    label = "vrefint";
>>>>>> -                };
>>>>>> -                channel@14 {
>>>>>> -                    reg = <14>;
>>>>>> -                    label = "vddcore";
>>>>>> -                };
>>>>>> -                channel@16 {
>>>>>> -                    reg = <16>;
>>>>>> -                    label = "vddcpu";
>>>>>> -                };
>>>>>> -                channel@17 {
>>>>>> -                    reg = <17>;
>>>>>> -                    label = "vddq_ddr";
>>>>>> -                };
>>>>>> -            };
>>>>>> -        };
>>>>>> -
>>>>>> -        usbotg_hs: usb@49000000 {
>>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>> -            reg = <0x49000000 0x40000>;
>>>>>> -            clocks = <&rcc USBO_K>;
>>>>>> -            clock-names = "otg";
>>>>>> -            resets = <&rcc USBO_R>;
>>>>>> -            reset-names = "dwc2";
>>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            g-rx-fifo-size = <512>;
>>>>>> -            g-np-tx-fifo-size = <32>;
>>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>> -            dr_mode = "otg";
>>>>>> -            otg-rev = <0x200>;
>>>>>> -            usb33d-supply = <&usb33>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        spi4: spi@4c002000 {
>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>> -            reg = <0x4c002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SPI4_K>;
>>>>>> -            resets = <&rcc SPI4_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        spi5: spi@4c003000 {
>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>> -            reg = <0x4c003000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SPI5_K>;
>>>>>> -            resets = <&rcc SPI5_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c3: i2c@4c004000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c004000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C3_K>;
>>>>>> -            resets = <&rcc I2C3_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c4: i2c@4c005000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c005000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C4_K>;
>>>>>> -            resets = <&rcc I2C4_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c5: i2c@4c006000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c006000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C5_K>;
>>>>>> -            resets = <&rcc I2C5_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>>            rcc: rcc@50000000 {
>>>>>>                compatible = "st,stm32mp13-rcc", "syscon";
>>>>>>                reg = <0x50000000 0x1000>;
>>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>>                dma-requests = <48>;
>>>>>>            };
>>>>>>    -        sdmmc1: mmc@58005000 {
>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>>> -            clock-names = "apb_pclk";
>>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>>> -            cap-sd-highspeed;
>>>>>> -            cap-mmc-highspeed;
>>>>>> -            max-frequency = <130000000>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        sdmmc2: mmc@58007000 {
>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>>> -            clock-names = "apb_pclk";
>>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>>> -            cap-sd-highspeed;
>>>>>> -            cap-mmc-highspeed;
>>>>>> -            max-frequency = <130000000>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>>            usbh_ohci: usb@5800c000 {
>>>>>>                compatible = "generic-ohci";
>>>>>>                reg = <0x5800c000 0x1000>;
>>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>>                status = "disabled";
>>>>>>            };
>>>>>>    -        usbphyc: usbphyc@5a006000 {
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            #clock-cells = <0>;
>>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>>> -            reg = <0x5a006000 0x1000>;
>>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>>> -            resets = <&rcc USBPHY_R>;
>>>>>> -            vdda1v1-supply = <&reg11>;
>>>>>> -            vdda1v8-supply = <&reg18>;
>>>>>> -            status = "disabled";
>>>>>> -
>>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>>> -                #phy-cells = <0>;
>>>>>> -                reg = <0>;
>>>>>> -            };
>>>>>> -
>>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>>> -                #phy-cells = <1>;
>>>>>> -                reg = <1>;
>>>>>> -            };
>>>>>> -        };
>>>>>> -
>>>>>>            rtc: rtc@5c004000 {
>>>>>>                compatible = "st,stm32mp1-rtc";
>>>>>>                reg = <0x5c004000 0x400>;
>>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>>                };
>>>>>>            };
>>>>>>    +        etzpc: bus@5c007000 {
>>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>>> +            reg = <0x5c007000 0x400>;
>>>>>> +            #address-cells = <1>;
>>>>>> +            #size-cells = <1>;
>>>>>> +            feature-domain-controller;
>>>>>> +            #feature-domain-cells = <1>;
>>>>>> +            ranges;
>>>>>> +
>>>>>> +            adc_2: adc@48004000 {
>>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>>> +                reg = <0x48004000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>> +                clock-names = "bus", "adc";
>>>>>> +                interrupt-controller;
>>>>>> +                #interrupt-cells = <1>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                feature-domains = <&etzpc 33>;
>>>>>> +                status = "disabled";
>>>>>> +
>>>>>> +                adc2: adc@0 {
>>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>>> +                    #io-channel-cells = <1>;
>>>>>> +                    #address-cells = <1>;
>>>>>> +                    #size-cells = <0>;
>>>>>> +                    reg = <0x0>;
>>>>>> +                    interrupt-parent = <&adc_2>;
>>>>>> +                    interrupts = <0>;
>>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>> +                    dma-names = "rx";
>>>>>> +                    status = "disabled";
>>>>>> +
>>>>>> +                    channel@13 {
>>>>>> +                        reg = <13>;
>>>>>> +                        label = "vrefint";
>>>>>> +                    };
>>>>>> +                    channel@14 {
>>>>>> +                        reg = <14>;
>>>>>> +                        label = "vddcore";
>>>>>> +                    };
>>>>>> +                    channel@16 {
>>>>>> +                        reg = <16>;
>>>>>> +                        label = "vddcpu";
>>>>>> +                    };
>>>>>> +                    channel@17 {
>>>>>> +                        reg = <17>;
>>>>>> +                        label = "vddq_ddr";
>>>>>> +                    };
>>>>>> +                };
>>>>>> +            };
>>>>>> +
>>>>>> +            usbotg_hs: usb@49000000 {
>>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>> +                reg = <0x49000000 0x40000>;
>>>>>> +                clocks = <&rcc USBO_K>;
>>>>>> +                clock-names = "otg";
>>>>>> +                resets = <&rcc USBO_R>;
>>>>>> +                reset-names = "dwc2";
>>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                g-rx-fifo-size = <512>;
>>>>>> +                g-np-tx-fifo-size = <32>;
>>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>> +                dr_mode = "otg";
>>>>>> +                otg-rev = <0x200>;
>>>>>> +                usb33d-supply = <&usb33>;
>>>>>> +                feature-domains = <&etzpc 34>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            spi4: spi@4c002000 {
>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>> +                reg = <0x4c002000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SPI4_K>;
>>>>>> +                resets = <&rcc SPI4_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                feature-domains = <&etzpc 18>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            spi5: spi@4c003000 {
>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>> +                reg = <0x4c003000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SPI5_K>;
>>>>>> +                resets = <&rcc SPI5_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                feature-domains = <&etzpc 19>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c3: i2c@4c004000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c004000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C3_K>;
>>>>>> +                resets = <&rcc I2C3_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 20>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c4: i2c@4c005000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c005000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C4_K>;
>>>>>> +                resets = <&rcc I2C4_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 21>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c5: i2c@4c006000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c006000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C5_K>;
>>>>>> +                resets = <&rcc I2C5_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 22>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            sdmmc1: mmc@58005000 {
>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>>> +                clock-names = "apb_pclk";
>>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>>> +                cap-sd-highspeed;
>>>>>> +                cap-mmc-highspeed;
>>>>>> +                max-frequency = <130000000>;
>>>>>> +                feature-domains = <&etzpc 50>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            sdmmc2: mmc@58007000 {
>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>>> +                clock-names = "apb_pclk";
>>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>>> +                cap-sd-highspeed;
>>>>>> +                cap-mmc-highspeed;
>>>>>> +                max-frequency = <130000000>;
>>>>>> +                feature-domains = <&etzpc 51>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                #clock-cells = <0>;
>>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>>> +                reg = <0x5a006000 0x1000>;
>>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>>> +                resets = <&rcc USBPHY_R>;
>>>>>> +                vdda1v1-supply = <&reg11>;
>>>>>> +                vdda1v8-supply = <&reg18>;
>>>>>> +                feature-domains = <&etzpc 5>;
>>>>>> +                status = "disabled";
>>>>>> +
>>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>>> +                    #phy-cells = <0>;
>>>>>> +                    reg = <0>;
>>>>>> +                };
>>>>>> +
>>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>>> +                    #phy-cells = <1>;
>>>>>> +                    reg = <1>;
>>>>>> +                };
>>>>>> +            };
>>>>>> +
>>>>>> +        };
>>>>>> +
>>>>>>            /*
>>>>>>             * Break node order to solve dependency probe issue 
>>>>>> between
>>>>>>             * pinctrl and exti.
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> index df451c3c2a26..be6061552683 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>>                bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>>                status = "disabled";
>>>>>>            };
>>>>>> +    };
>>>>>> +};
>>>>>>    -        adc_1: adc@48003000 {
>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>> -            reg = <0x48003000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>> -            clock-names = "bus", "adc";
>>>>>> -            interrupt-controller;
>>>>>> -            #interrupt-cells = <1>;
>>>>>> +&etzpc {
>>>>>> +    adc_1: adc@48003000 {
>>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>>> +        reg = <0x48003000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>> +        clock-names = "bus", "adc";
>>>>>> +        interrupt-controller;
>>>>>> +        #interrupt-cells = <1>;
>>>>>> +        #address-cells = <1>;
>>>>>> +        #size-cells = <0>;
>>>>>> +        feature-domains = <&etzpc 32>;
>>>>>> +        status = "disabled";
>>>>>> +
>>>>>> +        adc1: adc@0 {
>>>>>> +            compatible = "st,stm32mp13-adc";
>>>>>> +            #io-channel-cells = <1>;
>>>>>>                #address-cells = <1>;
>>>>>>                #size-cells = <0>;
>>>>>> +            reg = <0x0>;
>>>>>> +            interrupt-parent = <&adc_1>;
>>>>>> +            interrupts = <0>;
>>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>> +            dma-names = "rx";
>>>>>>                status = "disabled";
>>>>>>    -            adc1: adc@0 {
>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>> -                #io-channel-cells = <1>;
>>>>>> -                #address-cells = <1>;
>>>>>> -                #size-cells = <0>;
>>>>>> -                reg = <0x0>;
>>>>>> -                interrupt-parent = <&adc_1>;
>>>>>> -                interrupts = <0>;
>>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>> -                dma-names = "rx";
>>>>>> -                status = "disabled";
>>>>>> -
>>>>>> -                channel@18 {
>>>>>> -                    reg = <18>;
>>>>>> -                    label = "vrefint";
>>>>>> -             ��  };
>>>>>> +            channel@18 {
>>>>>> +                reg = <18>;
>>>>>> +                label = "vrefint";
>>>>>>                };
>>>>>>            };
>>>>>>        };
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> @@ -4,15 +4,14 @@
>>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for 
>>>>>> STMicroelectronics.
>>>>>>     */
>>>>>>    -/ {
>>>>>> -    soc {
>>>>>> -        cryp: crypto@54002000 {
>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>> -            reg = <0x54002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> +&etzpc {
>>>>>> +    cryp: crypto@54002000 {
>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>> +        reg = <0x54002000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>> +        feature-domains = <&etzpc 42>;
>>>>>> +        status = "disabled";
>>>>>>        };
>>>>>>    };
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> @@ -4,15 +4,13 @@
>>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for 
>>>>>> STMicroelectronics.
>>>>>>     */
>>>>>>    -/ {
>>>>>> -    soc {
>>>>>> -        cryp: crypto@54002000 {
>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>> -            reg = <0x54002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> +&etzpc {
>>>>>> +    cryp: crypto@54002000 {
>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>> +        reg = <0x54002000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>> +        status = "disabled";
>>>>>>        };
>>>>>>    };
>>>>>
>>>>
>>>
>>> Regarding the patch itself, I can separate it in two patches.
>>> 1)Introduce ETZPC
>>> 2)Move peripherals under ETZPC
>>>
>>> Best regards,
>>> Gatien
>>>
>>
-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-04-21 10:19               ` Oleksii Moisieiev
  0 siblings, 0 replies; 93+ messages in thread
From: Oleksii Moisieiev @ 2023-04-21 10:19 UTC (permalink / raw)
  To: Gatien CHEVALLIER, Ahmad Fatoum, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team, Peng Fan

Hello,

I'm just wandering what is the status of the Patch Series?

Cc'ed Peng Fang as he also has an interest in the domain-controller 
bindings.

Oleksii.

On 27.02.23 13:26, Gatien CHEVALLIER wrote:
> Hello Ahmad,
>
> Sorry for the delay :)
>
> On 2/13/23 12:27, Ahmad Fatoum wrote:
>> Hello Gatien,
>>
>> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>>> Hello Gatien,
>>>>>
>>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>>> The STM32 System Bus is an internal bus on which devices are 
>>>>>> connected.
>>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>>> and control access to the peripherals connected on it.
>>>>>>
>>>>>> For more information on which peripheral is securable, please read
>>>>>> the STM32MP13 reference manual.
>>>>>
>>>>> Diff is way too big. Please split up the alphabetic reordering 
>>>>> into its
>>>>> own commit, so actual functional changes are apparent.
>>>>
>>>> Ah, I see now that you are moving securable peripherals into a new 
>>>> bus.
>>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>>
>>>> Does this configuration even change dynamically? Why can't you 
>>>> implement
>>>> this binding in the bootloader and have Linux only see a DT where 
>>>> unavailable
>>>> nodes are status = "disabled"; secure-status = "okay"?
>>>>
>>>> For inspiration, see barebox' device tree fixups when devices are 
>>>> disabled
>>>> per fuse:
>>>>
>>>> https://urldefense.com/v3/__https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c*L122__;Iw!!GF_29dbcQIUBPA!2CT6VXNxfrLUg3mPkiAykgwwu8y8TVPaVa5FupuehHDyeuPvx4a2aNuMs-ayUCqP8q364P8u0GxYprlqwrvgvnXndYBmii57$ 
>>>> [elixir[.]bootlin[.]com]
>>>>
>>>> Cheers,
>>>> Ahmad
>>>
>>> This configuration can change dynamically. The binding will be 
>>> implemented in the bootloader, where the ETZPC is already 
>>> implemented as a bus in our downstream.
>>>
>>> I find the mentionned example valid.
>>>
>>> Now, why is it a bus? :D
>>>
>>> It is the result of the discussion on the previous submission by 
>>> Benjamin (Sorry for the lack of link but I saw that you participated 
>>> on these threads)+ we need the bus mechanism to control whether a 
>>> subnode should be probed or not. You can see it as a firewall bus.
>>>
>>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and 
>>> propagation through bridges to the APB bus. Therefore, I find it 
>>> relevant to consider it as a bus, what is your opinion?
>>>
>>> This patchset is a first step to the implementation of an API to 
>>> control accesses dynamically.
>>
>> I still don't get what's dynamic about this. Either:
>>
>>    - Configuration _can_ change while Linux is running: You'll need 
>> to do
>>      way more than what your current bus provides to somwhow 
>> synchronize state
>>      with the secure monitor; otherwise a newly secured device will 
>> cause the driver
>>      to trigger data aborts that you'll have to handle and unbind the 
>> driver.
>>      (like if a USB drive is yanked out).
>>
>>    - Configuration _can't_ change while Linux is running: You can 
>> have the bootloader
>>      fixup the device tree and Linux need not care at all about 
>> devices that the
>>      ETZPC is securing.
>>
>> My understanding is that the latter is your use case, so I don't see 
>> why we
>> even need the normal world to be aware of the partitioning.
>>
>> Cheers,
>> Ahmad
>>
> What about the case where we do not have a U-Boot/bootloader to fixup 
> the device tree?
>
> On the other hand, ETZPC is a hardware firewall and is on the bus. 
> Therefore, shouldn't it be represented as a bus in the file that 
> describes the hardware?
>
> Best regards,
> Gatien
>
>>>
>>>>
>>>>>
>>>>> Thanks,
>>>>> Ahmad
>>>>>
>>>>>>
>>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>>> ---
>>>>>>
>>>>>> No changes in V2.
>>>>>>
>>>>>> Changes in V3:
>>>>>>      -Use appriopriate node name: bus
>>>>>>
>>>>>>    arch/arm/boot/dts/stm32mp131.dtsi  | 407 
>>>>>> +++++++++++++++--------------
>>>>>>    arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>>    arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>>    arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>>    4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> index accc3824f7e9..24462a647101 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>>                dma-channels = <16>;
>>>>>>            };
>>>>>>    -        adc_2: adc@48004000 {
>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>> -            reg = <0x48004000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>> -            clock-names = "bus", "adc";
>>>>>> -            interrupt-controller;
>>>>>> -            #interrupt-cells = <1>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            status = "disabled";
>>>>>> -
>>>>>> -            adc2: adc@0 {
>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>> -                #io-channel-cells = <1>;
>>>>>> -                #address-cells = <1>;
>>>>>> -                #size-cells = <0>;
>>>>>> -                reg = <0x0>;
>>>>>> -                interrupt-parent = <&adc_2>;
>>>>>> -                interrupts = <0>;
>>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>> -                dma-names = "rx";
>>>>>> -                status = "disabled";
>>>>>> -
>>>>>> -                channel@13 {
>>>>>> -                    reg = <13>;
>>>>>> -                    label = "vrefint";
>>>>>> -                };
>>>>>> -                channel@14 {
>>>>>> -                    reg = <14>;
>>>>>> -                    label = "vddcore";
>>>>>> -                };
>>>>>> -                channel@16 {
>>>>>> -                    reg = <16>;
>>>>>> -                    label = "vddcpu";
>>>>>> -                };
>>>>>> -                channel@17 {
>>>>>> -                    reg = <17>;
>>>>>> -                    label = "vddq_ddr";
>>>>>> -                };
>>>>>> -            };
>>>>>> -        };
>>>>>> -
>>>>>> -        usbotg_hs: usb@49000000 {
>>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>> -            reg = <0x49000000 0x40000>;
>>>>>> -            clocks = <&rcc USBO_K>;
>>>>>> -            clock-names = "otg";
>>>>>> -            resets = <&rcc USBO_R>;
>>>>>> -            reset-names = "dwc2";
>>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            g-rx-fifo-size = <512>;
>>>>>> -            g-np-tx-fifo-size = <32>;
>>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>> -            dr_mode = "otg";
>>>>>> -            otg-rev = <0x200>;
>>>>>> -            usb33d-supply = <&usb33>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        spi4: spi@4c002000 {
>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>> -            reg = <0x4c002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SPI4_K>;
>>>>>> -            resets = <&rcc SPI4_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        spi5: spi@4c003000 {
>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>> -            reg = <0x4c003000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SPI5_K>;
>>>>>> -            resets = <&rcc SPI5_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c3: i2c@4c004000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c004000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C3_K>;
>>>>>> -            resets = <&rcc I2C3_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c4: i2c@4c005000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c005000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C4_K>;
>>>>>> -            resets = <&rcc I2C4_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c5: i2c@4c006000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c006000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C5_K>;
>>>>>> -            resets = <&rcc I2C5_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>>            rcc: rcc@50000000 {
>>>>>>                compatible = "st,stm32mp13-rcc", "syscon";
>>>>>>                reg = <0x50000000 0x1000>;
>>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>>                dma-requests = <48>;
>>>>>>            };
>>>>>>    -        sdmmc1: mmc@58005000 {
>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>>> -            clock-names = "apb_pclk";
>>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>>> -            cap-sd-highspeed;
>>>>>> -            cap-mmc-highspeed;
>>>>>> -            max-frequency = <130000000>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        sdmmc2: mmc@58007000 {
>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>>> -            clock-names = "apb_pclk";
>>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>>> -            cap-sd-highspeed;
>>>>>> -            cap-mmc-highspeed;
>>>>>> -            max-frequency = <130000000>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>>            usbh_ohci: usb@5800c000 {
>>>>>>                compatible = "generic-ohci";
>>>>>>                reg = <0x5800c000 0x1000>;
>>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>>                status = "disabled";
>>>>>>            };
>>>>>>    -        usbphyc: usbphyc@5a006000 {
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            #clock-cells = <0>;
>>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>>> -            reg = <0x5a006000 0x1000>;
>>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>>> -            resets = <&rcc USBPHY_R>;
>>>>>> -            vdda1v1-supply = <&reg11>;
>>>>>> -            vdda1v8-supply = <&reg18>;
>>>>>> -            status = "disabled";
>>>>>> -
>>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>>> -                #phy-cells = <0>;
>>>>>> -                reg = <0>;
>>>>>> -            };
>>>>>> -
>>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>>> -                #phy-cells = <1>;
>>>>>> -                reg = <1>;
>>>>>> -            };
>>>>>> -        };
>>>>>> -
>>>>>>            rtc: rtc@5c004000 {
>>>>>>                compatible = "st,stm32mp1-rtc";
>>>>>>                reg = <0x5c004000 0x400>;
>>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>>                };
>>>>>>            };
>>>>>>    +        etzpc: bus@5c007000 {
>>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>>> +            reg = <0x5c007000 0x400>;
>>>>>> +            #address-cells = <1>;
>>>>>> +            #size-cells = <1>;
>>>>>> +            feature-domain-controller;
>>>>>> +            #feature-domain-cells = <1>;
>>>>>> +            ranges;
>>>>>> +
>>>>>> +            adc_2: adc@48004000 {
>>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>>> +                reg = <0x48004000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>> +                clock-names = "bus", "adc";
>>>>>> +                interrupt-controller;
>>>>>> +                #interrupt-cells = <1>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                feature-domains = <&etzpc 33>;
>>>>>> +                status = "disabled";
>>>>>> +
>>>>>> +                adc2: adc@0 {
>>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>>> +                    #io-channel-cells = <1>;
>>>>>> +                    #address-cells = <1>;
>>>>>> +                    #size-cells = <0>;
>>>>>> +                    reg = <0x0>;
>>>>>> +                    interrupt-parent = <&adc_2>;
>>>>>> +                    interrupts = <0>;
>>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>> +                    dma-names = "rx";
>>>>>> +                    status = "disabled";
>>>>>> +
>>>>>> +                    channel@13 {
>>>>>> +                        reg = <13>;
>>>>>> +                        label = "vrefint";
>>>>>> +                    };
>>>>>> +                    channel@14 {
>>>>>> +                        reg = <14>;
>>>>>> +                        label = "vddcore";
>>>>>> +                    };
>>>>>> +                    channel@16 {
>>>>>> +                        reg = <16>;
>>>>>> +                        label = "vddcpu";
>>>>>> +                    };
>>>>>> +                    channel@17 {
>>>>>> +                        reg = <17>;
>>>>>> +                        label = "vddq_ddr";
>>>>>> +                    };
>>>>>> +                };
>>>>>> +            };
>>>>>> +
>>>>>> +            usbotg_hs: usb@49000000 {
>>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>> +                reg = <0x49000000 0x40000>;
>>>>>> +                clocks = <&rcc USBO_K>;
>>>>>> +                clock-names = "otg";
>>>>>> +                resets = <&rcc USBO_R>;
>>>>>> +                reset-names = "dwc2";
>>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                g-rx-fifo-size = <512>;
>>>>>> +                g-np-tx-fifo-size = <32>;
>>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>> +                dr_mode = "otg";
>>>>>> +                otg-rev = <0x200>;
>>>>>> +                usb33d-supply = <&usb33>;
>>>>>> +                feature-domains = <&etzpc 34>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            spi4: spi@4c002000 {
>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>> +                reg = <0x4c002000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SPI4_K>;
>>>>>> +                resets = <&rcc SPI4_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                feature-domains = <&etzpc 18>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            spi5: spi@4c003000 {
>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>> +                reg = <0x4c003000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SPI5_K>;
>>>>>> +                resets = <&rcc SPI5_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                feature-domains = <&etzpc 19>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c3: i2c@4c004000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c004000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C3_K>;
>>>>>> +                resets = <&rcc I2C3_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 20>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c4: i2c@4c005000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c005000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C4_K>;
>>>>>> +                resets = <&rcc I2C4_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 21>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c5: i2c@4c006000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c006000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C5_K>;
>>>>>> +                resets = <&rcc I2C5_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 22>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            sdmmc1: mmc@58005000 {
>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>>> +                clock-names = "apb_pclk";
>>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>>> +                cap-sd-highspeed;
>>>>>> +                cap-mmc-highspeed;
>>>>>> +                max-frequency = <130000000>;
>>>>>> +                feature-domains = <&etzpc 50>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            sdmmc2: mmc@58007000 {
>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>>> +                clock-names = "apb_pclk";
>>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>>> +                cap-sd-highspeed;
>>>>>> +                cap-mmc-highspeed;
>>>>>> +                max-frequency = <130000000>;
>>>>>> +                feature-domains = <&etzpc 51>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                #clock-cells = <0>;
>>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>>> +                reg = <0x5a006000 0x1000>;
>>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>>> +                resets = <&rcc USBPHY_R>;
>>>>>> +                vdda1v1-supply = <&reg11>;
>>>>>> +                vdda1v8-supply = <&reg18>;
>>>>>> +                feature-domains = <&etzpc 5>;
>>>>>> +                status = "disabled";
>>>>>> +
>>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>>> +                    #phy-cells = <0>;
>>>>>> +                    reg = <0>;
>>>>>> +                };
>>>>>> +
>>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>>> +                    #phy-cells = <1>;
>>>>>> +                    reg = <1>;
>>>>>> +                };
>>>>>> +            };
>>>>>> +
>>>>>> +        };
>>>>>> +
>>>>>>            /*
>>>>>>             * Break node order to solve dependency probe issue 
>>>>>> between
>>>>>>             * pinctrl and exti.
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> index df451c3c2a26..be6061552683 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>>                bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>>                status = "disabled";
>>>>>>            };
>>>>>> +    };
>>>>>> +};
>>>>>>    -        adc_1: adc@48003000 {
>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>> -            reg = <0x48003000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>> -            clock-names = "bus", "adc";
>>>>>> -            interrupt-controller;
>>>>>> -            #interrupt-cells = <1>;
>>>>>> +&etzpc {
>>>>>> +    adc_1: adc@48003000 {
>>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>>> +        reg = <0x48003000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>> +        clock-names = "bus", "adc";
>>>>>> +        interrupt-controller;
>>>>>> +        #interrupt-cells = <1>;
>>>>>> +        #address-cells = <1>;
>>>>>> +        #size-cells = <0>;
>>>>>> +        feature-domains = <&etzpc 32>;
>>>>>> +        status = "disabled";
>>>>>> +
>>>>>> +        adc1: adc@0 {
>>>>>> +            compatible = "st,stm32mp13-adc";
>>>>>> +            #io-channel-cells = <1>;
>>>>>>                #address-cells = <1>;
>>>>>>                #size-cells = <0>;
>>>>>> +            reg = <0x0>;
>>>>>> +            interrupt-parent = <&adc_1>;
>>>>>> +            interrupts = <0>;
>>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>> +            dma-names = "rx";
>>>>>>                status = "disabled";
>>>>>>    -            adc1: adc@0 {
>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>> -                #io-channel-cells = <1>;
>>>>>> -                #address-cells = <1>;
>>>>>> -                #size-cells = <0>;
>>>>>> -                reg = <0x0>;
>>>>>> -                interrupt-parent = <&adc_1>;
>>>>>> -                interrupts = <0>;
>>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>> -                dma-names = "rx";
>>>>>> -                status = "disabled";
>>>>>> -
>>>>>> -                channel@18 {
>>>>>> -                    reg = <18>;
>>>>>> -                    label = "vrefint";
>>>>>> -             ��  };
>>>>>> +            channel@18 {
>>>>>> +                reg = <18>;
>>>>>> +                label = "vrefint";
>>>>>>                };
>>>>>>            };
>>>>>>        };
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> @@ -4,15 +4,14 @@
>>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for 
>>>>>> STMicroelectronics.
>>>>>>     */
>>>>>>    -/ {
>>>>>> -    soc {
>>>>>> -        cryp: crypto@54002000 {
>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>> -            reg = <0x54002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> +&etzpc {
>>>>>> +    cryp: crypto@54002000 {
>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>> +        reg = <0x54002000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>> +        feature-domains = <&etzpc 42>;
>>>>>> +        status = "disabled";
>>>>>>        };
>>>>>>    };
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> @@ -4,15 +4,13 @@
>>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for 
>>>>>> STMicroelectronics.
>>>>>>     */
>>>>>>    -/ {
>>>>>> -    soc {
>>>>>> -        cryp: crypto@54002000 {
>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>> -            reg = <0x54002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> +&etzpc {
>>>>>> +    cryp: crypto@54002000 {
>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>> +        reg = <0x54002000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>> +        status = "disabled";
>>>>>>        };
>>>>>>    };
>>>>>
>>>>
>>>
>>> Regarding the patch itself, I can separate it in two patches.
>>> 1)Introduce ETZPC
>>> 2)Move peripherals under ETZPC
>>>
>>> Best regards,
>>> Gatien
>>>
>>
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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-04-21 10:19               ` Oleksii Moisieiev
  0 siblings, 0 replies; 93+ messages in thread
From: Oleksii Moisieiev @ 2023-04-21 10:19 UTC (permalink / raw)
  To: Gatien CHEVALLIER, Ahmad Fatoum, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team, Peng Fan

Hello,

I'm just wandering what is the status of the Patch Series?

Cc'ed Peng Fang as he also has an interest in the domain-controller 
bindings.

Oleksii.

On 27.02.23 13:26, Gatien CHEVALLIER wrote:
> Hello Ahmad,
>
> Sorry for the delay :)
>
> On 2/13/23 12:27, Ahmad Fatoum wrote:
>> Hello Gatien,
>>
>> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>>> Hello Gatien,
>>>>>
>>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>>> The STM32 System Bus is an internal bus on which devices are 
>>>>>> connected.
>>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>>> and control access to the peripherals connected on it.
>>>>>>
>>>>>> For more information on which peripheral is securable, please read
>>>>>> the STM32MP13 reference manual.
>>>>>
>>>>> Diff is way too big. Please split up the alphabetic reordering 
>>>>> into its
>>>>> own commit, so actual functional changes are apparent.
>>>>
>>>> Ah, I see now that you are moving securable peripherals into a new 
>>>> bus.
>>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>>
>>>> Does this configuration even change dynamically? Why can't you 
>>>> implement
>>>> this binding in the bootloader and have Linux only see a DT where 
>>>> unavailable
>>>> nodes are status = "disabled"; secure-status = "okay"?
>>>>
>>>> For inspiration, see barebox' device tree fixups when devices are 
>>>> disabled
>>>> per fuse:
>>>>
>>>> https://urldefense.com/v3/__https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c*L122__;Iw!!GF_29dbcQIUBPA!2CT6VXNxfrLUg3mPkiAykgwwu8y8TVPaVa5FupuehHDyeuPvx4a2aNuMs-ayUCqP8q364P8u0GxYprlqwrvgvnXndYBmii57$ 
>>>> [elixir[.]bootlin[.]com]
>>>>
>>>> Cheers,
>>>> Ahmad
>>>
>>> This configuration can change dynamically. The binding will be 
>>> implemented in the bootloader, where the ETZPC is already 
>>> implemented as a bus in our downstream.
>>>
>>> I find the mentionned example valid.
>>>
>>> Now, why is it a bus? :D
>>>
>>> It is the result of the discussion on the previous submission by 
>>> Benjamin (Sorry for the lack of link but I saw that you participated 
>>> on these threads)+ we need the bus mechanism to control whether a 
>>> subnode should be probed or not. You can see it as a firewall bus.
>>>
>>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and 
>>> propagation through bridges to the APB bus. Therefore, I find it 
>>> relevant to consider it as a bus, what is your opinion?
>>>
>>> This patchset is a first step to the implementation of an API to 
>>> control accesses dynamically.
>>
>> I still don't get what's dynamic about this. Either:
>>
>>    - Configuration _can_ change while Linux is running: You'll need 
>> to do
>>      way more than what your current bus provides to somwhow 
>> synchronize state
>>      with the secure monitor; otherwise a newly secured device will 
>> cause the driver
>>      to trigger data aborts that you'll have to handle and unbind the 
>> driver.
>>      (like if a USB drive is yanked out).
>>
>>    - Configuration _can't_ change while Linux is running: You can 
>> have the bootloader
>>      fixup the device tree and Linux need not care at all about 
>> devices that the
>>      ETZPC is securing.
>>
>> My understanding is that the latter is your use case, so I don't see 
>> why we
>> even need the normal world to be aware of the partitioning.
>>
>> Cheers,
>> Ahmad
>>
> What about the case where we do not have a U-Boot/bootloader to fixup 
> the device tree?
>
> On the other hand, ETZPC is a hardware firewall and is on the bus. 
> Therefore, shouldn't it be represented as a bus in the file that 
> describes the hardware?
>
> Best regards,
> Gatien
>
>>>
>>>>
>>>>>
>>>>> Thanks,
>>>>> Ahmad
>>>>>
>>>>>>
>>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>>> ---
>>>>>>
>>>>>> No changes in V2.
>>>>>>
>>>>>> Changes in V3:
>>>>>>      -Use appriopriate node name: bus
>>>>>>
>>>>>>    arch/arm/boot/dts/stm32mp131.dtsi  | 407 
>>>>>> +++++++++++++++--------------
>>>>>>    arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>>    arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>>    arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>>    4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> index accc3824f7e9..24462a647101 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>>                dma-channels = <16>;
>>>>>>            };
>>>>>>    -        adc_2: adc@48004000 {
>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>> -            reg = <0x48004000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>> -            clock-names = "bus", "adc";
>>>>>> -            interrupt-controller;
>>>>>> -            #interrupt-cells = <1>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            status = "disabled";
>>>>>> -
>>>>>> -            adc2: adc@0 {
>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>> -                #io-channel-cells = <1>;
>>>>>> -                #address-cells = <1>;
>>>>>> -                #size-cells = <0>;
>>>>>> -                reg = <0x0>;
>>>>>> -                interrupt-parent = <&adc_2>;
>>>>>> -                interrupts = <0>;
>>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>> -                dma-names = "rx";
>>>>>> -                status = "disabled";
>>>>>> -
>>>>>> -                channel@13 {
>>>>>> -                    reg = <13>;
>>>>>> -                    label = "vrefint";
>>>>>> -                };
>>>>>> -                channel@14 {
>>>>>> -                    reg = <14>;
>>>>>> -                    label = "vddcore";
>>>>>> -                };
>>>>>> -                channel@16 {
>>>>>> -                    reg = <16>;
>>>>>> -                    label = "vddcpu";
>>>>>> -                };
>>>>>> -                channel@17 {
>>>>>> -                    reg = <17>;
>>>>>> -                    label = "vddq_ddr";
>>>>>> -                };
>>>>>> -            };
>>>>>> -        };
>>>>>> -
>>>>>> -        usbotg_hs: usb@49000000 {
>>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>> -            reg = <0x49000000 0x40000>;
>>>>>> -            clocks = <&rcc USBO_K>;
>>>>>> -            clock-names = "otg";
>>>>>> -            resets = <&rcc USBO_R>;
>>>>>> -            reset-names = "dwc2";
>>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            g-rx-fifo-size = <512>;
>>>>>> -            g-np-tx-fifo-size = <32>;
>>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>> -            dr_mode = "otg";
>>>>>> -            otg-rev = <0x200>;
>>>>>> -            usb33d-supply = <&usb33>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        spi4: spi@4c002000 {
>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>> -            reg = <0x4c002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SPI4_K>;
>>>>>> -            resets = <&rcc SPI4_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        spi5: spi@4c003000 {
>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>> -            reg = <0x4c003000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SPI5_K>;
>>>>>> -            resets = <&rcc SPI5_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c3: i2c@4c004000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c004000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C3_K>;
>>>>>> -            resets = <&rcc I2C3_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c4: i2c@4c005000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c005000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C4_K>;
>>>>>> -            resets = <&rcc I2C4_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c5: i2c@4c006000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c006000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C5_K>;
>>>>>> -            resets = <&rcc I2C5_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>>            rcc: rcc@50000000 {
>>>>>>                compatible = "st,stm32mp13-rcc", "syscon";
>>>>>>                reg = <0x50000000 0x1000>;
>>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>>                dma-requests = <48>;
>>>>>>            };
>>>>>>    -        sdmmc1: mmc@58005000 {
>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>>> -            clock-names = "apb_pclk";
>>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>>> -            cap-sd-highspeed;
>>>>>> -            cap-mmc-highspeed;
>>>>>> -            max-frequency = <130000000>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        sdmmc2: mmc@58007000 {
>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>>> -            clock-names = "apb_pclk";
>>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>>> -            cap-sd-highspeed;
>>>>>> -            cap-mmc-highspeed;
>>>>>> -            max-frequency = <130000000>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>>            usbh_ohci: usb@5800c000 {
>>>>>>                compatible = "generic-ohci";
>>>>>>                reg = <0x5800c000 0x1000>;
>>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>>                status = "disabled";
>>>>>>            };
>>>>>>    -        usbphyc: usbphyc@5a006000 {
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            #clock-cells = <0>;
>>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>>> -            reg = <0x5a006000 0x1000>;
>>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>>> -            resets = <&rcc USBPHY_R>;
>>>>>> -            vdda1v1-supply = <&reg11>;
>>>>>> -            vdda1v8-supply = <&reg18>;
>>>>>> -            status = "disabled";
>>>>>> -
>>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>>> -                #phy-cells = <0>;
>>>>>> -                reg = <0>;
>>>>>> -            };
>>>>>> -
>>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>>> -                #phy-cells = <1>;
>>>>>> -                reg = <1>;
>>>>>> -            };
>>>>>> -        };
>>>>>> -
>>>>>>            rtc: rtc@5c004000 {
>>>>>>                compatible = "st,stm32mp1-rtc";
>>>>>>                reg = <0x5c004000 0x400>;
>>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>>                };
>>>>>>            };
>>>>>>    +        etzpc: bus@5c007000 {
>>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>>> +            reg = <0x5c007000 0x400>;
>>>>>> +            #address-cells = <1>;
>>>>>> +            #size-cells = <1>;
>>>>>> +            feature-domain-controller;
>>>>>> +            #feature-domain-cells = <1>;
>>>>>> +            ranges;
>>>>>> +
>>>>>> +            adc_2: adc@48004000 {
>>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>>> +                reg = <0x48004000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>> +                clock-names = "bus", "adc";
>>>>>> +                interrupt-controller;
>>>>>> +                #interrupt-cells = <1>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                feature-domains = <&etzpc 33>;
>>>>>> +                status = "disabled";
>>>>>> +
>>>>>> +                adc2: adc@0 {
>>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>>> +                    #io-channel-cells = <1>;
>>>>>> +                    #address-cells = <1>;
>>>>>> +                    #size-cells = <0>;
>>>>>> +                    reg = <0x0>;
>>>>>> +                    interrupt-parent = <&adc_2>;
>>>>>> +                    interrupts = <0>;
>>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>> +                    dma-names = "rx";
>>>>>> +                    status = "disabled";
>>>>>> +
>>>>>> +                    channel@13 {
>>>>>> +                        reg = <13>;
>>>>>> +                        label = "vrefint";
>>>>>> +                    };
>>>>>> +                    channel@14 {
>>>>>> +                        reg = <14>;
>>>>>> +                        label = "vddcore";
>>>>>> +                    };
>>>>>> +                    channel@16 {
>>>>>> +                        reg = <16>;
>>>>>> +                        label = "vddcpu";
>>>>>> +                    };
>>>>>> +                    channel@17 {
>>>>>> +                        reg = <17>;
>>>>>> +                        label = "vddq_ddr";
>>>>>> +                    };
>>>>>> +                };
>>>>>> +            };
>>>>>> +
>>>>>> +            usbotg_hs: usb@49000000 {
>>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>> +                reg = <0x49000000 0x40000>;
>>>>>> +                clocks = <&rcc USBO_K>;
>>>>>> +                clock-names = "otg";
>>>>>> +                resets = <&rcc USBO_R>;
>>>>>> +                reset-names = "dwc2";
>>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                g-rx-fifo-size = <512>;
>>>>>> +                g-np-tx-fifo-size = <32>;
>>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>> +                dr_mode = "otg";
>>>>>> +                otg-rev = <0x200>;
>>>>>> +                usb33d-supply = <&usb33>;
>>>>>> +                feature-domains = <&etzpc 34>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            spi4: spi@4c002000 {
>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>> +                reg = <0x4c002000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SPI4_K>;
>>>>>> +                resets = <&rcc SPI4_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                feature-domains = <&etzpc 18>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            spi5: spi@4c003000 {
>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>> +                reg = <0x4c003000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SPI5_K>;
>>>>>> +                resets = <&rcc SPI5_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                feature-domains = <&etzpc 19>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c3: i2c@4c004000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c004000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C3_K>;
>>>>>> +                resets = <&rcc I2C3_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 20>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c4: i2c@4c005000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c005000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C4_K>;
>>>>>> +                resets = <&rcc I2C4_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 21>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c5: i2c@4c006000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c006000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C5_K>;
>>>>>> +                resets = <&rcc I2C5_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 22>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            sdmmc1: mmc@58005000 {
>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>>> +                clock-names = "apb_pclk";
>>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>>> +                cap-sd-highspeed;
>>>>>> +                cap-mmc-highspeed;
>>>>>> +                max-frequency = <130000000>;
>>>>>> +                feature-domains = <&etzpc 50>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            sdmmc2: mmc@58007000 {
>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>>> +                clock-names = "apb_pclk";
>>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>>> +                cap-sd-highspeed;
>>>>>> +                cap-mmc-highspeed;
>>>>>> +                max-frequency = <130000000>;
>>>>>> +                feature-domains = <&etzpc 51>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                #clock-cells = <0>;
>>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>>> +                reg = <0x5a006000 0x1000>;
>>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>>> +                resets = <&rcc USBPHY_R>;
>>>>>> +                vdda1v1-supply = <&reg11>;
>>>>>> +                vdda1v8-supply = <&reg18>;
>>>>>> +                feature-domains = <&etzpc 5>;
>>>>>> +                status = "disabled";
>>>>>> +
>>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>>> +                    #phy-cells = <0>;
>>>>>> +                    reg = <0>;
>>>>>> +                };
>>>>>> +
>>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>>> +                    #phy-cells = <1>;
>>>>>> +                    reg = <1>;
>>>>>> +                };
>>>>>> +            };
>>>>>> +
>>>>>> +        };
>>>>>> +
>>>>>>            /*
>>>>>>             * Break node order to solve dependency probe issue 
>>>>>> between
>>>>>>             * pinctrl and exti.
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> index df451c3c2a26..be6061552683 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>>                bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>>                status = "disabled";
>>>>>>            };
>>>>>> +    };
>>>>>> +};
>>>>>>    -        adc_1: adc@48003000 {
>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>> -            reg = <0x48003000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>> -            clock-names = "bus", "adc";
>>>>>> -            interrupt-controller;
>>>>>> -            #interrupt-cells = <1>;
>>>>>> +&etzpc {
>>>>>> +    adc_1: adc@48003000 {
>>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>>> +        reg = <0x48003000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>> +        clock-names = "bus", "adc";
>>>>>> +        interrupt-controller;
>>>>>> +        #interrupt-cells = <1>;
>>>>>> +        #address-cells = <1>;
>>>>>> +        #size-cells = <0>;
>>>>>> +        feature-domains = <&etzpc 32>;
>>>>>> +        status = "disabled";
>>>>>> +
>>>>>> +        adc1: adc@0 {
>>>>>> +            compatible = "st,stm32mp13-adc";
>>>>>> +            #io-channel-cells = <1>;
>>>>>>                #address-cells = <1>;
>>>>>>                #size-cells = <0>;
>>>>>> +            reg = <0x0>;
>>>>>> +            interrupt-parent = <&adc_1>;
>>>>>> +            interrupts = <0>;
>>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>> +            dma-names = "rx";
>>>>>>                status = "disabled";
>>>>>>    -            adc1: adc@0 {
>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>> -                #io-channel-cells = <1>;
>>>>>> -                #address-cells = <1>;
>>>>>> -                #size-cells = <0>;
>>>>>> -                reg = <0x0>;
>>>>>> -                interrupt-parent = <&adc_1>;
>>>>>> -                interrupts = <0>;
>>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>> -                dma-names = "rx";
>>>>>> -                status = "disabled";
>>>>>> -
>>>>>> -                channel@18 {
>>>>>> -                    reg = <18>;
>>>>>> -                    label = "vrefint";
>>>>>> -             ��  };
>>>>>> +            channel@18 {
>>>>>> +                reg = <18>;
>>>>>> +                label = "vrefint";
>>>>>>                };
>>>>>>            };
>>>>>>        };
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> @@ -4,15 +4,14 @@
>>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for 
>>>>>> STMicroelectronics.
>>>>>>     */
>>>>>>    -/ {
>>>>>> -    soc {
>>>>>> -        cryp: crypto@54002000 {
>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>> -            reg = <0x54002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> +&etzpc {
>>>>>> +    cryp: crypto@54002000 {
>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>> +        reg = <0x54002000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>> +        feature-domains = <&etzpc 42>;
>>>>>> +        status = "disabled";
>>>>>>        };
>>>>>>    };
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> @@ -4,15 +4,13 @@
>>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for 
>>>>>> STMicroelectronics.
>>>>>>     */
>>>>>>    -/ {
>>>>>> -    soc {
>>>>>> -        cryp: crypto@54002000 {
>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>> -            reg = <0x54002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> +&etzpc {
>>>>>> +    cryp: crypto@54002000 {
>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>> +        reg = <0x54002000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>> +        status = "disabled";
>>>>>>        };
>>>>>>    };
>>>>>
>>>>
>>>
>>> Regarding the patch itself, I can separate it in two patches.
>>> 1)Introduce ETZPC
>>> 2)Move peripherals under ETZPC
>>>
>>> Best regards,
>>> Gatien
>>>
>>

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  2023-02-27 11:26             ` Gatien CHEVALLIER
                               ` (2 preceding siblings ...)
  (?)
@ 2023-04-21 10:19             ` Oleksii Moisieiev via Alsa-devel
  -1 siblings, 0 replies; 93+ messages in thread
From: Oleksii Moisieiev via Alsa-devel @ 2023-04-21 10:19 UTC (permalink / raw)
  To: Gatien CHEVALLIER, Ahmad Fatoum, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team, Peng Fan


[-- Attachment #0: Type: message/rfc822, Size: 62669 bytes --]

From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
To: Gatien CHEVALLIER <gatien.chevallier@foss.st.com>, Ahmad Fatoum <a.fatoum@pengutronix.de>, "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>, "herbert@gondor.apana.org.au" <herbert@gondor.apana.org.au>, "davem@davemloft.net" <davem@davemloft.net>, "robh+dt@kernel.org" <robh+dt@kernel.org>, "krzysztof.kozlowski+dt@linaro.org" <krzysztof.kozlowski+dt@linaro.org>, "alexandre.torgue@foss.st.com" <alexandre.torgue@foss.st.com>, "vkoul@kernel.org" <vkoul@kernel.org>, "jic23@kernel.org" <jic23@kernel.org>, "olivier.moysan@foss.st.com" <olivier.moysan@foss.st.com>, "arnaud.pouliquen@foss.st.com" <arnaud.pouliquen@foss.st.com>, "mchehab@kernel.org" <mchehab@kernel.org>, "fabrice.gasnier@foss.st.com" <fabrice.gasnier@foss.st.com>, "ulf.hansson@linaro.org" <ulf.hansson@linaro.org>, "edumazet@google.com" <edumazet@google.com>, "kuba@kernel.org" <kuba@kernel.org>, "pabeni@redhat.com" <pabeni@redhat.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>, "linux-iio@vger.kernel.org" <linux-iio@vger.kernel.org>, "netdev@vger.kernel.org" <netdev@vger.kernel.org>, "linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>, "linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>, "linux-i2c@vger.kernel.org" <linux-i2c@vger.kernel.org>, "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>, "linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>, "linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>, "linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>, "linux-stm32@st-md-mailman.stormreply.com" <linux-stm32@st-md-mailman.stormreply.com>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-media@vger.kernel.org" <linux-media@vger.kernel.org>, Pengutronix Kernel Team <kernel@pengutronix.de>, Peng Fan <peng.fan@oss.nxp.com>
Subject: Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
Date: Fri, 21 Apr 2023 10:19:15 +0000
Message-ID: <a1ef17b0-1a8f-5633-de30-1d96130ccc66@epam.com>

Hello,

I'm just wandering what is the status of the Patch Series?

Cc'ed Peng Fang as he also has an interest in the domain-controller 
bindings.

Oleksii.

On 27.02.23 13:26, Gatien CHEVALLIER wrote:
> Hello Ahmad,
>
> Sorry for the delay :)
>
> On 2/13/23 12:27, Ahmad Fatoum wrote:
>> Hello Gatien,
>>
>> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>>> Hello Gatien,
>>>>>
>>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>>> The STM32 System Bus is an internal bus on which devices are 
>>>>>> connected.
>>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>>> and control access to the peripherals connected on it.
>>>>>>
>>>>>> For more information on which peripheral is securable, please read
>>>>>> the STM32MP13 reference manual.
>>>>>
>>>>> Diff is way too big. Please split up the alphabetic reordering 
>>>>> into its
>>>>> own commit, so actual functional changes are apparent.
>>>>
>>>> Ah, I see now that you are moving securable peripherals into a new 
>>>> bus.
>>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>>
>>>> Does this configuration even change dynamically? Why can't you 
>>>> implement
>>>> this binding in the bootloader and have Linux only see a DT where 
>>>> unavailable
>>>> nodes are status = "disabled"; secure-status = "okay"?
>>>>
>>>> For inspiration, see barebox' device tree fixups when devices are 
>>>> disabled
>>>> per fuse:
>>>>
>>>> https://urldefense.com/v3/__https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c*L122__;Iw!!GF_29dbcQIUBPA!2CT6VXNxfrLUg3mPkiAykgwwu8y8TVPaVa5FupuehHDyeuPvx4a2aNuMs-ayUCqP8q364P8u0GxYprlqwrvgvnXndYBmii57$ 
>>>> [elixir[.]bootlin[.]com]
>>>>
>>>> Cheers,
>>>> Ahmad
>>>
>>> This configuration can change dynamically. The binding will be 
>>> implemented in the bootloader, where the ETZPC is already 
>>> implemented as a bus in our downstream.
>>>
>>> I find the mentionned example valid.
>>>
>>> Now, why is it a bus? :D
>>>
>>> It is the result of the discussion on the previous submission by 
>>> Benjamin (Sorry for the lack of link but I saw that you participated 
>>> on these threads)+ we need the bus mechanism to control whether a 
>>> subnode should be probed or not. You can see it as a firewall bus.
>>>
>>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and 
>>> propagation through bridges to the APB bus. Therefore, I find it 
>>> relevant to consider it as a bus, what is your opinion?
>>>
>>> This patchset is a first step to the implementation of an API to 
>>> control accesses dynamically.
>>
>> I still don't get what's dynamic about this. Either:
>>
>>    - Configuration _can_ change while Linux is running: You'll need 
>> to do
>>      way more than what your current bus provides to somwhow 
>> synchronize state
>>      with the secure monitor; otherwise a newly secured device will 
>> cause the driver
>>      to trigger data aborts that you'll have to handle and unbind the 
>> driver.
>>      (like if a USB drive is yanked out).
>>
>>    - Configuration _can't_ change while Linux is running: You can 
>> have the bootloader
>>      fixup the device tree and Linux need not care at all about 
>> devices that the
>>      ETZPC is securing.
>>
>> My understanding is that the latter is your use case, so I don't see 
>> why we
>> even need the normal world to be aware of the partitioning.
>>
>> Cheers,
>> Ahmad
>>
> What about the case where we do not have a U-Boot/bootloader to fixup 
> the device tree?
>
> On the other hand, ETZPC is a hardware firewall and is on the bus. 
> Therefore, shouldn't it be represented as a bus in the file that 
> describes the hardware?
>
> Best regards,
> Gatien
>
>>>
>>>>
>>>>>
>>>>> Thanks,
>>>>> Ahmad
>>>>>
>>>>>>
>>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>>> ---
>>>>>>
>>>>>> No changes in V2.
>>>>>>
>>>>>> Changes in V3:
>>>>>>      -Use appriopriate node name: bus
>>>>>>
>>>>>>    arch/arm/boot/dts/stm32mp131.dtsi  | 407 
>>>>>> +++++++++++++++--------------
>>>>>>    arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>>    arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>>    arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>>    4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> index accc3824f7e9..24462a647101 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>>                dma-channels = <16>;
>>>>>>            };
>>>>>>    -        adc_2: adc@48004000 {
>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>> -            reg = <0x48004000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>> -            clock-names = "bus", "adc";
>>>>>> -            interrupt-controller;
>>>>>> -            #interrupt-cells = <1>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            status = "disabled";
>>>>>> -
>>>>>> -            adc2: adc@0 {
>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>> -                #io-channel-cells = <1>;
>>>>>> -                #address-cells = <1>;
>>>>>> -                #size-cells = <0>;
>>>>>> -                reg = <0x0>;
>>>>>> -                interrupt-parent = <&adc_2>;
>>>>>> -                interrupts = <0>;
>>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>> -                dma-names = "rx";
>>>>>> -                status = "disabled";
>>>>>> -
>>>>>> -                channel@13 {
>>>>>> -                    reg = <13>;
>>>>>> -                    label = "vrefint";
>>>>>> -                };
>>>>>> -                channel@14 {
>>>>>> -                    reg = <14>;
>>>>>> -                    label = "vddcore";
>>>>>> -                };
>>>>>> -                channel@16 {
>>>>>> -                    reg = <16>;
>>>>>> -                    label = "vddcpu";
>>>>>> -                };
>>>>>> -                channel@17 {
>>>>>> -                    reg = <17>;
>>>>>> -                    label = "vddq_ddr";
>>>>>> -                };
>>>>>> -            };
>>>>>> -        };
>>>>>> -
>>>>>> -        usbotg_hs: usb@49000000 {
>>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>> -            reg = <0x49000000 0x40000>;
>>>>>> -            clocks = <&rcc USBO_K>;
>>>>>> -            clock-names = "otg";
>>>>>> -            resets = <&rcc USBO_R>;
>>>>>> -            reset-names = "dwc2";
>>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            g-rx-fifo-size = <512>;
>>>>>> -            g-np-tx-fifo-size = <32>;
>>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>> -            dr_mode = "otg";
>>>>>> -            otg-rev = <0x200>;
>>>>>> -            usb33d-supply = <&usb33>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        spi4: spi@4c002000 {
>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>> -            reg = <0x4c002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SPI4_K>;
>>>>>> -            resets = <&rcc SPI4_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        spi5: spi@4c003000 {
>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>> -            reg = <0x4c003000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SPI5_K>;
>>>>>> -            resets = <&rcc SPI5_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c3: i2c@4c004000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c004000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C3_K>;
>>>>>> -            resets = <&rcc I2C3_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c4: i2c@4c005000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c005000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C4_K>;
>>>>>> -            resets = <&rcc I2C4_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        i2c5: i2c@4c006000 {
>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>> -            reg = <0x4c006000 0x400>;
>>>>>> -            interrupt-names = "event", "error";
>>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc I2C5_K>;
>>>>>> -            resets = <&rcc I2C5_R>;
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>>> -            dma-names = "rx", "tx";
>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>> -            i2c-analog-filter;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>>            rcc: rcc@50000000 {
>>>>>>                compatible = "st,stm32mp13-rcc", "syscon";
>>>>>>                reg = <0x50000000 0x1000>;
>>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>>                dma-requests = <48>;
>>>>>>            };
>>>>>>    -        sdmmc1: mmc@58005000 {
>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>>> -            clock-names = "apb_pclk";
>>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>>> -            cap-sd-highspeed;
>>>>>> -            cap-mmc-highspeed;
>>>>>> -            max-frequency = <130000000>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>> -        sdmmc2: mmc@58007000 {
>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>>> -            clock-names = "apb_pclk";
>>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>>> -            cap-sd-highspeed;
>>>>>> -            cap-mmc-highspeed;
>>>>>> -            max-frequency = <130000000>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> -
>>>>>>            usbh_ohci: usb@5800c000 {
>>>>>>                compatible = "generic-ohci";
>>>>>>                reg = <0x5800c000 0x1000>;
>>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>>                status = "disabled";
>>>>>>            };
>>>>>>    -        usbphyc: usbphyc@5a006000 {
>>>>>> -            #address-cells = <1>;
>>>>>> -            #size-cells = <0>;
>>>>>> -            #clock-cells = <0>;
>>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>>> -            reg = <0x5a006000 0x1000>;
>>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>>> -            resets = <&rcc USBPHY_R>;
>>>>>> -            vdda1v1-supply = <&reg11>;
>>>>>> -            vdda1v8-supply = <&reg18>;
>>>>>> -            status = "disabled";
>>>>>> -
>>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>>> -                #phy-cells = <0>;
>>>>>> -                reg = <0>;
>>>>>> -            };
>>>>>> -
>>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>>> -                #phy-cells = <1>;
>>>>>> -                reg = <1>;
>>>>>> -            };
>>>>>> -        };
>>>>>> -
>>>>>>            rtc: rtc@5c004000 {
>>>>>>                compatible = "st,stm32mp1-rtc";
>>>>>>                reg = <0x5c004000 0x400>;
>>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>>                };
>>>>>>            };
>>>>>>    +        etzpc: bus@5c007000 {
>>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>>> +            reg = <0x5c007000 0x400>;
>>>>>> +            #address-cells = <1>;
>>>>>> +            #size-cells = <1>;
>>>>>> +            feature-domain-controller;
>>>>>> +            #feature-domain-cells = <1>;
>>>>>> +            ranges;
>>>>>> +
>>>>>> +            adc_2: adc@48004000 {
>>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>>> +                reg = <0x48004000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>> +                clock-names = "bus", "adc";
>>>>>> +                interrupt-controller;
>>>>>> +                #interrupt-cells = <1>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                feature-domains = <&etzpc 33>;
>>>>>> +                status = "disabled";
>>>>>> +
>>>>>> +                adc2: adc@0 {
>>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>>> +                    #io-channel-cells = <1>;
>>>>>> +                    #address-cells = <1>;
>>>>>> +                    #size-cells = <0>;
>>>>>> +                    reg = <0x0>;
>>>>>> +                    interrupt-parent = <&adc_2>;
>>>>>> +                    interrupts = <0>;
>>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>> +                    dma-names = "rx";
>>>>>> +                    status = "disabled";
>>>>>> +
>>>>>> +                    channel@13 {
>>>>>> +                        reg = <13>;
>>>>>> +                        label = "vrefint";
>>>>>> +                    };
>>>>>> +                    channel@14 {
>>>>>> +                        reg = <14>;
>>>>>> +                        label = "vddcore";
>>>>>> +                    };
>>>>>> +                    channel@16 {
>>>>>> +                        reg = <16>;
>>>>>> +                        label = "vddcpu";
>>>>>> +                    };
>>>>>> +                    channel@17 {
>>>>>> +                        reg = <17>;
>>>>>> +                        label = "vddq_ddr";
>>>>>> +                    };
>>>>>> +                };
>>>>>> +            };
>>>>>> +
>>>>>> +            usbotg_hs: usb@49000000 {
>>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>> +                reg = <0x49000000 0x40000>;
>>>>>> +                clocks = <&rcc USBO_K>;
>>>>>> +                clock-names = "otg";
>>>>>> +                resets = <&rcc USBO_R>;
>>>>>> +                reset-names = "dwc2";
>>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                g-rx-fifo-size = <512>;
>>>>>> +                g-np-tx-fifo-size = <32>;
>>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>> +                dr_mode = "otg";
>>>>>> +                otg-rev = <0x200>;
>>>>>> +                usb33d-supply = <&usb33>;
>>>>>> +                feature-domains = <&etzpc 34>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            spi4: spi@4c002000 {
>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>> +                reg = <0x4c002000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SPI4_K>;
>>>>>> +                resets = <&rcc SPI4_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                feature-domains = <&etzpc 18>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            spi5: spi@4c003000 {
>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>> +                reg = <0x4c003000 0x400>;
>>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SPI5_K>;
>>>>>> +                resets = <&rcc SPI5_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                feature-domains = <&etzpc 19>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c3: i2c@4c004000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c004000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C3_K>;
>>>>>> +                resets = <&rcc I2C3_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 20>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c4: i2c@4c005000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c005000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C4_K>;
>>>>>> +                resets = <&rcc I2C4_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 21>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            i2c5: i2c@4c006000 {
>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>> +                reg = <0x4c006000 0x400>;
>>>>>> +                interrupt-names = "event", "error";
>>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc I2C5_K>;
>>>>>> +                resets = <&rcc I2C5_R>;
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>>> +                dma-names = "rx", "tx";
>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>> +                i2c-analog-filter;
>>>>>> +                feature-domains = <&etzpc 22>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            sdmmc1: mmc@58005000 {
>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>>> +                clock-names = "apb_pclk";
>>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>>> +                cap-sd-highspeed;
>>>>>> +                cap-mmc-highspeed;
>>>>>> +                max-frequency = <130000000>;
>>>>>> +                feature-domains = <&etzpc 50>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            sdmmc2: mmc@58007000 {
>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x", 
>>>>>> "arm,primecell";
>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>>> +                clock-names = "apb_pclk";
>>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>>> +                cap-sd-highspeed;
>>>>>> +                cap-mmc-highspeed;
>>>>>> +                max-frequency = <130000000>;
>>>>>> +                feature-domains = <&etzpc 51>;
>>>>>> +                status = "disabled";
>>>>>> +            };
>>>>>> +
>>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>>> +                #address-cells = <1>;
>>>>>> +                #size-cells = <0>;
>>>>>> +                #clock-cells = <0>;
>>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>>> +                reg = <0x5a006000 0x1000>;
>>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>>> +                resets = <&rcc USBPHY_R>;
>>>>>> +                vdda1v1-supply = <&reg11>;
>>>>>> +                vdda1v8-supply = <&reg18>;
>>>>>> +                feature-domains = <&etzpc 5>;
>>>>>> +                status = "disabled";
>>>>>> +
>>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>>> +                    #phy-cells = <0>;
>>>>>> +                    reg = <0>;
>>>>>> +                };
>>>>>> +
>>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>>> +                    #phy-cells = <1>;
>>>>>> +                    reg = <1>;
>>>>>> +                };
>>>>>> +            };
>>>>>> +
>>>>>> +        };
>>>>>> +
>>>>>>            /*
>>>>>>             * Break node order to solve dependency probe issue 
>>>>>> between
>>>>>>             * pinctrl and exti.
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> index df451c3c2a26..be6061552683 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>>                bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>>                status = "disabled";
>>>>>>            };
>>>>>> +    };
>>>>>> +};
>>>>>>    -        adc_1: adc@48003000 {
>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>> -            reg = <0x48003000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>> -            clock-names = "bus", "adc";
>>>>>> -            interrupt-controller;
>>>>>> -            #interrupt-cells = <1>;
>>>>>> +&etzpc {
>>>>>> +    adc_1: adc@48003000 {
>>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>>> +        reg = <0x48003000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>> +        clock-names = "bus", "adc";
>>>>>> +        interrupt-controller;
>>>>>> +        #interrupt-cells = <1>;
>>>>>> +        #address-cells = <1>;
>>>>>> +        #size-cells = <0>;
>>>>>> +        feature-domains = <&etzpc 32>;
>>>>>> +        status = "disabled";
>>>>>> +
>>>>>> +        adc1: adc@0 {
>>>>>> +            compatible = "st,stm32mp13-adc";
>>>>>> +            #io-channel-cells = <1>;
>>>>>>                #address-cells = <1>;
>>>>>>                #size-cells = <0>;
>>>>>> +            reg = <0x0>;
>>>>>> +            interrupt-parent = <&adc_1>;
>>>>>> +            interrupts = <0>;
>>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>> +            dma-names = "rx";
>>>>>>                status = "disabled";
>>>>>>    -            adc1: adc@0 {
>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>> -                #io-channel-cells = <1>;
>>>>>> -                #address-cells = <1>;
>>>>>> -                #size-cells = <0>;
>>>>>> -                reg = <0x0>;
>>>>>> -                interrupt-parent = <&adc_1>;
>>>>>> -                interrupts = <0>;
>>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>> -                dma-names = "rx";
>>>>>> -                status = "disabled";
>>>>>> -
>>>>>> -                channel@18 {
>>>>>> -                    reg = <18>;
>>>>>> -                    label = "vrefint";
>>>>>> -             ��  };
>>>>>> +            channel@18 {
>>>>>> +                reg = <18>;
>>>>>> +                label = "vrefint";
>>>>>>                };
>>>>>>            };
>>>>>>        };
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>> @@ -4,15 +4,14 @@
>>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for 
>>>>>> STMicroelectronics.
>>>>>>     */
>>>>>>    -/ {
>>>>>> -    soc {
>>>>>> -        cryp: crypto@54002000 {
>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>> -            reg = <0x54002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> +&etzpc {
>>>>>> +    cryp: crypto@54002000 {
>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>> +        reg = <0x54002000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>> +        feature-domains = <&etzpc 42>;
>>>>>> +        status = "disabled";
>>>>>>        };
>>>>>>    };
>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi 
>>>>>> b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>> @@ -4,15 +4,13 @@
>>>>>>     * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for 
>>>>>> STMicroelectronics.
>>>>>>     */
>>>>>>    -/ {
>>>>>> -    soc {
>>>>>> -        cryp: crypto@54002000 {
>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>> -            reg = <0x54002000 0x400>;
>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>> -            status = "disabled";
>>>>>> -        };
>>>>>> +&etzpc {
>>>>>> +    cryp: crypto@54002000 {
>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>> +        reg = <0x54002000 0x400>;
>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>> +        status = "disabled";
>>>>>>        };
>>>>>>    };
>>>>>
>>>>
>>>
>>> Regarding the patch itself, I can separate it in two patches.
>>> 1)Introduce ETZPC
>>> 2)Move peripherals under ETZPC
>>>
>>> Best regards,
>>> Gatien
>>>
>>

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
  2023-04-21 10:19               ` Oleksii Moisieiev
  (?)
@ 2023-04-25  7:56                 ` Gatien CHEVALLIER
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-04-25  7:56 UTC (permalink / raw)
  To: Oleksii Moisieiev, Ahmad Fatoum, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team, Peng Fan

On 4/21/23 12:19, Oleksii Moisieiev wrote:
> Hello,
> 
> I'm just wandering what is the status of the Patch Series?
> 
> Cc'ed Peng Fang as he also has an interest in the domain-controller
> bindings.
> 
> Oleksii.
>

Hello Oleksii,

I need to rework this patch series before resubmitting it. I did not 
forget it :) I'd like to provide a good use-case on how to property can 
be used and maybe narrow down its perimeter/use-cases.

Peng, to which extent are you interested in this binding? What would be 
your use-case?

Best regards,
Gatien

> On 27.02.23 13:26, Gatien CHEVALLIER wrote:
>> Hello Ahmad,
>>
>> Sorry for the delay :)
>>
>> On 2/13/23 12:27, Ahmad Fatoum wrote:
>>> Hello Gatien,
>>>
>>> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>>>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>>>> Hello Gatien,
>>>>>>
>>>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>>>> The STM32 System Bus is an internal bus on which devices are
>>>>>>> connected.
>>>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>>>> and control access to the peripherals connected on it.
>>>>>>>
>>>>>>> For more information on which peripheral is securable, please read
>>>>>>> the STM32MP13 reference manual.
>>>>>>
>>>>>> Diff is way too big. Please split up the alphabetic reordering
>>>>>> into its
>>>>>> own commit, so actual functional changes are apparent.
>>>>>
>>>>> Ah, I see now that you are moving securable peripherals into a new
>>>>> bus.
>>>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>>>
>>>>> Does this configuration even change dynamically? Why can't you
>>>>> implement
>>>>> this binding in the bootloader and have Linux only see a DT where
>>>>> unavailable
>>>>> nodes are status = "disabled"; secure-status = "okay"?
>>>>>
>>>>> For inspiration, see barebox' device tree fixups when devices are
>>>>> disabled
>>>>> per fuse:
>>>>>
>>>>> https://urldefense.com/v3/__https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c*L122__;Iw!!GF_29dbcQIUBPA!2CT6VXNxfrLUg3mPkiAykgwwu8y8TVPaVa5FupuehHDyeuPvx4a2aNuMs-ayUCqP8q364P8u0GxYprlqwrvgvnXndYBmii57$
>>>>> [elixir[.]bootlin[.]com]
>>>>>
>>>>> Cheers,
>>>>> Ahmad
>>>>
>>>> This configuration can change dynamically. The binding will be
>>>> implemented in the bootloader, where the ETZPC is already
>>>> implemented as a bus in our downstream.
>>>>
>>>> I find the mentionned example valid.
>>>>
>>>> Now, why is it a bus? :D
>>>>
>>>> It is the result of the discussion on the previous submission by
>>>> Benjamin (Sorry for the lack of link but I saw that you participated
>>>> on these threads)+ we need the bus mechanism to control whether a
>>>> subnode should be probed or not. You can see it as a firewall bus.
>>>>
>>>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and
>>>> propagation through bridges to the APB bus. Therefore, I find it
>>>> relevant to consider it as a bus, what is your opinion?
>>>>
>>>> This patchset is a first step to the implementation of an API to
>>>> control accesses dynamically.
>>>
>>> I still don't get what's dynamic about this. Either:
>>>
>>>     - Configuration _can_ change while Linux is running: You'll need
>>> to do
>>>       way more than what your current bus provides to somwhow
>>> synchronize state
>>>       with the secure monitor; otherwise a newly secured device will
>>> cause the driver
>>>       to trigger data aborts that you'll have to handle and unbind the
>>> driver.
>>>       (like if a USB drive is yanked out).
>>>
>>>     - Configuration _can't_ change while Linux is running: You can
>>> have the bootloader
>>>       fixup the device tree and Linux need not care at all about
>>> devices that the
>>>       ETZPC is securing.
>>>
>>> My understanding is that the latter is your use case, so I don't see
>>> why we
>>> even need the normal world to be aware of the partitioning.
>>>
>>> Cheers,
>>> Ahmad
>>>
>> What about the case where we do not have a U-Boot/bootloader to fixup
>> the device tree?
>>
>> On the other hand, ETZPC is a hardware firewall and is on the bus.
>> Therefore, shouldn't it be represented as a bus in the file that
>> describes the hardware?
>>
>> Best regards,
>> Gatien
>>
>>>>
>>>>>
>>>>>>
>>>>>> Thanks,
>>>>>> Ahmad
>>>>>>
>>>>>>>
>>>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>>>> ---
>>>>>>>
>>>>>>> No changes in V2.
>>>>>>>
>>>>>>> Changes in V3:
>>>>>>>       -Use appriopriate node name: bus
>>>>>>>
>>>>>>>     arch/arm/boot/dts/stm32mp131.dtsi  | 407
>>>>>>> +++++++++++++++--------------
>>>>>>>     arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>>>     arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>>>     arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>>>     4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> index accc3824f7e9..24462a647101 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>>>                 dma-channels = <16>;
>>>>>>>             };
>>>>>>>     -        adc_2: adc@48004000 {
>>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>>> -            reg = <0x48004000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>>> -            clock-names = "bus", "adc";
>>>>>>> -            interrupt-controller;
>>>>>>> -            #interrupt-cells = <1>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            status = "disabled";
>>>>>>> -
>>>>>>> -            adc2: adc@0 {
>>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>>> -                #io-channel-cells = <1>;
>>>>>>> -                #address-cells = <1>;
>>>>>>> -                #size-cells = <0>;
>>>>>>> -                reg = <0x0>;
>>>>>>> -                interrupt-parent = <&adc_2>;
>>>>>>> -                interrupts = <0>;
>>>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>>> -                dma-names = "rx";
>>>>>>> -                status = "disabled";
>>>>>>> -
>>>>>>> -                channel@13 {
>>>>>>> -                    reg = <13>;
>>>>>>> -                    label = "vrefint";
>>>>>>> -                };
>>>>>>> -                channel@14 {
>>>>>>> -                    reg = <14>;
>>>>>>> -                    label = "vddcore";
>>>>>>> -                };
>>>>>>> -                channel@16 {
>>>>>>> -                    reg = <16>;
>>>>>>> -                    label = "vddcpu";
>>>>>>> -                };
>>>>>>> -                channel@17 {
>>>>>>> -                    reg = <17>;
>>>>>>> -                    label = "vddq_ddr";
>>>>>>> -                };
>>>>>>> -            };
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        usbotg_hs: usb@49000000 {
>>>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>>> -            reg = <0x49000000 0x40000>;
>>>>>>> -            clocks = <&rcc USBO_K>;
>>>>>>> -            clock-names = "otg";
>>>>>>> -            resets = <&rcc USBO_R>;
>>>>>>> -            reset-names = "dwc2";
>>>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            g-rx-fifo-size = <512>;
>>>>>>> -            g-np-tx-fifo-size = <32>;
>>>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>>> -            dr_mode = "otg";
>>>>>>> -            otg-rev = <0x200>;
>>>>>>> -            usb33d-supply = <&usb33>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        spi4: spi@4c002000 {
>>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>>> -            reg = <0x4c002000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SPI4_K>;
>>>>>>> -            resets = <&rcc SPI4_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        spi5: spi@4c003000 {
>>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>>> -            reg = <0x4c003000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SPI5_K>;
>>>>>>> -            resets = <&rcc SPI5_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        i2c3: i2c@4c004000 {
>>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>>> -            reg = <0x4c004000 0x400>;
>>>>>>> -            interrupt-names = "event", "error";
>>>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc I2C3_K>;
>>>>>>> -            resets = <&rcc I2C3_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>>> -            i2c-analog-filter;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        i2c4: i2c@4c005000 {
>>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>>> -            reg = <0x4c005000 0x400>;
>>>>>>> -            interrupt-names = "event", "error";
>>>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc I2C4_K>;
>>>>>>> -            resets = <&rcc I2C4_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>>> -            i2c-analog-filter;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        i2c5: i2c@4c006000 {
>>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>>> -            reg = <0x4c006000 0x400>;
>>>>>>> -            interrupt-names = "event", "error";
>>>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc I2C5_K>;
>>>>>>> -            resets = <&rcc I2C5_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>>> -            i2c-analog-filter;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>>             rcc: rcc@50000000 {
>>>>>>>                 compatible = "st,stm32mp13-rcc", "syscon";
>>>>>>>                 reg = <0x50000000 0x1000>;
>>>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>>>                 dma-requests = <48>;
>>>>>>>             };
>>>>>>>     -        sdmmc1: mmc@58005000 {
>>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>>>> -            clock-names = "apb_pclk";
>>>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>>>> -            cap-sd-highspeed;
>>>>>>> -            cap-mmc-highspeed;
>>>>>>> -            max-frequency = <130000000>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        sdmmc2: mmc@58007000 {
>>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>>>> -            clock-names = "apb_pclk";
>>>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>>>> -            cap-sd-highspeed;
>>>>>>> -            cap-mmc-highspeed;
>>>>>>> -            max-frequency = <130000000>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>>             usbh_ohci: usb@5800c000 {
>>>>>>>                 compatible = "generic-ohci";
>>>>>>>                 reg = <0x5800c000 0x1000>;
>>>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>>>                 status = "disabled";
>>>>>>>             };
>>>>>>>     -        usbphyc: usbphyc@5a006000 {
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            #clock-cells = <0>;
>>>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>>>> -            reg = <0x5a006000 0x1000>;
>>>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>>>> -            resets = <&rcc USBPHY_R>;
>>>>>>> -            vdda1v1-supply = <&reg11>;
>>>>>>> -            vdda1v8-supply = <&reg18>;
>>>>>>> -            status = "disabled";
>>>>>>> -
>>>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>>>> -                #phy-cells = <0>;
>>>>>>> -                reg = <0>;
>>>>>>> -            };
>>>>>>> -
>>>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>>>> -                #phy-cells = <1>;
>>>>>>> -                reg = <1>;
>>>>>>> -            };
>>>>>>> -        };
>>>>>>> -
>>>>>>>             rtc: rtc@5c004000 {
>>>>>>>                 compatible = "st,stm32mp1-rtc";
>>>>>>>                 reg = <0x5c004000 0x400>;
>>>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>>>                 };
>>>>>>>             };
>>>>>>>     +        etzpc: bus@5c007000 {
>>>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>>>> +            reg = <0x5c007000 0x400>;
>>>>>>> +            #address-cells = <1>;
>>>>>>> +            #size-cells = <1>;
>>>>>>> +            feature-domain-controller;
>>>>>>> +            #feature-domain-cells = <1>;
>>>>>>> +            ranges;
>>>>>>> +
>>>>>>> +            adc_2: adc@48004000 {
>>>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>>>> +                reg = <0x48004000 0x400>;
>>>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>>> +                clock-names = "bus", "adc";
>>>>>>> +                interrupt-controller;
>>>>>>> +                #interrupt-cells = <1>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                feature-domains = <&etzpc 33>;
>>>>>>> +                status = "disabled";
>>>>>>> +
>>>>>>> +                adc2: adc@0 {
>>>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>>>> +                    #io-channel-cells = <1>;
>>>>>>> +                    #address-cells = <1>;
>>>>>>> +                    #size-cells = <0>;
>>>>>>> +                    reg = <0x0>;
>>>>>>> +                    interrupt-parent = <&adc_2>;
>>>>>>> +                    interrupts = <0>;
>>>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>>> +                    dma-names = "rx";
>>>>>>> +                    status = "disabled";
>>>>>>> +
>>>>>>> +                    channel@13 {
>>>>>>> +                        reg = <13>;
>>>>>>> +                        label = "vrefint";
>>>>>>> +                    };
>>>>>>> +                    channel@14 {
>>>>>>> +                        reg = <14>;
>>>>>>> +                        label = "vddcore";
>>>>>>> +                    };
>>>>>>> +                    channel@16 {
>>>>>>> +                        reg = <16>;
>>>>>>> +                        label = "vddcpu";
>>>>>>> +                    };
>>>>>>> +                    channel@17 {
>>>>>>> +                        reg = <17>;
>>>>>>> +                        label = "vddq_ddr";
>>>>>>> +                    };
>>>>>>> +                };
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            usbotg_hs: usb@49000000 {
>>>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>>> +                reg = <0x49000000 0x40000>;
>>>>>>> +                clocks = <&rcc USBO_K>;
>>>>>>> +                clock-names = "otg";
>>>>>>> +                resets = <&rcc USBO_R>;
>>>>>>> +                reset-names = "dwc2";
>>>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                g-rx-fifo-size = <512>;
>>>>>>> +                g-np-tx-fifo-size = <32>;
>>>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>>> +                dr_mode = "otg";
>>>>>>> +                otg-rev = <0x200>;
>>>>>>> +                usb33d-supply = <&usb33>;
>>>>>>> +                feature-domains = <&etzpc 34>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            spi4: spi@4c002000 {
>>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>>> +                reg = <0x4c002000 0x400>;
>>>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SPI4_K>;
>>>>>>> +                resets = <&rcc SPI4_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                feature-domains = <&etzpc 18>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            spi5: spi@4c003000 {
>>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>>> +                reg = <0x4c003000 0x400>;
>>>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SPI5_K>;
>>>>>>> +                resets = <&rcc SPI5_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                feature-domains = <&etzpc 19>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            i2c3: i2c@4c004000 {
>>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>>> +                reg = <0x4c004000 0x400>;
>>>>>>> +                interrupt-names = "event", "error";
>>>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc I2C3_K>;
>>>>>>> +                resets = <&rcc I2C3_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>>> +                i2c-analog-filter;
>>>>>>> +                feature-domains = <&etzpc 20>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            i2c4: i2c@4c005000 {
>>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>>> +                reg = <0x4c005000 0x400>;
>>>>>>> +                interrupt-names = "event", "error";
>>>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc I2C4_K>;
>>>>>>> +                resets = <&rcc I2C4_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>>> +                i2c-analog-filter;
>>>>>>> +                feature-domains = <&etzpc 21>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            i2c5: i2c@4c006000 {
>>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>>> +                reg = <0x4c006000 0x400>;
>>>>>>> +                interrupt-names = "event", "error";
>>>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc I2C5_K>;
>>>>>>> +                resets = <&rcc I2C5_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>>> +                i2c-analog-filter;
>>>>>>> +                feature-domains = <&etzpc 22>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            sdmmc1: mmc@58005000 {
>>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>>>> +                clock-names = "apb_pclk";
>>>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>>>> +                cap-sd-highspeed;
>>>>>>> +                cap-mmc-highspeed;
>>>>>>> +                max-frequency = <130000000>;
>>>>>>> +                feature-domains = <&etzpc 50>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            sdmmc2: mmc@58007000 {
>>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>>>> +                clock-names = "apb_pclk";
>>>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>>>> +                cap-sd-highspeed;
>>>>>>> +                cap-mmc-highspeed;
>>>>>>> +                max-frequency = <130000000>;
>>>>>>> +                feature-domains = <&etzpc 51>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                #clock-cells = <0>;
>>>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>>>> +                reg = <0x5a006000 0x1000>;
>>>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>>>> +                resets = <&rcc USBPHY_R>;
>>>>>>> +                vdda1v1-supply = <&reg11>;
>>>>>>> +                vdda1v8-supply = <&reg18>;
>>>>>>> +                feature-domains = <&etzpc 5>;
>>>>>>> +                status = "disabled";
>>>>>>> +
>>>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>>>> +                    #phy-cells = <0>;
>>>>>>> +                    reg = <0>;
>>>>>>> +                };
>>>>>>> +
>>>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>>>> +                    #phy-cells = <1>;
>>>>>>> +                    reg = <1>;
>>>>>>> +                };
>>>>>>> +            };
>>>>>>> +
>>>>>>> +        };
>>>>>>> +
>>>>>>>             /*
>>>>>>>              * Break node order to solve dependency probe issue
>>>>>>> between
>>>>>>>              * pinctrl and exti.
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> index df451c3c2a26..be6061552683 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>>>                 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>>>                 status = "disabled";
>>>>>>>             };
>>>>>>> +    };
>>>>>>> +};
>>>>>>>     -        adc_1: adc@48003000 {
>>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>>> -            reg = <0x48003000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>>> -            clock-names = "bus", "adc";
>>>>>>> -            interrupt-controller;
>>>>>>> -            #interrupt-cells = <1>;
>>>>>>> +&etzpc {
>>>>>>> +    adc_1: adc@48003000 {
>>>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>>>> +        reg = <0x48003000 0x400>;
>>>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>>> +        clock-names = "bus", "adc";
>>>>>>> +        interrupt-controller;
>>>>>>> +        #interrupt-cells = <1>;
>>>>>>> +        #address-cells = <1>;
>>>>>>> +        #size-cells = <0>;
>>>>>>> +        feature-domains = <&etzpc 32>;
>>>>>>> +        status = "disabled";
>>>>>>> +
>>>>>>> +        adc1: adc@0 {
>>>>>>> +            compatible = "st,stm32mp13-adc";
>>>>>>> +            #io-channel-cells = <1>;
>>>>>>>                 #address-cells = <1>;
>>>>>>>                 #size-cells = <0>;
>>>>>>> +            reg = <0x0>;
>>>>>>> +            interrupt-parent = <&adc_1>;
>>>>>>> +            interrupts = <0>;
>>>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>>> +            dma-names = "rx";
>>>>>>>                 status = "disabled";
>>>>>>>     -            adc1: adc@0 {
>>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>>> -                #io-channel-cells = <1>;
>>>>>>> -                #address-cells = <1>;
>>>>>>> -                #size-cells = <0>;
>>>>>>> -                reg = <0x0>;
>>>>>>> -                interrupt-parent = <&adc_1>;
>>>>>>> -                interrupts = <0>;
>>>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>>> -                dma-names = "rx";
>>>>>>> -                status = "disabled";
>>>>>>> -
>>>>>>> -                channel@18 {
>>>>>>> -                    reg = <18>;
>>>>>>> -                    label = "vrefint";
>>>>>>> -             ��  };
>>>>>>> +            channel@18 {
>>>>>>> +                reg = <18>;
>>>>>>> +                label = "vrefint";
>>>>>>>                 };
>>>>>>>             };
>>>>>>>         };
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> @@ -4,15 +4,14 @@
>>>>>>>      * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for
>>>>>>> STMicroelectronics.
>>>>>>>      */
>>>>>>>     -/ {
>>>>>>> -    soc {
>>>>>>> -        cryp: crypto@54002000 {
>>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>>> -            reg = <0x54002000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> +&etzpc {
>>>>>>> +    cryp: crypto@54002000 {
>>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>>> +        reg = <0x54002000 0x400>;
>>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>>> +        feature-domains = <&etzpc 42>;
>>>>>>> +        status = "disabled";
>>>>>>>         };
>>>>>>>     };
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> @@ -4,15 +4,13 @@
>>>>>>>      * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for
>>>>>>> STMicroelectronics.
>>>>>>>      */
>>>>>>>     -/ {
>>>>>>> -    soc {
>>>>>>> -        cryp: crypto@54002000 {
>>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>>> -            reg = <0x54002000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> +&etzpc {
>>>>>>> +    cryp: crypto@54002000 {
>>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>>> +        reg = <0x54002000 0x400>;
>>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>>> +        status = "disabled";
>>>>>>>         };
>>>>>>>     };
>>>>>>
>>>>>
>>>>
>>>> Regarding the patch itself, I can separate it in two patches.
>>>> 1)Introduce ETZPC
>>>> 2)Move peripherals under ETZPC
>>>>
>>>> Best regards,
>>>> Gatien
>>>>
>> >

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-04-25  7:56                 ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-04-25  7:56 UTC (permalink / raw)
  To: Oleksii Moisieiev, Ahmad Fatoum, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team, Peng Fan

On 4/21/23 12:19, Oleksii Moisieiev wrote:
> Hello,
> 
> I'm just wandering what is the status of the Patch Series?
> 
> Cc'ed Peng Fang as he also has an interest in the domain-controller
> bindings.
> 
> Oleksii.
>

Hello Oleksii,

I need to rework this patch series before resubmitting it. I did not 
forget it :) I'd like to provide a good use-case on how to property can 
be used and maybe narrow down its perimeter/use-cases.

Peng, to which extent are you interested in this binding? What would be 
your use-case?

Best regards,
Gatien

> On 27.02.23 13:26, Gatien CHEVALLIER wrote:
>> Hello Ahmad,
>>
>> Sorry for the delay :)
>>
>> On 2/13/23 12:27, Ahmad Fatoum wrote:
>>> Hello Gatien,
>>>
>>> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>>>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>>>> Hello Gatien,
>>>>>>
>>>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>>>> The STM32 System Bus is an internal bus on which devices are
>>>>>>> connected.
>>>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>>>> and control access to the peripherals connected on it.
>>>>>>>
>>>>>>> For more information on which peripheral is securable, please read
>>>>>>> the STM32MP13 reference manual.
>>>>>>
>>>>>> Diff is way too big. Please split up the alphabetic reordering
>>>>>> into its
>>>>>> own commit, so actual functional changes are apparent.
>>>>>
>>>>> Ah, I see now that you are moving securable peripherals into a new
>>>>> bus.
>>>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>>>
>>>>> Does this configuration even change dynamically? Why can't you
>>>>> implement
>>>>> this binding in the bootloader and have Linux only see a DT where
>>>>> unavailable
>>>>> nodes are status = "disabled"; secure-status = "okay"?
>>>>>
>>>>> For inspiration, see barebox' device tree fixups when devices are
>>>>> disabled
>>>>> per fuse:
>>>>>
>>>>> https://urldefense.com/v3/__https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c*L122__;Iw!!GF_29dbcQIUBPA!2CT6VXNxfrLUg3mPkiAykgwwu8y8TVPaVa5FupuehHDyeuPvx4a2aNuMs-ayUCqP8q364P8u0GxYprlqwrvgvnXndYBmii57$
>>>>> [elixir[.]bootlin[.]com]
>>>>>
>>>>> Cheers,
>>>>> Ahmad
>>>>
>>>> This configuration can change dynamically. The binding will be
>>>> implemented in the bootloader, where the ETZPC is already
>>>> implemented as a bus in our downstream.
>>>>
>>>> I find the mentionned example valid.
>>>>
>>>> Now, why is it a bus? :D
>>>>
>>>> It is the result of the discussion on the previous submission by
>>>> Benjamin (Sorry for the lack of link but I saw that you participated
>>>> on these threads)+ we need the bus mechanism to control whether a
>>>> subnode should be probed or not. You can see it as a firewall bus.
>>>>
>>>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and
>>>> propagation through bridges to the APB bus. Therefore, I find it
>>>> relevant to consider it as a bus, what is your opinion?
>>>>
>>>> This patchset is a first step to the implementation of an API to
>>>> control accesses dynamically.
>>>
>>> I still don't get what's dynamic about this. Either:
>>>
>>>     - Configuration _can_ change while Linux is running: You'll need
>>> to do
>>>       way more than what your current bus provides to somwhow
>>> synchronize state
>>>       with the secure monitor; otherwise a newly secured device will
>>> cause the driver
>>>       to trigger data aborts that you'll have to handle and unbind the
>>> driver.
>>>       (like if a USB drive is yanked out).
>>>
>>>     - Configuration _can't_ change while Linux is running: You can
>>> have the bootloader
>>>       fixup the device tree and Linux need not care at all about
>>> devices that the
>>>       ETZPC is securing.
>>>
>>> My understanding is that the latter is your use case, so I don't see
>>> why we
>>> even need the normal world to be aware of the partitioning.
>>>
>>> Cheers,
>>> Ahmad
>>>
>> What about the case where we do not have a U-Boot/bootloader to fixup
>> the device tree?
>>
>> On the other hand, ETZPC is a hardware firewall and is on the bus.
>> Therefore, shouldn't it be represented as a bus in the file that
>> describes the hardware?
>>
>> Best regards,
>> Gatien
>>
>>>>
>>>>>
>>>>>>
>>>>>> Thanks,
>>>>>> Ahmad
>>>>>>
>>>>>>>
>>>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>>>> ---
>>>>>>>
>>>>>>> No changes in V2.
>>>>>>>
>>>>>>> Changes in V3:
>>>>>>>       -Use appriopriate node name: bus
>>>>>>>
>>>>>>>     arch/arm/boot/dts/stm32mp131.dtsi  | 407
>>>>>>> +++++++++++++++--------------
>>>>>>>     arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>>>     arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>>>     arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>>>     4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> index accc3824f7e9..24462a647101 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>>>                 dma-channels = <16>;
>>>>>>>             };
>>>>>>>     -        adc_2: adc@48004000 {
>>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>>> -            reg = <0x48004000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>>> -            clock-names = "bus", "adc";
>>>>>>> -            interrupt-controller;
>>>>>>> -            #interrupt-cells = <1>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            status = "disabled";
>>>>>>> -
>>>>>>> -            adc2: adc@0 {
>>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>>> -                #io-channel-cells = <1>;
>>>>>>> -                #address-cells = <1>;
>>>>>>> -                #size-cells = <0>;
>>>>>>> -                reg = <0x0>;
>>>>>>> -                interrupt-parent = <&adc_2>;
>>>>>>> -                interrupts = <0>;
>>>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>>> -                dma-names = "rx";
>>>>>>> -                status = "disabled";
>>>>>>> -
>>>>>>> -                channel@13 {
>>>>>>> -                    reg = <13>;
>>>>>>> -                    label = "vrefint";
>>>>>>> -                };
>>>>>>> -                channel@14 {
>>>>>>> -                    reg = <14>;
>>>>>>> -                    label = "vddcore";
>>>>>>> -                };
>>>>>>> -                channel@16 {
>>>>>>> -                    reg = <16>;
>>>>>>> -                    label = "vddcpu";
>>>>>>> -                };
>>>>>>> -                channel@17 {
>>>>>>> -                    reg = <17>;
>>>>>>> -                    label = "vddq_ddr";
>>>>>>> -                };
>>>>>>> -            };
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        usbotg_hs: usb@49000000 {
>>>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>>> -            reg = <0x49000000 0x40000>;
>>>>>>> -            clocks = <&rcc USBO_K>;
>>>>>>> -            clock-names = "otg";
>>>>>>> -            resets = <&rcc USBO_R>;
>>>>>>> -            reset-names = "dwc2";
>>>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            g-rx-fifo-size = <512>;
>>>>>>> -            g-np-tx-fifo-size = <32>;
>>>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>>> -            dr_mode = "otg";
>>>>>>> -            otg-rev = <0x200>;
>>>>>>> -            usb33d-supply = <&usb33>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        spi4: spi@4c002000 {
>>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>>> -            reg = <0x4c002000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SPI4_K>;
>>>>>>> -            resets = <&rcc SPI4_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        spi5: spi@4c003000 {
>>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>>> -            reg = <0x4c003000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SPI5_K>;
>>>>>>> -            resets = <&rcc SPI5_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        i2c3: i2c@4c004000 {
>>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>>> -            reg = <0x4c004000 0x400>;
>>>>>>> -            interrupt-names = "event", "error";
>>>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc I2C3_K>;
>>>>>>> -            resets = <&rcc I2C3_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>>> -            i2c-analog-filter;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        i2c4: i2c@4c005000 {
>>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>>> -            reg = <0x4c005000 0x400>;
>>>>>>> -            interrupt-names = "event", "error";
>>>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc I2C4_K>;
>>>>>>> -            resets = <&rcc I2C4_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>>> -            i2c-analog-filter;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        i2c5: i2c@4c006000 {
>>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>>> -            reg = <0x4c006000 0x400>;
>>>>>>> -            interrupt-names = "event", "error";
>>>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc I2C5_K>;
>>>>>>> -            resets = <&rcc I2C5_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>>> -            i2c-analog-filter;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>>             rcc: rcc@50000000 {
>>>>>>>                 compatible = "st,stm32mp13-rcc", "syscon";
>>>>>>>                 reg = <0x50000000 0x1000>;
>>>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>>>                 dma-requests = <48>;
>>>>>>>             };
>>>>>>>     -        sdmmc1: mmc@58005000 {
>>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>>>> -            clock-names = "apb_pclk";
>>>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>>>> -            cap-sd-highspeed;
>>>>>>> -            cap-mmc-highspeed;
>>>>>>> -            max-frequency = <130000000>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        sdmmc2: mmc@58007000 {
>>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>>>> -            clock-names = "apb_pclk";
>>>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>>>> -            cap-sd-highspeed;
>>>>>>> -            cap-mmc-highspeed;
>>>>>>> -            max-frequency = <130000000>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>>             usbh_ohci: usb@5800c000 {
>>>>>>>                 compatible = "generic-ohci";
>>>>>>>                 reg = <0x5800c000 0x1000>;
>>>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>>>                 status = "disabled";
>>>>>>>             };
>>>>>>>     -        usbphyc: usbphyc@5a006000 {
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            #clock-cells = <0>;
>>>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>>>> -            reg = <0x5a006000 0x1000>;
>>>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>>>> -            resets = <&rcc USBPHY_R>;
>>>>>>> -            vdda1v1-supply = <&reg11>;
>>>>>>> -            vdda1v8-supply = <&reg18>;
>>>>>>> -            status = "disabled";
>>>>>>> -
>>>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>>>> -                #phy-cells = <0>;
>>>>>>> -                reg = <0>;
>>>>>>> -            };
>>>>>>> -
>>>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>>>> -                #phy-cells = <1>;
>>>>>>> -                reg = <1>;
>>>>>>> -            };
>>>>>>> -        };
>>>>>>> -
>>>>>>>             rtc: rtc@5c004000 {
>>>>>>>                 compatible = "st,stm32mp1-rtc";
>>>>>>>                 reg = <0x5c004000 0x400>;
>>>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>>>                 };
>>>>>>>             };
>>>>>>>     +        etzpc: bus@5c007000 {
>>>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>>>> +            reg = <0x5c007000 0x400>;
>>>>>>> +            #address-cells = <1>;
>>>>>>> +            #size-cells = <1>;
>>>>>>> +            feature-domain-controller;
>>>>>>> +            #feature-domain-cells = <1>;
>>>>>>> +            ranges;
>>>>>>> +
>>>>>>> +            adc_2: adc@48004000 {
>>>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>>>> +                reg = <0x48004000 0x400>;
>>>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>>> +                clock-names = "bus", "adc";
>>>>>>> +                interrupt-controller;
>>>>>>> +                #interrupt-cells = <1>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                feature-domains = <&etzpc 33>;
>>>>>>> +                status = "disabled";
>>>>>>> +
>>>>>>> +                adc2: adc@0 {
>>>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>>>> +                    #io-channel-cells = <1>;
>>>>>>> +                    #address-cells = <1>;
>>>>>>> +                    #size-cells = <0>;
>>>>>>> +                    reg = <0x0>;
>>>>>>> +                    interrupt-parent = <&adc_2>;
>>>>>>> +                    interrupts = <0>;
>>>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>>> +                    dma-names = "rx";
>>>>>>> +                    status = "disabled";
>>>>>>> +
>>>>>>> +                    channel@13 {
>>>>>>> +                        reg = <13>;
>>>>>>> +                        label = "vrefint";
>>>>>>> +                    };
>>>>>>> +                    channel@14 {
>>>>>>> +                        reg = <14>;
>>>>>>> +                        label = "vddcore";
>>>>>>> +                    };
>>>>>>> +                    channel@16 {
>>>>>>> +                        reg = <16>;
>>>>>>> +                        label = "vddcpu";
>>>>>>> +                    };
>>>>>>> +                    channel@17 {
>>>>>>> +                        reg = <17>;
>>>>>>> +                        label = "vddq_ddr";
>>>>>>> +                    };
>>>>>>> +                };
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            usbotg_hs: usb@49000000 {
>>>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>>> +                reg = <0x49000000 0x40000>;
>>>>>>> +                clocks = <&rcc USBO_K>;
>>>>>>> +                clock-names = "otg";
>>>>>>> +                resets = <&rcc USBO_R>;
>>>>>>> +                reset-names = "dwc2";
>>>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                g-rx-fifo-size = <512>;
>>>>>>> +                g-np-tx-fifo-size = <32>;
>>>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>>> +                dr_mode = "otg";
>>>>>>> +                otg-rev = <0x200>;
>>>>>>> +                usb33d-supply = <&usb33>;
>>>>>>> +                feature-domains = <&etzpc 34>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            spi4: spi@4c002000 {
>>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>>> +                reg = <0x4c002000 0x400>;
>>>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SPI4_K>;
>>>>>>> +                resets = <&rcc SPI4_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                feature-domains = <&etzpc 18>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            spi5: spi@4c003000 {
>>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>>> +                reg = <0x4c003000 0x400>;
>>>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SPI5_K>;
>>>>>>> +                resets = <&rcc SPI5_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                feature-domains = <&etzpc 19>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            i2c3: i2c@4c004000 {
>>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>>> +                reg = <0x4c004000 0x400>;
>>>>>>> +                interrupt-names = "event", "error";
>>>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc I2C3_K>;
>>>>>>> +                resets = <&rcc I2C3_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>>> +                i2c-analog-filter;
>>>>>>> +                feature-domains = <&etzpc 20>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            i2c4: i2c@4c005000 {
>>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>>> +                reg = <0x4c005000 0x400>;
>>>>>>> +                interrupt-names = "event", "error";
>>>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc I2C4_K>;
>>>>>>> +                resets = <&rcc I2C4_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>>> +                i2c-analog-filter;
>>>>>>> +                feature-domains = <&etzpc 21>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            i2c5: i2c@4c006000 {
>>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>>> +                reg = <0x4c006000 0x400>;
>>>>>>> +                interrupt-names = "event", "error";
>>>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc I2C5_K>;
>>>>>>> +                resets = <&rcc I2C5_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>>> +                i2c-analog-filter;
>>>>>>> +                feature-domains = <&etzpc 22>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            sdmmc1: mmc@58005000 {
>>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>>>> +                clock-names = "apb_pclk";
>>>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>>>> +                cap-sd-highspeed;
>>>>>>> +                cap-mmc-highspeed;
>>>>>>> +                max-frequency = <130000000>;
>>>>>>> +                feature-domains = <&etzpc 50>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            sdmmc2: mmc@58007000 {
>>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>>>> +                clock-names = "apb_pclk";
>>>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>>>> +                cap-sd-highspeed;
>>>>>>> +                cap-mmc-highspeed;
>>>>>>> +                max-frequency = <130000000>;
>>>>>>> +                feature-domains = <&etzpc 51>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                #clock-cells = <0>;
>>>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>>>> +                reg = <0x5a006000 0x1000>;
>>>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>>>> +                resets = <&rcc USBPHY_R>;
>>>>>>> +                vdda1v1-supply = <&reg11>;
>>>>>>> +                vdda1v8-supply = <&reg18>;
>>>>>>> +                feature-domains = <&etzpc 5>;
>>>>>>> +                status = "disabled";
>>>>>>> +
>>>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>>>> +                    #phy-cells = <0>;
>>>>>>> +                    reg = <0>;
>>>>>>> +                };
>>>>>>> +
>>>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>>>> +                    #phy-cells = <1>;
>>>>>>> +                    reg = <1>;
>>>>>>> +                };
>>>>>>> +            };
>>>>>>> +
>>>>>>> +        };
>>>>>>> +
>>>>>>>             /*
>>>>>>>              * Break node order to solve dependency probe issue
>>>>>>> between
>>>>>>>              * pinctrl and exti.
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> index df451c3c2a26..be6061552683 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>>>                 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>>>                 status = "disabled";
>>>>>>>             };
>>>>>>> +    };
>>>>>>> +};
>>>>>>>     -        adc_1: adc@48003000 {
>>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>>> -            reg = <0x48003000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>>> -            clock-names = "bus", "adc";
>>>>>>> -            interrupt-controller;
>>>>>>> -            #interrupt-cells = <1>;
>>>>>>> +&etzpc {
>>>>>>> +    adc_1: adc@48003000 {
>>>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>>>> +        reg = <0x48003000 0x400>;
>>>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>>> +        clock-names = "bus", "adc";
>>>>>>> +        interrupt-controller;
>>>>>>> +        #interrupt-cells = <1>;
>>>>>>> +        #address-cells = <1>;
>>>>>>> +        #size-cells = <0>;
>>>>>>> +        feature-domains = <&etzpc 32>;
>>>>>>> +        status = "disabled";
>>>>>>> +
>>>>>>> +        adc1: adc@0 {
>>>>>>> +            compatible = "st,stm32mp13-adc";
>>>>>>> +            #io-channel-cells = <1>;
>>>>>>>                 #address-cells = <1>;
>>>>>>>                 #size-cells = <0>;
>>>>>>> +            reg = <0x0>;
>>>>>>> +            interrupt-parent = <&adc_1>;
>>>>>>> +            interrupts = <0>;
>>>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>>> +            dma-names = "rx";
>>>>>>>                 status = "disabled";
>>>>>>>     -            adc1: adc@0 {
>>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>>> -                #io-channel-cells = <1>;
>>>>>>> -                #address-cells = <1>;
>>>>>>> -                #size-cells = <0>;
>>>>>>> -                reg = <0x0>;
>>>>>>> -                interrupt-parent = <&adc_1>;
>>>>>>> -                interrupts = <0>;
>>>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>>> -                dma-names = "rx";
>>>>>>> -                status = "disabled";
>>>>>>> -
>>>>>>> -                channel@18 {
>>>>>>> -                    reg = <18>;
>>>>>>> -                    label = "vrefint";
>>>>>>> -             ��  };
>>>>>>> +            channel@18 {
>>>>>>> +                reg = <18>;
>>>>>>> +                label = "vrefint";
>>>>>>>                 };
>>>>>>>             };
>>>>>>>         };
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> @@ -4,15 +4,14 @@
>>>>>>>      * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for
>>>>>>> STMicroelectronics.
>>>>>>>      */
>>>>>>>     -/ {
>>>>>>> -    soc {
>>>>>>> -        cryp: crypto@54002000 {
>>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>>> -            reg = <0x54002000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> +&etzpc {
>>>>>>> +    cryp: crypto@54002000 {
>>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>>> +        reg = <0x54002000 0x400>;
>>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>>> +        feature-domains = <&etzpc 42>;
>>>>>>> +        status = "disabled";
>>>>>>>         };
>>>>>>>     };
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> @@ -4,15 +4,13 @@
>>>>>>>      * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for
>>>>>>> STMicroelectronics.
>>>>>>>      */
>>>>>>>     -/ {
>>>>>>> -    soc {
>>>>>>> -        cryp: crypto@54002000 {
>>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>>> -            reg = <0x54002000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> +&etzpc {
>>>>>>> +    cryp: crypto@54002000 {
>>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>>> +        reg = <0x54002000 0x400>;
>>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>>> +        status = "disabled";
>>>>>>>         };
>>>>>>>     };
>>>>>>
>>>>>
>>>>
>>>> Regarding the patch itself, I can separate it in two patches.
>>>> 1)Introduce ETZPC
>>>> 2)Move peripherals under ETZPC
>>>>
>>>> Best regards,
>>>> Gatien
>>>>
>> >

-- 
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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [Linux-stm32] [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
@ 2023-04-25  7:56                 ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-04-25  7:56 UTC (permalink / raw)
  To: Oleksii Moisieiev, Ahmad Fatoum, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: devicetree, alsa-devel, linux-iio, netdev, linux-usb, linux-mmc,
	linux-kernel, linux-spi, linux-i2c, dmaengine, linux-crypto,
	linux-serial, linux-phy, linux-stm32, linux-arm-kernel,
	linux-media, Pengutronix Kernel Team, Peng Fan

On 4/21/23 12:19, Oleksii Moisieiev wrote:
> Hello,
> 
> I'm just wandering what is the status of the Patch Series?
> 
> Cc'ed Peng Fang as he also has an interest in the domain-controller
> bindings.
> 
> Oleksii.
>

Hello Oleksii,

I need to rework this patch series before resubmitting it. I did not 
forget it :) I'd like to provide a good use-case on how to property can 
be used and maybe narrow down its perimeter/use-cases.

Peng, to which extent are you interested in this binding? What would be 
your use-case?

Best regards,
Gatien

> On 27.02.23 13:26, Gatien CHEVALLIER wrote:
>> Hello Ahmad,
>>
>> Sorry for the delay :)
>>
>> On 2/13/23 12:27, Ahmad Fatoum wrote:
>>> Hello Gatien,
>>>
>>> On 13.02.23 11:54, Gatien CHEVALLIER wrote:
>>>> On 2/9/23 09:10, Ahmad Fatoum wrote:
>>>>> On 09.02.23 08:46, Ahmad Fatoum wrote:
>>>>>> Hello Gatien,
>>>>>>
>>>>>> On 27.01.23 17:40, Gatien Chevallier wrote:
>>>>>>> The STM32 System Bus is an internal bus on which devices are
>>>>>>> connected.
>>>>>>> ETZPC is a peripheral overseeing the firewall bus that configures
>>>>>>> and control access to the peripherals connected on it.
>>>>>>>
>>>>>>> For more information on which peripheral is securable, please read
>>>>>>> the STM32MP13 reference manual.
>>>>>>
>>>>>> Diff is way too big. Please split up the alphabetic reordering
>>>>>> into its
>>>>>> own commit, so actual functional changes are apparent.
>>>>>
>>>>> Ah, I see now that you are moving securable peripherals into a new
>>>>> bus.
>>>>> I share Uwe's confusion of considering the ETZPC as bus.
>>>>>
>>>>> Does this configuration even change dynamically? Why can't you
>>>>> implement
>>>>> this binding in the bootloader and have Linux only see a DT where
>>>>> unavailable
>>>>> nodes are status = "disabled"; secure-status = "okay"?
>>>>>
>>>>> For inspiration, see barebox' device tree fixups when devices are
>>>>> disabled
>>>>> per fuse:
>>>>>
>>>>> https://urldefense.com/v3/__https://elixir.bootlin.com/barebox/v2023.01.0/source/drivers/base/featctrl.c*L122__;Iw!!GF_29dbcQIUBPA!2CT6VXNxfrLUg3mPkiAykgwwu8y8TVPaVa5FupuehHDyeuPvx4a2aNuMs-ayUCqP8q364P8u0GxYprlqwrvgvnXndYBmii57$
>>>>> [elixir[.]bootlin[.]com]
>>>>>
>>>>> Cheers,
>>>>> Ahmad
>>>>
>>>> This configuration can change dynamically. The binding will be
>>>> implemented in the bootloader, where the ETZPC is already
>>>> implemented as a bus in our downstream.
>>>>
>>>> I find the mentionned example valid.
>>>>
>>>> Now, why is it a bus? :D
>>>>
>>>> It is the result of the discussion on the previous submission by
>>>> Benjamin (Sorry for the lack of link but I saw that you participated
>>>> on these threads)+ we need the bus mechanism to control whether a
>>>> subnode should be probed or not. You can see it as a firewall bus.
>>>>
>>>> The ETZPC relies on the ARM TrustZone extension to the AHB bus and
>>>> propagation through bridges to the APB bus. Therefore, I find it
>>>> relevant to consider it as a bus, what is your opinion?
>>>>
>>>> This patchset is a first step to the implementation of an API to
>>>> control accesses dynamically.
>>>
>>> I still don't get what's dynamic about this. Either:
>>>
>>>     - Configuration _can_ change while Linux is running: You'll need
>>> to do
>>>       way more than what your current bus provides to somwhow
>>> synchronize state
>>>       with the secure monitor; otherwise a newly secured device will
>>> cause the driver
>>>       to trigger data aborts that you'll have to handle and unbind the
>>> driver.
>>>       (like if a USB drive is yanked out).
>>>
>>>     - Configuration _can't_ change while Linux is running: You can
>>> have the bootloader
>>>       fixup the device tree and Linux need not care at all about
>>> devices that the
>>>       ETZPC is securing.
>>>
>>> My understanding is that the latter is your use case, so I don't see
>>> why we
>>> even need the normal world to be aware of the partitioning.
>>>
>>> Cheers,
>>> Ahmad
>>>
>> What about the case where we do not have a U-Boot/bootloader to fixup
>> the device tree?
>>
>> On the other hand, ETZPC is a hardware firewall and is on the bus.
>> Therefore, shouldn't it be represented as a bus in the file that
>> describes the hardware?
>>
>> Best regards,
>> Gatien
>>
>>>>
>>>>>
>>>>>>
>>>>>> Thanks,
>>>>>> Ahmad
>>>>>>
>>>>>>>
>>>>>>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>>>>>>> ---
>>>>>>>
>>>>>>> No changes in V2.
>>>>>>>
>>>>>>> Changes in V3:
>>>>>>>       -Use appriopriate node name: bus
>>>>>>>
>>>>>>>     arch/arm/boot/dts/stm32mp131.dtsi  | 407
>>>>>>> +++++++++++++++--------------
>>>>>>>     arch/arm/boot/dts/stm32mp133.dtsi  |  51 ++--
>>>>>>>     arch/arm/boot/dts/stm32mp13xc.dtsi |  19 +-
>>>>>>>     arch/arm/boot/dts/stm32mp13xf.dtsi |  18 +-
>>>>>>>     4 files changed, 258 insertions(+), 237 deletions(-)
>>>>>>>
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> index accc3824f7e9..24462a647101 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp131.dtsi
>>>>>>> @@ -253,148 +253,6 @@ dmamux1: dma-router@48002000 {
>>>>>>>                 dma-channels = <16>;
>>>>>>>             };
>>>>>>>     -        adc_2: adc@48004000 {
>>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>>> -            reg = <0x48004000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>>> -            clock-names = "bus", "adc";
>>>>>>> -            interrupt-controller;
>>>>>>> -            #interrupt-cells = <1>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            status = "disabled";
>>>>>>> -
>>>>>>> -            adc2: adc@0 {
>>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>>> -                #io-channel-cells = <1>;
>>>>>>> -                #address-cells = <1>;
>>>>>>> -                #size-cells = <0>;
>>>>>>> -                reg = <0x0>;
>>>>>>> -                interrupt-parent = <&adc_2>;
>>>>>>> -                interrupts = <0>;
>>>>>>> -                dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>>> -                dma-names = "rx";
>>>>>>> -                status = "disabled";
>>>>>>> -
>>>>>>> -                channel@13 {
>>>>>>> -                    reg = <13>;
>>>>>>> -                    label = "vrefint";
>>>>>>> -                };
>>>>>>> -                channel@14 {
>>>>>>> -                    reg = <14>;
>>>>>>> -                    label = "vddcore";
>>>>>>> -                };
>>>>>>> -                channel@16 {
>>>>>>> -                    reg = <16>;
>>>>>>> -                    label = "vddcpu";
>>>>>>> -                };
>>>>>>> -                channel@17 {
>>>>>>> -                    reg = <17>;
>>>>>>> -                    label = "vddq_ddr";
>>>>>>> -                };
>>>>>>> -            };
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        usbotg_hs: usb@49000000 {
>>>>>>> -            compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>>> -            reg = <0x49000000 0x40000>;
>>>>>>> -            clocks = <&rcc USBO_K>;
>>>>>>> -            clock-names = "otg";
>>>>>>> -            resets = <&rcc USBO_R>;
>>>>>>> -            reset-names = "dwc2";
>>>>>>> -            interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            g-rx-fifo-size = <512>;
>>>>>>> -            g-np-tx-fifo-size = <32>;
>>>>>>> -            g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>>> -            dr_mode = "otg";
>>>>>>> -            otg-rev = <0x200>;
>>>>>>> -            usb33d-supply = <&usb33>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        spi4: spi@4c002000 {
>>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>>> -            reg = <0x4c002000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SPI4_K>;
>>>>>>> -            resets = <&rcc SPI4_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 83 0x400 0x01>,
>>>>>>> -                   <&dmamux1 84 0x400 0x01>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        spi5: spi@4c003000 {
>>>>>>> -            compatible = "st,stm32h7-spi";
>>>>>>> -            reg = <0x4c003000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SPI5_K>;
>>>>>>> -            resets = <&rcc SPI5_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 85 0x400 0x01>,
>>>>>>> -                   <&dmamux1 86 0x400 0x01>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        i2c3: i2c@4c004000 {
>>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>>> -            reg = <0x4c004000 0x400>;
>>>>>>> -            interrupt-names = "event", "error";
>>>>>>> -            interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> -                     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc I2C3_K>;
>>>>>>> -            resets = <&rcc I2C3_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 73 0x400 0x1>,
>>>>>>> -                   <&dmamux1 74 0x400 0x1>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>>> -            i2c-analog-filter;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        i2c4: i2c@4c005000 {
>>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>>> -            reg = <0x4c005000 0x400>;
>>>>>>> -            interrupt-names = "event", "error";
>>>>>>> -            interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> -                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc I2C4_K>;
>>>>>>> -            resets = <&rcc I2C4_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 75 0x400 0x1>,
>>>>>>> -                   <&dmamux1 76 0x400 0x1>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>>> -            i2c-analog-filter;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        i2c5: i2c@4c006000 {
>>>>>>> -            compatible = "st,stm32mp13-i2c";
>>>>>>> -            reg = <0x4c006000 0x400>;
>>>>>>> -            interrupt-names = "event", "error";
>>>>>>> -            interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> -                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc I2C5_K>;
>>>>>>> -            resets = <&rcc I2C5_R>;
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            dmas = <&dmamux1 115 0x400 0x1>,
>>>>>>> -                   <&dmamux1 116 0x400 0x1>;
>>>>>>> -            dma-names = "rx", "tx";
>>>>>>> -            st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>>> -            i2c-analog-filter;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>>             rcc: rcc@50000000 {
>>>>>>>                 compatible = "st,stm32mp13-rcc", "syscon";
>>>>>>>                 reg = <0x50000000 0x1000>;
>>>>>>> @@ -431,34 +289,6 @@ mdma: dma-controller@58000000 {
>>>>>>>                 dma-requests = <48>;
>>>>>>>             };
>>>>>>>     -        sdmmc1: mmc@58005000 {
>>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>>> -            reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>>> -            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SDMMC1_K>;
>>>>>>> -            clock-names = "apb_pclk";
>>>>>>> -            resets = <&rcc SDMMC1_R>;
>>>>>>> -            cap-sd-highspeed;
>>>>>>> -            cap-mmc-highspeed;
>>>>>>> -            max-frequency = <130000000>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>> -        sdmmc2: mmc@58007000 {
>>>>>>> -            compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> -            arm,primecell-periphid = <0x20253180>;
>>>>>>> -            reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>>> -            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc SDMMC2_K>;
>>>>>>> -            clock-names = "apb_pclk";
>>>>>>> -            resets = <&rcc SDMMC2_R>;
>>>>>>> -            cap-sd-highspeed;
>>>>>>> -            cap-mmc-highspeed;
>>>>>>> -            max-frequency = <130000000>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> -
>>>>>>>             usbh_ohci: usb@5800c000 {
>>>>>>>                 compatible = "generic-ohci";
>>>>>>>                 reg = <0x5800c000 0x1000>;
>>>>>>> @@ -486,29 +316,6 @@ iwdg2: watchdog@5a002000 {
>>>>>>>                 status = "disabled";
>>>>>>>             };
>>>>>>>     -        usbphyc: usbphyc@5a006000 {
>>>>>>> -            #address-cells = <1>;
>>>>>>> -            #size-cells = <0>;
>>>>>>> -            #clock-cells = <0>;
>>>>>>> -            compatible = "st,stm32mp1-usbphyc";
>>>>>>> -            reg = <0x5a006000 0x1000>;
>>>>>>> -            clocks = <&rcc USBPHY_K>;
>>>>>>> -            resets = <&rcc USBPHY_R>;
>>>>>>> -            vdda1v1-supply = <&reg11>;
>>>>>>> -            vdda1v8-supply = <&reg18>;
>>>>>>> -            status = "disabled";
>>>>>>> -
>>>>>>> -            usbphyc_port0: usb-phy@0 {
>>>>>>> -                #phy-cells = <0>;
>>>>>>> -                reg = <0>;
>>>>>>> -            };
>>>>>>> -
>>>>>>> -            usbphyc_port1: usb-phy@1 {
>>>>>>> -                #phy-cells = <1>;
>>>>>>> -                reg = <1>;
>>>>>>> -            };
>>>>>>> -        };
>>>>>>> -
>>>>>>>             rtc: rtc@5c004000 {
>>>>>>>                 compatible = "st,stm32mp1-rtc";
>>>>>>>                 reg = <0x5c004000 0x400>;
>>>>>>> @@ -536,6 +343,220 @@ ts_cal2: calib@5e {
>>>>>>>                 };
>>>>>>>             };
>>>>>>>     +        etzpc: bus@5c007000 {
>>>>>>> +            compatible = "st,stm32mp13-sys-bus";
>>>>>>> +            reg = <0x5c007000 0x400>;
>>>>>>> +            #address-cells = <1>;
>>>>>>> +            #size-cells = <1>;
>>>>>>> +            feature-domain-controller;
>>>>>>> +            #feature-domain-cells = <1>;
>>>>>>> +            ranges;
>>>>>>> +
>>>>>>> +            adc_2: adc@48004000 {
>>>>>>> +                compatible = "st,stm32mp13-adc-core";
>>>>>>> +                reg = <0x48004000 0x400>;
>>>>>>> +                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc ADC2>, <&rcc ADC2_K>;
>>>>>>> +                clock-names = "bus", "adc";
>>>>>>> +                interrupt-controller;
>>>>>>> +                #interrupt-cells = <1>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                feature-domains = <&etzpc 33>;
>>>>>>> +                status = "disabled";
>>>>>>> +
>>>>>>> +                adc2: adc@0 {
>>>>>>> +                    compatible = "st,stm32mp13-adc";
>>>>>>> +                    #io-channel-cells = <1>;
>>>>>>> +                    #address-cells = <1>;
>>>>>>> +                    #size-cells = <0>;
>>>>>>> +                    reg = <0x0>;
>>>>>>> +                    interrupt-parent = <&adc_2>;
>>>>>>> +                    interrupts = <0>;
>>>>>>> +                    dmas = <&dmamux1 10 0x400 0x80000001>;
>>>>>>> +                    dma-names = "rx";
>>>>>>> +                    status = "disabled";
>>>>>>> +
>>>>>>> +                    channel@13 {
>>>>>>> +                        reg = <13>;
>>>>>>> +                        label = "vrefint";
>>>>>>> +                    };
>>>>>>> +                    channel@14 {
>>>>>>> +                        reg = <14>;
>>>>>>> +                        label = "vddcore";
>>>>>>> +                    };
>>>>>>> +                    channel@16 {
>>>>>>> +                        reg = <16>;
>>>>>>> +                        label = "vddcpu";
>>>>>>> +                    };
>>>>>>> +                    channel@17 {
>>>>>>> +                        reg = <17>;
>>>>>>> +                        label = "vddq_ddr";
>>>>>>> +                    };
>>>>>>> +                };
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            usbotg_hs: usb@49000000 {
>>>>>>> +                compatible = "st,stm32mp15-hsotg", "snps,dwc2";
>>>>>>> +                reg = <0x49000000 0x40000>;
>>>>>>> +                clocks = <&rcc USBO_K>;
>>>>>>> +                clock-names = "otg";
>>>>>>> +                resets = <&rcc USBO_R>;
>>>>>>> +                reset-names = "dwc2";
>>>>>>> +                interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                g-rx-fifo-size = <512>;
>>>>>>> +                g-np-tx-fifo-size = <32>;
>>>>>>> +                g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
>>>>>>> +                dr_mode = "otg";
>>>>>>> +                otg-rev = <0x200>;
>>>>>>> +                usb33d-supply = <&usb33>;
>>>>>>> +                feature-domains = <&etzpc 34>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            spi4: spi@4c002000 {
>>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>>> +                reg = <0x4c002000 0x400>;
>>>>>>> +                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SPI4_K>;
>>>>>>> +                resets = <&rcc SPI4_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 83 0x400 0x01>,
>>>>>>> +                       <&dmamux1 84 0x400 0x01>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                feature-domains = <&etzpc 18>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            spi5: spi@4c003000 {
>>>>>>> +                compatible = "st,stm32h7-spi";
>>>>>>> +                reg = <0x4c003000 0x400>;
>>>>>>> +                interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SPI5_K>;
>>>>>>> +                resets = <&rcc SPI5_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 85 0x400 0x01>,
>>>>>>> +                       <&dmamux1 86 0x400 0x01>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                feature-domains = <&etzpc 19>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            i2c3: i2c@4c004000 {
>>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>>> +                reg = <0x4c004000 0x400>;
>>>>>>> +                interrupt-names = "event", "error";
>>>>>>> +                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> +                         <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc I2C3_K>;
>>>>>>> +                resets = <&rcc I2C3_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 73 0x400 0x1>,
>>>>>>> +                       <&dmamux1 74 0x400 0x1>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x4>;
>>>>>>> +                i2c-analog-filter;
>>>>>>> +                feature-domains = <&etzpc 20>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            i2c4: i2c@4c005000 {
>>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>>> +                reg = <0x4c005000 0x400>;
>>>>>>> +                interrupt-names = "event", "error";
>>>>>>> +                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> +                         <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc I2C4_K>;
>>>>>>> +                resets = <&rcc I2C4_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 75 0x400 0x1>,
>>>>>>> +                       <&dmamux1 76 0x400 0x1>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x8>;
>>>>>>> +                i2c-analog-filter;
>>>>>>> +                feature-domains = <&etzpc 21>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            i2c5: i2c@4c006000 {
>>>>>>> +                compatible = "st,stm32mp13-i2c";
>>>>>>> +                reg = <0x4c006000 0x400>;
>>>>>>> +                interrupt-names = "event", "error";
>>>>>>> +                interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>>>>> +                         <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc I2C5_K>;
>>>>>>> +                resets = <&rcc I2C5_R>;
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                dmas = <&dmamux1 115 0x400 0x1>,
>>>>>>> +                       <&dmamux1 116 0x400 0x1>;
>>>>>>> +                dma-names = "rx", "tx";
>>>>>>> +                st,syscfg-fmp = <&syscfg 0x4 0x10>;
>>>>>>> +                i2c-analog-filter;
>>>>>>> +                feature-domains = <&etzpc 22>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            sdmmc1: mmc@58005000 {
>>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>>> +                reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
>>>>>>> +                interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SDMMC1_K>;
>>>>>>> +                clock-names = "apb_pclk";
>>>>>>> +                resets = <&rcc SDMMC1_R>;
>>>>>>> +                cap-sd-highspeed;
>>>>>>> +                cap-mmc-highspeed;
>>>>>>> +                max-frequency = <130000000>;
>>>>>>> +                feature-domains = <&etzpc 50>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            sdmmc2: mmc@58007000 {
>>>>>>> +                compatible = "st,stm32-sdmmc2", "arm,pl18x",
>>>>>>> "arm,primecell";
>>>>>>> +                arm,primecell-periphid = <0x20253180>;
>>>>>>> +                reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
>>>>>>> +                interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +                clocks = <&rcc SDMMC2_K>;
>>>>>>> +                clock-names = "apb_pclk";
>>>>>>> +                resets = <&rcc SDMMC2_R>;
>>>>>>> +                cap-sd-highspeed;
>>>>>>> +                cap-mmc-highspeed;
>>>>>>> +                max-frequency = <130000000>;
>>>>>>> +                feature-domains = <&etzpc 51>;
>>>>>>> +                status = "disabled";
>>>>>>> +            };
>>>>>>> +
>>>>>>> +            usbphyc: usbphyc@5a006000 {
>>>>>>> +                #address-cells = <1>;
>>>>>>> +                #size-cells = <0>;
>>>>>>> +                #clock-cells = <0>;
>>>>>>> +                compatible = "st,stm32mp1-usbphyc";
>>>>>>> +                reg = <0x5a006000 0x1000>;
>>>>>>> +                clocks = <&rcc USBPHY_K>;
>>>>>>> +                resets = <&rcc USBPHY_R>;
>>>>>>> +                vdda1v1-supply = <&reg11>;
>>>>>>> +                vdda1v8-supply = <&reg18>;
>>>>>>> +                feature-domains = <&etzpc 5>;
>>>>>>> +                status = "disabled";
>>>>>>> +
>>>>>>> +                usbphyc_port0: usb-phy@0 {
>>>>>>> +                    #phy-cells = <0>;
>>>>>>> +                    reg = <0>;
>>>>>>> +                };
>>>>>>> +
>>>>>>> +                usbphyc_port1: usb-phy@1 {
>>>>>>> +                    #phy-cells = <1>;
>>>>>>> +                    reg = <1>;
>>>>>>> +                };
>>>>>>> +            };
>>>>>>> +
>>>>>>> +        };
>>>>>>> +
>>>>>>>             /*
>>>>>>>              * Break node order to solve dependency probe issue
>>>>>>> between
>>>>>>>              * pinctrl and exti.
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> index df451c3c2a26..be6061552683 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp133.dtsi
>>>>>>> @@ -33,35 +33,38 @@ m_can2: can@4400f000 {
>>>>>>>                 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
>>>>>>>                 status = "disabled";
>>>>>>>             };
>>>>>>> +    };
>>>>>>> +};
>>>>>>>     -        adc_1: adc@48003000 {
>>>>>>> -            compatible = "st,stm32mp13-adc-core";
>>>>>>> -            reg = <0x48003000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>>> -            clock-names = "bus", "adc";
>>>>>>> -            interrupt-controller;
>>>>>>> -            #interrupt-cells = <1>;
>>>>>>> +&etzpc {
>>>>>>> +    adc_1: adc@48003000 {
>>>>>>> +        compatible = "st,stm32mp13-adc-core";
>>>>>>> +        reg = <0x48003000 0x400>;
>>>>>>> +        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +        clocks = <&rcc ADC1>, <&rcc ADC1_K>;
>>>>>>> +        clock-names = "bus", "adc";
>>>>>>> +        interrupt-controller;
>>>>>>> +        #interrupt-cells = <1>;
>>>>>>> +        #address-cells = <1>;
>>>>>>> +        #size-cells = <0>;
>>>>>>> +        feature-domains = <&etzpc 32>;
>>>>>>> +        status = "disabled";
>>>>>>> +
>>>>>>> +        adc1: adc@0 {
>>>>>>> +            compatible = "st,stm32mp13-adc";
>>>>>>> +            #io-channel-cells = <1>;
>>>>>>>                 #address-cells = <1>;
>>>>>>>                 #size-cells = <0>;
>>>>>>> +            reg = <0x0>;
>>>>>>> +            interrupt-parent = <&adc_1>;
>>>>>>> +            interrupts = <0>;
>>>>>>> +            dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>>> +            dma-names = "rx";
>>>>>>>                 status = "disabled";
>>>>>>>     -            adc1: adc@0 {
>>>>>>> -                compatible = "st,stm32mp13-adc";
>>>>>>> -                #io-channel-cells = <1>;
>>>>>>> -                #address-cells = <1>;
>>>>>>> -                #size-cells = <0>;
>>>>>>> -                reg = <0x0>;
>>>>>>> -                interrupt-parent = <&adc_1>;
>>>>>>> -                interrupts = <0>;
>>>>>>> -                dmas = <&dmamux1 9 0x400 0x80000001>;
>>>>>>> -                dma-names = "rx";
>>>>>>> -                status = "disabled";
>>>>>>> -
>>>>>>> -                channel@18 {
>>>>>>> -                    reg = <18>;
>>>>>>> -                    label = "vrefint";
>>>>>>> -             ��  };
>>>>>>> +            channel@18 {
>>>>>>> +                reg = <18>;
>>>>>>> +                label = "vrefint";
>>>>>>>                 };
>>>>>>>             };
>>>>>>>         };
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> index 4d00e7592882..a1a7a40c2a3e 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi
>>>>>>> @@ -4,15 +4,14 @@
>>>>>>>      * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for
>>>>>>> STMicroelectronics.
>>>>>>>      */
>>>>>>>     -/ {
>>>>>>> -    soc {
>>>>>>> -        cryp: crypto@54002000 {
>>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>>> -            reg = <0x54002000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> +&etzpc {
>>>>>>> +    cryp: crypto@54002000 {
>>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>>> +        reg = <0x54002000 0x400>;
>>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>>> +        feature-domains = <&etzpc 42>;
>>>>>>> +        status = "disabled";
>>>>>>>         };
>>>>>>>     };
>>>>>>> diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> index 4d00e7592882..b9fb071a1471 100644
>>>>>>> --- a/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi
>>>>>>> @@ -4,15 +4,13 @@
>>>>>>>      * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for
>>>>>>> STMicroelectronics.
>>>>>>>      */
>>>>>>>     -/ {
>>>>>>> -    soc {
>>>>>>> -        cryp: crypto@54002000 {
>>>>>>> -            compatible = "st,stm32mp1-cryp";
>>>>>>> -            reg = <0x54002000 0x400>;
>>>>>>> -            interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> -            clocks = <&rcc CRYP1>;
>>>>>>> -            resets = <&rcc CRYP1_R>;
>>>>>>> -            status = "disabled";
>>>>>>> -        };
>>>>>>> +&etzpc {
>>>>>>> +    cryp: crypto@54002000 {
>>>>>>> +        compatible = "st,stm32mp1-cryp";
>>>>>>> +        reg = <0x54002000 0x400>;
>>>>>>> +        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
>>>>>>> +        clocks = <&rcc CRYP1>;
>>>>>>> +        resets = <&rcc CRYP1_R>;
>>>>>>> +        status = "disabled";
>>>>>>>         };
>>>>>>>     };
>>>>>>
>>>>>
>>>>
>>>> Regarding the patch itself, I can separate it in two patches.
>>>> 1)Introduce ETZPC
>>>> 2)Move peripherals under ETZPC
>>>>
>>>> Best regards,
>>>> Gatien
>>>>
>> >

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 0/6] Introduce STM32 system bus
  2023-01-27 16:40 ` Gatien Chevallier
  (?)
@ 2023-07-05 17:35   ` Gatien CHEVALLIER
  -1 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-07-05 17:35 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb

Hello all,

I'm abandoning this series for:
https://lore.kernel.org/lkml/20230705172759.1610753

Sorry for the noise.

Best regards,
Gatien

On 1/27/23 17:40, Gatien Chevallier wrote:
> Document STM32 System Bus. This bus is intended to control firewall
> access for the peripherals connected to it.
> 
> For every peripheral, the bus checks the firewall registers to see
> if the peripheral is configured as non-secure. If the peripheral
> is configured as secure, the node is marked populated, so the
> device won't be probed.
> 
> This is useful as a firewall configuration sanity check and avoid
> platform crashes in case peripherals are incorrectly configured.
> 
> The STM32 System Bus implements the feature-domain-controller
> bindings. It is used by peripherals to reference a domain
> controller, in this case the firewall feature domain.
> The bus uses the ID referenced by the feature-domains property to
> know where to look in the firewall to get the security configuration
> for the peripheral. This allows a device tree description rather
> than a hardcoded peripheral table in the bus driver.
> 
> On STM32MP13/15 platforms, the firewall bus is represented by the
> ETZPC node, which is responsible for the securing / MCU isolating
> the capable peripherals.
> 
> STM32MP13/15 device trees are updated in this series to implement
> the bus. All peripherals that are securable or MCU isolation capable
> by the ETZPC are connected to the bus.
> 
> Changes in V2:
> 	- Corrected YAMLS errors highlighted by Rob's robot
> 	- Re-ordered Signed-off-by tags in two patches
> 
> Changes in V3:
> 	- Document feature-domains property in YAML documentation for
> 	concerned periperals under the System Bus
> 	- Fix STM32 System Bus YAML documentation
> 	- Remove STM32 System bus bindings that were currently used
> 	as helpers for device tree
> 	- Correct few errors in driver
> 	- Add missing peripherals under the System Bus that were in
> 	SoC variation device tree files
> 	- Fix node names
> 
> Gatien Chevallier (5):
>    dt-bindings: treewide: add feature-domains description in binding
>      files
>    dt-bindings: bus: add STM32 System Bus
>    bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
>    ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
>    ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
> 
> Oleksii Moisieiev (1):
>    dt-bindings: Document common device controller bindings
> 
>   .../devicetree/bindings/bus/st,sys-bus.yaml   |  127 +
>   .../bindings/crypto/st,stm32-hash.yaml        |    5 +
>   .../devicetree/bindings/dma/st,stm32-dma.yaml |    5 +
>   .../bindings/dma/st,stm32-dmamux.yaml         |    5 +
>   .../feature-domain-controller.yaml            |   84 +
>   .../devicetree/bindings/i2c/st,stm32-i2c.yaml |    5 +
>   .../bindings/iio/adc/st,stm32-adc.yaml        |    5 +
>   .../bindings/iio/adc/st,stm32-dfsdm-adc.yaml  |    5 +
>   .../bindings/iio/dac/st,stm32-dac.yaml        |    5 +
>   .../bindings/media/st,stm32-cec.yaml          |    5 +
>   .../bindings/media/st,stm32-dcmi.yaml         |    5 +
>   .../memory-controllers/st,stm32-fmc2-ebi.yaml |    5 +
>   .../bindings/mfd/st,stm32-lptimer.yaml        |    5 +
>   .../bindings/mfd/st,stm32-timers.yaml         |    6 +
>   .../devicetree/bindings/mmc/arm,pl18x.yaml    |    5 +
>   .../devicetree/bindings/net/stm32-dwmac.yaml  |    5 +
>   .../bindings/phy/phy-stm32-usbphyc.yaml       |    5 +
>   .../bindings/regulator/st,stm32-vrefbuf.yaml  |    5 +
>   .../devicetree/bindings/rng/st,stm32-rng.yaml |    5 +
>   .../bindings/serial/st,stm32-uart.yaml        |    5 +
>   .../bindings/sound/st,stm32-i2s.yaml          |    5 +
>   .../bindings/sound/st,stm32-sai.yaml          |    5 +
>   .../bindings/sound/st,stm32-spdifrx.yaml      |    5 +
>   .../bindings/spi/st,stm32-qspi.yaml           |    5 +
>   .../devicetree/bindings/spi/st,stm32-spi.yaml |    5 +
>   .../devicetree/bindings/usb/dwc2.yaml         |    5 +
>   MAINTAINERS                                   |    6 +
>   arch/arm/boot/dts/stm32mp131.dtsi             |  407 +--
>   arch/arm/boot/dts/stm32mp133.dtsi             |   51 +-
>   arch/arm/boot/dts/stm32mp13xc.dtsi            |   19 +-
>   arch/arm/boot/dts/stm32mp13xf.dtsi            |   18 +-
>   arch/arm/boot/dts/stm32mp151.dtsi             | 2722 +++++++++--------
>   arch/arm/boot/dts/stm32mp153.dtsi             |   52 +-
>   arch/arm/boot/dts/stm32mp15xc.dtsi            |   19 +-
>   drivers/bus/Kconfig                           |    9 +
>   drivers/bus/Makefile                          |    1 +
>   drivers/bus/stm32_sys_bus.c                   |  168 +
>   37 files changed, 2208 insertions(+), 1596 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
>   create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
>   create mode 100644 drivers/bus/stm32_sys_bus.c
> 

^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 0/6] Introduce STM32 system bus
@ 2023-07-05 17:35   ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-07-05 17:35 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb

Hello all,

I'm abandoning this series for:
https://lore.kernel.org/lkml/20230705172759.1610753

Sorry for the noise.

Best regards,
Gatien

On 1/27/23 17:40, Gatien Chevallier wrote:
> Document STM32 System Bus. This bus is intended to control firewall
> access for the peripherals connected to it.
> 
> For every peripheral, the bus checks the firewall registers to see
> if the peripheral is configured as non-secure. If the peripheral
> is configured as secure, the node is marked populated, so the
> device won't be probed.
> 
> This is useful as a firewall configuration sanity check and avoid
> platform crashes in case peripherals are incorrectly configured.
> 
> The STM32 System Bus implements the feature-domain-controller
> bindings. It is used by peripherals to reference a domain
> controller, in this case the firewall feature domain.
> The bus uses the ID referenced by the feature-domains property to
> know where to look in the firewall to get the security configuration
> for the peripheral. This allows a device tree description rather
> than a hardcoded peripheral table in the bus driver.
> 
> On STM32MP13/15 platforms, the firewall bus is represented by the
> ETZPC node, which is responsible for the securing / MCU isolating
> the capable peripherals.
> 
> STM32MP13/15 device trees are updated in this series to implement
> the bus. All peripherals that are securable or MCU isolation capable
> by the ETZPC are connected to the bus.
> 
> Changes in V2:
> 	- Corrected YAMLS errors highlighted by Rob's robot
> 	- Re-ordered Signed-off-by tags in two patches
> 
> Changes in V3:
> 	- Document feature-domains property in YAML documentation for
> 	concerned periperals under the System Bus
> 	- Fix STM32 System Bus YAML documentation
> 	- Remove STM32 System bus bindings that were currently used
> 	as helpers for device tree
> 	- Correct few errors in driver
> 	- Add missing peripherals under the System Bus that were in
> 	SoC variation device tree files
> 	- Fix node names
> 
> Gatien Chevallier (5):
>    dt-bindings: treewide: add feature-domains description in binding
>      files
>    dt-bindings: bus: add STM32 System Bus
>    bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
>    ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
>    ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
> 
> Oleksii Moisieiev (1):
>    dt-bindings: Document common device controller bindings
> 
>   .../devicetree/bindings/bus/st,sys-bus.yaml   |  127 +
>   .../bindings/crypto/st,stm32-hash.yaml        |    5 +
>   .../devicetree/bindings/dma/st,stm32-dma.yaml |    5 +
>   .../bindings/dma/st,stm32-dmamux.yaml         |    5 +
>   .../feature-domain-controller.yaml            |   84 +
>   .../devicetree/bindings/i2c/st,stm32-i2c.yaml |    5 +
>   .../bindings/iio/adc/st,stm32-adc.yaml        |    5 +
>   .../bindings/iio/adc/st,stm32-dfsdm-adc.yaml  |    5 +
>   .../bindings/iio/dac/st,stm32-dac.yaml        |    5 +
>   .../bindings/media/st,stm32-cec.yaml          |    5 +
>   .../bindings/media/st,stm32-dcmi.yaml         |    5 +
>   .../memory-controllers/st,stm32-fmc2-ebi.yaml |    5 +
>   .../bindings/mfd/st,stm32-lptimer.yaml        |    5 +
>   .../bindings/mfd/st,stm32-timers.yaml         |    6 +
>   .../devicetree/bindings/mmc/arm,pl18x.yaml    |    5 +
>   .../devicetree/bindings/net/stm32-dwmac.yaml  |    5 +
>   .../bindings/phy/phy-stm32-usbphyc.yaml       |    5 +
>   .../bindings/regulator/st,stm32-vrefbuf.yaml  |    5 +
>   .../devicetree/bindings/rng/st,stm32-rng.yaml |    5 +
>   .../bindings/serial/st,stm32-uart.yaml        |    5 +
>   .../bindings/sound/st,stm32-i2s.yaml          |    5 +
>   .../bindings/sound/st,stm32-sai.yaml          |    5 +
>   .../bindings/sound/st,stm32-spdifrx.yaml      |    5 +
>   .../bindings/spi/st,stm32-qspi.yaml           |    5 +
>   .../devicetree/bindings/spi/st,stm32-spi.yaml |    5 +
>   .../devicetree/bindings/usb/dwc2.yaml         |    5 +
>   MAINTAINERS                                   |    6 +
>   arch/arm/boot/dts/stm32mp131.dtsi             |  407 +--
>   arch/arm/boot/dts/stm32mp133.dtsi             |   51 +-
>   arch/arm/boot/dts/stm32mp13xc.dtsi            |   19 +-
>   arch/arm/boot/dts/stm32mp13xf.dtsi            |   18 +-
>   arch/arm/boot/dts/stm32mp151.dtsi             | 2722 +++++++++--------
>   arch/arm/boot/dts/stm32mp153.dtsi             |   52 +-
>   arch/arm/boot/dts/stm32mp15xc.dtsi            |   19 +-
>   drivers/bus/Kconfig                           |    9 +
>   drivers/bus/Makefile                          |    1 +
>   drivers/bus/stm32_sys_bus.c                   |  168 +
>   37 files changed, 2208 insertions(+), 1596 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
>   create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
>   create mode 100644 drivers/bus/stm32_sys_bus.c
> 

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^ permalink raw reply	[flat|nested] 93+ messages in thread

* Re: [PATCH v3 0/6] Introduce STM32 system bus
@ 2023-07-05 17:35   ` Gatien CHEVALLIER
  0 siblings, 0 replies; 93+ messages in thread
From: Gatien CHEVALLIER @ 2023-07-05 17:35 UTC (permalink / raw)
  To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
	krzysztof.kozlowski+dt, alexandre.torgue, vkoul, jic23,
	olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
	ulf.hansson, edumazet, kuba, pabeni
  Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
	linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
	linux-media, linux-mmc, netdev, linux-phy, linux-serial,
	linux-spi, linux-usb

Hello all,

I'm abandoning this series for:
https://lore.kernel.org/lkml/20230705172759.1610753

Sorry for the noise.

Best regards,
Gatien

On 1/27/23 17:40, Gatien Chevallier wrote:
> Document STM32 System Bus. This bus is intended to control firewall
> access for the peripherals connected to it.
> 
> For every peripheral, the bus checks the firewall registers to see
> if the peripheral is configured as non-secure. If the peripheral
> is configured as secure, the node is marked populated, so the
> device won't be probed.
> 
> This is useful as a firewall configuration sanity check and avoid
> platform crashes in case peripherals are incorrectly configured.
> 
> The STM32 System Bus implements the feature-domain-controller
> bindings. It is used by peripherals to reference a domain
> controller, in this case the firewall feature domain.
> The bus uses the ID referenced by the feature-domains property to
> know where to look in the firewall to get the security configuration
> for the peripheral. This allows a device tree description rather
> than a hardcoded peripheral table in the bus driver.
> 
> On STM32MP13/15 platforms, the firewall bus is represented by the
> ETZPC node, which is responsible for the securing / MCU isolating
> the capable peripherals.
> 
> STM32MP13/15 device trees are updated in this series to implement
> the bus. All peripherals that are securable or MCU isolation capable
> by the ETZPC are connected to the bus.
> 
> Changes in V2:
> 	- Corrected YAMLS errors highlighted by Rob's robot
> 	- Re-ordered Signed-off-by tags in two patches
> 
> Changes in V3:
> 	- Document feature-domains property in YAML documentation for
> 	concerned periperals under the System Bus
> 	- Fix STM32 System Bus YAML documentation
> 	- Remove STM32 System bus bindings that were currently used
> 	as helpers for device tree
> 	- Correct few errors in driver
> 	- Add missing peripherals under the System Bus that were in
> 	SoC variation device tree files
> 	- Fix node names
> 
> Gatien Chevallier (5):
>    dt-bindings: treewide: add feature-domains description in binding
>      files
>    dt-bindings: bus: add STM32 System Bus
>    bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
>    ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
>    ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
> 
> Oleksii Moisieiev (1):
>    dt-bindings: Document common device controller bindings
> 
>   .../devicetree/bindings/bus/st,sys-bus.yaml   |  127 +
>   .../bindings/crypto/st,stm32-hash.yaml        |    5 +
>   .../devicetree/bindings/dma/st,stm32-dma.yaml |    5 +
>   .../bindings/dma/st,stm32-dmamux.yaml         |    5 +
>   .../feature-domain-controller.yaml            |   84 +
>   .../devicetree/bindings/i2c/st,stm32-i2c.yaml |    5 +
>   .../bindings/iio/adc/st,stm32-adc.yaml        |    5 +
>   .../bindings/iio/adc/st,stm32-dfsdm-adc.yaml  |    5 +
>   .../bindings/iio/dac/st,stm32-dac.yaml        |    5 +
>   .../bindings/media/st,stm32-cec.yaml          |    5 +
>   .../bindings/media/st,stm32-dcmi.yaml         |    5 +
>   .../memory-controllers/st,stm32-fmc2-ebi.yaml |    5 +
>   .../bindings/mfd/st,stm32-lptimer.yaml        |    5 +
>   .../bindings/mfd/st,stm32-timers.yaml         |    6 +
>   .../devicetree/bindings/mmc/arm,pl18x.yaml    |    5 +
>   .../devicetree/bindings/net/stm32-dwmac.yaml  |    5 +
>   .../bindings/phy/phy-stm32-usbphyc.yaml       |    5 +
>   .../bindings/regulator/st,stm32-vrefbuf.yaml  |    5 +
>   .../devicetree/bindings/rng/st,stm32-rng.yaml |    5 +
>   .../bindings/serial/st,stm32-uart.yaml        |    5 +
>   .../bindings/sound/st,stm32-i2s.yaml          |    5 +
>   .../bindings/sound/st,stm32-sai.yaml          |    5 +
>   .../bindings/sound/st,stm32-spdifrx.yaml      |    5 +
>   .../bindings/spi/st,stm32-qspi.yaml           |    5 +
>   .../devicetree/bindings/spi/st,stm32-spi.yaml |    5 +
>   .../devicetree/bindings/usb/dwc2.yaml         |    5 +
>   MAINTAINERS                                   |    6 +
>   arch/arm/boot/dts/stm32mp131.dtsi             |  407 +--
>   arch/arm/boot/dts/stm32mp133.dtsi             |   51 +-
>   arch/arm/boot/dts/stm32mp13xc.dtsi            |   19 +-
>   arch/arm/boot/dts/stm32mp13xf.dtsi            |   18 +-
>   arch/arm/boot/dts/stm32mp151.dtsi             | 2722 +++++++++--------
>   arch/arm/boot/dts/stm32mp153.dtsi             |   52 +-
>   arch/arm/boot/dts/stm32mp15xc.dtsi            |   19 +-
>   drivers/bus/Kconfig                           |    9 +
>   drivers/bus/Makefile                          |    1 +
>   drivers/bus/stm32_sys_bus.c                   |  168 +
>   37 files changed, 2208 insertions(+), 1596 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
>   create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
>   create mode 100644 drivers/bus/stm32_sys_bus.c
> 

-- 
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 93+ messages in thread

end of thread, other threads:[~2023-07-05 17:36 UTC | newest]

Thread overview: 93+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-27 16:40 [PATCH v3 0/6] Introduce STM32 system bus Gatien Chevallier
2023-01-27 16:40 ` Gatien Chevallier
2023-01-27 16:40 ` Gatien Chevallier
2023-01-27 16:40 ` Gatien Chevallier
2023-01-27 16:40 ` [PATCH v3 1/6] dt-bindings: Document common device controller bindings Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:49   ` Krzysztof Kozlowski
2023-01-27 16:49     ` Krzysztof Kozlowski
2023-01-27 16:49     ` Krzysztof Kozlowski
2023-01-27 16:49     ` Krzysztof Kozlowski
2023-01-27 17:00     ` Gatien CHEVALLIER
2023-01-27 17:00       ` Gatien CHEVALLIER
2023-01-27 17:00       ` Gatien CHEVALLIER
2023-01-27 17:00       ` Gatien CHEVALLIER
2023-01-27 16:40 ` [PATCH v3 2/6] dt-bindings: treewide: add feature-domains description in binding files Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-28 15:46   ` Jonathan Cameron
2023-01-28 15:46     ` Jonathan Cameron
2023-01-28 15:46     ` Jonathan Cameron
2023-01-28 15:46     ` Jonathan Cameron
2023-02-03 20:57   ` Rob Herring
2023-02-03 20:57     ` Rob Herring
2023-02-03 20:57     ` Rob Herring
2023-02-03 20:57     ` Rob Herring
2023-01-27 16:40 ` [PATCH v3 3/6] dt-bindings: bus: add STM32 System Bus Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-28 15:48   ` Jonathan Cameron
2023-01-28 15:48     ` Jonathan Cameron
2023-01-28 15:48     ` Jonathan Cameron
2023-01-28 15:48     ` Jonathan Cameron
2023-02-07 13:31     ` Gatien CHEVALLIER
2023-02-07 13:31       ` Gatien CHEVALLIER
2023-02-07 13:31       ` Gatien CHEVALLIER
2023-01-27 16:40 ` [PATCH v3 4/6] bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-28 16:12   ` Jonathan Cameron
2023-01-28 16:12     ` Jonathan Cameron
2023-01-28 16:12     ` Jonathan Cameron
2023-01-28 16:12     ` Jonathan Cameron
2023-02-07 14:12     ` Gatien CHEVALLIER
2023-02-07 14:12       ` Gatien CHEVALLIER
2023-02-07 14:12       ` Gatien CHEVALLIER
2023-02-07 14:12       ` Gatien CHEVALLIER
2023-02-08 19:08       ` Jonathan Cameron
2023-02-08 19:08         ` Jonathan Cameron
2023-02-08 19:08         ` Jonathan Cameron
2023-02-08 19:08         ` Jonathan Cameron
2023-01-27 16:40 ` [PATCH v3 5/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-02-09  7:51   ` Uwe Kleine-König
2023-02-09  7:51     ` Uwe Kleine-König
2023-02-09  7:51     ` Uwe Kleine-König
2023-01-27 16:40 ` [PATCH v3 6/6] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-01-27 16:40   ` Gatien Chevallier
2023-02-09  7:46   ` [Linux-stm32] " Ahmad Fatoum
2023-02-09  7:46     ` Ahmad Fatoum
2023-02-09  7:46     ` Ahmad Fatoum
2023-02-09  8:10     ` Ahmad Fatoum
2023-02-09  8:10       ` Ahmad Fatoum
2023-02-09  8:10       ` Ahmad Fatoum
2023-02-13 10:54       ` Gatien CHEVALLIER
2023-02-13 10:54         ` Gatien CHEVALLIER
2023-02-13 10:54         ` Gatien CHEVALLIER
2023-02-13 10:54         ` Gatien CHEVALLIER
2023-02-13 11:27         ` Ahmad Fatoum
2023-02-13 11:27           ` Ahmad Fatoum
2023-02-13 11:27           ` Ahmad Fatoum
2023-02-27 11:26           ` Gatien CHEVALLIER
2023-02-27 11:26             ` Gatien CHEVALLIER
2023-02-27 11:26             ` Gatien CHEVALLIER
2023-02-27 11:26             ` Gatien CHEVALLIER
2023-04-21 10:19             ` Oleksii Moisieiev via Alsa-devel
2023-04-21 10:19             ` Oleksii Moisieiev
2023-04-21 10:19               ` Oleksii Moisieiev
2023-04-21 10:19               ` Oleksii Moisieiev
2023-04-25  7:56               ` Gatien CHEVALLIER
2023-04-25  7:56                 ` Gatien CHEVALLIER
2023-04-25  7:56                 ` Gatien CHEVALLIER
2023-07-05 17:35 ` [PATCH v3 0/6] Introduce STM32 system bus Gatien CHEVALLIER
2023-07-05 17:35   ` Gatien CHEVALLIER
2023-07-05 17:35   ` Gatien CHEVALLIER

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