[PULL 00/32] riscv-to-apply queue

* [PULL 00/32] riscv-to-apply queue
@ 2023-02-07  7:09 Alistair Francis
  2023-02-07  7:09 ` [PULL 01/32] target/riscv: update disas.c for xnor/orn/andn and slli.uw Alistair Francis
                   ` (32 more replies)
  0 siblings, 33 replies; 34+ messages in thread
From: Alistair Francis @ 2023-02-07  7:09 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b:

  Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging (2023-02-05 16:49:09 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230207

for you to fetch changes up to 5474aa4f3e0a3e9c171db7c55b5baf15f2e2778c:

  hw/riscv: virt: Simplify virt_{get,set}_aclint() (2023-02-07 08:21:32 +1000)

----------------------------------------------------------------
Third RISC-V PR for QEMU 8.0

* Update disas for xnor/orn/andn and slli.uw
* Update opentitan IRQs
* Fix rom code when Zicsr is disabled
* Update VS timer whenever htimedelta changes
* A collection of fixes for virtulisation
* Set tval for triggered watchpoints
* Cleanups for board and FDT creation
* Add support for the T-Head vendor extensions
* A fix for virtual instr exception
* Fix ctzw behavior
* Fix SBI getchar handler for KVM

----------------------------------------------------------------
Alistair Francis (1):
      hw/riscv: boot: Don't use CSRs if they are disabled

Anup Patel (4):
      target/riscv: Update VS timer whenever htimedelta changes
      target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
      target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX
      target/riscv: Ensure opcode is saved for all relevant instructions

Bin Meng (1):
      hw/riscv: virt: Simplify virt_{get,set}_aclint()

Christoph Müllner (14):
      RISC-V: Adding XTheadCmo ISA extension
      RISC-V: Adding XTheadSync ISA extension
      RISC-V: Adding XTheadBa ISA extension
      RISC-V: Adding XTheadBb ISA extension
      RISC-V: Adding XTheadBs ISA extension
      RISC-V: Adding XTheadCondMov ISA extension
      RISC-V: Adding T-Head multiply-accumulate instructions
      RISC-V: Adding T-Head MemPair extension
      RISC-V: Adding T-Head MemIdx extension
      RISC-V: Adding T-Head FMemIdx extension
      RISC-V: Set minimum priv version for Zfh to 1.11
      RISC-V: Add initial support for T-Head C906
      RISC-V: Adding XTheadFmv ISA extension
      target/riscv: add a MAINTAINERS entry for XThead* extension support

Daniel Henrique Barboza (6):
      hw/riscv/virt.c: calculate socket count once in create_fdt_imsic()
      hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms'
      hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms'
      hw/riscv/boot.c: calculate fdt size after fdt_pack()
      hw/riscv: split fdt address calculation from fdt load
      hw/riscv: change riscv_compute_fdt_addr() semantics

Deepak Gupta (1):
      target/riscv: fix for virtual instr exception

Philipp Tomsich (1):
      target/riscv: update disas.c for xnor/orn/andn and slli.uw

Sergey Matyukevich (1):
      target/riscv: set tval for triggered watchpoints

Vladimir Isaev (2):
      target/riscv: fix ctzw behavior
      target/riscv: fix SBI getchar handler for KVM

Wilfred Mallawa (1):
      include/hw/riscv/opentitan: update opentitan IRQs

 MAINTAINERS                                 |    8 +
 include/hw/riscv/boot.h                     |    4 +-
 include/hw/riscv/opentitan.h                |   14 +-
 target/riscv/cpu.h                          |   12 +
 target/riscv/cpu_vendorid.h                 |    6 +
 target/riscv/helper.h                       |    1 +
 target/riscv/xthead.decode                  |  185 +++++
 disas/riscv.c                               |    8 +-
 hw/riscv/boot.c                             |   62 +-
 hw/riscv/microchip_pfsoc.c                  |    7 +-
 hw/riscv/opentitan.c                        |   80 +-
 hw/riscv/sifive_u.c                         |    8 +-
 hw/riscv/spike.c                            |   25 +-
 hw/riscv/virt.c                             |  476 ++++++------
 target/riscv/cpu.c                          |   55 +-
 target/riscv/cpu_helper.c                   |    8 +-
 target/riscv/csr.c                          |   16 +
 target/riscv/debug.c                        |    1 -
 target/riscv/kvm.c                          |    5 +-
 target/riscv/op_helper.c                    |    6 +
 target/riscv/time_helper.c                  |   36 +-
 target/riscv/translate.c                    |   32 +
 target/riscv/insn_trans/trans_rva.c.inc     |   10 +-
 target/riscv/insn_trans/trans_rvb.c.inc     |    1 +
 target/riscv/insn_trans/trans_rvd.c.inc     |    2 +
 target/riscv/insn_trans/trans_rvf.c.inc     |    2 +
 target/riscv/insn_trans/trans_rvh.c.inc     |    3 +
 target/riscv/insn_trans/trans_rvi.c.inc     |    2 +
 target/riscv/insn_trans/trans_rvzfh.c.inc   |    2 +
 target/riscv/insn_trans/trans_svinval.c.inc |    3 +
 target/riscv/insn_trans/trans_xthead.c.inc  | 1094 +++++++++++++++++++++++++++
 target/riscv/meson.build                    |    1 +
 32 files changed, 1847 insertions(+), 328 deletions(-)
 create mode 100644 target/riscv/cpu_vendorid.h
 create mode 100644 target/riscv/xthead.decode
 create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc

^ permalink raw reply	[flat|nested] 34+ messages in thread