From: Jagan Teki <jagan@amarulasolutions.com> To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>, Marek Szyprowski <m.szyprowski@samsung.com>, Neil Armstrong <neil.armstrong@linaro.org>, Marek Vasut <marex@denx.de>, Maxime Ripard <mripard@kernel.org> Cc: Seung-Woo Kim <sw0312.kim@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Frieder Schrempf <frieder.schrempf@kontron.de>, Tim Harvey <tharvey@gateworks.com>, Adam Ford <aford173@gmail.com>, Matteo Lisi <matteo.lisi@engicam.com>, dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula <linux-amarula@amarulasolutions.com>, Jagan Teki <jagan@amarulasolutions.com> Subject: [PATCH v15 04/16] drm: exynos: dsi: Add platform PLL_P (PMS_P) offset Date: Fri, 3 Mar 2023 20:21:26 +0530 [thread overview] Message-ID: <20230303145138.29233-5-jagan@amarulasolutions.com> (raw) In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> Look like PLL PMS_P offset value varies between platforms that have Samsung DSIM IP. However, there is no clear evidence for it as both Exynos and i.MX 8M Mini Application Processor Reference Manual is still referring the PMS_P offset as 13. The offset 13 is not working for i.MX8M Mini SoCs but the downstream NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms [1] [2]. PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P() with offset 13 and then an additional offset of one bit added in sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS(). Not sure whether it is reference manual documentation or something else but this patch trusts the downstream code and handle PLL_P offset via platform driver data so-that imx8mm driver data shall use pll_p_offset to 14. Similar to Mini the i.MX8M Nano/Plus also has P=14, unlike Exynos. [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210 [2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- Changes for v15, v13, v12, v11, v10, v9: - none Changes for v8: - updated commit message for 8M Nano/Plus Changes for v7, v6: - none Changes for v5: - updated clear commit message Changes for v4, v3, v2: - none Changes for v1: - updated commit message - add downstream driver link drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index af16af404e87..603fed107fd1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -194,7 +194,7 @@ /* DSIM_PLLCTRL */ #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN (1 << 23) -#define DSIM_PLL_P(x) ((x) << 13) +#define DSIM_PLL_P(x, offset) ((x) << (offset)) #define DSIM_PLL_M(x) ((x) << 4) #define DSIM_PLL_S(x) ((x) << 1) @@ -263,6 +263,7 @@ struct exynos_dsi_driver_data { unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; + unsigned int pll_p_offset; const unsigned int *reg_values; }; @@ -471,6 +472,7 @@ static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -483,6 +485,7 @@ static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -493,6 +496,7 @@ static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -504,6 +508,7 @@ static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 0, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5433_reg_values, }; @@ -515,6 +520,7 @@ static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 1, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5422_reg_values, }; @@ -628,7 +634,8 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg); - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | + DSIM_PLL_M(m) | DSIM_PLL_S(s); if (driver_data->has_freqband) { static const unsigned long freq_bands[] = { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Jagan Teki <jagan@amarulasolutions.com> To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>, Marek Szyprowski <m.szyprowski@samsung.com>, Neil Armstrong <neil.armstrong@linaro.org>, Marek Vasut <marex@denx.de>, Maxime Ripard <mripard@kernel.org> Cc: linux-samsung-soc@vger.kernel.org, Matteo Lisi <matteo.lisi@engicam.com>, linux-amarula <linux-amarula@amarulasolutions.com>, Seung-Woo Kim <sw0312.kim@samsung.com>, Frieder Schrempf <frieder.schrempf@kontron.de>, Kyungmin Park <kyungmin.park@samsung.com>, dri-devel@lists.freedesktop.org, Adam Ford <aford173@gmail.com>, Jagan Teki <jagan@amarulasolutions.com> Subject: [PATCH v15 04/16] drm: exynos: dsi: Add platform PLL_P (PMS_P) offset Date: Fri, 3 Mar 2023 20:21:26 +0530 [thread overview] Message-ID: <20230303145138.29233-5-jagan@amarulasolutions.com> (raw) In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> Look like PLL PMS_P offset value varies between platforms that have Samsung DSIM IP. However, there is no clear evidence for it as both Exynos and i.MX 8M Mini Application Processor Reference Manual is still referring the PMS_P offset as 13. The offset 13 is not working for i.MX8M Mini SoCs but the downstream NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms [1] [2]. PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P() with offset 13 and then an additional offset of one bit added in sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS(). Not sure whether it is reference manual documentation or something else but this patch trusts the downstream code and handle PLL_P offset via platform driver data so-that imx8mm driver data shall use pll_p_offset to 14. Similar to Mini the i.MX8M Nano/Plus also has P=14, unlike Exynos. [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210 [2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211 Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- Changes for v15, v13, v12, v11, v10, v9: - none Changes for v8: - updated commit message for 8M Nano/Plus Changes for v7, v6: - none Changes for v5: - updated clear commit message Changes for v4, v3, v2: - none Changes for v1: - updated commit message - add downstream driver link drivers/gpu/drm/exynos/exynos_drm_dsi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index af16af404e87..603fed107fd1 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -194,7 +194,7 @@ /* DSIM_PLLCTRL */ #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN (1 << 23) -#define DSIM_PLL_P(x) ((x) << 13) +#define DSIM_PLL_P(x, offset) ((x) << (offset)) #define DSIM_PLL_M(x) ((x) << 4) #define DSIM_PLL_S(x) ((x) << 1) @@ -263,6 +263,7 @@ struct exynos_dsi_driver_data { unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol; + unsigned int pll_p_offset; const unsigned int *reg_values; }; @@ -471,6 +472,7 @@ static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -483,6 +485,7 @@ static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -493,6 +496,7 @@ static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11, + .pll_p_offset = 13, .reg_values = reg_values, }; @@ -504,6 +508,7 @@ static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 0, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5433_reg_values, }; @@ -515,6 +520,7 @@ static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 1, .num_bits_resol = 12, + .pll_p_offset = 13, .reg_values = exynos5422_reg_values, }; @@ -628,7 +634,8 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg); - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | + DSIM_PLL_M(m) | DSIM_PLL_S(s); if (driver_data->has_freqband) { static const unsigned long freq_bands[] = { -- 2.25.1
next prev parent reply other threads:[~2023-03-03 14:52 UTC|newest] Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20230303145219eucas1p218c2e302e41464432627c8ac074302f8@eucas1p2.samsung.com> 2023-03-03 14:51 ` [PATCH v15 00/16] drm: Add Samsung MIPI DSIM bridge Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 01/16] drm: exynos: dsi: Drop explicit call to bridge detach Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 16:39 ` Marek Vasut 2023-03-03 16:39 ` Marek Vasut 2023-03-03 14:51 ` [PATCH v15 02/16] drm: exynos: dsi: Lookup OF-graph or Child node devices Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 16:41 ` Marek Vasut 2023-03-03 16:41 ` Marek Vasut 2023-03-03 14:51 ` [PATCH v15 03/16] drm: exynos: dsi: Mark PHY as optional Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` Jagan Teki [this message] 2023-03-03 14:51 ` [PATCH v15 04/16] drm: exynos: dsi: Add platform PLL_P (PMS_P) offset Jagan Teki 2023-03-03 14:51 ` [PATCH v15 05/16] drm: exynos: dsi: Introduce hw_type platform data Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 06/16] drm: exynos: dsi: Handle proper host initialization Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 07/16] drm: exynos: dsi: Add atomic check Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 08/16] drm: exynos: dsi: Add input_bus_flags Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 15:00 ` Maxime Ripard 2023-03-03 15:00 ` Maxime Ripard 2023-03-03 15:02 ` Maxime Ripard 2023-03-03 15:02 ` Maxime Ripard 2023-03-03 14:51 ` [PATCH v15 09/16] drm: exynos: dsi: Add atomic_get_input_bus_fmts Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 10/16] drm: exynos: dsi: Consolidate component and bridge Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 11/16] drm: exynos: dsi: Add host helper for te_irq_handler Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 12/16] drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge Jagan Teki 2023-03-03 15:08 ` Maxime Ripard 2023-03-03 15:08 ` Maxime Ripard 2023-03-03 15:11 ` Jagan Teki 2023-03-03 15:11 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 13/16] dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 14/16] drm: bridge: samsung-dsim: Add " Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 15/16] dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 16/16] drm: bridge: samsung-dsim: Add " Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 22:26 ` [PATCH v15 00/16] drm: Add Samsung MIPI DSIM bridge Marek Szyprowski 2023-03-03 22:26 ` Marek Szyprowski 2023-03-04 18:59 ` Jagan Teki 2023-03-04 18:59 ` Jagan Teki 2023-03-06 11:02 ` Marek Szyprowski 2023-03-06 11:02 ` Marek Szyprowski 2023-03-06 17:24 ` Jagan Teki 2023-03-06 17:24 ` Jagan Teki 2023-03-06 22:41 ` Marek Szyprowski 2023-03-06 22:41 ` Marek Szyprowski 2023-03-07 7:55 ` Jagan Teki 2023-03-07 7:55 ` Jagan Teki 2023-03-07 9:22 ` Jagan Teki 2023-03-07 9:22 ` Jagan Teki 2023-03-07 10:44 ` Marek Szyprowski 2023-03-07 10:44 ` Marek Szyprowski 2023-03-06 5:24 ` 대인기/Tizen Platform Lab(SR)/삼성전자 2023-03-06 5:24 ` 대인기/Tizen Platform Lab(SR)/삼성전자 2023-03-06 8:48 ` Jagan Teki 2023-03-06 8:48 ` Jagan Teki 2023-03-14 0:31 ` Fabio Estevam 2023-03-14 0:31 ` Fabio Estevam 2023-03-14 0:51 ` Inki Dae 2023-03-23 15:34 ` Fabio Estevam 2023-03-23 15:34 ` Fabio Estevam 2023-03-27 14:08 ` Neil Armstrong 2023-03-27 14:08 ` Neil Armstrong 2023-03-28 0:03 ` Inki Dae 2023-03-28 7:53 ` Neil Armstrong 2023-03-28 7:53 ` Neil Armstrong
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